2 * Copyright (c) 2011 NetApp, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/kernel.h>
34 #include <sys/systm.h>
35 #include <sys/malloc.h>
40 #include <dev/pci/pcireg.h>
42 #include <machine/pmap.h>
43 #include <machine/vmparam.h>
44 #include <contrib/dev/acpica/include/acpi.h>
49 * Documented in the "Intel Virtualization Technology for Directed I/O",
50 * Architecture Spec, September 2008.
53 /* Section 10.4 "Register Descriptions" */
55 volatile uint32_t version;
56 volatile uint32_t res0;
57 volatile uint64_t cap;
58 volatile uint64_t ext_cap;
59 volatile uint32_t gcr;
60 volatile uint32_t gsr;
61 volatile uint64_t rta;
62 volatile uint64_t ccr;
65 #define VTD_CAP_SAGAW(cap) (((cap) >> 8) & 0x1F)
66 #define VTD_CAP_ND(cap) ((cap) & 0x7)
67 #define VTD_CAP_CM(cap) (((cap) >> 7) & 0x1)
68 #define VTD_CAP_SPS(cap) (((cap) >> 34) & 0xF)
69 #define VTD_CAP_RWBF(cap) (((cap) >> 4) & 0x1)
71 #define VTD_ECAP_DI(ecap) (((ecap) >> 2) & 0x1)
72 #define VTD_ECAP_COHERENCY(ecap) ((ecap) & 0x1)
73 #define VTD_ECAP_IRO(ecap) (((ecap) >> 8) & 0x3FF)
75 #define VTD_GCR_WBF (1 << 27)
76 #define VTD_GCR_SRTP (1 << 30)
77 #define VTD_GCR_TE (1 << 31)
79 #define VTD_GSR_WBFS (1 << 27)
80 #define VTD_GSR_RTPS (1 << 30)
81 #define VTD_GSR_TES (1 << 31)
83 #define VTD_CCR_ICC (1UL << 63) /* invalidate context cache */
84 #define VTD_CCR_CIRG_GLOBAL (1UL << 61) /* global invalidation */
86 #define VTD_IIR_IVT (1UL << 63) /* invalidation IOTLB */
87 #define VTD_IIR_IIRG_GLOBAL (1ULL << 60) /* global IOTLB invalidation */
88 #define VTD_IIR_IIRG_DOMAIN (2ULL << 60) /* domain IOTLB invalidation */
89 #define VTD_IIR_IIRG_PAGE (3ULL << 60) /* page IOTLB invalidation */
90 #define VTD_IIR_DRAIN_READS (1ULL << 49) /* drain pending DMA reads */
91 #define VTD_IIR_DRAIN_WRITES (1ULL << 48) /* drain pending DMA writes */
92 #define VTD_IIR_DOMAIN_P 32
94 #define VTD_ROOT_PRESENT 0x1
95 #define VTD_CTX_PRESENT 0x1
96 #define VTD_CTX_TT_ALL (1UL << 2)
98 #define VTD_PTE_RD (1UL << 0)
99 #define VTD_PTE_WR (1UL << 1)
100 #define VTD_PTE_SUPERPAGE (1UL << 7)
101 #define VTD_PTE_ADDR_M (0x000FFFFFFFFFF000UL)
104 uint64_t *ptp; /* first level page table page */
105 int pt_levels; /* number of page table levels */
106 int addrwidth; /* 'AW' field in context entry */
107 int spsmask; /* supported super page sizes */
108 u_int id; /* domain id */
109 vm_paddr_t maxaddr; /* highest address to be mapped */
110 SLIST_ENTRY(domain) next;
113 static SLIST_HEAD(, domain) domhead;
115 #define DRHD_MAX_UNITS 8
117 static struct vtdmap *vtdmaps[DRHD_MAX_UNITS];
118 static int max_domains;
119 typedef int (*drhd_ident_func_t)(void);
121 static uint64_t root_table[PAGE_SIZE / sizeof(uint64_t)] __aligned(4096);
122 static uint64_t ctx_tables[256][PAGE_SIZE / sizeof(uint64_t)] __aligned(4096);
124 static MALLOC_DEFINE(M_VTD, "vtd", "vtd");
127 vtd_max_domains(struct vtdmap *vtdmap)
131 nd = VTD_CAP_ND(vtdmap->cap);
149 panic("vtd_max_domains: invalid value of nd (0x%0x)", nd);
159 /* Skip domain id 0 - it is reserved when Caching Mode field is set */
160 for (id = 1; id < max_domains; id++) {
161 SLIST_FOREACH(dom, &domhead, next) {
166 break; /* found it */
169 if (id >= max_domains)
170 panic("domain ids exhausted");
176 vtd_wbflush(struct vtdmap *vtdmap)
179 if (VTD_ECAP_COHERENCY(vtdmap->ext_cap) == 0)
180 pmap_invalidate_cache();
182 if (VTD_CAP_RWBF(vtdmap->cap)) {
183 vtdmap->gcr = VTD_GCR_WBF;
184 while ((vtdmap->gsr & VTD_GSR_WBFS) != 0)
190 vtd_ctx_global_invalidate(struct vtdmap *vtdmap)
193 vtdmap->ccr = VTD_CCR_ICC | VTD_CCR_CIRG_GLOBAL;
194 while ((vtdmap->ccr & VTD_CCR_ICC) != 0)
199 vtd_iotlb_global_invalidate(struct vtdmap *vtdmap)
202 volatile uint64_t *iotlb_reg, val;
206 offset = VTD_ECAP_IRO(vtdmap->ext_cap) * 16;
207 iotlb_reg = (volatile uint64_t *)((caddr_t)vtdmap + offset + 8);
209 *iotlb_reg = VTD_IIR_IVT | VTD_IIR_IIRG_GLOBAL |
210 VTD_IIR_DRAIN_READS | VTD_IIR_DRAIN_WRITES;
214 if ((val & VTD_IIR_IVT) == 0)
220 vtd_translation_enable(struct vtdmap *vtdmap)
223 vtdmap->gcr = VTD_GCR_TE;
224 while ((vtdmap->gsr & VTD_GSR_TES) == 0)
229 vtd_translation_disable(struct vtdmap *vtdmap)
233 while ((vtdmap->gsr & VTD_GSR_TES) != 0)
240 int i, units, remaining;
241 struct vtdmap *vtdmap;
242 vm_paddr_t ctx_paddr;
243 char *end, envname[32];
244 unsigned long mapaddr;
246 ACPI_TABLE_DMAR *dmar;
247 ACPI_DMAR_HEADER *hdr;
248 ACPI_DMAR_HARDWARE_UNIT *drhd;
251 * Allow the user to override the ACPI DMAR table by specifying the
252 * physical address of each remapping unit.
254 * The following example specifies two remapping units at
255 * physical addresses 0xfed90000 and 0xfeda0000 respectively.
256 * set vtd.regmap.0.addr=0xfed90000
257 * set vtd.regmap.1.addr=0xfeda0000
259 for (units = 0; units < DRHD_MAX_UNITS; units++) {
260 snprintf(envname, sizeof(envname), "vtd.regmap.%d.addr", units);
261 if (getenv_ulong(envname, &mapaddr) == 0)
263 vtdmaps[units] = (struct vtdmap *)PHYS_TO_DMAP(mapaddr);
269 /* Search for DMAR table. */
270 status = AcpiGetTable(ACPI_SIG_DMAR, 0, (ACPI_TABLE_HEADER **)&dmar);
271 if (ACPI_FAILURE(status))
274 end = (char *)dmar + dmar->Header.Length;
275 remaining = dmar->Header.Length - sizeof(ACPI_TABLE_DMAR);
276 while (remaining > sizeof(ACPI_DMAR_HEADER)) {
277 hdr = (ACPI_DMAR_HEADER *)(end - remaining);
278 if (hdr->Length > remaining)
281 * From Intel VT-d arch spec, version 1.3:
282 * BIOS implementations must report mapping structures
283 * in numerical order, i.e. All remapping structures of
284 * type 0 (DRHD) enumerated before remapping structures of
285 * type 1 (RMRR) and so forth.
287 if (hdr->Type != ACPI_DMAR_TYPE_HARDWARE_UNIT)
290 drhd = (ACPI_DMAR_HARDWARE_UNIT *)hdr;
291 vtdmaps[units++] = (struct vtdmap *)PHYS_TO_DMAP(drhd->Address);
292 if (units >= DRHD_MAX_UNITS)
294 remaining -= hdr->Length;
304 if (VTD_CAP_CM(vtdmap->cap) != 0)
305 panic("vtd_init: invalid caching mode");
307 max_domains = vtd_max_domains(vtdmap);
310 * Set up the root-table to point to the context-entry tables
312 for (i = 0; i < 256; i++) {
313 ctx_paddr = vtophys(ctx_tables[i]);
314 if (ctx_paddr & PAGE_MASK)
315 panic("ctx table (0x%0lx) not page aligned", ctx_paddr);
317 root_table[i * 2] = ctx_paddr | VTD_ROOT_PRESENT;
332 struct vtdmap *vtdmap;
334 for (i = 0; i < drhd_num; i++) {
338 /* Update the root table address */
339 vtdmap->rta = vtophys(root_table);
340 vtdmap->gcr = VTD_GCR_SRTP;
341 while ((vtdmap->gsr & VTD_GSR_RTPS) == 0)
344 vtd_ctx_global_invalidate(vtdmap);
345 vtd_iotlb_global_invalidate(vtdmap);
347 vtd_translation_enable(vtdmap);
355 struct vtdmap *vtdmap;
357 for (i = 0; i < drhd_num; i++) {
359 vtd_translation_disable(vtdmap);
364 vtd_add_device(void *arg, int bus, int slot, int func)
368 struct domain *dom = arg;
370 struct vtdmap *vtdmap;
372 if (bus < 0 || bus > PCI_BUSMAX ||
373 slot < 0 || slot > PCI_SLOTMAX ||
374 func < 0 || func > PCI_FUNCMAX)
375 panic("vtd_add_device: invalid bsf %d/%d/%d", bus, slot, func);
378 ctxp = ctx_tables[bus];
379 pt_paddr = vtophys(dom->ptp);
380 idx = (slot << 3 | func) * 2;
382 if (ctxp[idx] & VTD_CTX_PRESENT) {
383 panic("vtd_add_device: device %d/%d/%d is already owned by "
384 "domain %d", bus, slot, func,
385 (uint16_t)(ctxp[idx + 1] >> 8));
389 * Order is important. The 'present' bit is set only after all fields
390 * of the context pointer are initialized.
392 ctxp[idx + 1] = dom->addrwidth | (dom->id << 8);
394 if (VTD_ECAP_DI(vtdmap->ext_cap))
395 ctxp[idx] = VTD_CTX_TT_ALL;
399 ctxp[idx] |= pt_paddr | VTD_CTX_PRESENT;
402 * 'Not Present' entries are not cached in either the Context Cache
403 * or in the IOTLB, so there is no need to invalidate either of them.
408 vtd_remove_device(void *arg, int bus, int slot, int func)
412 struct vtdmap *vtdmap;
414 if (bus < 0 || bus > PCI_BUSMAX ||
415 slot < 0 || slot > PCI_SLOTMAX ||
416 func < 0 || func > PCI_FUNCMAX)
417 panic("vtd_add_device: invalid bsf %d/%d/%d", bus, slot, func);
419 ctxp = ctx_tables[bus];
420 idx = (slot << 3 | func) * 2;
423 * Order is important. The 'present' bit is must be cleared first.
429 * Invalidate the Context Cache and the IOTLB.
431 * XXX use device-selective invalidation for Context Cache
432 * XXX use domain-selective invalidation for IOTLB
434 for (i = 0; i < drhd_num; i++) {
436 vtd_ctx_global_invalidate(vtdmap);
437 vtd_iotlb_global_invalidate(vtdmap);
441 #define CREATE_MAPPING 0
442 #define REMOVE_MAPPING 1
445 vtd_update_mapping(void *arg, vm_paddr_t gpa, vm_paddr_t hpa, uint64_t len,
449 int i, spshift, ptpshift, ptpindex, nlevels;
450 uint64_t spsize, *ptp;
457 panic("vtd_create_mapping: unaligned gpa 0x%0lx", gpa);
460 panic("vtd_create_mapping: unaligned hpa 0x%0lx", hpa);
463 panic("vtd_create_mapping: unaligned len 0x%0lx", len);
466 * Compute the size of the mapping that we can accomodate.
468 * This is based on three factors:
469 * - supported super page size
470 * - alignment of the region starting at 'gpa' and 'hpa'
471 * - length of the region 'len'
474 for (i = 3; i >= 0; i--) {
475 spsize = 1UL << spshift;
476 if ((dom->spsmask & (1 << i)) != 0 &&
477 (gpa & (spsize - 1)) == 0 &&
478 (hpa & (spsize - 1)) == 0 &&
486 nlevels = dom->pt_levels;
487 while (--nlevels >= 0) {
488 ptpshift = 12 + nlevels * 9;
489 ptpindex = (gpa >> ptpshift) & 0x1FF;
491 /* We have reached the leaf mapping */
492 if (spshift >= ptpshift) {
497 * We are working on a non-leaf page table page.
499 * Create a downstream page table page if necessary and point
500 * to it from the current page table.
502 if (ptp[ptpindex] == 0) {
503 void *nlp = malloc(PAGE_SIZE, M_VTD, M_WAITOK | M_ZERO);
504 ptp[ptpindex] = vtophys(nlp)| VTD_PTE_RD | VTD_PTE_WR;
507 ptp = (uint64_t *)PHYS_TO_DMAP(ptp[ptpindex] & VTD_PTE_ADDR_M);
510 if ((gpa & ((1UL << ptpshift) - 1)) != 0)
511 panic("gpa 0x%lx and ptpshift %d mismatch", gpa, ptpshift);
514 * Update the 'gpa' -> 'hpa' mapping
519 ptp[ptpindex] = hpa | VTD_PTE_RD | VTD_PTE_WR;
522 ptp[ptpindex] |= VTD_PTE_SUPERPAGE;
525 return (1UL << ptpshift);
529 vtd_create_mapping(void *arg, vm_paddr_t gpa, vm_paddr_t hpa, uint64_t len)
532 return (vtd_update_mapping(arg, gpa, hpa, len, CREATE_MAPPING));
536 vtd_remove_mapping(void *arg, vm_paddr_t gpa, uint64_t len)
539 return (vtd_update_mapping(arg, gpa, 0, len, REMOVE_MAPPING));
543 vtd_invalidate_tlb(void *dom)
546 struct vtdmap *vtdmap;
549 * Invalidate the IOTLB.
550 * XXX use domain-selective invalidation for IOTLB
552 for (i = 0; i < drhd_num; i++) {
554 vtd_iotlb_global_invalidate(vtdmap);
559 vtd_create_domain(vm_paddr_t maxaddr)
563 int tmp, i, gaw, agaw, sagaw, res, pt_levels, addrwidth;
564 struct vtdmap *vtdmap;
567 panic("vtd_create_domain: no dma remapping hardware available");
573 * Section 3.4.2 "Adjusted Guest Address Width", Architecture Spec.
576 for (gaw = 0; addr < maxaddr; gaw++)
579 res = (gaw - 12) % 9;
583 agaw = gaw + 9 - res;
589 * Select the smallest Supported AGAW and the corresponding number
590 * of page table levels.
595 tmp = VTD_CAP_SAGAW(vtdmap->cap);
596 for (i = 0; i < 5; i++) {
597 if ((tmp & (1 << i)) != 0 && sagaw >= agaw)
607 panic("vtd_create_domain: SAGAW 0x%lx does not support AGAW %d",
608 VTD_CAP_SAGAW(vtdmap->cap), agaw);
611 dom = malloc(sizeof(struct domain), M_VTD, M_ZERO | M_WAITOK);
612 dom->pt_levels = pt_levels;
613 dom->addrwidth = addrwidth;
614 dom->id = domain_id();
615 dom->maxaddr = maxaddr;
616 dom->ptp = malloc(PAGE_SIZE, M_VTD, M_ZERO | M_WAITOK);
617 if ((uintptr_t)dom->ptp & PAGE_MASK)
618 panic("vtd_create_domain: ptp (%p) not page aligned", dom->ptp);
622 * XXX superpage mappings for the iommu do not work correctly.
624 * By default all physical memory is mapped into the host_domain.
625 * When a VM is allocated wired memory the pages belonging to it
626 * are removed from the host_domain and added to the vm's domain.
628 * If the page being removed was mapped using a superpage mapping
629 * in the host_domain then we need to demote the mapping before
632 * There is not any code to deal with the demotion at the moment
633 * so we disable superpage mappings altogether.
635 dom->spsmask = VTD_CAP_SPS(vtdmap->cap);
638 SLIST_INSERT_HEAD(&domhead, dom, next);
644 vtd_free_ptp(uint64_t *ptp, int level)
650 for (i = 0; i < 512; i++) {
651 if ((ptp[i] & (VTD_PTE_RD | VTD_PTE_WR)) == 0)
653 if ((ptp[i] & VTD_PTE_SUPERPAGE) != 0)
655 nlp = (uint64_t *)PHYS_TO_DMAP(ptp[i] & VTD_PTE_ADDR_M);
656 vtd_free_ptp(nlp, level - 1);
660 bzero(ptp, PAGE_SIZE);
665 vtd_destroy_domain(void *arg)
671 SLIST_REMOVE(&domhead, dom, domain, next);
672 vtd_free_ptp(dom->ptp, dom->pt_levels);
676 struct iommu_ops iommu_ops_intel = {