2 * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@gmail.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #ifndef _A20_CPU_CFG_H_
30 #define _A20_CPU_CFG_H_
32 #define CPU_CFG_BASE 0xe1c25c00
34 #define CPU0_RST_CTRL 0x0040
35 #define CPU0_CTRL_REG 0x0044
36 #define CPU0_STATUS_REG 0x0048
38 #define CPU1_RST_CTRL 0x0080
39 #define CPU1_CTRL_REG 0x0084
40 #define CPU1_STATUS_REG 0x0088
42 #define GENER_CTRL_REG 0x0184
44 #define EVENT_IN_REG 0x0190
45 #define PRIVATE_REG 0x01a4
47 #define IDLE_CNT0_LOW_REG 0x0200
48 #define IDLE_CNT0_HIGH_REG 0x0204
49 #define IDLE_CNT0_CTRL_REG 0x0208
51 #define IDLE_CNT1_LOW_REG 0x0210
52 #define IDLE_CNT1_HIGH_REG 0x0214
53 #define IDLE_CNT1_CTRL_REG 0x0218
55 #define OSC24M_CNT64_CTRL_REG 0x0280
56 #define OSC24M_CNT64_LOW_REG 0x0284
57 #define OSC24M_CNT64_HIGH_REG 0x0288
59 #define LOSC_CNT64_CTRL_REG 0x0290
60 #define LOSC_CNT64_LOW_REG 0x0294
61 #define LOSC_CNT64_HIGH_REG 0x0298
63 #define CNT64_RL_EN 0x02 /* read latch enable */
65 uint64_t a20_read_counter64(void);
67 #endif /* _A20_CPU_CFG_H_ */