1 /* $NetBSD: locore.S,v 1.14 2003/04/20 16:21:40 thorpej Exp $ */
4 * Copyright 2011 Semihalf
5 * Copyright (C) 1994-1997 Mark Brinicombe
6 * Copyright (C) 1994 Brini
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by Brini.
20 * 4. The name of Brini may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 #include <sys/syscall.h>
38 #include <machine/asm.h>
39 #include <machine/armreg.h>
40 #include <machine/pte.h>
42 __FBSDID("$FreeBSD$");
44 /* What size should this really be ? It is only used by initarm() */
45 #define INIT_ARM_STACK_SIZE (2048 * 4)
47 #define CPWAIT_BRANCH \
51 mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\
52 mov tmp, tmp /* wait for it to complete */ ;\
53 CPWAIT_BRANCH /* branch to next insn */
56 * This is for kvm_mkdb, and should be the address of the beginning
57 * of the kernel text segment (not necessarily the same as kernbase).
62 .set kernbase,KERNBASE
64 .set physaddr,PHYSADDR
67 * On entry for FreeBSD boot ABI:
68 * r0 - metadata pointer or 0 (boothowto on AT91's boot2)
69 * r1 - if (r0 == 0) then metadata pointer
70 * On entry for Linux boot ABI:
72 * r1 - machine type (passed as arg2 to initarm)
73 * r2 - Pointer to a tagged list or dtb image (phys addr) (passed as arg1 initarm)
75 * For both types of boot we gather up the args, put them in a struct arm_boot_params
76 * structure and pass that to initarm.
80 STOP_UNWINDING /* Can't unwind into the bootloader! */
82 mov r9, r0 /* 0 or boot mode from boot2 */
83 mov r8, r1 /* Save Machine type */
84 mov ip, r2 /* Save meta data */
85 mov fp, r3 /* Future expantion */
87 /* Make sure interrupts are disabled. */
89 orr r7, r7, #(I32_bit|F32_bit)
92 #if defined (FLASHADDR) && defined(LOADERRAMADDR)
93 /* Check if we're running from flash. */
96 * If we're running with MMU disabled, test against the
97 * physical address instead.
99 mrc p15, 0, r2, c1, c0, 0
100 ands r2, r2, #CPU_CONTROL_MMU_ENABLE
102 ldrne r6, =LOADERRAMADDR
124 Lram_offset: .word from_ram-_C_LABEL(_start)
129 bic r7, r7, #0xf0000000
130 orr r7, r7, #PHYSADDR
134 /* Disable MMU for a while */
135 mrc p15, 0, r2, c1, c0, 0
136 bic r2, r2, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE |\
137 CPU_CONTROL_WBUF_ENABLE)
138 bic r2, r2, #(CPU_CONTROL_IC_ENABLE)
139 bic r2, r2, #(CPU_CONTROL_BPRD_ENABLE)
140 mcr p15, 0, r2, c1, c0, 0
147 #ifdef STARTUP_PAGETABLE_ADDR
148 /* build page table from scratch */
149 ldr r0, Lstartup_pagetable
150 adr r4, mmu_init_table
156 add r3, r3, #(L1_S_SIZE)
160 ldmia r4!, {r1,r2,r3} /* # of sections, VA, PA|attr */
163 bicne r5, r5, #0xf0000000
164 orrne r5, r5, #PHYSADDR
168 orr r0, r0, #2 /* Set TTB shared memory flag */
170 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
171 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
173 #if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B)
175 mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */
178 /* Set the Domain Access register. Very important! */
179 mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT)
180 mcr p15, 0, r0, c3, c0, 0
183 * On armv6 enable extended page tables, and set alignment checking
184 * to modulo-4 (CPU_CONTROL_UNAL_ENABLE) for the ldrd/strd
185 * instructions emitted by clang.
187 mrc p15, 0, r0, c1, c0, 0
189 orr r0, r0, #(CPU_CONTROL_V6_EXTPAGE | CPU_CONTROL_UNAL_ENABLE)
190 orr r2, r2, #(CPU_CONTROL_AFLT_ENABLE)
191 orr r0, r0, #(CPU_CONTROL_AF_ENABLE)
193 orr r0, r0, #(CPU_CONTROL_MMU_ENABLE)
194 mcr p15, 0, r0, c1, c0, 0
204 ldmia r1, {r1, r2, sp} /* Set initial stack and */
205 sub r2, r2, r1 /* get zero init data */
208 str r3, [r1], #0x0004 /* get zero init data */
214 mov r1, #20 /* loader info size is 20 bytes also second arg */
215 subs sp, sp, r1 /* allocate arm_boot_params struct on stack */
216 bic sp, sp, #7 /* align stack to 8 bytes */
217 mov r0, sp /* loader info pointer is first arg */
218 str r1, [r0] /* Store length of loader info */
219 str r9, [r0, #4] /* Store r0 from boot loader */
220 str r8, [r0, #8] /* Store r1 from boot loader */
221 str ip, [r0, #12] /* store r2 from boot loader */
222 str fp, [r0, #16] /* store r3 from boot loader */
223 mov fp, #0 /* trace back starts here */
224 bl _C_LABEL(initarm) /* Off we go */
226 /* init arm will return the new stack pointer. */
229 bl _C_LABEL(mi_startup) /* call mi_startup()! */
231 adr r0, .Lmainreturned
234 #ifdef STARTUP_PAGETABLE_ADDR
235 #define MMU_INIT(va,pa,n_sec,attr) \
237 .word 4*((va)>>L1_S_SHIFT) ; \
249 .word STARTUP_PAGETABLE_ADDR
251 Lstartup_pagetable_secondary:
258 /* fill all table VA==PA */
259 /* map SDRAM VA==PA, WT cacheable */
261 MMU_INIT(PHYSADDR, PHYSADDR , 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW))
262 /* map VA 0xc0000000..0xc3ffffff to PA */
263 MMU_INIT(KERNBASE, PHYSADDR, 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW))
265 MMU_INIT(PHYSADDR, PHYSADDR , 64, L1_TYPE_S|L1_SHARED|L1_S_C|L1_S_AP(AP_KRW))
266 /* map VA 0xc0000000..0xc3ffffff to PA */
267 MMU_INIT(KERNBASE, PHYSADDR, 64, L1_TYPE_S|L1_SHARED|L1_S_C|L1_S_AP(AP_KRW))
268 MMU_INIT(0x48000000, 0x48000000, 1, L1_TYPE_S|L1_SHARED|L1_S_C|L1_S_AP(AP_KRW))
269 #if defined(CPU_MV_PJ4B)
270 /* map VA 0xf1000000..0xf1100000 to PA 0xd0000000 */
271 MMU_INIT(0xf1000000, 0xd0000000, 1, L1_TYPE_S|L1_SHARED|L1_S_B|L1_S_AP(AP_KRW))
272 #endif /* CPU_MV_PJ4B */
274 .word 0 /* end of table */
279 .word svcstk + INIT_ARM_STACK_SIZE
289 .asciz "main() returned"
294 .space INIT_ARM_STACK_SIZE
300 .word _C_LABEL(cpufuncs)
307 #define AP_DEBUG(tmp) \
308 mrc p15, 0, r1, c0, c0, 5; \
310 add r0, r1, lsl #2; \
312 str r1, [r0], #0x0000;
314 #define AP_DEBUG(tmp)
320 mcr p15, 0, r0, c7, c7, 0
325 bic r3, r3, #(PSR_MODE)
326 orr r3, r3, #(PSR_SVC32_MODE)
329 mrc p15, 0, r0, c0, c0, 5
330 and r0, #0x0f /* Get CPU ID */
332 /* Read boot address for CPU */
349 /* Make sure interrupts are disabled. */
351 orr r7, r7, #(I32_bit|F32_bit)
356 bic r7, r7, #0xf0000000
357 orr r7, r7, #PHYSADDR
359 /* Disable MMU for a while */
360 mrc p15, 0, r2, c1, c0, 0
361 bic r2, r2, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE |\
362 CPU_CONTROL_WBUF_ENABLE)
363 bic r2, r2, #(CPU_CONTROL_IC_ENABLE)
364 bic r2, r2, #(CPU_CONTROL_BPRD_ENABLE)
365 mcr p15, 0, r2, c1, c0, 0
374 ldr r0, Lstartup_pagetable_secondary
375 bic r0, r0, #0xf0000000
376 orr r0, r0, #PHYSADDR
379 orr r0, r0, #0 /* Set TTB shared memory flag */
381 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
382 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
384 #if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA)
386 mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */
391 /* Set the Domain Access register. Very important! */
392 mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT)
393 mcr p15, 0, r0, c3, c0, 0
395 mrc p15, 0, r0, c1, c0, 0
396 #if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA)
397 orr r0, r0, #CPU_CONTROL_V6_EXTPAGE
399 orr r0, r0, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE)
400 mcr p15, 0, r0, c1, c0, 0
407 ldmia r1, {r1, r2, sp} /* Set initial stack and */
408 mrc p15, 0, r0, c0, c0, 5
414 ldr pc, .Lmpvirt_done
418 mov fp, #0 /* trace back starts here */
419 bl _C_LABEL(init_secondary) /* Off we go */
426 .asciz "main() returned"
433 bic r2, r2, #(PSR_MODE)
434 orr r2, r2, #(PSR_SVC32_MODE)
435 orr r2, r2, #(I32_bit | F32_bit)
438 ldr r4, .Lcpu_reset_address
443 ldr pc, [r0, #CF_IDCACHE_WBINV_ALL]
445 ldr pc, [r0, #CF_L2CACHE_WBINV_ALL]
448 * Load the cpu_reset_needs_v4_MMU_disable flag to determine if it's
452 ldr r1, .Lcpu_reset_needs_v4_MMU_disable
458 * MMU & IDC off, 32 bit program & data space
459 * Hurl ourselves into the ROM
461 mov r0, #(CPU_CONTROL_32BP_ENABLE | CPU_CONTROL_32BD_ENABLE)
462 mcr 15, 0, r0, c1, c0, 0
463 mcrne 15, 0, r2, c8, c7, 0 /* nail I+D TLB on ARMv4 and greater */
467 * _cpu_reset_address contains the address to branch to, to complete
468 * the cpu reset after turning the MMU off
469 * This variable is provided by the hardware specific code
472 .word _C_LABEL(cpu_reset_address)
475 * cpu_reset_needs_v4_MMU_disable contains a flag that signals if the
476 * v4 MMU disable instruction needs executing... it is an illegal instruction
477 * on f.e. ARM6/7 that locks up the computer in an endless illegal
478 * instruction / data-abort / reset loop.
480 .Lcpu_reset_needs_v4_MMU_disable:
481 .word _C_LABEL(cpu_reset_needs_v4_MMU_disable)
501 .global _C_LABEL(esym)
502 _C_LABEL(esym): .word _C_LABEL(end)
512 * Call the sigreturn system call.
514 * We have to load r7 manually rather than using
515 * "ldr r7, =SYS_sigreturn" to ensure the value of szsigcode is
516 * correct. Using the alternative places esigcode at the address
517 * of the data rather than the address one past the data.
520 ldr r7, [pc, #12] /* Load SYS_sigreturn */
523 /* Well if that failed we better exit quick ! */
525 ldr r7, [pc, #8] /* Load SYS_exit */
528 /* Branch back to retry SYS_sigreturn */
535 .global _C_LABEL(esigcode)
541 .long esigcode-sigcode
543 /* End of locore.S */