1 /* $NetBSD: cpuswitch.S,v 1.41 2003/11/15 08:44:18 scw Exp $ */
4 * Copyright 2003 Wasabi Systems, Inc.
7 * Written by Steve C. Woodford for Wasabi Systems, Inc.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
38 * Copyright (c) 1994-1998 Mark Brinicombe.
39 * Copyright (c) 1994 Brini.
40 * All rights reserved.
42 * This code is derived from software written for Brini by Mark Brinicombe
44 * Redistribution and use in source and binary forms, with or without
45 * modification, are permitted provided that the following conditions
47 * 1. Redistributions of source code must retain the above copyright
48 * notice, this list of conditions and the following disclaimer.
49 * 2. Redistributions in binary form must reproduce the above copyright
50 * notice, this list of conditions and the following disclaimer in the
51 * documentation and/or other materials provided with the distribution.
52 * 3. All advertising materials mentioning features or use of this software
53 * must display the following acknowledgement:
54 * This product includes software developed by Brini.
55 * 4. The name of the company nor the name of the author may be used to
56 * endorse or promote products derived from this software without specific
57 * prior written permission.
59 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
60 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
61 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
62 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
63 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
64 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
65 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
71 * RiscBSD kernel project
75 * cpu switching functions
82 #include "opt_sched.h"
84 #include <machine/asm.h>
85 #include <machine/asmacros.h>
86 #include <machine/armreg.h>
87 __FBSDID("$FreeBSD$");
89 #define DOMAIN_CLIENT 0x01
92 #define GET_PCPU(tmp) \
93 mrc p15, 0, tmp, c13, c0, 4;
96 .word _C_LABEL(__pcpu)
98 #define GET_PCPU(tmp) \
103 .word _C_LABEL(cpufuncs)
105 .word _C_LABEL(blocked_lock)
119 * vfp_discard will clear pcpu->pc_vfpcthread, and modify
120 * and modify the control as needed.
122 ldr r4, [r7, #(PC_VFPCTHREAD)] /* this thread using vfp? */
125 bl _C_LABEL(vfp_discard) /* yes, shut down vfp */
129 ldr r7, [r5, #(TD_PCB)] /* r7 = new thread's PCB */
131 /* Switch to lwp0 context */
134 #if !defined(CPU_ARM11) && !defined(CPU_CORTEXA) && !defined(CPU_MV_PJ4B)
136 ldr pc, [r9, #CF_IDCACHE_WBINV_ALL]
138 ldr r0, [r7, #(PCB_PL1VEC)]
139 ldr r1, [r7, #(PCB_DACR)]
141 * r0 = Pointer to L1 slot for vector_page (or NULL)
150 * Ensure the vector table is accessible by fixing up lwp0's L1
152 cmp r0, #0 /* No need to fixup vector table? */
153 ldrne r3, [r0] /* But if yes, fetch current value */
154 ldrne r2, [r7, #(PCB_L1VEC)] /* Fetch new vector_page value */
155 mcr p15, 0, r1, c3, c0, 0 /* Update DACR for lwp0's context */
156 cmpne r3, r2 /* Stuffing the same value? */
157 strne r2, [r0] /* Store if not. */
159 #ifdef PMAP_INCLUDE_PTE_SYNC
161 * Need to sync the cache to make sure that last store is
162 * visible to the MMU.
166 ldrne pc, [r9, #CF_DCACHE_WB_RANGE]
167 #endif /* PMAP_INCLUDE_PTE_SYNC */
170 * Note: We don't do the same optimisation as cpu_switch() with
171 * respect to avoiding flushing the TLB if we're switching to
172 * the same L1 since this process' VM space may be about to go
173 * away, so we don't want *any* turds left in the TLB.
176 /* Switch the memory to the new process */
177 ldr r0, [r7, #(PCB_PAGEDIR)]
179 ldr pc, [r9, #CF_CONTEXT_SWITCH]
181 /* Restore all the save registers */
186 ldr r8, [r7, #(PCB_R8)]
187 ldr r9, [r7, #(PCB_R9)]
188 ldr r10, [r7, #(PCB_R10)]
189 ldr r11, [r7, #(PCB_R11)]
190 ldr r12, [r7, #(PCB_R12)]
191 ldr r13, [r7, #(PCB_SP)]
194 /* We have a new curthread now so make a note it */
195 GET_CURTHREAD_PTR(r6)
199 ldr r6, [r5, #(TD_MD + MD_TP)]
200 #ifdef ARM_TP_ADDRESS
201 ldr r4, =ARM_TP_ADDRESS
203 ldr r6, [r5, #(TD_MD + MD_RAS_START)]
204 str r6, [r4, #4] /* ARM_RAS_START */
205 ldr r6, [r5, #(TD_MD + MD_RAS_END)]
206 str r6, [r4, #8] /* ARM_RAS_END */
208 mcr p15, 0, r6, c13, c0, 3
210 /* Hook in a new pcb */
212 str r7, [r6, #PC_CURPCB]
215 ldmfd sp!, {r4-r7, pc}
219 stmfd sp!, {r4-r7, lr}
226 mov r6, r2 /* Save the mutex */
229 /* rem: r0 = old lwp */
230 /* rem: interrupts are disabled */
232 /* Process is now on a processor. */
233 /* We have a new curthread now so make a note it */
234 GET_CURTHREAD_PTR(r7)
237 /* Hook in a new pcb */
239 ldr r2, [r1, #TD_PCB]
240 str r2, [r7, #PC_CURPCB]
242 /* rem: r1 = new process */
243 /* rem: interrupts are enabled */
245 /* Stage two : Save old context */
247 /* Get the user structure for the old thread. */
248 ldr r2, [r0, #(TD_PCB)]
249 mov r4, r0 /* Save the old thread. */
251 /* Save all the registers in the old thread's pcb */
253 add r7, r2, #(PCB_R8)
256 strd r8, [r2, #(PCB_R8)]
257 strd r10, [r2, #(PCB_R10)]
258 strd r12, [r2, #(PCB_R12)]
260 str pc, [r2, #(PCB_PC)]
263 * NOTE: We can now use r8-r13 until it is time to restore
264 * them for the new process.
266 #ifdef ARM_TP_ADDRESS
267 /* Store the old tp */
268 ldr r3, =ARM_TP_ADDRESS
270 str r9, [r0, #(TD_MD + MD_TP)]
272 str r9, [r0, #(TD_MD + MD_RAS_START)]
274 str r9, [r0, #(TD_MD + MD_RAS_END)]
277 ldr r9, [r1, #(TD_MD + MD_TP)]
279 ldr r9, [r1, #(TD_MD + MD_RAS_START)]
281 ldr r9, [r1, #(TD_MD + MD_RAS_END)]
284 /* Store the old tp */
285 mrc p15, 0, r9, c13, c0, 3
286 str r9, [r0, #(TD_MD + MD_TP)]
289 ldr r9, [r1, #(TD_MD + MD_TP)]
290 mcr p15, 0, r9, c13, c0, 3
293 /* Get the user structure for the new process in r9 */
294 ldr r9, [r1, #(TD_PCB)]
298 * We can do that, since
299 * PSR_SVC32_MODE|PSR_UND32_MODE == MSR_UND32_MODE
301 orr r8, r3, #(PSR_UND32_MODE)
304 str sp, [r2, #(PCB_UND_SP)]
306 msr cpsr_c, r3 /* Restore the old mode */
307 /* rem: r2 = old PCB */
308 /* rem: r9 = new PCB */
309 /* rem: interrupts are enabled */
313 * vfp_store will clear pcpu->pc_vfpcthread, save
314 * registers and state, and modify the control as needed.
315 * a future exception will bounce the backup settings in the fp unit.
316 * XXX vfp_store can't change r4
319 ldr r8, [r7, #(PC_VFPCTHREAD)]
320 cmp r4, r8 /* old thread used vfp? */
321 bne 1f /* no, don't save */
322 cmp r1, r4 /* same thread ? */
323 beq 1f /* yes, skip vfp store */
325 ldr r8, [r7, #(PC_CPU)] /* last used on this cpu? */
326 ldr r3, [r2, #(PCB_VFPCPU)]
327 cmp r8, r3 /* last cpu to use these registers? */
328 bne 1f /* no. these values are stale */
330 add r0, r2, #(PCB_VFPSTATE)
331 bl _C_LABEL(vfp_store)
337 /* Third phase : restore saved context */
339 /* rem: r2 = old PCB */
340 /* rem: r9 = new PCB */
341 /* rem: interrupts are enabled */
343 ldr r5, [r9, #(PCB_DACR)] /* r5 = new DACR */
344 mov r2, #DOMAIN_CLIENT
345 cmp r5, r2, lsl #(PMAP_DOMAIN_KERNEL * 2) /* Sw to kernel thread? */
346 beq .Lcs_context_switched /* Yup. Don't flush cache */
347 mrc p15, 0, r0, c3, c0, 0 /* r0 = old DACR */
349 * Get the new L1 table pointer into r11. If we're switching to
350 * an LWP with the same address space as the outgoing one, we can
351 * skip the cache purge and the TTB load.
353 * To avoid data dep stalls that would happen anyway, we try
354 * and get some useful work done in the mean time.
356 mrc p15, 0, r10, c2, c0, 0 /* r10 = old L1 */
357 ldr r11, [r9, #(PCB_PAGEDIR)] /* r11 = new L1 */
360 teq r10, r11 /* Same L1? */
361 cmpeq r0, r5 /* Same DACR? */
362 beq .Lcs_context_switched /* yes! */
364 #if !defined(CPU_ARM11) && !defined(CPU_CORTEXA) && !defined(CPU_MV_PJ4B)
366 * Definately need to flush the cache.
371 ldr pc, [r1, #CF_IDCACHE_WBINV_ALL]
373 .Lcs_cache_purge_skipped:
375 /* rem: r9 = new PCB */
376 /* rem: r10 = old L1 */
377 /* rem: r11 = new L1 */
380 ldr r7, [r9, #(PCB_PL1VEC)]
383 * Ensure the vector table is accessible by fixing up the L1
385 cmp r7, #0 /* No need to fixup vector table? */
386 ldrne r2, [r7] /* But if yes, fetch current value */
387 ldrne r0, [r9, #(PCB_L1VEC)] /* Fetch new vector_page value */
388 mcr p15, 0, r5, c3, c0, 0 /* Update DACR for new context */
389 cmpne r2, r0 /* Stuffing the same value? */
390 #ifndef PMAP_INCLUDE_PTE_SYNC
391 strne r0, [r7] /* Nope, update it */
394 str r0, [r7] /* Otherwise, update it */
397 * Need to sync the cache to make sure that last store is
398 * visible to the MMU.
404 ldr pc, [r2, #CF_DCACHE_WB_RANGE]
407 #endif /* PMAP_INCLUDE_PTE_SYNC */
409 cmp r10, r11 /* Switching to the same L1? */
411 beq .Lcs_same_l1 /* Yup. */
413 * Do a full context switch, including full TLB flush.
417 ldr pc, [r10, #CF_CONTEXT_SWITCH]
419 b .Lcs_context_switched
422 * We're switching to a different process in the same L1.
423 * In this situation, we only need to flush the TLB for the
424 * vector_page mapping, and even then only if r7 is non-NULL.
428 movne r0, #0 /* We *know* vector_page's VA is 0x0 */
430 ldrne pc, [r10, #CF_TLB_FLUSHID_SE]
432 * We can do that, since
433 * PSR_SVC32_MODE|PSR_UND32_MODE == MSR_UND32_MODE
436 .Lcs_context_switched:
438 /* Release the old thread */
439 str r6, [r4, #TD_LOCK]
440 #if defined(SCHED_ULE) && defined(SMP)
441 ldr r6, .Lblocked_lock
442 GET_CURTHREAD_PTR(r3)
445 ldr r4, [r3, #TD_LOCK]
450 /* XXXSCW: Safe to re-enable FIQs here */
452 /* rem: r9 = new PCB */
456 * We can do that, since
457 * PSR_SVC32_MODE|PSR_UND32_MODE == MSR_UND32_MODE
459 orr r2, r3, #(PSR_UND32_MODE)
462 ldr sp, [r9, #(PCB_UND_SP)]
464 msr cpsr_c, r3 /* Restore the old mode */
465 /* Restore all the save registers */
469 sub r7, r7, #PCB_R8 /* restore PCB pointer */
472 ldr r8, [r7, #(PCB_R8)]
473 ldr r9, [r7, #(PCB_R9)]
474 ldr r10, [r7, #(PCB_R10)]
475 ldr r11, [r7, #(PCB_R11)]
476 ldr r12, [r7, #(PCB_R12)]
477 ldr r13, [r7, #(PCB_SP)]
480 /* rem: r5 = new lwp's proc */
482 /* rem: r7 = new PCB */
487 * Pull the registers that got pushed when either savectx() or
488 * cpu_switch() was called and return.
491 ldmfd sp!, {r4-r7, pc}
494 adr r0, .Lswitch_panic_str
500 .asciz "cpu_switch: sched_qs empty with non-zero sched_whichqs!\n"
505 stmfd sp!, {r4-r7, lr}
510 /* Store all the registers in the process's pcb */
511 add r2, r0, #(PCB_R8)
515 * vfp_store will clear pcpu->pc_vfpcthread, save
516 * registers and state, and modify the control as needed.
517 * a future exception will bounce the backup settings in the fp unit.
520 ldr r4, [r7, #(PC_VFPCTHREAD)] /* vfp thread */
521 ldr r2, [r7, #(PC_CURTHREAD)] /* current thread */
525 ldr r2, [r7, #(PC_CPU)] /* last used on this cpu? */
526 ldr r3, [r0, #(PCB_VFPCPU)]
528 bne 1f /* no. these values are stale */
530 add r0, r0, #(PCB_VFPSTATE)
531 bl _C_LABEL(vfp_store)
535 ldmfd sp!, {r4-r7, pc}
538 ENTRY(fork_trampoline)
539 STOP_UNWINDING /* Can't unwind beyond the thread enty point */
544 bl _C_LABEL(fork_exit)
547 orr r0, r0, #(I32_bit|F32_bit)
552 movs pc, lr /* Exit */