2 * Copyright (c) 2006 M. Warner Losh. All rights reserved.
3 * Copyright (c) 2010 Greg Ansley. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/kernel.h>
33 #include <sys/malloc.h>
34 #include <sys/module.h>
37 #include <sys/resource.h>
39 #include <sys/timetc.h>
41 #include <machine/bus.h>
42 #include <machine/cpu.h>
43 #include <machine/cpufunc.h>
44 #include <machine/resource.h>
45 #include <machine/frame.h>
46 #include <machine/intr.h>
47 #include <arm/at91/at91reg.h>
48 #include <arm/at91/at91var.h>
50 #include <arm/at91/at91_pmcreg.h>
51 #include <arm/at91/at91_pmcvar.h>
53 static struct at91_pmc_softc {
54 bus_space_tag_t sc_st;
55 bus_space_handle_t sc_sh;
56 struct resource *mem_res; /* Memory resource */
60 static uint32_t pllb_init;
62 MALLOC_DECLARE(M_PMC);
63 MALLOC_DEFINE(M_PMC, "at91_pmc_clocks", "AT91 PMC Clock descriptors");
65 #define AT91_PMC_BASE 0xffffc00
67 static void at91_pmc_set_pllb_mode(struct at91_pmc_clock *, int);
68 static void at91_pmc_set_upll_mode(struct at91_pmc_clock *, int);
69 static void at91_pmc_set_sys_mode(struct at91_pmc_clock *, int);
70 static void at91_pmc_set_periph_mode(struct at91_pmc_clock *, int);
71 static void at91_pmc_clock_alias(const char *name, const char *alias);
73 static struct at91_pmc_clock slck = {
74 .name = "slck", /* 32,768 Hz slow clock */
82 * NOTE: Clocks for "ordinary peripheral" devices e.g. spi0, udp0, uhp0 etc.
83 * are now created automatically. Only "system" clocks need be defined here.
85 static struct at91_pmc_clock main_ck = {
86 .name = "main", /* Main clock */
90 .pmc_mask = PMC_IER_MOSCS,
93 static struct at91_pmc_clock plla = {
94 .name = "plla", /* PLLA Clock, used for CPU clocking */
100 .pmc_mask = PMC_IER_LOCKA,
103 static struct at91_pmc_clock pllb = {
104 .name = "pllb", /* PLLB Clock, used for USB functions */
110 .pmc_mask = PMC_IER_LOCKB,
111 .set_mode = &at91_pmc_set_pllb_mode,
114 /* Used by USB on at91sam9g45 */
115 static struct at91_pmc_clock upll = {
116 .name = "upll", /* UTMI PLL, used for USB functions on 9G45 family */
122 .pmc_mask = (1 << 6),
123 .set_mode = &at91_pmc_set_upll_mode,
126 static struct at91_pmc_clock udpck = {
129 .pmc_mask = PMC_SCER_UDP,
130 .set_mode = at91_pmc_set_sys_mode
133 static struct at91_pmc_clock uhpck = {
136 .pmc_mask = PMC_SCER_UHP,
137 .set_mode = at91_pmc_set_sys_mode
140 static struct at91_pmc_clock mck = {
141 .name = "mck", /* Master (Peripheral) Clock */
142 .pmc_mask = PMC_IER_MCKRDY,
146 static struct at91_pmc_clock cpu = {
147 .name = "cpu", /* CPU Clock */
149 .pmc_mask = PMC_SCER_PCK,
153 /* "+32" or the automatic peripheral clocks */
154 static struct at91_pmc_clock *clock_list[16+32] = {
166 static inline uint32_t
167 RD4(struct at91_pmc_softc *sc, bus_size_t off)
171 uint32_t *p = (uint32_t *)(AT91_BASE + AT91_PMC_BASE + off);
175 return (bus_read_4(sc->mem_res, off));
179 WR4(struct at91_pmc_softc *sc, bus_size_t off, uint32_t val)
183 uint32_t *p = (uint32_t *)(AT91_BASE + AT91_PMC_BASE + off);
187 bus_write_4(sc->mem_res, off, val);
191 * The following is unused currently since we don't ever set the PLLA
192 * frequency of the device. If we did, we'd have to also pay attention
193 * to the ICPLLA bit in the PMC_PLLICPR register for frequencies lower
194 * than ~600MHz, which the PMC code doesn't do right now.
197 at91_pmc_800mhz_plla_outb(int freq)
202 * Set OUTA, per the data sheet. See Table 46-16 titled
203 * PLLA Frequency Regarding ICPLLA and OUTA in the SAM9X25 doc,
204 * Table 46-17 in the SAM9G20 doc, or Table 46-16 in the SAM9G45 doc.
205 * Note: the frequencies overlap by 5MHz, so we add 3 here to
206 * center shoot the transition.
209 freq /= 1000000; /* MHz */
212 freq += 3; /* Allow for overlap. */
213 outa = 3 - ((freq / 50) & 3); /* 750 / 50 = 7, see table */
214 return (1 << 29)| (outa << 14);
218 at91_pmc_800mhz_pllb_outb(int freq)
225 at91_pmc_set_pllb_mode(struct at91_pmc_clock *clk, int on)
227 struct at91_pmc_softc *sc = pmc_softc;
230 value = on ? pllb_init : 0;
233 * Only write to the register if the value is changing. Besides being
234 * good common sense, this works around RM9200 Errata #26 (CKGR_PLL[AB]R
235 * must not be written with the same value currently in the register).
237 if (RD4(sc, CKGR_PLLBR) != value) {
238 WR4(sc, CKGR_PLLBR, value);
239 while (on && (RD4(sc, PMC_SR) & PMC_IER_LOCKB) != PMC_IER_LOCKB)
245 at91_pmc_set_upll_mode(struct at91_pmc_clock *clk, int on)
247 struct at91_pmc_softc *sc = pmc_softc;
252 value = CKGR_UCKR_UPLLEN | CKGR_UCKR_BIASEN;
256 WR4(sc, CKGR_UCKR, RD4(sc, CKGR_UCKR) | value);
257 while ((RD4(sc, PMC_SR) & PMC_IER_LOCKU) != on)
260 WR4(sc, PMC_USB, PMC_USB_USBDIV(9) | PMC_USB_USBS);
261 WR4(sc, PMC_SCER, PMC_SCER_UHP_SAM9);
265 at91_pmc_set_sys_mode(struct at91_pmc_clock *clk, int on)
267 struct at91_pmc_softc *sc = pmc_softc;
269 WR4(sc, on ? PMC_SCER : PMC_SCDR, clk->pmc_mask);
271 while ((RD4(sc, PMC_SCSR) & clk->pmc_mask) != clk->pmc_mask)
274 while ((RD4(sc, PMC_SCSR) & clk->pmc_mask) == clk->pmc_mask)
279 at91_pmc_set_periph_mode(struct at91_pmc_clock *clk, int on)
281 struct at91_pmc_softc *sc = pmc_softc;
283 WR4(sc, on ? PMC_PCER : PMC_PCDR, clk->pmc_mask);
285 while ((RD4(sc, PMC_PCSR) & clk->pmc_mask) != clk->pmc_mask)
288 while ((RD4(sc, PMC_PCSR) & clk->pmc_mask) == clk->pmc_mask)
292 struct at91_pmc_clock *
293 at91_pmc_clock_add(const char *name, uint32_t irq,
294 struct at91_pmc_clock *parent)
296 struct at91_pmc_clock *clk;
299 clk = malloc(sizeof(*clk), M_PMC, M_NOWAIT | M_ZERO);
303 buflen = strlen(name) + 1;
304 clk->name = malloc(buflen, M_PMC, M_NOWAIT);
305 if (clk->name == NULL)
308 strlcpy(clk->name, name, buflen);
309 clk->pmc_mask = 1 << irq;
310 clk->set_mode = &at91_pmc_set_periph_mode;
314 clk->parent = parent;
316 for (i = 0; i < sizeof(clock_list) / sizeof(clock_list[0]); i++) {
317 if (clock_list[i] == NULL) {
324 if (clk->name != NULL)
325 free(clk->name, M_PMC);
329 panic("could not allocate pmc clock '%s'", name);
334 at91_pmc_clock_alias(const char *name, const char *alias)
336 struct at91_pmc_clock *clk, *alias_clk;
338 clk = at91_pmc_clock_ref(name);
340 alias_clk = at91_pmc_clock_add(alias, 0, clk->parent);
342 if (clk && alias_clk) {
343 alias_clk->hz = clk->hz;
344 alias_clk->pmc_mask = clk->pmc_mask;
345 alias_clk->set_mode = clk->set_mode;
349 struct at91_pmc_clock *
350 at91_pmc_clock_ref(const char *name)
354 for (i = 0; i < sizeof(clock_list) / sizeof(clock_list[0]); i++) {
355 if (clock_list[i] == NULL)
357 if (strcmp(name, clock_list[i]->name) == 0)
358 return (clock_list[i]);
365 at91_pmc_clock_deref(struct at91_pmc_clock *clk)
372 at91_pmc_clock_enable(struct at91_pmc_clock *clk)
377 /* XXX LOCKING? XXX */
379 at91_pmc_clock_enable(clk->parent);
380 if (clk->refcnt++ == 0 && clk->set_mode)
381 clk->set_mode(clk, 1);
385 at91_pmc_clock_disable(struct at91_pmc_clock *clk)
390 /* XXX LOCKING? XXX */
391 if (--clk->refcnt == 0 && clk->set_mode)
392 clk->set_mode(clk, 0);
394 at91_pmc_clock_disable(clk->parent);
398 at91_pmc_pll_rate(struct at91_pmc_clock *clk, uint32_t reg)
400 uint32_t mul, div, freq;
402 freq = clk->parent->hz;
403 div = (reg >> clk->pll_div_shift) & clk->pll_div_mask;
404 mul = (reg >> clk->pll_mul_shift) & clk->pll_mul_mask;
407 printf("pll = (%d / %d) * %d = %d\n",
408 freq, div, mul + 1, (freq/div) * (mul+1));
411 if (div != 0 && mul != 0) {
422 at91_pmc_pll_calc(struct at91_pmc_clock *clk, uint32_t out_freq)
424 uint32_t i, div = 0, mul = 0, diff = 1 << 30;
426 unsigned ret = 0x3e00;
428 if (out_freq > clk->pll_max_out)
431 for (i = 1; i < 256; i++) {
433 uint32_t input, mul1;
435 input = clk->parent->hz / i;
436 if (input < clk->pll_min_in)
438 if (input > clk->pll_max_in)
441 mul1 = out_freq / input;
442 if (mul1 > (clk->pll_mul_mask + 1))
447 diff1 = out_freq - input * mul1;
458 if (diff > (out_freq >> PMC_PLL_SHIFT_TOL))
461 if (clk->set_outb != NULL)
462 ret |= clk->set_outb(out_freq);
465 ((mul - 1) << clk->pll_mul_shift) |
466 (div << clk->pll_div_shift));
471 #if !defined(AT91C_MAIN_CLOCK)
472 static const unsigned int at91_main_clock_tbl[] = {
473 3000000, 3276800, 3686400, 3840000, 4000000,
474 4433619, 4915200, 5000000, 5242880, 6000000,
475 6144000, 6400000, 6553600, 7159090, 7372800,
476 7864320, 8000000, 9830400, 10000000, 11059200,
477 12000000, 12288000, 13560000, 14318180, 14745600,
478 16000000, 17344700, 18432000, 20000000
480 #define MAIN_CLOCK_TBL_LEN (sizeof(at91_main_clock_tbl) / sizeof(*at91_main_clock_tbl))
484 at91_pmc_sense_main_clock(void)
486 #if !defined(AT91C_MAIN_CLOCK)
487 unsigned int ckgr_val;
488 unsigned int diff, matchdiff, freq;
491 ckgr_val = (RD4(NULL, CKGR_MCFR) & CKGR_MCFR_MAINF_MASK) << 11;
494 * Clocks up to 50MHz can be connected to some models. If
495 * the frequency is >= 21MHz, assume that the slow clock can
496 * measure it correctly, and that any error can be adequately
497 * compensated for by roudning to the nearest 500Hz. Users
498 * with fast, or odd-ball clocks will need to set
499 * AT91C_MAIN_CLOCK in the kernel config file.
501 if (ckgr_val >= 21000000)
502 return ((ckgr_val + 250) / 500 * 500);
505 * Try to find the standard frequency that match best.
507 freq = at91_main_clock_tbl[0];
508 matchdiff = abs(ckgr_val - at91_main_clock_tbl[0]);
509 for (i = 1; i < MAIN_CLOCK_TBL_LEN; i++) {
510 diff = abs(ckgr_val - at91_main_clock_tbl[i]);
511 if (diff < matchdiff) {
512 freq = at91_main_clock_tbl[i];
518 return (AT91C_MAIN_CLOCK);
523 at91_pmc_init_clock(void)
525 struct at91_pmc_softc *sc = NULL;
526 unsigned int main_clock;
530 main_clock = at91_pmc_sense_main_clock();
532 if (at91_is_sam9() || at91_is_sam9xe()) {
533 uhpck.pmc_mask = PMC_SCER_UHP_SAM9;
534 udpck.pmc_mask = PMC_SCER_UDP_SAM9;
537 /* There is no pllb on AT91SAM9G45 */
538 if (at91_cpu_is(AT91_T_SAM9G45)) {
539 uhpck.parent = &upll;
540 uhpck.pmc_mask = PMC_SCER_UHP_SAM9;
543 mckr = RD4(sc, PMC_MCKR);
544 main_ck.hz = main_clock;
547 * Note: this means outa calc code for plla never used since
548 * we never change it. If we did, we'd also have to mind
549 * ICPLLA to get the charge pump current right.
551 at91_pmc_pll_rate(&plla, RD4(sc, CKGR_PLLAR));
553 if (at91_cpu_is(AT91_T_SAM9G45) && (mckr & PMC_MCKR_PLLADIV2))
557 * Initialize the usb clock. This sets up pllb, but disables the
558 * actual clock. XXX except for the if 0 :(
560 if (!at91_cpu_is(AT91_T_SAM9G45)) {
561 pllb_init = at91_pmc_pll_calc(&pllb, 48000000 * 2) | 0x10000000;
562 at91_pmc_pll_rate(&pllb, pllb_init);
564 /* Turn off USB clocks */
565 at91_pmc_set_periph_mode(&ohci_clk, 0);
566 at91_pmc_set_periph_mode(&udc_clk, 0);
570 if (at91_is_rm92()) {
571 WR4(sc, PMC_SCDR, PMC_SCER_UHP | PMC_SCER_UDP);
572 WR4(sc, PMC_SCER, PMC_SCER_MCKUDP);
574 WR4(sc, PMC_SCDR, PMC_SCER_UHP_SAM9 | PMC_SCER_UDP_SAM9);
577 * MCK and PCU derive from one of the primary clocks. Initialize
580 mck.parent = clock_list[mckr & 0x3];
581 mck.parent->refcnt++;
583 cpu.hz = mck.hz = mck.parent->hz /
584 (1 << ((mckr & PMC_MCKR_PRES_MASK) >> 2));
586 mdiv = (mckr & PMC_MCKR_MDIV_MASK) >> 8;
587 if (at91_is_sam9() || at91_is_sam9xe()) {
589 * On AT91SAM9G45 when mdiv == 3 we need to divide
590 * MCK by 3 but not, for example, on 9g20.
592 if (!at91_cpu_is(AT91_T_SAM9G45) || mdiv <= 2)
597 mck.hz /= (1 + mdiv);
599 /* Only found on SAM9G20 */
600 if (at91_cpu_is(AT91_T_SAM9G20))
601 cpu.hz /= (mckr & PMC_MCKR_PDIV) ? 2 : 1;
603 at91_master_clock = mck.hz;
605 /* These clocks refrenced by "special" names */
606 at91_pmc_clock_alias("ohci0", "ohci_clk");
607 at91_pmc_clock_alias("udp0", "udp_clk");
609 /* Turn off "Progamable" clocks */
610 WR4(sc, PMC_SCDR, PMC_SCER_PCK0 | PMC_SCER_PCK1 | PMC_SCER_PCK2 |
613 /* XXX kludge, turn on all peripherals */
614 WR4(sc, PMC_PCER, 0xffffffff);
616 /* Disable all interrupts for PMC */
617 WR4(sc, PMC_IDR, 0xffffffff);
621 at91_pmc_deactivate(device_t dev)
623 struct at91_pmc_softc *sc;
625 sc = device_get_softc(dev);
626 bus_generic_detach(sc->dev);
628 bus_release_resource(dev, SYS_RES_IOPORT,
629 rman_get_rid(sc->mem_res), sc->mem_res);
634 at91_pmc_activate(device_t dev)
636 struct at91_pmc_softc *sc;
639 sc = device_get_softc(dev);
641 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
643 if (sc->mem_res == NULL)
647 at91_pmc_deactivate(dev);
652 at91_pmc_probe(device_t dev)
655 device_set_desc(dev, "PMC");
660 at91_pmc_attach(device_t dev)
664 pmc_softc = device_get_softc(dev);
665 pmc_softc->dev = dev;
666 if ((err = at91_pmc_activate(dev)) != 0)
670 * Configure main clock frequency.
672 at91_pmc_init_clock();
675 * Display info about clocks previously computed
678 "Primary: %d Hz PLLA: %d MHz CPU: %d MHz MCK: %d MHz\n",
681 cpu.hz / 1000000, mck.hz / 1000000);
686 static device_method_t at91_pmc_methods[] = {
687 DEVMETHOD(device_probe, at91_pmc_probe),
688 DEVMETHOD(device_attach, at91_pmc_attach),
692 static driver_t at91_pmc_driver = {
695 sizeof(struct at91_pmc_softc),
697 static devclass_t at91_pmc_devclass;
699 DRIVER_MODULE(at91_pmc, atmelarm, at91_pmc_driver, at91_pmc_devclass, NULL,