2 * Copyright (c) 2005 Olivier Houchard. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/kernel.h>
32 #include <sys/module.h>
35 #include <sys/resource.h>
37 #include <sys/timetc.h>
38 #include <sys/watchdog.h>
40 #include <machine/bus.h>
41 #include <machine/cpu.h>
42 #include <machine/cpufunc.h>
43 #include <machine/resource.h>
44 #include <machine/frame.h>
45 #include <machine/intr.h>
46 #include <arm/at91/at91var.h>
47 #include <arm/at91/at91_streg.h>
48 #include <arm/at91/at91rm92reg.h>
50 static struct at91_st_softc {
51 struct resource * sc_irq_res;
52 struct resource * sc_mem_res;
54 eventhandler_tag sc_wet; /* watchdog event handler tag */
57 static inline uint32_t
61 if (timer_softc == NULL) {
62 uint32_t *p = (uint32_t *)(AT91_BASE + AT91RM92_ST_BASE + off);
67 return (bus_read_4(timer_softc->sc_mem_res, off));
71 WR4(bus_size_t off, uint32_t val)
74 if (timer_softc == NULL) {
75 uint32_t *p = (uint32_t *)(AT91_BASE + AT91RM92_ST_BASE + off);
80 bus_write_4(timer_softc->sc_mem_res, off, val);
83 static void at91_st_watchdog(void *, u_int, int *);
84 static void at91_st_initclocks(device_t , struct at91_st_softc *);
93 } while (cur1 != cur2);
97 static unsigned at91_st_get_timecount(struct timecounter *tc);
99 static struct timecounter at91_st_timecounter = {
100 at91_st_get_timecount, /* get_timecount */
101 NULL, /* no poll_pps */
102 0xfffffu, /* counter_mask */
103 32768, /* frequency */
104 "AT91RM9200 timer", /* name */
109 clock_intr(void *arg)
111 struct trapframe *fp = arg;
113 /* The interrupt is shared, so we have to make sure it's for us. */
114 if (RD4(ST_SR) & ST_SR_PITS) {
115 hardclock(TRAPF_USERMODE(fp), TRAPF_PC(fp));
116 return (FILTER_HANDLED);
118 return (FILTER_STRAY);
124 uint32_t start, end, cur;
127 n = (n * 1000) / 32768;
130 end = (start + n) & ST_CRTR_MASK;
133 while (cur >= start || cur < end)
142 at91_st_cpu_reset(void)
145 * Reset the CPU by programmig the watchdog timer to reset the
146 * CPU after 128 'slow' clocks, or about ~4ms. Loop until
147 * the reset happens for safety.
149 WR4(ST_WDMR, ST_WDMR_RSTEN | 2);
150 WR4(ST_CR, ST_CR_WDRST);
156 at91_st_probe(device_t dev)
159 device_set_desc(dev, "ST");
164 at91_st_deactivate(device_t dev)
166 struct at91_st_softc *sc = timer_softc;
169 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
170 sc->sc_intrhand = NULL;
173 bus_release_resource(dev, SYS_RES_IRQ,
174 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res);
175 sc->sc_irq_res = NULL;
178 bus_release_resource(dev, SYS_RES_MEMORY,
179 rman_get_rid(sc->sc_mem_res), sc->sc_mem_res);
180 sc->sc_mem_res = NULL;
184 at91_st_activate(device_t dev)
188 struct at91_st_softc *sc = timer_softc;
191 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
194 if (sc->sc_mem_res == NULL)
196 /* Disable all interrupts */
197 WR4(ST_IDR, 0xffffffff);
199 /* The system timer shares the system irq (1) */
201 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
202 RF_ACTIVE | RF_SHAREABLE);
203 if (sc->sc_irq_res == NULL) {
204 printf("Unable to allocate irq for the system timer");
207 err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_CLK, clock_intr,
208 NULL, NULL, &sc->sc_intrhand);
211 at91_st_deactivate(dev);
216 at91_st_attach(device_t dev)
220 timer_softc = device_get_softc(dev);
221 err = at91_st_activate(dev);
225 timer_softc->sc_wet = EVENTHANDLER_REGISTER(watchdog_list,
226 at91_st_watchdog, dev, 0);
229 "watchdog registered, timeout intervall max. 64 sec\n");
231 at91_st_initclocks(dev, timer_softc);
235 static device_method_t at91_st_methods[] = {
236 DEVMETHOD(device_probe, at91_st_probe),
237 DEVMETHOD(device_attach, at91_st_attach),
241 static driver_t at91_st_driver = {
244 sizeof(struct at91_st_softc),
246 static devclass_t at91_st_devclass;
248 DRIVER_MODULE(at91_st, atmelarm, at91_st_driver, at91_st_devclass, 0, 0);
251 at91_st_get_timecount(struct timecounter *tc)
257 * t below is in a weird unit. The watchdog is set to 2^t
258 * nanoseconds. Since our watchdog timer can't really do that too
259 * well, we approximate it by assuming that the timeout interval for
260 * the lsb is 2^22 ns, which is 4.194ms. This is an overestimation of
261 * the actual time (3.906ms), but close enough for watchdogging.
262 * These approximations, though a violation of the spec, improve the
263 * performance of the application which typically specifies things as
264 * WD_TO_32SEC. In that last case, we'd wait 32s before the wdog
265 * reset. The spec says we should wait closer to 34s, but given how
266 * it is likely to be used, and the extremely coarse nature time
267 * interval, I think this is the best solution.
270 at91_st_watchdog(void *argp, u_int cmd, int *error)
275 t = cmd & WD_INTERVAL;
276 if (t >= 22 && t <= 37) {
277 wdog = (1 << (t - 22)) | ST_WDMR_RSTEN;
283 WR4(ST_CR, ST_CR_WDRST);
287 at91_st_initclocks(device_t dev, struct at91_st_softc *sc)
292 * Real time counter increments every clock cycle, need to set before
293 * initializing clocks so that DELAY works.
296 /* disable watchdog timer */
299 rel_value = 32768 / hz;
303 device_printf(dev, "Cannot get %d Hz clock; using %dHz\n", hz,
305 hz = 32768 / rel_value;
308 WR4(ST_PIMR, rel_value);
310 /* Enable PITS interrupts. */
311 WR4(ST_IER, ST_SR_PITS);
312 tc_init(&at91_st_timecounter);