sys/arm/at91/at91sam9260reg.h

   1 /*-
   2  * Copyright (c) 2010 Greg Ansley.  All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  */
  25
  26 /* $FreeBSD$ */
  27
  28 #ifndef AT91SAM9260REG_H_
  29 #define AT91SAM9260REG_H_
  30
  31 /* Chip Specific limits */
  32 #define SAM9260_PLL_A_MIN_IN_FREQ         1000000 /*   1 Mhz */
  33 #define SAM9260_PLL_A_MAX_IN_FREQ        32000000 /*  32 Mhz */
  34 #define SAM9260_PLL_A_MIN_OUT_FREQ       80000000 /*  80 Mhz */
  35 #define SAM9260_PLL_A_MAX_OUT_FREQ      240000000 /* 240 Mhz */
  36 #define SAM9260_PLL_A_MUL_SHIFT 16
  37 #define SAM9260_PLL_A_MUL_MASK 0x3FF
  38 #define SAM9260_PLL_A_DIV_SHIFT 0
  39 #define SAM9260_PLL_A_DIV_MASK 0xFF
  40
  41 #define SAM9260_PLL_B_MIN_IN_FREQ         1000000 /*   1 Mhz */
  42 #define SAM9260_PLL_B_MAX_IN_FREQ         5000000 /*   5 Mhz */
  43 #define SAM9260_PLL_B_MIN_OUT_FREQ       70000000 /*  70 Mhz */
  44 #define SAM9260_PLL_B_MAX_OUT_FREQ      130000000 /* 130 Mhz */
  45 #define SAM9260_PLL_B_MUL_SHIFT 16
  46 #define SAM9260_PLL_B_MUL_MASK 0x3FF
  47 #define SAM9260_PLL_B_DIV_SHIFT 0
  48 #define SAM9260_PLL_B_DIV_MASK 0xFF
  49
  50 /*
  51  * Memory map, from datasheet :
  52  * 0x00000000 - 0x0ffffffff : Internal Memories
  53  * 0x10000000 - 0x1ffffffff : Chip Select 0
  54  * 0x20000000 - 0x2ffffffff : Chip Select 1
  55  * 0x30000000 - 0x3ffffffff : Chip Select 2
  56  * 0x40000000 - 0x4ffffffff : Chip Select 3
  57  * 0x50000000 - 0x5ffffffff : Chip Select 4
  58  * 0x60000000 - 0x6ffffffff : Chip Select 5
  59  * 0x70000000 - 0x7ffffffff : Chip Select 6
  60  * 0x80000000 - 0x8ffffffff : Chip Select 7
  61  * 0x90000000 - 0xeffffffff : Undefined (Abort)
  62  * 0xf0000000 - 0xfffffffff : Peripherals
  63  */
  64
  65 #define AT91_CHIPSELECT_0 0x10000000
  66 #define AT91_CHIPSELECT_1 0x20000000
  67 #define AT91_CHIPSELECT_2 0x30000000
  68 #define AT91_CHIPSELECT_3 0x40000000
  69 #define AT91_CHIPSELECT_4 0x50000000
  70 #define AT91_CHIPSELECT_5 0x60000000
  71 #define AT91_CHIPSELECT_6 0x70000000
  72 #define AT91_CHIPSELECT_7 0x80000000
  73
  74
  75 #define AT91SAM9260_EMAC_BASE 0xffc4000
  76 #define AT91SAM9260_EMAC_SIZE 0x4000
  77
  78 #define AT91SAM9260_RSTC_BASE   0xffffd00
  79 #define AT91SAM9260_RSTC_SIZE   0x10
  80
  81 #define RSTC_CR                 0
  82 #define RSTC_PROCRST            (1 << 0)
  83 #define RSTC_PERRST             (1 << 2)
  84 #define RSTC_KEY                (0xa5 << 24)
  85
  86 /* USART*/
  87
  88 #define AT91SAM9260_USART_SIZE  0x4000
  89 #define AT91SAM9260_USART0_BASE 0xffb0000
  90 #define AT91SAM9260_USART0_PDC  0xffb0100
  91 #define AT91SAM9260_USART0_SIZE AT91SAM9260_USART_SIZE
  92 #define AT91SAM9260_USART1_BASE 0xffb4000
  93 #define AT91SAM9260_USART1_PDC  0xffb4100
  94 #define AT91SAM9260_USART1_SIZE AT91SAM9260_USART_SIZE
  95 #define AT91SAM9260_USART2_BASE 0xffb8000
  96 #define AT91SAM9260_USART2_PDC  0xffb8100
  97 #define AT91SAM9260_USART2_SIZE AT91SAM9260_USART_SIZE
  98 #define AT91SAM9260_USART3_BASE 0xffd0000
  99 #define AT91SAM9260_USART3_PDC  0xffd0100
 100 #define AT91SAM9260_USART3_SIZE AT91SAM9260_USART_SIZE
 101 #define AT91SAM9260_USART4_BASE 0xffd4000
 102 #define AT91SAM9260_USART4_PDC  0xffd4100
 103 #define AT91SAM9260_USART4_SIZE AT91SAM9260_USART_SIZE
 104 #define AT91SAM9260_USART5_BASE 0xffd8000
 105 #define AT91SAM9260_USART5_PDC  0xffd8100
 106 #define AT91SAM9260_USART5_SIZE AT91SAM9260_USART_SIZE
 107
 108 /*TC*/
 109 #define AT91SAM9260_TC0_BASE    0xffa0000
 110 #define AT91SAM9260_TC0_SIZE    0x4000
 111 #define AT91SAM9260_TC0C0_BASE  0xffa0000
 112 #define AT91SAM9260_TC0C1_BASE  0xffa0040
 113 #define AT91SAM9260_TC0C2_BASE  0xffa0080
 114
 115 #define AT91SAM9260_TC1_BASE    0xffdc000
 116 #define AT91SAM9260_TC1_SIZE    0x4000
 117
 118 /*SPI*/
 119
 120 #define AT91SAM9260_SPI0_BASE   0xffc8000
 121
 122 #define AT91SAM9260_SPI0_SIZE   0x4000
 123 #define AT91SAM9260_IRQ_SPI0    12
 124
 125 #define AT91SAM9260_SPI1_BASE   0xffcc000
 126 #define AT91SAM9260_SPI1_SIZE   0x4000
 127 #define AT91SAM9260_IRQ_SPI1    13
 128
 129 /* System Registers */
 130 #define AT91SAM9260_SYS_BASE    0xffff000
 131 #define AT91SAM9260_SYS_SIZE    0x1000
 132
 133 #define AT91SAM9260_MATRIX_BASE 0xfffee00
 134 #define AT91SAM9260_MATRIX_SIZE 0x1000
 135 #define AT91SAM9260_EBICSA      0x011C
 136
 137 #define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA     (1 << 3)
 138
 139 #define AT91SAM9260_DBGU_BASE   0xffff200
 140 #define AT91SAM9260_DBGU_SIZE   0x200
 141
 142 /*
 143  * PIO
 144  */
 145 #define AT91SAM9260_PIOA_BASE   0xffff400
 146 #define AT91SAM9260_PIOA_SIZE   0x200
 147 #define AT91SAM9260_PIOB_BASE   0xffff600
 148 #define AT91SAM9260_PIOB_SIZE   0x200
 149 #define AT91SAM9260_PIOC_BASE   0xffff800
 150 #define AT91SAM9260_PIOC_SIZE   0x200
 151
 152 #define AT91RM92_PMC_BASE       0xffffc00
 153 #define AT91RM92_PMC_SIZE       0x100
 154 /* IRQs : */
 155 /*
 156  * 0: AIC
 157  * 1: System peripheral (System timer, RTC, DBGU)
 158  * 2: PIO Controller A
 159  * 3: PIO Controller B
 160  * 4: PIO Controller C
 161  * 5: ADC
 162  * 6: USART 0
 163  * 7: USART 1
 164  * 8: USART 2
 165  * 9: MMC Interface
 166  * 10: USB device port
 167  * 11: Two-wirte interface
 168  * 12: SPI 0
 169  * 13: SPI 1
 170  * 14: SSC
 171  * 15: - (reserved)
 172  * 16: - (reserved)
 173  * 17: Timer Counter 0
 174  * 18: Timer Counter 1
 175  * 19: Timer Counter 2
 176  * 20: USB Host port
 177  * 21: EMAC
 178  * 22: ISI
 179  * 23: USART 3
 180  * 24: USART 4
 181  * 25: USART 2
 182  * 26: Timer Counter 3
 183  * 27: Timer Counter 4
 184  * 28: Timer Counter 5
 185  * 29: AIC IRQ0
 186  * 30: AIC IRQ1
 187  * 31: AIC IRQ2
 188  */
 189
 190 #define AT91SAM9260_IRQ_SYSTEM  1
 191 #define AT91SAM9260_IRQ_PIOA    2
 192 #define AT91SAM9260_IRQ_PIOB    3
 193 #define AT91SAM9260_IRQ_PIOC    4
 194 #define AT91SAM9260_IRQ_USART0  6
 195 #define AT91SAM9260_IRQ_USART1  7
 196 #define AT91SAM9260_IRQ_USART2  8
 197 #define AT91SAM9260_IRQ_MCI     9
 198 #define AT91SAM9260_IRQ_UDP     10
 199 #define AT91SAM9260_IRQ_TWI     11
 200 #define AT91SAM9260_IRQ_SPI0    12
 201 #define AT91SAM9260_IRQ_SPI1    13
 202 #define AT91SAM9260_IRQ_SSC0    14
 203 #define AT91SAM9260_IRQ_SSC1    15
 204 #define AT91SAM9260_IRQ_SSC2    16
 205 #define AT91SAM9260_IRQ_TC0     17
 206 #define AT91SAM9260_IRQ_TC1     18
 207 #define AT91SAM9260_IRQ_TC2     19
 208 #define AT91SAM9260_IRQ_UHP     20
 209 #define AT91SAM9260_IRQ_EMAC    21
 210 #define AT91SAM9260_IRQ_USART3  23
 211 #define AT91SAM9260_IRQ_USART4  24
 212 #define AT91SAM9260_IRQ_USART5  25
 213 #define AT91SAM9260_IRQ_AICBASE 29
 214
 215 /* Alias */
 216 #define AT91SAM9260_IRQ_DBGU    AT91SAM9260_IRQ_SYSTEM
 217 #define AT91SAM9260_IRQ_PMC     AT91SAM9260_IRQ_SYSTEM
 218 #define AT91SAM9260_IRQ_WDT     AT91SAM9260_IRQ_SYSTEM
 219 #define AT91SAM9260_IRQ_PIT     AT91SAM9260_IRQ_SYSTEM
 220 #define AT91SAM9260_IRQ_RSTC    AT91SAM9260_IRQ_SYSTEM
 221 #define AT91SAM9260_IRQ_OHCI    AT91SAM9260_IRQ_UHP
 222 #define AT91SAM9260_IRQ_NAND    (-1)
 223
 224 #define AT91SAM9260_AIC_BASE    0xffff000
 225 #define AT91SAM9260_AIC_SIZE    0x200
 226
 227 /* Timer */
 228
 229 #define AT91SAM9260_WDT_BASE    0xffffd40
 230 #define AT91SAM9260_WDT_SIZE    0x10
 231
 232 #define AT91SAM9260_PIT_BASE    0xffffd30
 233 #define AT91SAM9260_PIT_SIZE    10
 234
 235 #define AT91SAM9260_SMC_BASE    0xfffec00
 236 #define AT91SAM9260_SMC_SIZE    0x200
 237
 238 #define AT91SAM9260_PMC_BASE    0xffffc00
 239 #define AT91SAM9260_PMC_SIZE    0x100
 240
 241 #define AT91SAM9260_UDP_BASE    0xffa4000
 242 #define AT91SAM9260_UDP_SIZE    0x4000
 243
 244 #define AT91SAM9260_MCI_BASE    0xffa8000
 245 #define AT91SAM9260_MCI_SIZE    0x4000
 246
 247 #define AT91SAM9260_TWI_BASE    0xffaC000
 248 #define AT91SAM9260_TWI_SIZE    0x4000
 249
 250 /* XXX Needs to be carfully coordinated with
 251  * other * soc's so phyical and vm address
 252  * mapping are unique. XXX
 253  */
 254 #define AT91SAM9260_OHCI_BASE     0xdfc00000
 255 #define AT91SAM9260_OHCI_PA_BASE  0x00500000
 256 #define AT91SAM9260_OHCI_SIZE     0x00100000
 257
 258 #define AT91SAM9260_NAND_BASE     0xe0000000
 259 #define AT91SAM9260_NAND_PA_BASE  0x40000000
 260 #define AT91SAM9260_NAND_SIZE     0x10000000
 261
 262
 263 /* SDRAMC */
 264 #define AT91SAM9260_SDRAMC_BASE 0xfffea00
 265 #define AT91SAM9260_SDRAMC_MR   0x00
 266 #define AT91SAM9260_SDRAMC_MR_MODE_NORMAL       0
 267 #define AT91SAM9260_SDRAMC_MR_MODE_NOP  1
 268 #define AT91SAM9260_SDRAMC_MR_MODE_PRECHARGE 2
 269 #define AT91SAM9260_SDRAMC_MR_MODE_LOAD_MODE_REGISTER 3
 270 #define AT91SAM9260_SDRAMC_MR_MODE_REFRESH      4
 271 #define AT91SAM9260_SDRAMC_TR   0x04
 272 #define AT91SAM9260_SDRAMC_CR   0x08
 273 #define AT91SAM9260_SDRAMC_CR_NC_8              0x0
 274 #define AT91SAM9260_SDRAMC_CR_NC_9              0x1
 275 #define AT91SAM9260_SDRAMC_CR_NC_10     0x2
 276 #define AT91SAM9260_SDRAMC_CR_NC_11     0x3
 277 #define AT91SAM9260_SDRAMC_CR_NC_MASK   0x00000003
 278 #define AT91SAM9260_SDRAMC_CR_NR_11     0x0
 279 #define AT91SAM9260_SDRAMC_CR_NR_12     0x4
 280 #define AT91SAM9260_SDRAMC_CR_NR_13     0x8
 281 #define AT91SAM9260_SDRAMC_CR_NR_RES    0xc
 282 #define AT91SAM9260_SDRAMC_CR_NR_MASK   0x0000000c
 283 #define AT91SAM9260_SDRAMC_CR_NB_2              0x00
 284 #define AT91SAM9260_SDRAMC_CR_NB_4              0x10
 285 #define AT91SAM9260_SDRAMC_CR_DBW_16            0x80
 286 #define AT91SAM9260_SDRAMC_CR_NB_MASK   0x00000010
 287 #define AT91SAM9260_SDRAMC_CR_NCAS_MASK 0x00000060
 288 #define AT91SAM9260_SDRAMC_CR_TWR_MASK  0x00000780
 289 #define AT91SAM9260_SDRAMC_CR_TRC_MASK  0x00007800
 290 #define AT91SAM9260_SDRAMC_CR_TRP_MASK  0x00078000
 291 #define AT91SAM9260_SDRAMC_CR_TRCD_MASK 0x00780000
 292 #define AT91SAM9260_SDRAMC_CR_TRAS_MASK 0x07800000
 293 #define AT91SAM9260_SDRAMC_CR_TXSR_MASK 0x78000000
 294 #define AT91SAM9260_SDRAMC_HSR  0x0c
 295 #define AT91SAM9260_SDRAMC_LPR  0x10
 296 #define AT91SAM9260_SDRAMC_IER  0x14
 297 #define AT91SAM9260_SDRAMC_IDR  0x18
 298 #define AT91SAM9260_SDRAMC_IMR  0x1c
 299 #define AT91SAM9260_SDRAMC_ISR  0x20
 300 #define AT91SAM9260_SDRAMC_MDR  0x24
 301
 302 #endif /* AT91SAM9260REG_H_*/
 303