sys/arm/at91/at91sam9g20reg.h

   1 /*-
   2  * Copyright (c) 2009 Sylvestre Gallon.  All rights reserved.
   3  * Copyright (c) 2010 Greg Ansley.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 /* $FreeBSD$ */
  28
  29 #ifndef AT91SAM9G20REG_H_
  30 #define AT91SAM9G20REG_H_
  31
  32 /* Chip Specific limits */
  33 #define SAM9G20_PLL_A_MIN_IN_FREQ         2000000 /*   2 Mhz */
  34 #define SAM9G20_PLL_A_MAX_IN_FREQ        32000000 /*  32 Mhz */
  35 #define SAM9G20_PLL_A_MIN_OUT_FREQ      400000000 /* 400 Mhz */
  36 #define SAM9G20_PLL_A_MAX_OUT_FREQ      800000000 /* 800 Mhz */
  37 #define SAM9G20_PLL_A_MUL_SHIFT 16
  38 #define SAM9G20_PLL_A_MUL_MASK 0xFF
  39 #define SAM9G20_PLL_A_DIV_SHIFT 0
  40 #define SAM9G20_PLL_A_DIV_MASK 0xFF
  41
  42 #define SAM9G20_PLL_B_MIN_IN_FREQ         2000000 /*   2 Mhz */
  43 #define SAM9G20_PLL_B_MAX_IN_FREQ        32000000 /*  32 Mhz */
  44 #define SAM9G20_PLL_B_MIN_OUT_FREQ       30000000 /*  30 Mhz */
  45 #define SAM9G20_PLL_B_MAX_OUT_FREQ      100000000 /* 100 Mhz */
  46 #define SAM9G20_PLL_B_MUL_SHIFT 16
  47 #define SAM9G20_PLL_B_MUL_MASK 0x3F
  48 #define SAM9G20_PLL_B_DIV_SHIFT 0
  49 #define SAM9G20_PLL_B_DIV_MASK 0xFF
  50
  51 /*
  52  * Memory map, from datasheet :
  53  * 0x00000000 - 0x0ffffffff : Internal Memories
  54  * 0x10000000 - 0x1ffffffff : Chip Select 0
  55  * 0x20000000 - 0x2ffffffff : Chip Select 1
  56  * 0x30000000 - 0x3ffffffff : Chip Select 2
  57  * 0x40000000 - 0x4ffffffff : Chip Select 3
  58  * 0x50000000 - 0x5ffffffff : Chip Select 4
  59  * 0x60000000 - 0x6ffffffff : Chip Select 5
  60  * 0x70000000 - 0x7ffffffff : Chip Select 6
  61  * 0x80000000 - 0x8ffffffff : Chip Select 7
  62  * 0x90000000 - 0xeffffffff : Undefined (Abort)
  63  * 0xf0000000 - 0xfffffffff : Peripherals
  64  */
  65
  66 #define AT91_CHIPSELECT_0 0x10000000
  67 #define AT91_CHIPSELECT_1 0x20000000
  68 #define AT91_CHIPSELECT_2 0x30000000
  69 #define AT91_CHIPSELECT_3 0x40000000
  70 #define AT91_CHIPSELECT_4 0x50000000
  71 #define AT91_CHIPSELECT_5 0x60000000
  72 #define AT91_CHIPSELECT_6 0x70000000
  73 #define AT91_CHIPSELECT_7 0x80000000
  74
  75
  76 #define AT91SAM9G20_EMAC_BASE 0xffc4000
  77 #define AT91SAM9G20_EMAC_SIZE 0x4000
  78
  79 #define AT91SAM9G20_RSTC_BASE   0xffffd00
  80 #define AT91SAM9G20_RSTC_SIZE   0x10
  81
  82 #define RSTC_CR                 0
  83 #define RSTC_PROCRST            (1 << 0)
  84 #define RSTC_PERRST             (1 << 2)
  85 #define RSTC_KEY                (0xa5 << 24)
  86
  87 /* USART*/
  88
  89 #define AT91SAM9G20_USART_SIZE  0x4000
  90 #define AT91SAM9G20_USART0_BASE 0xffb0000
  91 #define AT91SAM9G20_USART0_PDC  0xffb0100
  92 #define AT91SAM9G20_USART0_SIZE AT91SAM9G20_USART_SIZE
  93 #define AT91SAM9G20_USART1_BASE 0xffb4000
  94 #define AT91SAM9G20_USART1_PDC  0xffb4100
  95 #define AT91SAM9G20_USART1_SIZE AT91SAM9G20_USART_SIZE
  96 #define AT91SAM9G20_USART2_BASE 0xffb8000
  97 #define AT91SAM9G20_USART2_PDC  0xffb8100
  98 #define AT91SAM9G20_USART2_SIZE AT91SAM9G20_USART_SIZE
  99 #define AT91SAM9G20_USART3_BASE 0xffd0000
 100 #define AT91SAM9G20_USART3_PDC  0xffd0100
 101 #define AT91SAM9G20_USART3_SIZE AT91SAM9G20_USART_SIZE
 102 #define AT91SAM9G20_USART4_BASE 0xffd4000
 103 #define AT91SAM9G20_USART4_PDC  0xffd4100
 104 #define AT91SAM9G20_USART4_SIZE AT91SAM9G20_USART_SIZE
 105 #define AT91SAM9G20_USART5_BASE 0xffd8000
 106 #define AT91SAM9G20_USART5_PDC  0xffd8100
 107 #define AT91SAM9G20_USART5_SIZE AT91SAM9G20_USART_SIZE
 108
 109 /*TC*/
 110 #define AT91SAM9G20_TC0_BASE    0xffa0000
 111 #define AT91SAM9G20_TC0_SIZE    0x4000
 112 #define AT91SAM9G20_TC0C0_BASE  0xffa0000
 113 #define AT91SAM9G20_TC0C1_BASE  0xffa0040
 114 #define AT91SAM9G20_TC0C2_BASE  0xffa0080
 115
 116 #define AT91SAM9G20_TC1_BASE    0xffdc000
 117 #define AT91SAM9G20_TC1_SIZE    0x4000
 118
 119 /*SPI*/
 120
 121 #define AT91SAM9G20_SPI0_BASE   0xffc8000
 122
 123 #define AT91SAM9G20_SPI0_SIZE   0x4000
 124 #define AT91SAM9G20_IRQ_SPI0    12
 125
 126 #define AT91SAM9G20_SPI1_BASE   0xffcc000
 127 #define AT91SAM9G20_SPI1_SIZE   0x4000
 128 #define AT91SAM9G20_IRQ_SPI1    13
 129
 130 /* System Registers */
 131 #define AT91SAM9G20_SYS_BASE    0xffff000
 132 #define AT91SAM9G20_SYS_SIZE    0x1000
 133
 134 #define AT91SAM9G20_MATRIX_BASE 0xfffee00
 135 #define AT91SAM9G20_MATRIX_SIZE 0x1000
 136 #define AT91SAM9G20_EBICSA      0x011C
 137
 138 #define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA     (1 << 3)
 139
 140 #define AT91SAM9G20_DBGU_BASE   0xffff200
 141 #define AT91SAM9G20_DBGU_SIZE   0x200
 142
 143 /*
 144  * PIO
 145  */
 146 #define AT91SAM9G20_PIOA_BASE   0xffff400
 147 #define AT91SAM9G20_PIOA_SIZE   0x200
 148 #define AT91SAM9G20_PIOB_BASE   0xffff600
 149 #define AT91SAM9G20_PIOB_SIZE   0x200
 150 #define AT91SAM9G20_PIOC_BASE   0xffff800
 151 #define AT91SAM9G20_PIOC_SIZE   0x200
 152
 153 #define AT91RM92_PMC_BASE       0xffffc00
 154 #define AT91RM92_PMC_SIZE       0x100
 155 /* IRQs : */
 156 /*
 157  * 0: AIC
 158  * 1: System peripheral (System timer, RTC, DBGU)
 159  * 2: PIO Controller A
 160  * 3: PIO Controller B
 161  * 4: PIO Controller C
 162  * 5: ADC
 163  * 6: USART 0
 164  * 7: USART 1
 165  * 8: USART 2
 166  * 9: MMC Interface
 167  * 10: USB device port
 168  * 11: Two-wirte interface
 169  * 12: SPI 0
 170  * 13: SPI 1
 171  * 14: SSC
 172  * 15: - (reserved)
 173  * 16: - (reserved)
 174  * 17: Timer Counter 0
 175  * 18: Timer Counter 1
 176  * 19: Timer Counter 2
 177  * 20: USB Host port
 178  * 21: EMAC
 179  * 22: ISI
 180  * 23: USART 3
 181  * 24: USART 4
 182  * 25: USART 2
 183  * 26: Timer Counter 3
 184  * 27: Timer Counter 4
 185  * 28: Timer Counter 5
 186  * 29: AIC IRQ0
 187  * 30: AIC IRQ1
 188  * 31: AIC IRQ2
 189  */
 190
 191 #define AT91SAM9G20_IRQ_SYSTEM  1
 192 #define AT91SAM9G20_IRQ_PIOA    2
 193 #define AT91SAM9G20_IRQ_PIOB    3
 194 #define AT91SAM9G20_IRQ_PIOC    4
 195 #define AT91SAM9G20_IRQ_USART0  6
 196 #define AT91SAM9G20_IRQ_USART1  7
 197 #define AT91SAM9G20_IRQ_USART2  8
 198 #define AT91SAM9G20_IRQ_MCI     9
 199 #define AT91SAM9G20_IRQ_UDP     10
 200 #define AT91SAM9G20_IRQ_TWI     11
 201 #define AT91SAM9G20_IRQ_SPI0    12
 202 #define AT91SAM9G20_IRQ_SPI1    13
 203 #define AT91SAM9G20_IRQ_SSC0    14
 204 #define AT91SAM9G20_IRQ_SSC1    15
 205 #define AT91SAM9G20_IRQ_SSC2    16
 206 #define AT91SAM9G20_IRQ_TC0     17
 207 #define AT91SAM9G20_IRQ_TC1     18
 208 #define AT91SAM9G20_IRQ_TC2     19
 209 #define AT91SAM9G20_IRQ_UHP     20
 210 #define AT91SAM9G20_IRQ_EMAC    21
 211 #define AT91SAM9G20_IRQ_USART3  23
 212 #define AT91SAM9G20_IRQ_USART4  24
 213 #define AT91SAM9G20_IRQ_USART5  25
 214 #define AT91SAM9G20_IRQ_AICBASE 29
 215
 216 /* Alias */
 217 #define AT91SAM9G20_IRQ_DBGU    AT91SAM9G20_IRQ_SYSTEM
 218 #define AT91SAM9G20_IRQ_PMC     AT91SAM9G20_IRQ_SYSTEM
 219 #define AT91SAM9G20_IRQ_WDT     AT91SAM9G20_IRQ_SYSTEM
 220 #define AT91SAM9G20_IRQ_PIT     AT91SAM9G20_IRQ_SYSTEM
 221 #define AT91SAM9G20_IRQ_RSTC    AT91SAM9G20_IRQ_SYSTEM
 222 #define AT91SAM9G20_IRQ_OHCI    AT91SAM9G20_IRQ_UHP
 223 #define AT91SAM9G20_IRQ_NAND    (-1)
 224
 225 #define AT91SAM9G20_AIC_BASE    0xffff000
 226 #define AT91SAM9G20_AIC_SIZE    0x200
 227
 228 /* Timer */
 229
 230 #define AT91SAM9G20_WDT_BASE    0xffffd40
 231 #define AT91SAM9G20_WDT_SIZE    0x10
 232
 233 #define AT91SAM9G20_PIT_BASE    0xffffd30
 234 #define AT91SAM9G20_PIT_SIZE    0x10
 235
 236 #define AT91SAM9G20_SMC_BASE    0xfffec00
 237 #define AT91SAM9G20_SMC_SIZE    0x200
 238
 239 #define AT91SAM9G20_PMC_BASE    0xffffc00
 240 #define AT91SAM9G20_PMC_SIZE    0x100
 241
 242 #define AT91SAM9G20_UDP_BASE    0xffa4000
 243 #define AT91SAM9G20_UDP_SIZE    0x4000
 244
 245 #define AT91SAM9G20_MCI_BASE    0xffa8000
 246 #define AT91SAM9G20_MCI_SIZE    0x4000
 247
 248 #define AT91SAM9G20_TWI_BASE    0xffaC000
 249 #define AT91SAM9G20_TWI_SIZE    0x4000
 250
 251 /* XXX Needs to be carfully coordinated with
 252  * other * soc's so phyical and vm address
 253  * mapping are unique. XXX
 254  */
 255 #define AT91SAM9G20_OHCI_BASE     0xdfc00000
 256 #define AT91SAM9G20_OHCI_PA_BASE  0x00500000
 257 #define AT91SAM9G20_OHCI_SIZE     0x00100000
 258
 259 #define AT91SAM9G20_NAND_BASE     0xe0000000
 260 #define AT91SAM9G20_NAND_PA_BASE  0x40000000
 261 #define AT91SAM9G20_NAND_SIZE     0x10000000
 262
 263
 264 /* SDRAMC */
 265 #define AT91SAM9G20_SDRAMC_BASE 0xfffea00
 266 #define AT91SAM9G20_SDRAMC_MR   0x00
 267 #define AT91SAM9G20_SDRAMC_MR_MODE_NORMAL       0
 268 #define AT91SAM9G20_SDRAMC_MR_MODE_NOP  1
 269 #define AT91SAM9G20_SDRAMC_MR_MODE_PRECHARGE 2
 270 #define AT91SAM9G20_SDRAMC_MR_MODE_LOAD_MODE_REGISTER 3
 271 #define AT91SAM9G20_SDRAMC_MR_MODE_REFRESH      4
 272 #define AT91SAM9G20_SDRAMC_TR   0x04
 273 #define AT91SAM9G20_SDRAMC_CR   0x08
 274 #define AT91SAM9G20_SDRAMC_CR_NC_8              0x0
 275 #define AT91SAM9G20_SDRAMC_CR_NC_9              0x1
 276 #define AT91SAM9G20_SDRAMC_CR_NC_10     0x2
 277 #define AT91SAM9G20_SDRAMC_CR_NC_11     0x3
 278 #define AT91SAM9G20_SDRAMC_CR_NC_MASK   0x00000003
 279 #define AT91SAM9G20_SDRAMC_CR_NR_11     0x0
 280 #define AT91SAM9G20_SDRAMC_CR_NR_12     0x4
 281 #define AT91SAM9G20_SDRAMC_CR_NR_13     0x8
 282 #define AT91SAM9G20_SDRAMC_CR_NR_RES    0xc
 283 #define AT91SAM9G20_SDRAMC_CR_NR_MASK   0x0000000c
 284 #define AT91SAM9G20_SDRAMC_CR_NB_2              0x00
 285 #define AT91SAM9G20_SDRAMC_CR_NB_4              0x10
 286 #define AT91SAM9G20_SDRAMC_CR_DBW_16            0x80
 287 #define AT91SAM9G20_SDRAMC_CR_NB_MASK   0x00000010
 288 #define AT91SAM9G20_SDRAMC_CR_NCAS_MASK 0x00000060
 289 #define AT91SAM9G20_SDRAMC_CR_TWR_MASK  0x00000780
 290 #define AT91SAM9G20_SDRAMC_CR_TRC_MASK  0x00007800
 291 #define AT91SAM9G20_SDRAMC_CR_TRP_MASK  0x00078000
 292 #define AT91SAM9G20_SDRAMC_CR_TRCD_MASK 0x00780000
 293 #define AT91SAM9G20_SDRAMC_CR_TRAS_MASK 0x07800000
 294 #define AT91SAM9G20_SDRAMC_CR_TXSR_MASK 0x78000000
 295 #define AT91SAM9G20_SDRAMC_HSR  0x0c
 296 #define AT91SAM9G20_SDRAMC_LPR  0x10
 297 #define AT91SAM9G20_SDRAMC_IER  0x14
 298 #define AT91SAM9G20_SDRAMC_IDR  0x18
 299 #define AT91SAM9G20_SDRAMC_IMR  0x1c
 300 #define AT91SAM9G20_SDRAMC_ISR  0x20
 301 #define AT91SAM9G20_SDRAMC_MDR  0x24
 302
 303 #endif /* AT91SAM9G20REG_H_*/
 304