sys/boot/fdt/dts/db78460.dts

   1 /*
   2  * Copyright (c) 2010 The FreeBSD Foundation
   3  * Copyright (c) 2010-2011 Semihalf
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  *
  27  * Marvell DB-78460 Device Tree Source.
  28  *
  29  * $FreeBSD$
  30  */
  31
  32 /dts-v1/;
  33
  34 / {
  35         model = "mrvl,DB-78460";
  36         #address-cells = <1>;
  37         #size-cells = <1>;
  38
  39         aliases {
  40                 serial0 = &serial0;
  41         };
  42
  43         cpus {
  44                 #address-cells = <1>;
  45                 #size-cells = <0>;
  46
  47                 cpu@0 {
  48                         device_type = "cpu";
  49                         compatible = "ARM,88VS584";
  50                         reg = <0x0>;
  51                         d-cache-line-size = <32>;       // 32 bytes
  52                         i-cache-line-size = <32>;       // 32 bytes
  53                         d-cache-size = <0x8000>;        // L1, 32K
  54                         i-cache-size = <0x8000>;        // L1, 32K
  55                         timebase-frequency = <0>;
  56                         bus-frequency = <200000000>;
  57                         clock-frequency = <0>;
  58                 };
  59         };
  60
  61         memory {
  62                 device_type = "memory";
  63                 reg = <0x0 0x80000000>;         // 2G at 0x0
  64         };
  65
  66         soc78460@d0000000 {
  67                 #address-cells = <1>;
  68                 #size-cells = <1>;
  69                 compatible = "simple-bus";
  70                 ranges = <0x0 0xd0000000 0x00100000>;
  71                 bus-frequency = <0>;
  72
  73
  74                 MPIC: mpic@20a00 {
  75                         interrupt-controller;
  76                         #address-cells = <0>;
  77                         #interrupt-cells = <1>;
  78                         reg = <0x20a00 0x500 0x21000 0x800 0x20400 0x100>;
  79                         compatible = "mrvl,mpic";
  80                 };
  81
  82                 rtc@10300 {
  83                         compatible = "mrvl,rtc";
  84                         reg = <0x10300 0x08>;
  85                 };
  86
  87                 timer@21840 {
  88                         compatible = "mrvl,timer";
  89                         reg = <0x21840 0x30>;
  90                         interrupts = <5>;
  91                         interrupt-parent = <&MPIC>;
  92                         mrvl,has-wdt;
  93                 };
  94
  95                 twsi@11000 {
  96                         #address-cells = <1>;
  97                         #size-cells = <0>;
  98                         compatible = "mrvl,twsi";
  99                         reg = <0x11000 0x20>;
 100                         interrupts = <31>;
 101                         interrupt-parent = <&MPIC>;
 102                 };
 103
 104                 twsi@11100 {
 105                         #address-cells = <1>;
 106                         #size-cells = <0>;
 107                         compatible = "mrvl,twsi";
 108                         reg = <0x11100 0x20>;
 109                         interrupts = <32>;
 110                         interrupt-parent = <&MPIC>;
 111                 };
 112
 113                 serial0: serial@12000 {
 114                         compatible = "ns16550";
 115                         reg = <0x12000 0x20>;
 116                         reg-shift = <2>;
 117                         current-speed = <115200>;
 118                         clock-frequency = <0>;
 119                         interrupts = <41>;
 120                         interrupt-parent = <&MPIC>;
 121                 };
 122
 123                 serial1: serial@12100 {
 124                         compatible = "ns16550";
 125                         reg = <0x12100 0x20>;
 126                         reg-shift = <2>;
 127                         current-speed = <115200>;
 128                         clock-frequency = <0>;
 129                         interrupts = <42>;
 130                         interrupt-parent = <&MPIC>;
 131                 };
 132
 133                 serial2: serial@12200 {
 134                         compatible = "ns16550";
 135                         reg = <0x12200 0x20>;
 136                         reg-shift = <2>;
 137                         current-speed = <115200>;
 138                         clock-frequency = <0>;
 139                         interrupts = <43>;
 140                         interrupt-parent = <&MPIC>;
 141                 };
 142
 143                 serial3: serial@12300 {
 144                         compatible = "ns16550";
 145                         reg = <0x12300 0x20>;
 146                         reg-shift = <2>;
 147                         current-speed = <115200>;
 148                         clock-frequency = <0>;
 149                         interrupts = <44>;
 150                         interrupt-parent = <&MPIC>;
 151                 };
 152
 153                 MPP: mpp@10000 {
 154                         #pin-cells = <2>;
 155                         compatible = "mrvl,mpp";
 156                         reg = <0x18000 0x34>;
 157                         pin-count = <68>;
 158                         pin-map = <
 159                                 0  1            /* MPP[0]:  GE1_TXCLK */
 160                                 1  1            /* MPP[1]:  GE1_TXCTL */
 161                                 2  1            /* MPP[2]:  GE1_RXCTL */
 162                                 3  1            /* MPP[3]:  GE1_RXCLK */
 163                                 4  1            /* MPP[4]:  GE1_TXD[0] */
 164                                 5  1            /* MPP[5]:  GE1_TXD[1] */
 165                                 6  1            /* MPP[6]:  GE1_TXD[2] */
 166                                 7  1            /* MPP[7]:  GE1_TXD[3] */
 167                                 8  1            /* MPP[8]:  GE1_RXD[0] */
 168                                 9  1            /* MPP[9]:  GE1_RXD[1] */
 169                                 10 1            /* MPP[10]: GE1_RXD[2] */
 170                                 11 1            /* MPP[11]: GE1_RXD[3] */
 171                                 12 2            /* MPP[13]: SYSRST_OUTn */
 172                                 13 2            /* MPP[13]: SYSRST_OUTn */
 173                                 14 2            /* MPP[14]: SATA1_ACTn */
 174                                 15 2            /* MPP[15]: SATA0_ACTn */
 175                                 16 2            /* MPP[16]: UA2_TXD */
 176                                 17 2            /* MPP[17]: UA2_RXD */
 177                                 18 2            /* MPP[18]: <UNKNOWN> */
 178                                 19 2            /* MPP[19]: <UNKNOWN> */
 179                                 20 2            /* MPP[20]: <UNKNOWN> */
 180                                 21 2            /* MPP[21]: <UNKNOWN> */
 181                                 22 2            /* MPP[22]: UA3_TXD */
 182                                 23 2
 183                                 24 0
 184                                 25 0
 185                                 26 0
 186                                 27 0
 187                                 28 4
 188                                 29 0
 189                                 30 1
 190                                 31 1
 191                                 32 1
 192                                 33 1
 193                                 34 1
 194                                 35 1
 195                                 36 1
 196                                 37 1
 197                                 38 1
 198                                 39 1
 199                                 40 0
 200                                 41 3
 201                                 42 1
 202                                 43 1
 203                                 44 2
 204                                 45 2
 205                                 46 4
 206                                 47 3
 207                                 48 0
 208                                 49 1
 209                                 50 1
 210                                 51 1
 211                                 52 1
 212                                 53 1
 213                                 54 1
 214                                 55 1
 215                                 56 1
 216                                 57 0
 217                                 58 1
 218                                 59 1
 219                                 60 1
 220                                 61 1
 221                                 62 1
 222                                 63 1
 223                                 64 1
 224                                 65 1
 225                                 66 1
 226                                 67 2 >;
 227                 };
 228
 229                 usb@50000 {
 230                         compatible = "mrvl,usb-ehci", "usb-ehci";
 231                         reg = <0x50000 0x1000>;
 232                         interrupts = <124 45>;
 233                         interrupt-parent = <&MPIC>;
 234                 };
 235
 236                 usb@51000 {
 237                         compatible = "mrvl,usb-ehci", "usb-ehci";
 238                         reg = <0x51000 0x1000>;
 239                         interrupts = <124 46>;
 240                         interrupt-parent = <&MPIC>;
 241                 };
 242
 243                 usb@52000 {
 244                         compatible = "mrvl,usb-ehci", "usb-ehci";
 245                         reg = <0x52000 0x1000>;
 246                         interrupts = <124 47>;
 247                         interrupt-parent = <&MPIC>;
 248                 };
 249
 250                 enet0: ethernet@72000 {
 251                         #address-cells = <1>;
 252                         #size-cells = <1>;
 253                         model = "V2";
 254                         compatible = "mrvl,ge";
 255                         reg = <0x72000 0x2000>;
 256                         ranges = <0x0 0x72000 0x2000>;
 257                         local-mac-address = [ 00 04 01 07 84 60 ];
 258                         interrupts = <67 68 122 >;
 259                         interrupt-parent = <&MPIC>;
 260                         phy-handle = <&phy0>;
 261                         has-neta;
 262
 263                         mdio@0 {
 264                                 #address-cells = <1>;
 265                                 #size-cells = <0>;
 266                                 compatible = "mrvl,mdio";
 267
 268                                 phy0: ethernet-phy@0 {
 269                                         reg = <0x0>;
 270                                 };
 271                                 phy1: ethernet-phy@1 {
 272                                         reg = <0x1>;
 273                                 };
 274                                 phy2: ethernet-phy@2 {
 275                                         reg = <0x19>;
 276                                 };
 277                                 phy3: ethernet-phy@3 {
 278                                         reg = <0x1b>;
 279                                 };
 280                         };
 281                 };
 282         };
 283
 284         pci0: pcie@d0040000 {
 285                 compatible = "mrvl,pcie";
 286                 device_type = "pci";
 287                 #interrupt-cells = <1>;
 288                 #size-cells = <2>;
 289                 #address-cells = <3>;
 290                 reg = <0xd0040000 0x2000>;
 291                 bus-range = <0 255>;
 292                 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
 293                           0x01000000 0x0 0x00000000 0xa0000000 0x0 0x08000000>;
 294                 clock-frequency = <33333333>;
 295                 interrupt-parent = <&MPIC>;
 296                 interrupts = <120>;
 297                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 298                 interrupt-map = <
 299                         0x0800 0x0 0x0 0x1 &MPIC 0x3A
 300                         0x0800 0x0 0x0 0x2 &MPIC 0x3A
 301                         0x0800 0x0 0x0 0x3 &MPIC 0x3A
 302                         0x0800 0x0 0x0 0x4 &MPIC 0x3A
 303                         >;
 304         };
 305
 306         sram@ffff0000 {
 307                 compatible = "mrvl,cesa-sram";
 308                 reg = <0xffff0000 0x00010000>;
 309         };
 310
 311         chosen {
 312                 stdin = "serial0";
 313                 stdout = "serial0";
 314                 stddbg = "serial0";
 315         };
 316 };