sys/boot/fdt/dts/dockstar.dts

   1 /*
   2  * Copyright (c) 2010 The FreeBSD Foundation
   3  * All rights reserved.
   4  *
   5  * This software was developed by Semihalf under sponsorship from
   6  * the FreeBSD Foundation.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  20  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  27  * SUCH DAMAGE.
  28  *
  29  * Seagate DockStar (Marvell SheevaPlug based) Device Tree Source.
  30  *
  31  * $FreeBSD$
  32  */
  33
  34 /dts-v1/;
  35
  36 / {
  37         model = "seagate,DockStar";
  38         compatible = "DockStar";
  39         #address-cells = <1>;
  40         #size-cells = <1>;
  41
  42         aliases {
  43                 ethernet0 = &enet0;
  44                 mpp = &MPP;
  45                 serial0 = &serial0;
  46                 serial1 = &serial1;
  47                 soc = &SOC;
  48                 sram = &SRAM;
  49         };
  50
  51         cpus {
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54
  55                 cpu@0 {
  56                         device_type = "cpu";
  57                         compatible = "ARM,88FR131";
  58                         reg = <0x0>;
  59                         d-cache-line-size = <32>;       // 32 bytes
  60                         i-cache-line-size = <32>;       // 32 bytes
  61                         d-cache-size = <0x4000>;        // L1, 16K
  62                         i-cache-size = <0x4000>;        // L1, 16K
  63                         timebase-frequency = <0>;
  64                         bus-frequency = <0>;
  65                         clock-frequency = <0>;
  66                 };
  67         };
  68
  69         memory {
  70                 device_type = "memory";
  71                 reg = <0x0 0x8000000>;          // 128M at 0x0
  72         };
  73
  74         localbus@f1000000 {
  75                 #address-cells = <2>;
  76                 #size-cells = <1>;
  77                 compatible = "mrvl,lbc";
  78
  79                 /* This reflects CPU decode windows setup. */
  80                 ranges = <0x0 0x0f 0xf9300000 0x00100000
  81                           0x1 0x1e 0xfa000000 0x00100000
  82                           0x2 0x1d 0xfa100000 0x02000000
  83                           0x3 0x1b 0xfc100000 0x00000400>;
  84
  85                 nor@0,0 {
  86                         #address-cells = <1>;
  87                         #size-cells = <1>;
  88                         compatible = "cfi-flash";
  89                         reg = <0x0 0x0 0x00100000>;
  90                         bank-width = <2>;
  91                         device-width = <1>;
  92                 };
  93
  94                 led@1,0 {
  95                         #address-cells = <1>;
  96                         #size-cells = <1>;
  97                         compatible = "led";
  98                         reg = <0x1 0x0 0x00100000>;
  99                 };
 100
 101                 nor@2,0 {
 102                         #address-cells = <1>;
 103                         #size-cells = <1>;
 104                         compatible = "cfi-flash";
 105                         reg = <0x2 0x0 0x02000000>;
 106                         bank-width = <2>;
 107                         device-width = <1>;
 108                 };
 109
 110                 nand@3,0 {
 111                         #address-cells = <1>;
 112                         #size-cells = <1>;
 113                         reg = <0x3 0x0 0x00100000>;
 114                         bank-width = <2>;
 115                         device-width = <1>;
 116                 };
 117         };
 118
 119         SOC: soc88f6281@f1000000 {
 120                 #address-cells = <1>;
 121                 #size-cells = <1>;
 122                 compatible = "simple-bus";
 123                 ranges = <0x0 0xf1000000 0x00100000>;
 124                 bus-frequency = <0>;
 125
 126                 PIC: pic@20200 {
 127                         interrupt-controller;
 128                         #address-cells = <0>;
 129                         #interrupt-cells = <1>;
 130                         reg = <0x20200 0x3c>;
 131                         compatible = "mrvl,pic";
 132                 };
 133
 134                 timer@20300 {
 135                         compatible = "mrvl,timer";
 136                         reg = <0x20300 0x30>;
 137                         interrupts = <1>;
 138                         interrupt-parent = <&PIC>;
 139                         mrvl,has-wdt;
 140                 };
 141
 142                 MPP: mpp@10000 {
 143                         #pin-cells = <2>;
 144                         compatible = "mrvl,mpp";
 145                         reg = <0x10000 0x34>;
 146                         pin-count = <50>;
 147                         pin-map = <
 148                                 0  1            /* MPP[0]:  NF_IO[2] */
 149                                 1  1            /* MPP[1]:  NF_IO[3] */
 150                                 2  1            /* MPP[2]:  NF_IO[4] */
 151                                 3  1            /* MPP[3]:  NF_IO[5] */
 152                                 4  1            /* MPP[4]:  NF_IO[6] */
 153                                 5  1            /* MPP[5]:  NF_IO[7] */
 154                                 6  1            /* MPP[6]:  SYSRST_OUTn */
 155                                 8  2            /* MPP[8]:  UA0_RTS */
 156                                 9  2            /* MPP[9]:  UA0_CTS */
 157                                 10 3            /* MPP[10]: UA0_TXD */
 158                                 11 3            /* MPP[11]: UA0_RXD */
 159                                 12 1            /* MPP[12]: SD_CLK */
 160                                 13 1            /* MPP[13]: SD_CMD */
 161                                 14 1            /* MPP[14]: SD_D[0] */
 162                                 15 1            /* MPP[15]: SD_D[1] */
 163                                 16 1            /* MPP[16]: SD_D[2] */
 164                                 17 1            /* MPP[17]: SD_D[3] */
 165                                 18 1            /* MPP[18]: NF_IO[0] */
 166                                 19 1            /* MPP[19]: NF_IO[1] */
 167                                 29 1 >;         /* MPP[29]: TSMP[9] */
 168                 };
 169
 170                 GPIO: gpio@10100 {
 171                         #gpio-cells = <3>;
 172                         compatible = "mrvl,gpio";
 173                         reg = <0x10100 0x20>;
 174                         gpio-controller;
 175                         interrupts = <35 36 37 38 39 40 41>;
 176                         interrupt-parent = <&PIC>;
 177                 };
 178
 179                 rtc@10300 {
 180                         compatible = "mrvl,rtc";
 181                         reg = <0x10300 0x08>;
 182                 };
 183
 184                 twsi@11000 {
 185                         #address-cells = <1>;
 186                         #size-cells = <0>;
 187                         compatible = "mrvl,twsi";
 188                         reg = <0x11000 0x20>;
 189                         interrupts = <43>;
 190                         interrupt-parent = <&PIC>;
 191                 };
 192
 193                 enet0: ethernet@72000 {
 194                         #address-cells = <1>;
 195                         #size-cells = <1>;
 196                         model = "V2";
 197                         compatible = "mrvl,ge";
 198                         reg = <0x72000 0x2000>;
 199                         ranges = <0x0 0x72000 0x2000>;
 200                         local-mac-address = [ 00 00 00 00 00 00 ];
 201                         interrupts = <12 13 14 11 46>;
 202                         interrupt-parent = <&PIC>;
 203                         phy-handle = <&phy0>;
 204
 205                         mdio@0 {
 206                                 #address-cells = <1>;
 207                                 #size-cells = <0>;
 208                                 compatible = "mrvl,mdio";
 209
 210                                 phy0: ethernet-phy@0 {
 211                                         reg = <0x0>;
 212                                 };
 213                         };
 214                 };
 215
 216                 serial0: serial@12000 {
 217                         compatible = "ns16550";
 218                         reg = <0x12000 0x20>;
 219                         reg-shift = <2>;
 220                         clock-frequency = <0>;
 221                         interrupts = <33>;
 222                         interrupt-parent = <&PIC>;
 223                 };
 224
 225                 serial1: serial@12100 {
 226                         compatible = "ns16550";
 227                         reg = <0x12100 0x20>;
 228                         reg-shift = <2>;
 229                         clock-frequency = <0>;
 230                         interrupts = <34>;
 231                         interrupt-parent = <&PIC>;
 232                 };
 233
 234                 crypto@30000 {
 235                         compatible = "mrvl,cesa";
 236                         reg = <0x30000 0x10000>;
 237                         interrupts = <22>;
 238                         interrupt-parent = <&PIC>;
 239                 };
 240
 241                 usb@50000 {
 242                         compatible = "mrvl,usb-ehci", "usb-ehci";
 243                         reg = <0x50000 0x1000>;
 244                         interrupts = <48 19>;
 245                         interrupt-parent = <&PIC>;
 246                 };
 247
 248                 xor@60000 {
 249                         compatible = "mrvl,xor";
 250                         reg = <0x60000 0x1000>;
 251                         interrupts = <5 6 7 8>;
 252                         interrupt-parent = <&PIC>;
 253                 };
 254         };
 255
 256         SRAM: sram@fd000000 {
 257                 compatible = "mrvl,cesa-sram";
 258                 reg = <0xfd000000 0x00100000>;
 259         };
 260
 261         chosen {
 262                 stdin = "serial0";
 263                 stdout = "serial0";
 264         };
 265 };