sys/boot/fdt/dts/dreamplug-1001.dts

   1 /*
   2  * Copyright (c) 2013 Ian Lepore
   3  * Copyright (c) 2010 The FreeBSD Foundation
   4  * All rights reserved.
   5  *
   6  * This software substantially based on work developed by Semihalf
   7  * under sponsorship from the FreeBSD Foundation.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28  * SUCH DAMAGE.
  29  *
  30  * GlobalScale Technologies DreamPlug Device Tree Source.
  31  *
  32  * This source is for version 10 revision 01 units with NOR SPI flash.
  33  * These units are marked "1001" on the serial number label.
  34  *
  35  * $FreeBSD$
  36  */
  37
  38 /dts-v1/;
  39
  40 / {
  41         model = "GlobalScale Technologies Dreamplug v1001";
  42         compatible = "globalscale,dreamplug-003-ds2001", "globalscale,dreamplug", "marvell,kirkwood-88f6281", "marvell,kirkwood";
  43         #address-cells = <1>;
  44         #size-cells = <1>;
  45
  46         aliases {
  47                 ethernet0 = &enet0;
  48                 ethernet1 = &enet1;
  49                 mpp = &MPP;
  50                 serial0 = &serial0;
  51                 serial1 = &serial1;
  52                 soc = &SOC;
  53                 sram = &SRAM;
  54         };
  55
  56         cpus {
  57                 #address-cells = <1>;
  58                 #size-cells = <0>;
  59
  60                 cpu@0 {
  61                         device_type = "cpu";
  62                         compatible = "ARM,88FR131";
  63                         reg = <0x0>;
  64                         d-cache-line-size = <32>;       // 32 bytes
  65                         i-cache-line-size = <32>;       // 32 bytes
  66                         d-cache-size = <0x4000>;        // L1, 16K
  67                         i-cache-size = <0x4000>;        // L1, 16K
  68                         timebase-frequency = <0>;
  69                         bus-frequency = <0>;
  70                         clock-frequency = <0>;
  71                 };
  72
  73         };
  74
  75         memory {
  76                 device_type = "memory";
  77                 reg = <0x0 0x20000000>;         // 512M at 0x0
  78         };
  79
  80         localbus@0 {
  81                 #address-cells = <2>;
  82                 #size-cells = <1>;
  83                 compatible = "mrvl,lbc";
  84                 bank-count = <1>;
  85
  86                 /* This reflects CPU decode windows setup. */
  87                 ranges = <0x0 0x1e 0xfa000000 0x00100000>;
  88
  89                 nor@0,0 {
  90                         #address-cells = <1>;
  91                         #size-cells = <1>;
  92                         compatible = "cfi-flash";
  93                         reg = <0x0 0x0 0x00100000>;
  94                         bank-width = <2>;
  95                         device-width = <1>;
  96                 };
  97         };
  98
  99         SOC: soc88f6281@f1000000 {
 100                 #address-cells = <1>;
 101                 #size-cells = <1>;
 102                 compatible = "simple-bus";
 103                 ranges = <0x0 0xf1000000 0x00100000>;
 104                 bus-frequency = <0>;
 105
 106                 PIC: pic@20200 {
 107                         interrupt-controller;
 108                         #address-cells = <0>;
 109                         #interrupt-cells = <1>;
 110                         reg = <0x20200 0x3c>;
 111                         compatible = "mrvl,pic";
 112                 };
 113
 114                 timer@20300 {
 115                         compatible = "mrvl,timer";
 116                         reg = <0x20300 0x30>;
 117                         interrupts = <1>;
 118                         interrupt-parent = <&PIC>;
 119                         mrvl,has-wdt;
 120                 };
 121
 122                 MPP: mpp@10000 {
 123                         #pin-cells = <2>;
 124                         compatible = "mrvl,mpp";
 125                         reg = <0x10000 0x34>;
 126                         pin-count = <50>;
 127                         pin-map = <
 128                                  0 2            /* MPP[ 0]:  SPI_SCn */
 129                                  1 2            /* MPP[ 1]:  SPI_MOSI */
 130                                  2 2            /* MPP[ 2]:  SPI_SCK */
 131                                  3 2            /* MPP[ 3]:  SPI_MISO */
 132                                  4 1            /* MPP[ 4]: NF_IO[6] */
 133                                  5 1            /* MPP[ 5]: NF_IO[7] */
 134                                  6 1            /* MPP[ 6]: SYSRST_OUTn */
 135                                  7 0            /* MPP[ 7]: GPO[7] */
 136                                  8 1            /* MPP[ 8]: TW_SDA */
 137                                  9 1            /* MPP[ 9]: TW_SCK */
 138                                 10 3            /* MPP[10]: UA0_TXD */
 139                                 11 3            /* MPP[11]: US0_RXD */
 140                                 12 1            /* MPP[12]: SD_CLK */
 141                                 13 1            /* MPP[13]: SD_CMD */
 142                                 14 1            /* MPP[14]: SD_D[0] */
 143                                 15 1            /* MPP[15]: SD_D[1] */
 144                                 16 1            /* MPP[16]: SD_D[2] */
 145                                 17 1            /* MPP[17]: SD_D[3] */
 146                                 18 1            /* MPP[18]: NF_IO[0] */
 147                                 19 1            /* MPP[19]: NF_IO[1] */
 148                                 20 3            /* MPP[20]: GE1[ 0] */
 149                                 21 3            /* MPP[21]: GE1[ 1] */
 150                                 22 3            /* MPP[22]: GE1[ 2] */
 151                                 23 3            /* MPP[23]: GE1[ 3] */
 152                                 24 3            /* MPP[24]: GE1[ 4] */
 153                                 25 3            /* MPP[25]: GE1[ 5] */
 154                                 26 3            /* MPP[26]: GE1[ 6] */
 155                                 27 3            /* MPP[27]: GE1[ 7] */
 156                                 28 3            /* MPP[28]: GE1[ 8] */
 157                                 29 3            /* MPP[29]: GE1[ 9] */
 158                                 30 3            /* MPP[30]: GE1[10] */
 159                                 31 3            /* MPP[31]: GE1[11] */
 160                                 32 3            /* MPP[32]: GE1[12] */
 161                                 33 3            /* MPP[33]: GE1[13] */
 162                                 34 3            /* MPP[34]: GE1[14] */
 163                                 35 3            /* MPP[35]: GE1[15] */
 164                                 36 0            /* MPP[36]: GPIO[36] */
 165                                 37 0            /* MPP[37]: GPIO[37] */
 166                                 38 0            /* MPP[38]: GPIO[38] */
 167                                 39 0            /* MPP[39]: GPIO[39] */
 168                                 40 2            /* MPP[40]: TDM_SPI_SCK */
 169                                 41 2            /* MPP[41]: TDM_SPI_MISO */
 170                                 42 2            /* MPP[42]: TDM_SPI_MOSI */
 171                                 43 0            /* MPP[43]: GPIO[43] */
 172                                 44 0            /* MPP[44]: GPIO[44] */
 173                                 45 0            /* MPP[45]: GPIO[45] */
 174                                 46 0            /* MPP[46]: GPIO[46] */
 175                                 47 0            /* MPP[47]: GPIO[47] */
 176                                 48 0            /* MPP[48]: GPIO[48] */
 177                                 49 0            /* MPP[49]: GPIO[49] */
 178                                 >;
 179                 };
 180
 181                 GPIO: gpio@10100 {
 182                         #gpio-cells = <3>;
 183                         compatible = "mrvl,gpio";
 184                         reg = <0x10100 0x20>;
 185                         gpio-controller;
 186                         interrupts = <35 36 37 38 39 40 41>;
 187                         interrupt-parent = <&PIC>;
 188                         pin-count = <50>;
 189                 };
 190
 191                 gpioled@0 {
 192                         compatible = "mrvl,gpioled";
 193
 194                         gpios = <&GPIO 47 2 0   /* GPIO[47] BT LED: OUT */
 195                                  &GPIO 48 2 0   /* GPIO[48] WLAN LED: OUT */
 196                                  &GPIO 49 2 0>; /* GPIO[49] WLAN AP LED: OUT */
 197                 };
 198
 199                 rtc@10300 {
 200                         compatible = "mrvl,rtc";
 201                         reg = <0x10300 0x08>;
 202                 };
 203
 204                 twsi@11000 {
 205                         #address-cells = <1>;
 206                         #size-cells = <0>;
 207                         compatible = "mrvl,twsi";
 208                         reg = <0x11000 0x20>;
 209                         interrupts = <43>;
 210                         interrupt-parent = <&PIC>;
 211                 };
 212
 213                 enet0: ethernet@72000 {
 214                         #address-cells = <1>;
 215                         #size-cells = <1>;
 216                         model = "V2";
 217                         compatible = "mrvl,ge";
 218                         reg = <0x72000 0x2000>;
 219                         ranges = <0x0 0x72000 0x2000>;
 220                         local-mac-address = [ 00 00 00 00 00 00 ];
 221                         interrupts = <12 13 14 11 46>;
 222                         interrupt-parent = <&PIC>;
 223                         phy-handle = <&phy0>;
 224
 225                         mdio@0 {
 226                                 #address-cells = <1>;
 227                                 #size-cells = <0>;
 228                                 compatible = "mrvl,mdio";
 229
 230                                 phy0: ethernet-phy@0 {
 231                                         reg = <0x0>;
 232                                 };
 233
 234                                 phy1: ethernet-phy@1 {
 235                                         reg = <0x1>;
 236                                 };
 237                         };
 238                 };
 239
 240                 enet1: ethernet@76000 {
 241                         #address-cells = <1>;
 242                         #size-cells = <1>;
 243                         model = "V2";
 244                         compatible = "mrvl,ge";
 245                         reg = <0x76000 0x02000>;
 246                         ranges = <0x0 0x76000 0x2000>;
 247                         local-mac-address = [ 00 00 00 00 00 00 ];
 248                         interrupts = <16 17 18 15 47>;
 249                         interrupt-parent = <&PIC>;
 250                         phy-handle = <&phy1>;
 251                 };
 252
 253                 serial0: serial@12000 {
 254                         compatible = "ns16550";
 255                         reg = <0x12000 0x20>;
 256                         reg-shift = <2>;
 257                         clock-frequency = <0>;
 258                         interrupts = <33>;
 259                         interrupt-parent = <&PIC>;
 260                 };
 261
 262                 serial1: serial@12100 {
 263                         compatible = "ns16550";
 264                         reg = <0x12100 0x20>;
 265                         reg-shift = <2>;
 266                         clock-frequency = <0>;
 267                         interrupts = <34>;
 268                         interrupt-parent = <&PIC>;
 269                 };
 270
 271                 crypto@30000 {
 272                         compatible = "mrvl,cesa";
 273                         reg = <0x30000 0x10000>;
 274                         interrupts = <22>;
 275                         interrupt-parent = <&PIC>;
 276
 277                         sram-handle = <&SRAM>;
 278                 };
 279
 280                 usb@50000 {
 281                         compatible = "mrvl,usb-ehci", "usb-ehci";
 282                         reg = <0x50000 0x1000>;
 283                         interrupts = <48 19>;
 284                         interrupt-parent = <&PIC>;
 285                 };
 286
 287                 xor@60000 {
 288                         compatible = "mrvl,xor";
 289                         reg = <0x60000 0x1000>;
 290                         interrupts = <5 6 7 8>;
 291                         interrupt-parent = <&PIC>;
 292                 };
 293
 294                 sata@80000 {
 295                         compatible = "mrvl,sata";
 296                         reg = <0x80000 0x6000>;
 297                         interrupts = <21>;
 298                         interrupt-parent = <&PIC>;
 299                 };
 300
 301                 sdio@90000 {
 302                         compatible = "mrvl,sdio";
 303                         reg = <0x90000 0x134>;
 304                         interrupts = <28>;
 305                         interrupt-parent = <&PIC>;
 306                 };
 307         };
 308
 309         SRAM: sram@fd000000 {
 310                 compatible = "mrvl,cesa-sram";
 311                 reg = <0xfd000000 0x00100000>;
 312         };
 313
 314         chosen {
 315                 stdin = "serial0";
 316                 stdout = "serial0";
 317         };
 318
 319 };