sys/boot/fdt/dts/p5020ds.dts

   1 /*
   2  * P5020DS Device Tree Source
   3  *
   4  * Copyright 2010-2011 Freescale Semiconductor Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *     * Redistributions of source code must retain the above copyright
   9  *       notice, this list of conditions and the following disclaimer.
  10  *     * Redistributions in binary form must reproduce the above copyright
  11  *       notice, this list of conditions and the following disclaimer in the
  12  *       documentation and/or other materials provided with the distribution.
  13  *     * Neither the name of Freescale Semiconductor nor the
  14  *       names of its contributors may be used to endorse or promote products
  15  *       derived from this software without specific prior written permission.
  16  *
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation, either version 2 of that License or (at your option) any
  21  * later version.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34 /* $FreeBSD$ */
  35
  36 /include/ "p5020si.dtsi"
  37
  38 / {
  39         model = "fsl,P5020DS";
  40         compatible = "fsl,P5020DS";
  41         #address-cells = <2>;
  42         #size-cells = <2>;
  43         interrupt-parent = <&mpic>;
  44
  45         aliases {
  46                 phy_rgmii_0 = &phy_rgmii_0;
  47                 phy_rgmii_1 = &phy_rgmii_1;
  48                 phy_sgmii_1c = &phy_sgmii_1c;
  49                 phy_sgmii_1d = &phy_sgmii_1d;
  50                 phy_sgmii_1e = &phy_sgmii_1e;
  51                 phy_sgmii_1f = &phy_sgmii_1f;
  52                 phy_xgmii_1 = &phy_xgmii_1;
  53                 phy_xgmii_2 = &phy_xgmii_2;
  54                 emi1_rgmii = &hydra_mdio_rgmii;
  55                 emi1_sgmii = &hydra_mdio_sgmii;
  56                 emi2_xgmii = &hydra_mdio_xgmii;
  57         };
  58
  59         memory {
  60                 device_type = "memory";
  61                 reg = <0x00000000 0x00000000 0x00000000 0x80000000>;
  62         };
  63
  64         dcsr: dcsr@f00000000 {
  65                 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
  66         };
  67
  68         bman-portals@ff4000000 {
  69                 bman-portal@0 {
  70                         cpu-handle = <&cpu0>;
  71                 };
  72                 bman-portal@4000 {
  73                         cpu-handle = <&cpu1>;
  74                 };
  75                 bman-portal@8000 {
  76                 };
  77                 bman-portal@c000 {
  78                 };
  79                 bman-portal@10000 {
  80                 };
  81                 bman-portal@14000 {
  82                 };
  83                 bman-portal@18000 {
  84                 };
  85                 bman-portal@1c000 {
  86                 };
  87                 bman-portal@20000 {
  88                 };
  89                 bman-portal@24000 {
  90                 };
  91
  92                 buffer-pool@0 {
  93                         compatible = "fsl,p5020-bpool", "fsl,bpool";
  94                         fsl,bpid = <0>;
  95                         fsl,bpool-cfg = <0 0x100 0 1 0 0x100>;
  96                 };
  97         };
  98
  99         qman-portals@ff4200000 {
 100                 qportal0: qman-portal@0 {
 101                         cpu-handle = <&cpu0>;
 102                         fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
 103                                                   &qpool4 &qpool5 &qpool6
 104                                                   &qpool7 &qpool8 &qpool9
 105                                                   &qpool10 &qpool11 &qpool12
 106                                                   &qpool13 &qpool14 &qpool15>;
 107                 };
 108
 109                 qportal1: qman-portal@4000 {
 110                         cpu-handle = <&cpu1>;
 111                         fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
 112                                                   &qpool4 &qpool5 &qpool6
 113                                                   &qpool7 &qpool8 &qpool9
 114                                                   &qpool10 &qpool11 &qpool12
 115                                                   &qpool13 &qpool14 &qpool15>;
 116                 };
 117
 118                 qportal2: qman-portal@8000 {
 119                         fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
 120                                                   &qpool4 &qpool5 &qpool6
 121                                                   &qpool7 &qpool8 &qpool9
 122                                                   &qpool10 &qpool11 &qpool12
 123                                                   &qpool13 &qpool14 &qpool15>;
 124                 };
 125
 126                 qportal3: qman-portal@c000 {
 127                         fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
 128                                                   &qpool4 &qpool5 &qpool6
 129                                                   &qpool7 &qpool8 &qpool9
 130                                                   &qpool10 &qpool11 &qpool12
 131                                                   &qpool13 &qpool14 &qpool15>;
 132                 };
 133
 134                 qportal4: qman-portal@10000 {
 135                         fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
 136                                                   &qpool4 &qpool5 &qpool6
 137                                                   &qpool7 &qpool8 &qpool9
 138                                                   &qpool10 &qpool11 &qpool12
 139                                                   &qpool13 &qpool14 &qpool15>;
 140                 };
 141
 142                 qportal5: qman-portal@14000 {
 143                         fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
 144                                                   &qpool4 &qpool5 &qpool6
 145                                                   &qpool7 &qpool8 &qpool9
 146                                                   &qpool10 &qpool11 &qpool12
 147                                                   &qpool13 &qpool14 &qpool15>;
 148                 };
 149
 150                 qportal6: qman-portal@18000 {
 151                         fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
 152                                                   &qpool4 &qpool5 &qpool6
 153                                                   &qpool7 &qpool8 &qpool9
 154                                                   &qpool10 &qpool11 &qpool12
 155                                                   &qpool13 &qpool14 &qpool15>;
 156                 };
 157
 158                 qportal7: qman-portal@1c000 {
 159                         fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
 160                                                   &qpool4 &qpool5 &qpool6
 161                                                   &qpool7 &qpool8 &qpool9
 162                                                   &qpool10 &qpool11 &qpool12
 163                                                   &qpool13 &qpool14 &qpool15>;
 164                 };
 165
 166                 qportal8: qman-portal@20000 {
 167                         fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
 168                                                   &qpool4 &qpool5 &qpool6
 169                                                   &qpool7 &qpool8 &qpool9
 170                                                   &qpool10 &qpool11 &qpool12
 171                                                   &qpool13 &qpool14 &qpool15>;
 172                 };
 173
 174                 qportal9: qman-portal@24000 {
 175                         fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
 176                                                   &qpool4 &qpool5 &qpool6
 177                                                   &qpool7 &qpool8 &qpool9
 178                                                   &qpool10 &qpool11 &qpool12
 179                                                   &qpool13 &qpool14 &qpool15>;
 180                 };
 181         };
 182
 183         soc: soc@ffe000000 {
 184                 spi@110000 {
 185                         flash@0 {
 186                                 #address-cells = <1>;
 187                                 #size-cells = <1>;
 188                                 compatible = "spansion,s25sl12801";
 189                                 reg = <0>;
 190                                 spi-max-frequency = <40000000>; /* input clock */
 191                                 partition@u-boot {
 192                                         label = "u-boot";
 193                                         reg = <0x00000000 0x00100000>;
 194                                         read-only;
 195                                 };
 196                                 partition@kernel {
 197                                         label = "kernel";
 198                                         reg = <0x00100000 0x00500000>;
 199                                         read-only;
 200                                 };
 201                                 partition@dtb {
 202                                         label = "dtb";
 203                                         reg = <0x00600000 0x00100000>;
 204                                         read-only;
 205                                 };
 206                                 partition@fs {
 207                                         label = "file system";
 208                                         reg = <0x00700000 0x00900000>;
 209                                 };
 210                         };
 211                 };
 212
 213                 i2c@118100 {
 214                         eeprom@51 {
 215                                 compatible = "at24,24c256";
 216                                 reg = <0x51>;
 217                         };
 218                         eeprom@52 {
 219                                 compatible = "at24,24c256";
 220                                 reg = <0x52>;
 221                         };
 222                 };
 223
 224                 i2c@119100 {
 225                         rtc@68 {
 226                                 compatible = "dallas,ds3232";
 227                                 reg = <0x68>;
 228                                 interrupts = <0x1 0x1 0 0>;
 229                         };
 230                 };
 231
 232                 pme: pme@316000 {
 233                         /* Commented out, use default allocation */
 234                         /* fsl,pme-pdsr = <0x0 0x23000000 0x0 0x01000000>; */
 235                         /* fsl,pme-sre = <0x0 0x24000000 0x0 0x00a00000>; */
 236                 };
 237
 238                 qman: qman@318000 {
 239                         /* Commented out, use default allocation */
 240                         /* fsl,qman-fqd = <0x0 0x20000000 0x0 0x01000000>; */
 241                         /* fsl,qman-pfdr = <0x0 0x21000000 0x0 0x01000000>; */
 242                 };
 243
 244                 bman: bman@31a000 {
 245                         /* Same as fsl,qman-*, use default allocation */
 246                         /* fsl,bman-fbpr = <0x0 0x22000000 0x0 0x01000000>; */
 247                 };
 248
 249                 fman0: fman@400000 {
 250                         enet0: ethernet@e0000 {
 251                                 tbi-handle = <&tbi0>;
 252                                 phy-handle = <&phy_rgmii_0>;
 253                                 phy-connection-type = "rgmii";
 254                         };
 255
 256                         mdio0: mdio@e1120 {
 257                                 tbi0: tbi-phy@8 {
 258                                         reg = <0x8>;
 259                                         device_type = "tbi-phy";
 260                                 };
 261
 262                                 /*
 263                                  * Virtual MDIO for the two on-board RGMII
 264                                  * ports.  The fsl,hydra-mdio-muxval property
 265                                  * is already correct.
 266                                  */
 267                                 hydra_mdio_rgmii: hydra-mdio-rgmii {
 268                                         #address-cells = <1>;
 269                                         #size-cells = <0>;
 270                                         compatible = "fsl,hydra-mdio";
 271                                         fsl,mdio-handle = <&mdio0>;
 272                                         fsl,hydra-mdio-muxval = <0x00>;
 273                                         status = "disabled";
 274
 275                                         phy_rgmii_0: ethernet-phy@0 {
 276                                                 reg = <0x0>;
 277                                         };
 278                                         phy_rgmii_1: ethernet-phy@1 {
 279                                                 reg = <0x1>;
 280                                         };
 281                                 };
 282
 283                                 /*
 284                                  * Virtual MDIO for the four-port SGMII card.
 285                                  * The fsl,hydra-mdio-muxval property will be
 286                                  * fixed-up by U-Boot based on the slot that
 287                                  * the SGMII card is in.
 288                                  *
 289                                  * Note: we do not support DTSEC5 connected to
 290                                  * SGMII, so this is the only SGMII node.
 291                                  */
 292                                 hydra_mdio_sgmii: hydra-mdio-sgmii {
 293                                         #address-cells = <1>;
 294                                         #size-cells = <0>;
 295                                         compatible = "fsl,hydra-mdio";
 296                                         fsl,mdio-handle = <&mdio0>;
 297                                         fsl,hydra-mdio-muxval = <0x00>;
 298                                         status = "disabled";
 299
 300                                         phy_sgmii_1c: ethernet-phy@1c {
 301                                                 reg = <0x1c>;
 302                                         };
 303                                         phy_sgmii_1d: ethernet-phy@1d {
 304                                                 reg = <0x1d>;
 305                                         };
 306                                         phy_sgmii_1e: ethernet-phy@1e {
 307                                                 reg = <0x1e>;
 308                                         };
 309                                         phy_sgmii_1f: ethernet-phy@1f {
 310                                                 reg = <0x1f>;
 311                                         };
 312                                 };
 313                         };
 314
 315                         enet1: ethernet@e2000 {
 316                                 tbi-handle = <&tbi1>;
 317                                 phy-handle = <&phy_sgmii_1d>;
 318                                 phy-connection-type = "sgmii";
 319                         };
 320
 321                         mdio@e3120 {
 322                                 tbi1: tbi-phy@8 {
 323                                         reg = <8>;
 324                                         device_type = "tbi-phy";
 325                                 };
 326                         };
 327
 328                         enet2: ethernet@e4000 {
 329                                 tbi-handle = <&tbi2>;
 330                                 phy-handle = <&phy_sgmii_1e>;
 331                                 phy-connection-type = "sgmii";
 332                         };
 333
 334                         mdio@e5120 {
 335                                 tbi2: tbi-phy@8 {
 336                                         reg = <8>;
 337                                         device_type = "tbi-phy";
 338                                 };
 339                         };
 340
 341                         enet3: ethernet@e6000 {
 342                                 tbi-handle = <&tbi3>;
 343                                 phy-handle = <&phy_sgmii_1f>;
 344                                 phy-connection-type = "sgmii";
 345                         };
 346
 347                         mdio@e7120 {
 348                                 #address-cells = <1>;
 349                                 #size-cells = <0>;
 350                                 compatible = "fsl,fman-tbi";
 351                                 reg = <0xe7120 0xee0>;
 352                                 interrupts = <100 1 0 0>;
 353
 354                                 tbi3: tbi-phy@8 {
 355                                         reg = <8>;
 356                                         device_type = "tbi-phy";
 357                                 };
 358                         };
 359
 360                         enet4: ethernet@e8000 {
 361                                 tbi-handle = <&tbi4>;
 362                                 phy-handle = <&phy_rgmii_1>;
 363                                 phy-connection-type = "rgmii";
 364                         };
 365
 366                         mdio@e9120 {
 367                                 tbi4: tbi-phy@8 {
 368                                         reg = <8>;
 369                                         device_type = "tbi-phy";
 370                                 };
 371                         };
 372
 373                         enet5: ethernet@f0000 {
 374                                 /*
 375                                  * phy-handle will be updated by U-Boot to
 376                                  * reflect the actual slot the XAUI card is in.
 377                                  */
 378                                 phy-handle = <&phy_xgmii_1>;
 379                                 phy-connection-type = "xgmii";
 380                         };
 381
 382                         /*
 383                          * We only support one XAUI card, so the MDIO muxing
 384                          * is set by U-Boot, and Linux never touches it.
 385                          * Therefore, we don't need a virtual MDIO node.
 386                          * However, the phy address depends on the slot, so
 387                          * only one of the ethernet-phy nodes below will be
 388                          * used.
 389                          */
 390                         hydra_mdio_xgmii: mdio@f1000 {
 391                                 status = "disabled";
 392
 393                                 /* XAUI card in slot 1 */
 394                                 phy_xgmii_1: ethernet-phy@4 {
 395                                         reg = <0x4>;
 396                                 };
 397
 398                                 /* XAUI card in slot 2 */
 399                                 phy_xgmii_2: ethernet-phy@0 {
 400                                         reg = <0x0>;
 401                                 };
 402                         };
 403                 };
 404         };
 405
 406         rapidio@ffe0c0000 {
 407                 reg = <0xf 0xfe0c0000 0 0x11000>;
 408
 409                 port1 {
 410                         ranges = <0 0 0xc 0x20000000 0 0x10000000>;
 411                 };
 412                 port2 {
 413                         ranges = <0 0 0xc 0x30000000 0 0x10000000>;
 414                 };
 415         };
 416
 417         localbus@ffe124000 {
 418                 reg = <0xf 0xfe124000 0 0x1000>;
 419                 ranges = <0 0 0xf 0xb8000000 0x04000000>;
 420
 421                 flash@0,0 {
 422                         compatible = "cfi-flash";
 423                         /*
 424                          * Map 64Mb of 128MB NOR flash memory. Since highest
 425                          * line of address of NOR flash memory are set by
 426                          * FPGA, memory are divided into two pages equal to
 427                          * 64MB. One of the pages can be accessed at once.
 428                          */
 429                         reg = <0 0 0x04000000>;
 430                         bank-width = <2>;
 431                         device-width = <2>;
 432                 };
 433
 434                 nand@2,0 {
 435                         #address-cells = <1>;
 436                         #size-cells = <1>;
 437                         compatible = "fsl,elbc-fcm-nand";
 438                         reg = <0x2 0x0 0x40000>;
 439
 440                         partition@0 {
 441                                 label = "NAND U-Boot Image";
 442                                 reg = <0x0 0x02000000>;
 443                                 read-only;
 444                         };
 445
 446                         partition@2000000 {
 447                                 label = "NAND Root File System";
 448                                 reg = <0x02000000 0x10000000>;
 449                         };
 450
 451                         partition@12000000 {
 452                                 label = "NAND Compressed RFS Image";
 453                                 reg = <0x12000000 0x08000000>;
 454                         };
 455
 456                         partition@1a000000 {
 457                                 label = "NAND Linux Kernel Image";
 458                                 reg = <0x1a000000 0x04000000>;
 459                         };
 460
 461                         partition@1e000000 {
 462                                 label = "NAND DTB Image";
 463                                 reg = <0x1e000000 0x01000000>;
 464                         };
 465
 466                         partition@1f000000 {
 467                                 label = "NAND Writable User area";
 468                                 reg = <0x1f000000 0x21000000>;
 469                         };
 470                 };
 471
 472                 board-control@3,0 {
 473                         compatible = "fsl,p5020ds-fpga", "fsl,fpga-ngpixis";
 474                         reg = <3 0 0x30>;
 475                 };
 476         };
 477
 478         pci0: pcie@ffe200000 {
 479                 reg = <0xf 0xfe200000 0 0x1000>;
 480                 ranges = <0x02000000 0 0x80000000 0x0 0x80000000 0x0 0x10000000
 481                           0x01000000 0 0x00000000 0x0 0xff000000 0x0 0x00010000>;
 482                 pcie@0 {
 483                         ranges = <0x02000000 0 0x80000000
 484                                   0x02000000 0 0x80000000
 485                                   0 0x10000000
 486
 487                                   0x01000000 0 0x00000000
 488                                   0x01000000 0 0xff000000
 489                                   0 0x00010000>;
 490                 };
 491         };
 492
 493         pci1: pcie@ffe201000 {
 494                 reg = <0xf 0xfe201000 0 0x1000>;
 495                 ranges = <0x02000000 0x0 0x90000000 0x0 0x90000000 0x0 0x10000000
 496                           0x01000000 0x0 0x00000000 0x0 0xff010000 0x0 0x00010000>;
 497                 pcie@0 {
 498                         ranges = <0x02000000 0 0x90000000
 499                                   0x02000000 0 0x90000000
 500                                   0 0x10000000
 501
 502                                   0x01000000 0 0x00000000
 503                                   0x01000000 0 0xff010000
 504                                   0 0x00010000>;
 505                 };
 506         };
 507
 508         pci2: pcie@ffe202000 {
 509                 reg = <0xf 0xfe202000 0 0x1000>;
 510                 ranges = <0x02000000 0 0xa0000000 0x0 0xa0000000 0 0x10000000
 511                           0x01000000 0 0x00000000 0x0 0xff020000 0 0x00010000>;
 512                 pcie@0 {
 513                         ranges = <0x02000000 0 0xa0000000
 514                                   0x02000000 0 0xa0000000
 515                                   0 0x10000000
 516
 517                                   0x01000000 0 0x00000000
 518                                   0x01000000 0 0xff020000
 519                                   0 0x00010000>;
 520                 };
 521         };
 522
 523         pci3: pcie@ffe203000 {
 524                 reg = <0xf 0xfe203000 0 0x1000>;
 525                 ranges = <0x02000000 0 0xb0000000 0x0 0xb0000000 0 0x08000000
 526                           0x01000000 0 0x00000000 0x0 0xff030000 0 0x00010000>;
 527                 pcie@0 {
 528                         ranges = <0x02000000 0 0xb0000000
 529                                   0x02000000 0 0xb0000000
 530                                   0 0x08000000
 531
 532                                   0x01000000 0 0x00000000
 533                                   0x01000000 0 0xff030000
 534                                   0 0x00010000>;
 535                 };
 536         };
 537
 538         fsl,dpaa {
 539                 compatible = "fsl,p5020-dpaa", "fsl,dpaa";
 540
 541                 ethernet@0 {
 542                         compatible = "fsl,p5020-dpa-ethernet", "fsl,dpa-ethernet";
 543                         fsl,qman-channel = <&qpool1>;
 544                         fsl,fman-mac = <&enet0>;
 545                         status = "okay";
 546                 };
 547                 ethernet@1 {
 548                         compatible = "fsl,p5020-dpa-ethernet", "fsl,dpa-ethernet";
 549                         fsl,qman-channel = <&qpool1>;
 550                         fsl,fman-mac = <&enet1>;
 551                         status = "disabled";
 552                 };
 553                 ethernet@2 {
 554                         compatible = "fsl,p5020-dpa-ethernet", "fsl,dpa-ethernet";
 555                         fsl,qman-channel = <&qpool1>;
 556                         fsl,fman-mac = <&enet2>;
 557                         status = "disabled";
 558                 };
 559                 ethernet@3 {
 560                         compatible = "fsl,p5020-dpa-ethernet", "fsl,dpa-ethernet";
 561                         fsl,qman-channel = <&qpool1>;
 562                         fsl,fman-mac = <&enet3>;
 563                         status = "disabled";
 564                 };
 565                 ethernet@4 {
 566                         compatible = "fsl,p5020-dpa-ethernet", "fsl,dpa-ethernet";
 567                         fsl,qman-channel = <&qpool1>;
 568                         fsl,fman-mac = <&enet4>;
 569                         status = "okay";
 570                 };
 571                 ethernet@5 {
 572                         compatible = "fsl,p5020-dpa-ethernet", "fsl,dpa-ethernet";
 573                         fsl,qman-channel = <&qpool1>;
 574                         fsl,fman-mac = <&enet5>;
 575                         status = "disabled";
 576                 };
 577         };
 578
 579         chosen {
 580                 stdin = "serial0";
 581                 stdout = "serial0";
 582         };
 583 };