2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
14 * PERFORMANCE OF THIS SOFTWARE.
22 #include "ah_internal.h"
24 #include "ar9300/ar9300.h"
25 #include "ar9300/ar9300phy.h"
26 #include "ar9300/ar9300reg.h"
29 * Default 5413/9300 radar phy parameters
30 * Values adjusted to fix EV76432/EV76320
32 #define AR9300_DFS_FIRPWR -28
33 #define AR9300_DFS_RRSSI 0
34 #define AR9300_DFS_HEIGHT 10
35 #define AR9300_DFS_PRSSI 6
36 #define AR9300_DFS_INBAND 8
37 #define AR9300_DFS_RELPWR 8
38 #define AR9300_DFS_RELSTEP 12
39 #define AR9300_DFS_MAXLEN 255
42 * This PRSSI value should be used during CAC.
44 #define AR9300_DFS_PRSSI_CAC 10
47 * make sure that value matches value in ar9300_osprey_2p2_mac_core[][2]
48 * for register 0x1040 to 0x104c
50 #define AR9300_DEFAULT_DIFS 0x002ffc0f
51 #define AR9300_FCC_RADARS_FCC_OFFSET 4
53 struct dfs_pulse ar9300_etsi_radars[] = {
55 /* for short pulses, RSSI threshold should be smaller than
56 * Kquick-drop. The chip has only one chance to drop the gain which
57 * will be reported as the estimated RSSI */
59 /* TYPE staggered pulse */
60 /* 0.8-2us, 2-3 bursts,300-400 PRF, 10 pulses each */
61 {30, 2, 300, 400, 2, 30, 3, 0, 5, 15, 0, 0, 1, 31}, /* Type 5*/
62 /* 0.8-2us, 2-3 bursts, 400-1200 PRF, 15 pulses each */
63 {30, 2, 400, 1200, 2, 30, 7, 0, 5, 15, 0, 0, 0, 32}, /* Type 6 */
65 /* constant PRF based */
66 /* 0.8-5us, 200 300 PRF, 10 pulses */
67 {10, 5, 200, 400, 0, 24, 5, 0, 8, 15, 0, 0, 2, 33}, /* Type 1 */
68 {10, 5, 400, 600, 0, 24, 5, 0, 8, 15, 0, 0, 2, 37}, /* Type 1 */
69 {10, 5, 600, 800, 0, 24, 5, 0, 8, 15, 0, 0, 2, 38}, /* Type 1 */
70 {10, 5, 800, 1000, 0, 24, 5, 0, 8, 15, 0, 0, 2, 39}, /* Type 1 */
71 // {10, 5, 200, 1000, 0, 24, 5, 0, 8, 15, 0, 0, 2, 33},
73 /* 0.8-15us, 200-1600 PRF, 15 pulses */
74 {15, 15, 200, 1600, 0, 24, 8, 0, 18, 24, 0, 0, 0, 34}, /* Type 2 */
76 /* 0.8-15us, 2300-4000 PRF, 25 pulses*/
77 {25, 15, 2300, 4000, 0, 24, 10, 0, 18, 24, 0, 0, 0, 35}, /* Type 3 */
79 /* 20-30us, 2000-4000 PRF, 20 pulses*/
80 {20, 30, 2000, 4000, 0, 24, 8, 19, 33, 24, 0, 0, 0, 36}, /* Type 4 */
84 /* The following are for FCC Bin 1-4 pulses */
85 struct dfs_pulse ar9300_fcc_radars[] = {
87 /* following two filters are specific to Japan/MKK4 */
88 // {18, 1, 720, 720, 1, 6, 6, 0, 1, 18, 0, 3, 0, 17}, // 1389 +/- 6 us
89 // {18, 4, 250, 250, 1, 10, 5, 1, 6, 18, 0, 3, 0, 18}, // 4000 +/- 6 us
90 // {18, 5, 260, 260, 1, 10, 6, 1, 6, 18, 0, 3, 0, 19}, // 3846 +/- 7 us
91 {18, 1, 720, 720, 0, 6, 6, 0, 1, 18, 0, 3, 0, 17}, // 1389 +/- 6 us
92 {18, 4, 250, 250, 0, 10, 5, 1, 6, 18, 0, 3, 0, 18}, // 4000 +/- 6 us
93 {18, 5, 260, 260, 0, 10, 6, 1, 6, 18, 0, 3, 1, 19}, // 3846 +/- 7 us
94 // {18, 5, 260, 260, 1, 10, 6, 1, 6, 18, 0, 3, 1, 20}, // 3846 +/- 7 us
96 {18, 5, 260, 260, 1, 10, 6, 1, 6, 18, 0, 3, 1, 20}, // 3846 +/- 7 us
99 /* following filters are common to both FCC and JAPAN */
102 // {18, 1, 325, 1930, 0, 6, 7, 0, 1, 18, 0, 3, 0, 0}, // 518 to 3066
103 {18, 1, 700, 700, 0, 6, 5, 0, 1, 18, 0, 3, 1, 8},
104 {18, 1, 350, 350, 0, 6, 5, 0, 1, 18, 0, 3, 0, 0},
108 // {9, 1, 3003, 3003, 1, 7, 5, 0, 1, 18, 0, 0, 0, 1}, // 333 +/- 7 us
109 //{9, 1, 3003, 3003, 1, 7, 5, 0, 1, 18, 0, 0, 0, 1},
110 {9, 1, 3003, 3003, 0, 7, 5, 0, 1, 18, 0, 0, 1, 1},
113 {23, 5, 4347, 6666, 0, 18, 11, 0, 7, 22, 0, 3, 0, 2},
116 {18, 10, 2000, 5000, 0, 23, 8, 6, 13, 22, 0, 3, 0, 5},
119 {16, 15, 2000, 5000, 0, 25, 7, 11, 23, 22, 0, 3, 0, 11},
123 struct dfs_bin5pulse ar9300_bin5pulses[] = {
124 {2, 28, 105, 12, 22, 5},
130 * Find the internal HAL channel corresponding to the
131 * public HAL channel specified in c
134 static HAL_CHANNEL_INTERNAL *
135 getchannel(struct ath_hal *ah, const struct ieee80211_channel *c)
137 #define CHAN_FLAGS (CHANNEL_ALL | CHANNEL_HALF | CHANNEL_QUARTER)
138 HAL_CHANNEL_INTERNAL *base, *cc;
139 int flags = c->channel_flags & CHAN_FLAGS;
143 * Check current channel to avoid the lookup.
145 cc = AH_PRIVATE(ah)->ah_curchan;
146 if (cc != AH_NULL && cc->channel == c->channel &&
147 (cc->channel_flags & CHAN_FLAGS) == flags) {
151 /* binary search based on known sorting order */
152 base = AH_TABLES(ah)->ah_channels;
153 n = AH_PRIVATE(ah)->ah_nchan;
154 /* binary search based on known sorting order */
155 for (lim = n; lim != 0; lim >>= 1) {
157 cc = &base[lim >> 1];
158 d = c->channel - cc->channel;
160 if ((cc->channel_flags & CHAN_FLAGS) == flags) {
163 d = flags - (cc->channel_flags & CHAN_FLAGS);
165 HALDEBUG(ah, HAL_DEBUG_DFS, "%s: channel %u/0x%x d %d\n", __func__,
166 cc->channel, cc->channel_flags, d);
172 HALDEBUG(ah, HAL_DEBUG_DFS, "%s: no match for %u/0x%x\n",
173 __func__, c->channel, c->channel_flags);
179 * Check the internal channel list to see if the desired channel
180 * is ok to release from the NOL. If not, then do nothing. If so,
181 * mark the channel as clear and reset the internal tsf time
184 ar9300_check_dfs(struct ath_hal *ah, struct ieee80211_channel *chan)
186 HAL_CHANNEL_INTERNAL *ichan = AH_NULL;
188 ichan = getchannel(ah, chan);
189 if (ichan == AH_NULL) {
192 if (!(ichan->priv_flags & CHANNEL_INTERFERENCE)) {
196 ichan->priv_flags &= ~CHANNEL_INTERFERENCE;
201 * This function marks the channel as having found a dfs event
202 * It also marks the end time that the dfs event should be cleared
203 * If the channel is already marked, then tsf end time can only
207 ar9300_dfs_found(struct ath_hal *ah, struct ieee80211_channel *chan, u_int64_t nol_time)
209 HAL_CHANNEL_INTERNAL *ichan;
211 ichan = getchannel(ah, chan);
212 if (ichan == AH_NULL) {
215 if (!(ichan->priv_flags & CHANNEL_INTERFERENCE)) {
216 ichan->dfs_tsf = ar9300_get_tsf64(ah);
218 ichan->dfs_tsf += nol_time;
219 ichan->priv_flags |= CHANNEL_INTERFERENCE;
220 chan->priv_flags |= CHANNEL_INTERFERENCE;
225 * Enable radar detection and set the radar parameters per the
229 ar9300_enable_dfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
232 struct ath_hal_private *ahp = AH_PRIVATE(ah);
233 const struct ieee80211_channel *chan = ahp->ah_curchan;
234 struct ath_hal_9300 *ah9300 = AH9300(ah);
237 val = OS_REG_READ(ah, AR_PHY_RADAR_0);
238 val |= AR_PHY_RADAR_0_FFT_ENA | AR_PHY_RADAR_0_ENA;
239 if (pe->pe_firpwr != HAL_PHYERR_PARAM_NOVAL) {
240 val &= ~AR_PHY_RADAR_0_FIRPWR;
241 val |= SM(pe->pe_firpwr, AR_PHY_RADAR_0_FIRPWR);
243 if (pe->pe_rrssi != HAL_PHYERR_PARAM_NOVAL) {
244 val &= ~AR_PHY_RADAR_0_RRSSI;
245 val |= SM(pe->pe_rrssi, AR_PHY_RADAR_0_RRSSI);
247 if (pe->pe_height != HAL_PHYERR_PARAM_NOVAL) {
248 val &= ~AR_PHY_RADAR_0_HEIGHT;
249 val |= SM(pe->pe_height, AR_PHY_RADAR_0_HEIGHT);
251 if (pe->pe_prssi != HAL_PHYERR_PARAM_NOVAL) {
252 val &= ~AR_PHY_RADAR_0_PRSSI;
253 if (AR_SREV_AR9580(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) {
255 if (ah->ah_use_cac_prssi) {
256 val |= SM(AR9300_DFS_PRSSI_CAC, AR_PHY_RADAR_0_PRSSI);
259 val |= SM(pe->pe_prssi, AR_PHY_RADAR_0_PRSSI);
262 val |= SM(pe->pe_prssi, AR_PHY_RADAR_0_PRSSI);
265 if (pe->pe_inband != HAL_PHYERR_PARAM_NOVAL) {
266 val &= ~AR_PHY_RADAR_0_INBAND;
267 val |= SM(pe->pe_inband, AR_PHY_RADAR_0_INBAND);
269 OS_REG_WRITE(ah, AR_PHY_RADAR_0, val);
271 val = OS_REG_READ(ah, AR_PHY_RADAR_1);
272 val |= AR_PHY_RADAR_1_MAX_RRSSI | AR_PHY_RADAR_1_BLOCK_CHECK;
273 if (pe->pe_maxlen != HAL_PHYERR_PARAM_NOVAL) {
274 val &= ~AR_PHY_RADAR_1_MAXLEN;
275 val |= SM(pe->pe_maxlen, AR_PHY_RADAR_1_MAXLEN);
277 if (pe->pe_relstep != HAL_PHYERR_PARAM_NOVAL) {
278 val &= ~AR_PHY_RADAR_1_RELSTEP_THRESH;
279 val |= SM(pe->pe_relstep, AR_PHY_RADAR_1_RELSTEP_THRESH);
281 if (pe->pe_relpwr != HAL_PHYERR_PARAM_NOVAL) {
282 val &= ~AR_PHY_RADAR_1_RELPWR_THRESH;
283 val |= SM(pe->pe_relpwr, AR_PHY_RADAR_1_RELPWR_THRESH);
285 OS_REG_WRITE(ah, AR_PHY_RADAR_1, val);
287 if (ath_hal_getcapability(ah, HAL_CAP_EXT_CHAN_DFS, 0, 0) == HAL_OK) {
288 val = OS_REG_READ(ah, AR_PHY_RADAR_EXT);
289 if (IEEE80211_IS_CHAN_HT40(chan)) {
290 /* Enable extension channel radar detection */
291 OS_REG_WRITE(ah, AR_PHY_RADAR_EXT, val | AR_PHY_RADAR_EXT_ENA);
293 /* HT20 mode, disable extension channel radar detect */
294 OS_REG_WRITE(ah, AR_PHY_RADAR_EXT, val & ~AR_PHY_RADAR_EXT_ENA);
298 apply DFS postamble array from INI
299 column 0 is register ID, column 1 is HT20 value, colum2 is HT40 value
302 if (AR_SREV_AR9580(ah) || AR_SREV_WASP(ah) || AR_SREV_OSPREY_22(ah) || AR_SREV_SCORPION(ah)) {
303 REG_WRITE_ARRAY(&ah9300->ah_ini_dfs, IEEE80211_IS_CHAN_HT40(chan)? 2:1, reg_writes);
305 #ifdef ATH_HAL_DFS_CHIRPING_FIX_APH128
306 ath_hal_printf(ah, "DFS change the timing value\n");
307 if (AR_SREV_AR9580(ah) && IEEE80211_IS_CHAN_HT40(chan)) {
308 OS_REG_WRITE(ah, AR_PHY_TIMING6, 0x3140c00a);
315 * Get the radar parameter values and return them in the pe
319 ar9300_get_dfs_thresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
323 val = OS_REG_READ(ah, AR_PHY_RADAR_0);
324 temp = MS(val, AR_PHY_RADAR_0_FIRPWR);
325 temp |= ~(AR_PHY_RADAR_0_FIRPWR >> AR_PHY_RADAR_0_FIRPWR_S);
326 pe->pe_firpwr = temp;
327 pe->pe_rrssi = MS(val, AR_PHY_RADAR_0_RRSSI);
328 pe->pe_height = MS(val, AR_PHY_RADAR_0_HEIGHT);
329 pe->pe_prssi = MS(val, AR_PHY_RADAR_0_PRSSI);
330 pe->pe_inband = MS(val, AR_PHY_RADAR_0_INBAND);
332 val = OS_REG_READ(ah, AR_PHY_RADAR_1);
334 pe->pe_relpwr = MS(val, AR_PHY_RADAR_1_RELPWR_THRESH);
335 pe->pe_enrelpwr = !! (val & AR_PHY_RADAR_1_RELPWR_ENA);
337 pe->pe_relstep = MS(val, AR_PHY_RADAR_1_RELSTEP_THRESH);
338 pe->pe_en_relstep_check = !! (val & AR_PHY_RADAR_1_RELSTEP_CHECK);
340 pe->pe_maxlen = MS(val, AR_PHY_RADAR_1_MAXLEN);
345 ar9300_radar_wait(struct ath_hal *ah, struct ieee80211_channel *chan)
347 struct ath_hal_private *ahp = AH_PRIVATE(ah);
349 if (!ahp->ah_curchan) {
354 * Rely on the upper layers to determine that we have spent
355 * enough time waiting.
357 chan->channel = ahp->ah_curchan->channel;
358 chan->channel_flags = ahp->ah_curchan->channel_flags;
359 chan->max_reg_tx_power = ahp->ah_curchan->max_reg_tx_power;
361 ahp->ah_curchan->priv_flags |= CHANNEL_DFS_CLEAR;
362 chan->priv_flags = ahp->ah_curchan->priv_flags;
369 ar9300_get_dfs_radars(
373 struct dfs_bin5pulse **bin5pulses,
375 HAL_PHYERR_PARAM *pe)
377 struct dfs_pulse *dfs_radars = AH_NULL;
379 case HAL_DFS_FCC_DOMAIN:
380 dfs_radars = &ar9300_fcc_radars[AR9300_FCC_RADARS_FCC_OFFSET];
382 ARRAY_LENGTH(ar9300_fcc_radars) - AR9300_FCC_RADARS_FCC_OFFSET;
383 *bin5pulses = &ar9300_bin5pulses[0];
384 *numb5radars = ARRAY_LENGTH(ar9300_bin5pulses);
385 HALDEBUG(ah, HAL_DEBUG_DFS, "%s: DFS_FCC_DOMAIN_9300\n", __func__);
387 case HAL_DFS_ETSI_DOMAIN:
388 dfs_radars = &ar9300_etsi_radars[0];
389 *numradars = ARRAY_LENGTH(ar9300_etsi_radars);
390 *bin5pulses = &ar9300_bin5pulses[0];
391 *numb5radars = ARRAY_LENGTH(ar9300_bin5pulses);
392 HALDEBUG(ah, HAL_DEBUG_DFS, "%s: DFS_ETSI_DOMAIN_9300\n", __func__);
394 case HAL_DFS_MKK4_DOMAIN:
395 dfs_radars = &ar9300_fcc_radars[0];
396 *numradars = ARRAY_LENGTH(ar9300_fcc_radars);
397 *bin5pulses = &ar9300_bin5pulses[0];
398 *numb5radars = ARRAY_LENGTH(ar9300_bin5pulses);
399 HALDEBUG(ah, HAL_DEBUG_DFS, "%s: DFS_MKK4_DOMAIN_9300\n", __func__);
402 HALDEBUG(ah, HAL_DEBUG_DFS, "%s: no domain\n", __func__);
405 /* Set the default phy parameters per chip */
406 pe->pe_firpwr = AR9300_DFS_FIRPWR;
407 pe->pe_rrssi = AR9300_DFS_RRSSI;
408 pe->pe_height = AR9300_DFS_HEIGHT;
409 pe->pe_prssi = AR9300_DFS_PRSSI;
411 we have an issue with PRSSI.
412 For normal operation we use AR9300_DFS_PRSSI, which is set to 6.
413 Please refer to EV91563, 94164.
414 However, this causes problem during CAC as no radar is detected
415 during that period with PRSSI=6. Only PRSSI= 10 seems to fix this.
416 We use this flag to keep track of change in PRSSI.
419 // ah->ah_use_cac_prssi = 0;
421 pe->pe_inband = AR9300_DFS_INBAND;
422 pe->pe_relpwr = AR9300_DFS_RELPWR;
423 pe->pe_relstep = AR9300_DFS_RELSTEP;
424 pe->pe_maxlen = AR9300_DFS_MAXLEN;
428 void ar9300_adjust_difs(struct ath_hal *ah, u_int32_t val)
433 * Restore the register values with that of the HAL structure.
434 * Do not assume and overwrite these values to whatever
435 * is in ar9300_osprey22.ini.
437 struct ath_hal_9300 *ahp = AH9300(ah);
438 HAL_TX_QUEUE_INFO *qi;
441 AH9300(ah)->ah_fccaifs = 0;
442 HALDEBUG(ah, HAL_DEBUG_DFS, "%s: restore DIFS \n", __func__);
443 for (q = 0; q < 4; q++) {
444 qi = &ahp->ah_txq[q];
445 OS_REG_WRITE(ah, AR_DLCL_IFS(q),
446 SM(qi->tqi_cwmin, AR_D_LCL_IFS_CWMIN)
447 | SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX)
448 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
452 * These are values from George Lai and are specific to
453 * FCC domain. They are yet to be determined for other domains.
456 AH9300(ah)->ah_fccaifs = 1;
457 HALDEBUG(ah, HAL_DEBUG_DFS, "%s: set DIFS to default\n", __func__);
458 /*printk("%s: modify DIFS\n", __func__);*/
460 OS_REG_WRITE(ah, AR_DLCL_IFS(0), 0x05fffc0f);
461 OS_REG_WRITE(ah, AR_DLCL_IFS(1), 0x05f0fc0f);
462 OS_REG_WRITE(ah, AR_DLCL_IFS(2), 0x05f03c07);
463 OS_REG_WRITE(ah, AR_DLCL_IFS(3), 0x05f01c03);
467 u_int32_t ar9300_dfs_config_fft(struct ath_hal *ah, HAL_BOOL is_enable)
471 val = OS_REG_READ(ah, AR_PHY_RADAR_0);
474 val |= AR_PHY_RADAR_0_FFT_ENA;
476 val &= ~AR_PHY_RADAR_0_FFT_ENA;
479 OS_REG_WRITE(ah, AR_PHY_RADAR_0, val);
480 val = OS_REG_READ(ah, AR_PHY_RADAR_0);
484 function to adjust PRSSI value for CAC problem
488 ar9300_dfs_cac_war(struct ath_hal *ah, u_int32_t start)
492 if (AR_SREV_AR9580(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) {
493 val = OS_REG_READ(ah, AR_PHY_RADAR_0);
495 val &= ~AR_PHY_RADAR_0_PRSSI;
496 val |= SM(AR9300_DFS_PRSSI_CAC, AR_PHY_RADAR_0_PRSSI);
498 val &= ~AR_PHY_RADAR_0_PRSSI;
499 val |= SM(AR9300_DFS_PRSSI, AR_PHY_RADAR_0_PRSSI);
501 OS_REG_WRITE(ah, AR_PHY_RADAR_0, val | AR_PHY_RADAR_0_ENA);
502 // ah->ah_use_cac_prssi = start;
507 struct ieee80211_channel *
508 ar9300_get_extension_channel(struct ath_hal *ah)
510 struct ath_hal_private *ahp = AH_PRIVATE(ah);
511 struct ath_hal_private_tables *aht = AH_TABLES(ah);
514 HAL_CHANNEL_INTERNAL *ichan = AH_NULL;
515 CHAN_CENTERS centers;
517 ichan = ahp->ah_curchan;
518 ar9300_get_channel_centers(ah, ichan, ¢ers);
519 if (centers.ctl_center == centers.ext_center) {
522 for (i = 0; i < ahp->ah_nchan; i++) {
523 ichan = &aht->ah_channels[i];
524 if (ichan->channel == centers.ext_center) {
525 return (struct ieee80211_channel*)ichan;
533 ar9300_is_fast_clock_enabled(struct ath_hal *ah)
535 struct ath_hal_private *ahp = AH_PRIVATE(ah);
537 if (IS_5GHZ_FAST_CLOCK_EN(ah, ahp->ah_curchan)) {
544 * This should be enabled and linked into the build once
545 * radar support is enabled.
549 ar9300_handle_radar_bb_panic(struct ath_hal *ah)
554 struct ath_hal_9300 *ahp = AH9300(ah);
557 status = AH_PRIVATE(ah)->ah_bb_panic_last_status;
559 if ( status == 0x04000539 ) {
560 /* recover from this BB panic without reset*/
561 /* set AR9300_DFS_FIRPWR to -1 */
562 val = OS_REG_READ(ah, AR_PHY_RADAR_0);
563 val &= (~AR_PHY_RADAR_0_FIRPWR);
564 val |= SM( 0x7f, AR_PHY_RADAR_0_FIRPWR);
565 OS_REG_WRITE(ah, AR_PHY_RADAR_0, val);
567 /* set AR9300_DFS_FIRPWR to its default value */
568 val = OS_REG_READ(ah, AR_PHY_RADAR_0);
569 val &= ~AR_PHY_RADAR_0_FIRPWR;
570 val |= SM( AR9300_DFS_FIRPWR, AR_PHY_RADAR_0_FIRPWR);
571 OS_REG_WRITE(ah, AR_PHY_RADAR_0, val);
573 } else if (status == 0x0400000a) {
574 /* EV 92527 : reset required if we see this signature */
575 HALDEBUG(ah, HAL_DEBUG_DFS, "%s: BB Panic -- 0x0400000a\n", __func__);
577 } else if (status == 0x1300000a) {
578 /* EV92527: we do not need a reset if we see this signature */
579 HALDEBUG(ah, HAL_DEBUG_DFS, "%s: BB Panic -- 0x1300000a\n", __func__);
581 } else if (AR_SREV_WASP(ah) && (status == 0x04000409)) {
584 if (ar9300_get_capability(ah, HAL_CAP_LDPCWAR, 0, AH_NULL) == HAL_OK &&
585 (status & 0xff00000f) == 0x04000009 &&
586 status != 0x04000409 &&
587 status != 0x04000b09 &&
588 status != 0x04000e09 &&
589 (status & 0x0000ff00))
591 /* disable RIFS Rx */
593 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "%s: BB status=0x%08x rifs=%d - disable\n",
594 __func__, status, ahp->ah_rifs_enabled);
595 ar9300_set_rifs_delay(ah, AH_FALSE);