sys/contrib/dev/ath/ath_hal/ar9300/poseidon_reg_map_macro.h

   1 /*
   2  * Copyright (c) 2013 Qualcomm Atheros, Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
   9  * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
  10  * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
  11  * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
  12  * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
  13  * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  14  * PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 /*                                                                           */
  18 /* File:       /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/top/poseidon_reg_map_macro.h*/
  19 /* Creator:    kcwo                                                          */
  20 /* Time:       Tuesday Nov 2, 2010 [5:38:25 pm]                              */
  21 /*                                                                           */
  22 /* Path:       /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/top   */
  23 /* Arguments:  /cad/denali/blueprint/3.7.3//Linux-64bit/blueprint -codegen   */
  24 /*             /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/env/blueprint/ath_ansic.codegen*/
  25 /*             -ath_ansic -Wdesc -I                                          */
  26 /*             /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/top -I*/
  27 /*             /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint -I    */
  28 /*             /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/env/blueprint -I*/
  29 /*             /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig*/
  30 /*             -odir                                                         */
  31 /*             /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/top   */
  32 /*             -eval {$INCLUDE_SYSCONFIG_FILES=1} -eval                      */
  33 /*             $WAR_EV58615_for_ansic_codegen=1 poseidon_reg.rdl             */
  34 /*                                                                           */
  35 /* Sources:    /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/rtc/blueprint/rtc_reg.rdl*/
  36 /*             /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/mac_pcu_reg_sysconfig.rdl*/
  37 /*             /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/host_intf/rtl/blueprint/host_intf_reg.rdl*/
  38 /*             /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/merlin2_0_radio_reg_sysconfig.rdl*/
  39 /*             /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/rtc_reg_sysconfig.rdl*/
  40 /*             /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/mac/rtl/mac_dma/blueprint/mac_dma_reg.rdl*/
  41 /*             /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/top/poseidon_reg.rdl*/
  42 /*             /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/efuse_reg_sysconfig.rdl*/
  43 /*             /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/top/merlin2_0_radio_reg_map.rdl*/
  44 /*             /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/mac/rtl/mac_dma/blueprint/mac_dcu_reg.rdl*/
  45 /*             /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/mac_dma_reg_sysconfig.rdl*/
  46 /*             /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/mac/rtl/mac_pcu/blueprint/mac_pcu_reg.rdl*/
  47 /*             /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/bb/blueprint/bb_reg_map.rdl*/
  48 /*             /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/mac/rtl/mac_dma/blueprint/mac_qcu_reg.rdl*/
  49 /*             /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/apb_analog/analog_intf_reg.rdl*/
  50 /*             /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/top/emulation_misc.rdl*/
  51 /*             /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/top/pcie_phy_reg_csr.rdl*/
  52 /*             /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/analog_intf_reg_sysconfig.rdl*/
  53 /*             /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/svd_reg_sysconfig.rdl*/
  54 /*             /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/top/poseidon_radio_reg.rdl*/
  55 /*             /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/host_intf/rtl/blueprint/efuse_reg.rdl*/
  56 /*             /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/amba_mac/svd/blueprint/svd_reg.rdl*/
  57 /*             /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/mac_qcu_reg_sysconfig.rdl*/
  58 /*             /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/radio_65_reg_sysconfig.rdl*/
  59 /*             /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/rtc_sync_reg_sysconfig.rdl*/
  60 /*             /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/amba_mac/blueprint/rtc_sync_reg.rdl*/
  61 /*             /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/pcie_phy_reg_csr_sysconfig.rdl*/
  62 /*             /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/bb_reg_map_sysconfig.rdl*/
  63 /*             /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/mac_dcu_reg_sysconfig.rdl*/
  64 /*             /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/env/blueprint/ath_ansic.pm*/
  65 /*             /cad/local/lib/perl/Pinfo.pm                                  */
  66 /*                                                                           */
  67 /* Blueprint:   3.7.3 (Fri Aug 29 12:39:16 PDT 2008)                         */
  68 /* Machine:    zydasc19                                                      */
  69 /* OS:         Linux 2.6.9-78.0.8.ELsmp                                      */
  70 /* Description:                                                              */
  71 /*                                                                           */
  72 /*This Register Map contains the complete register set for Poseidon.         */
  73 /*                                                                           */
  74 /* Copyright (C) 2010 Denali Software Inc.  All rights reserved              */
  75 /* THIS FILE IS AUTOMATICALLY GENERATED BY DENALI BLUEPRINT, DO NOT EDIT     */
  76 /*                                                                           */
  77
  78
  79 #ifndef __REG_POSEIDON_REG_MAP_MACRO_H__
  80 #define __REG_POSEIDON_REG_MAP_MACRO_H__
  81
  82 /* macros for BlueprintGlobalNameSpace::AXI_INTERCONNECT_CTRL */
  83 #ifndef __AXI_INTERCONNECT_CTRL_MACRO__
  84 #define __AXI_INTERCONNECT_CTRL_MACRO__
  85
  86 /* macros for field FORCE_SEL_ON */
  87 #define AXI_INTERCONNECT_CTRL__FORCE_SEL_ON__SHIFT                            0
  88 #define AXI_INTERCONNECT_CTRL__FORCE_SEL_ON__WIDTH                            1
  89 #define AXI_INTERCONNECT_CTRL__FORCE_SEL_ON__MASK                   0x00000001U
  90 #define AXI_INTERCONNECT_CTRL__FORCE_SEL_ON__READ(src) \
  91                     (u_int32_t)(src)\
  92                     & 0x00000001U
  93 #define AXI_INTERCONNECT_CTRL__FORCE_SEL_ON__WRITE(src) \
  94                     ((u_int32_t)(src)\
  95                     & 0x00000001U)
  96 #define AXI_INTERCONNECT_CTRL__FORCE_SEL_ON__MODIFY(dst, src) \
  97                     (dst) = ((dst) &\
  98                     ~0x00000001U) | ((u_int32_t)(src) &\
  99                     0x00000001U)
 100 #define AXI_INTERCONNECT_CTRL__FORCE_SEL_ON__VERIFY(src) \
 101                     (!(((u_int32_t)(src)\
 102                     & ~0x00000001U)))
 103 #define AXI_INTERCONNECT_CTRL__FORCE_SEL_ON__SET(dst) \
 104                     (dst) = ((dst) &\
 105                     ~0x00000001U) | (u_int32_t)(1)
 106 #define AXI_INTERCONNECT_CTRL__FORCE_SEL_ON__CLR(dst) \
 107                     (dst) = ((dst) &\
 108                     ~0x00000001U) | (u_int32_t)(0)
 109
 110 /* macros for field SELECT_SLV_PCIE */
 111 #define AXI_INTERCONNECT_CTRL__SELECT_SLV_PCIE__SHIFT                         1
 112 #define AXI_INTERCONNECT_CTRL__SELECT_SLV_PCIE__WIDTH                         1
 113 #define AXI_INTERCONNECT_CTRL__SELECT_SLV_PCIE__MASK                0x00000002U
 114 #define AXI_INTERCONNECT_CTRL__SELECT_SLV_PCIE__READ(src) \
 115                     (((u_int32_t)(src)\
 116                     & 0x00000002U) >> 1)
 117 #define AXI_INTERCONNECT_CTRL__SELECT_SLV_PCIE__WRITE(src) \
 118                     (((u_int32_t)(src)\
 119                     << 1) & 0x00000002U)
 120 #define AXI_INTERCONNECT_CTRL__SELECT_SLV_PCIE__MODIFY(dst, src) \
 121                     (dst) = ((dst) &\
 122                     ~0x00000002U) | (((u_int32_t)(src) <<\
 123                     1) & 0x00000002U)
 124 #define AXI_INTERCONNECT_CTRL__SELECT_SLV_PCIE__VERIFY(src) \
 125                     (!((((u_int32_t)(src)\
 126                     << 1) & ~0x00000002U)))
 127 #define AXI_INTERCONNECT_CTRL__SELECT_SLV_PCIE__SET(dst) \
 128                     (dst) = ((dst) &\
 129                     ~0x00000002U) | ((u_int32_t)(1) << 1)
 130 #define AXI_INTERCONNECT_CTRL__SELECT_SLV_PCIE__CLR(dst) \
 131                     (dst) = ((dst) &\
 132                     ~0x00000002U) | ((u_int32_t)(0) << 1)
 133
 134 /* macros for field SW_WOW_ENABLE */
 135 #define AXI_INTERCONNECT_CTRL__SW_WOW_ENABLE__SHIFT                           2
 136 #define AXI_INTERCONNECT_CTRL__SW_WOW_ENABLE__WIDTH                           1
 137 #define AXI_INTERCONNECT_CTRL__SW_WOW_ENABLE__MASK                  0x00000004U
 138 #define AXI_INTERCONNECT_CTRL__SW_WOW_ENABLE__READ(src) \
 139                     (((u_int32_t)(src)\
 140                     & 0x00000004U) >> 2)
 141 #define AXI_INTERCONNECT_CTRL__SW_WOW_ENABLE__WRITE(src) \
 142                     (((u_int32_t)(src)\
 143                     << 2) & 0x00000004U)
 144 #define AXI_INTERCONNECT_CTRL__SW_WOW_ENABLE__MODIFY(dst, src) \
 145                     (dst) = ((dst) &\
 146                     ~0x00000004U) | (((u_int32_t)(src) <<\
 147                     2) & 0x00000004U)
 148 #define AXI_INTERCONNECT_CTRL__SW_WOW_ENABLE__VERIFY(src) \
 149                     (!((((u_int32_t)(src)\
 150                     << 2) & ~0x00000004U)))
 151 #define AXI_INTERCONNECT_CTRL__SW_WOW_ENABLE__SET(dst) \
 152                     (dst) = ((dst) &\
 153                     ~0x00000004U) | ((u_int32_t)(1) << 2)
 154 #define AXI_INTERCONNECT_CTRL__SW_WOW_ENABLE__CLR(dst) \
 155                     (dst) = ((dst) &\
 156                     ~0x00000004U) | ((u_int32_t)(0) << 2)
 157 #define AXI_INTERCONNECT_CTRL__TYPE                                   u_int32_t
 158 #define AXI_INTERCONNECT_CTRL__READ                                 0x00000007U
 159 #define AXI_INTERCONNECT_CTRL__WRITE                                0x00000007U
 160
 161 #endif /* __AXI_INTERCONNECT_CTRL_MACRO__ */
 162
 163
 164 /* macros for host_intf_reg_block.AXI_INTERCONNECT_CTRL */
 165 #define INST_HOST_INTF_REG_BLOCK__AXI_INTERCONNECT_CTRL__NUM                  1
 166
 167 /* macros for BlueprintGlobalNameSpace::green_tx_control_1 */
 168 #ifndef __GREEN_TX_CONTROL_1_MACRO__
 169 #define __GREEN_TX_CONTROL_1_MACRO__
 170
 171 /* macros for field green_tx_enable */
 172 #define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__SHIFT                            0
 173 #define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__WIDTH                            1
 174 #define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__MASK                   0x00000001U
 175 #define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__READ(src) \
 176                     (u_int32_t)(src)\
 177                     & 0x00000001U
 178 #define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__WRITE(src) \
 179                     ((u_int32_t)(src)\
 180                     & 0x00000001U)
 181 #define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__MODIFY(dst, src) \
 182                     (dst) = ((dst) &\
 183                     ~0x00000001U) | ((u_int32_t)(src) &\
 184                     0x00000001U)
 185 #define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__VERIFY(src) \
 186                     (!(((u_int32_t)(src)\
 187                     & ~0x00000001U)))
 188 #define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__SET(dst) \
 189                     (dst) = ((dst) &\
 190                     ~0x00000001U) | (u_int32_t)(1)
 191 #define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__CLR(dst) \
 192                     (dst) = ((dst) &\
 193                     ~0x00000001U) | (u_int32_t)(0)
 194
 195 /* macros for field green_cases */
 196 #define GREEN_TX_CONTROL_1__GREEN_CASES__SHIFT                                1
 197 #define GREEN_TX_CONTROL_1__GREEN_CASES__WIDTH                                1
 198 #define GREEN_TX_CONTROL_1__GREEN_CASES__MASK                       0x00000002U
 199 #define GREEN_TX_CONTROL_1__GREEN_CASES__READ(src) \
 200                     (((u_int32_t)(src)\
 201                     & 0x00000002U) >> 1)
 202 #define GREEN_TX_CONTROL_1__GREEN_CASES__WRITE(src) \
 203                     (((u_int32_t)(src)\
 204                     << 1) & 0x00000002U)
 205 #define GREEN_TX_CONTROL_1__GREEN_CASES__MODIFY(dst, src) \
 206                     (dst) = ((dst) &\
 207                     ~0x00000002U) | (((u_int32_t)(src) <<\
 208                     1) & 0x00000002U)
 209 #define GREEN_TX_CONTROL_1__GREEN_CASES__VERIFY(src) \
 210                     (!((((u_int32_t)(src)\
 211                     << 1) & ~0x00000002U)))
 212 #define GREEN_TX_CONTROL_1__GREEN_CASES__SET(dst) \
 213                     (dst) = ((dst) &\
 214                     ~0x00000002U) | ((u_int32_t)(1) << 1)
 215 #define GREEN_TX_CONTROL_1__GREEN_CASES__CLR(dst) \
 216                     (dst) = ((dst) &\
 217                     ~0x00000002U) | ((u_int32_t)(0) << 1)
 218 #define GREEN_TX_CONTROL_1__TYPE                                      u_int32_t
 219 #define GREEN_TX_CONTROL_1__READ                                    0x00000003U
 220 #define GREEN_TX_CONTROL_1__WRITE                                   0x00000003U
 221
 222 #endif /* __GREEN_TX_CONTROL_1_MACRO__ */
 223
 224 /* macros for BlueprintGlobalNameSpace::bb_reg_page_control */
 225 #ifndef __BB_REG_PAGE_CONTROL_MACRO__
 226 #define __BB_REG_PAGE_CONTROL_MACRO__
 227
 228 /* macros for field disable_bb_reg_page */
 229 #define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__SHIFT                       0
 230 #define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__WIDTH                       1
 231 #define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__MASK              0x00000001U
 232 #define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__READ(src) \
 233                     (u_int32_t)(src)\
 234                     & 0x00000001U
 235 #define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__WRITE(src) \
 236                     ((u_int32_t)(src)\
 237                     & 0x00000001U)
 238 #define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__MODIFY(dst, src) \
 239                     (dst) = ((dst) &\
 240                     ~0x00000001U) | ((u_int32_t)(src) &\
 241                     0x00000001U)
 242 #define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__VERIFY(src) \
 243                     (!(((u_int32_t)(src)\
 244                     & ~0x00000001U)))
 245 #define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__SET(dst) \
 246                     (dst) = ((dst) &\
 247                     ~0x00000001U) | (u_int32_t)(1)
 248 #define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__CLR(dst) \
 249                     (dst) = ((dst) &\
 250                     ~0x00000001U) | (u_int32_t)(0)
 251
 252 /* macros for field bb_register_page */
 253 #define BB_REG_PAGE_CONTROL__BB_REGISTER_PAGE__SHIFT                          1
 254 #define BB_REG_PAGE_CONTROL__BB_REGISTER_PAGE__WIDTH                          3
 255 #define BB_REG_PAGE_CONTROL__BB_REGISTER_PAGE__MASK                 0x0000000eU
 256 #define BB_REG_PAGE_CONTROL__BB_REGISTER_PAGE__READ(src) \
 257                     (((u_int32_t)(src)\
 258                     & 0x0000000eU) >> 1)
 259 #define BB_REG_PAGE_CONTROL__BB_REGISTER_PAGE__WRITE(src) \
 260                     (((u_int32_t)(src)\
 261                     << 1) & 0x0000000eU)
 262 #define BB_REG_PAGE_CONTROL__BB_REGISTER_PAGE__MODIFY(dst, src) \
 263                     (dst) = ((dst) &\
 264                     ~0x0000000eU) | (((u_int32_t)(src) <<\
 265                     1) & 0x0000000eU)
 266 #define BB_REG_PAGE_CONTROL__BB_REGISTER_PAGE__VERIFY(src) \
 267                     (!((((u_int32_t)(src)\
 268                     << 1) & ~0x0000000eU)))
 269
 270 /* macros for field direct_access_page */
 271 #define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__SHIFT                        4
 272 #define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__WIDTH                        1
 273 #define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__MASK               0x00000010U
 274 #define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__READ(src) \
 275                     (((u_int32_t)(src)\
 276                     & 0x00000010U) >> 4)
 277 #define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__WRITE(src) \
 278                     (((u_int32_t)(src)\
 279                     << 4) & 0x00000010U)
 280 #define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__MODIFY(dst, src) \
 281                     (dst) = ((dst) &\
 282                     ~0x00000010U) | (((u_int32_t)(src) <<\
 283                     4) & 0x00000010U)
 284 #define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__VERIFY(src) \
 285                     (!((((u_int32_t)(src)\
 286                     << 4) & ~0x00000010U)))
 287 #define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__SET(dst) \
 288                     (dst) = ((dst) &\
 289                     ~0x00000010U) | ((u_int32_t)(1) << 4)
 290 #define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__CLR(dst) \
 291                     (dst) = ((dst) &\
 292                     ~0x00000010U) | ((u_int32_t)(0) << 4)
 293 #define BB_REG_PAGE_CONTROL__TYPE                                     u_int32_t
 294 #define BB_REG_PAGE_CONTROL__READ                                   0x0000001fU
 295 #define BB_REG_PAGE_CONTROL__WRITE                                  0x0000001fU
 296
 297 #endif /* __BB_REG_PAGE_CONTROL_MACRO__ */
 298
 299
 300 /* macros for bb_reg_block.bb_bbb_reg_map.BB_bb_reg_page_control */
 301 #define INST_BB_REG_BLOCK__BB_BBB_REG_MAP__BB_BB_REG_PAGE_CONTROL__NUM        1
 302
 303 /* macros for BlueprintGlobalNameSpace::peak_det_ctrl_1 */
 304
 305 /* macros for field peak_det_tally_thr_low_0 */
 306 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__SHIFT                      8
 307 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__WIDTH                      5
 308 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__MASK             0x00001f00U
 309 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__READ(src) \
 310                     (((u_int32_t)(src)\
 311                     & 0x00001f00U) >> 8)
 312 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__WRITE(src) \
 313                     (((u_int32_t)(src)\
 314                     << 8) & 0x00001f00U)
 315 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__MODIFY(dst, src) \
 316                     (dst) = ((dst) &\
 317                     ~0x00001f00U) | (((u_int32_t)(src) <<\
 318                     8) & 0x00001f00U)
 319 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__VERIFY(src) \
 320                     (!((((u_int32_t)(src)\
 321                     << 8) & ~0x00001f00U)))
 322
 323 /* macros for field peak_det_tally_thr_med_0 */
 324 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__SHIFT                     13
 325 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__WIDTH                      5
 326 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__MASK             0x0003e000U
 327 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__READ(src) \
 328                     (((u_int32_t)(src)\
 329                     & 0x0003e000U) >> 13)
 330 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__WRITE(src) \
 331                     (((u_int32_t)(src)\
 332                     << 13) & 0x0003e000U)
 333 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__MODIFY(dst, src) \
 334                     (dst) = ((dst) &\
 335                     ~0x0003e000U) | (((u_int32_t)(src) <<\
 336                     13) & 0x0003e000U)
 337 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__VERIFY(src) \
 338                     (!((((u_int32_t)(src)\
 339                     << 13) & ~0x0003e000U)))
 340
 341 /* macros for field peak_det_tally_thr_high_0 */
 342 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__SHIFT                    18
 343 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__WIDTH                     5
 344 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__MASK            0x007c0000U
 345 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__READ(src) \
 346                     (((u_int32_t)(src)\
 347                     & 0x007c0000U) >> 18)
 348 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__WRITE(src) \
 349                     (((u_int32_t)(src)\
 350                     << 18) & 0x007c0000U)
 351 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__MODIFY(dst, src) \
 352                     (dst) = ((dst) &\
 353                     ~0x007c0000U) | (((u_int32_t)(src) <<\
 354                     18) & 0x007c0000U)
 355 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__VERIFY(src) \
 356                     (!((((u_int32_t)(src)\
 357                     << 18) & ~0x007c0000U)))
 358
 359 /* macros for bb_reg_block.bb_agc_reg_map.BB_peak_det_ctrl_1 */
 360
 361
 362 /* macros for BlueprintGlobalNameSpace::peak_det_ctrl_2 */
 363
 364 /* macros for field rf_gain_drop_db_low_0 */
 365 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__SHIFT                        10
 366 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__WIDTH                         5
 367 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__MASK                0x00007c00U
 368 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__READ(src) \
 369                     (((u_int32_t)(src)\
 370                     & 0x00007c00U) >> 10)
 371 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__WRITE(src) \
 372                     (((u_int32_t)(src)\
 373                     << 10) & 0x00007c00U)
 374 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__MODIFY(dst, src) \
 375                     (dst) = ((dst) &\
 376                     ~0x00007c00U) | (((u_int32_t)(src) <<\
 377                     10) & 0x00007c00U)
 378 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__VERIFY(src) \
 379                     (!((((u_int32_t)(src)\
 380                     << 10) & ~0x00007c00U)))
 381
 382 /* macros for field rf_gain_drop_db_med_0 */
 383 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__SHIFT                        15
 384 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__WIDTH                         5
 385 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__MASK                0x000f8000U
 386 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__READ(src) \
 387                     (((u_int32_t)(src)\
 388                     & 0x000f8000U) >> 15)
 389 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__WRITE(src) \
 390                     (((u_int32_t)(src)\
 391                     << 15) & 0x000f8000U)
 392 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__MODIFY(dst, src) \
 393                     (dst) = ((dst) &\
 394                     ~0x000f8000U) | (((u_int32_t)(src) <<\
 395                     15) & 0x000f8000U)
 396 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__VERIFY(src) \
 397                     (!((((u_int32_t)(src)\
 398                     << 15) & ~0x000f8000U)))
 399
 400 /* macros for field rf_gain_drop_db_high_0 */
 401 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__SHIFT                       20
 402 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__WIDTH                        5
 403 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__MASK               0x01f00000U
 404 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__READ(src) \
 405                     (((u_int32_t)(src)\
 406                     & 0x01f00000U) >> 20)
 407 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__WRITE(src) \
 408                     (((u_int32_t)(src)\
 409                     << 20) & 0x01f00000U)
 410 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__MODIFY(dst, src) \
 411                     (dst) = ((dst) &\
 412                     ~0x01f00000U) | (((u_int32_t)(src) <<\
 413                     20) & 0x01f00000U)
 414 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__VERIFY(src) \
 415                     (!((((u_int32_t)(src)\
 416                     << 20) & ~0x01f00000U)))
 417
 418 /* macros for field rf_gain_drop_db_non_0 */
 419 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__SHIFT                        25
 420 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__WIDTH                         5
 421 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__MASK                0x3e000000U
 422 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__READ(src) \
 423                     (((u_int32_t)(src)\
 424                     & 0x3e000000U) >> 25)
 425 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__WRITE(src) \
 426                     (((u_int32_t)(src)\
 427                     << 25) & 0x3e000000U)
 428 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__MODIFY(dst, src) \
 429                     (dst) = ((dst) &\
 430                     ~0x3e000000U) | (((u_int32_t)(src) <<\
 431                     25) & 0x3e000000U)
 432 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__VERIFY(src) \
 433                     (!((((u_int32_t)(src)\
 434                     << 25) & ~0x3e000000U)))
 435
 436 /* macros for field enable_rfsat_restart */
 437 #define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__SHIFT                         30
 438 #define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__WIDTH                          1
 439 #define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__MASK                 0x40000000U
 440 #define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__READ(src) \
 441                     (((u_int32_t)(src)\
 442                     & 0x40000000U) >> 30)
 443 #define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__WRITE(src) \
 444                     (((u_int32_t)(src)\
 445                     << 30) & 0x40000000U)
 446 #define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__MODIFY(dst, src) \
 447                     (dst) = ((dst) &\
 448                     ~0x40000000U) | (((u_int32_t)(src) <<\
 449                     30) & 0x40000000U)
 450 #define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__VERIFY(src) \
 451                     (!((((u_int32_t)(src)\
 452                     << 30) & ~0x40000000U)))
 453 #define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__SET(dst) \
 454                     (dst) = ((dst) &\
 455                     ~0x40000000U) | ((u_int32_t)(1) << 30)
 456 #define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__CLR(dst) \
 457                     (dst) = ((dst) &\
 458                     ~0x40000000U) | ((u_int32_t)(0) << 30)
 459 #define PEAK_DET_CTRL_2__TYPE                                         u_int32_t
 460 #define PEAK_DET_CTRL_2__READ                                       0x7fffffffU
 461 #define PEAK_DET_CTRL_2__WRITE                                      0x7fffffffU
 462
 463 /* macros for bb_reg_block.bb_agc_reg_map.BB_peak_det_ctrl_2 */
 464
 465 /* macros for BlueprintGlobalNameSpace::bt_coex_1 */
 466 #ifndef __BT_COEX_1_MACRO__
 467 #define __BT_COEX_1_MACRO__
 468
 469 /* macros for field peak_det_tally_thr_low_1 */
 470 #define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__SHIFT                            0
 471 #define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__WIDTH                            5
 472 #define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__MASK                   0x0000001fU
 473 #define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__READ(src) \
 474                     (u_int32_t)(src)\
 475                     & 0x0000001fU
 476 #define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__WRITE(src) \
 477                     ((u_int32_t)(src)\
 478                     & 0x0000001fU)
 479 #define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__MODIFY(dst, src) \
 480                     (dst) = ((dst) &\
 481                     ~0x0000001fU) | ((u_int32_t)(src) &\
 482                     0x0000001fU)
 483 #define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__VERIFY(src) \
 484                     (!(((u_int32_t)(src)\
 485                     & ~0x0000001fU)))
 486
 487 /* macros for field peak_det_tally_thr_med_1 */
 488 #define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__SHIFT                            5
 489 #define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__WIDTH                            5
 490 #define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__MASK                   0x000003e0U
 491 #define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__READ(src) \
 492                     (((u_int32_t)(src)\
 493                     & 0x000003e0U) >> 5)
 494 #define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__WRITE(src) \
 495                     (((u_int32_t)(src)\
 496                     << 5) & 0x000003e0U)
 497 #define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__MODIFY(dst, src) \
 498                     (dst) = ((dst) &\
 499                     ~0x000003e0U) | (((u_int32_t)(src) <<\
 500                     5) & 0x000003e0U)
 501 #define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__VERIFY(src) \
 502                     (!((((u_int32_t)(src)\
 503                     << 5) & ~0x000003e0U)))
 504
 505 /* macros for field peak_det_tally_thr_high_1 */
 506 #define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__SHIFT                          10
 507 #define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__WIDTH                           5
 508 #define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__MASK                  0x00007c00U
 509 #define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__READ(src) \
 510                     (((u_int32_t)(src)\
 511                     & 0x00007c00U) >> 10)
 512 #define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__WRITE(src) \
 513                     (((u_int32_t)(src)\
 514                     << 10) & 0x00007c00U)
 515 #define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__MODIFY(dst, src) \
 516                     (dst) = ((dst) &\
 517                     ~0x00007c00U) | (((u_int32_t)(src) <<\
 518                     10) & 0x00007c00U)
 519 #define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__VERIFY(src) \
 520                     (!((((u_int32_t)(src)\
 521                     << 10) & ~0x00007c00U)))
 522
 523 /* macros for field rf_gain_drop_db_low_1 */
 524 #define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__SHIFT                              15
 525 #define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__WIDTH                               5
 526 #define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__MASK                      0x000f8000U
 527 #define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__READ(src) \
 528                     (((u_int32_t)(src)\
 529                     & 0x000f8000U) >> 15)
 530 #define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__WRITE(src) \
 531                     (((u_int32_t)(src)\
 532                     << 15) & 0x000f8000U)
 533 #define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__MODIFY(dst, src) \
 534                     (dst) = ((dst) &\
 535                     ~0x000f8000U) | (((u_int32_t)(src) <<\
 536                     15) & 0x000f8000U)
 537 #define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__VERIFY(src) \
 538                     (!((((u_int32_t)(src)\
 539                     << 15) & ~0x000f8000U)))
 540
 541 /* macros for field rf_gain_drop_db_med_1 */
 542 #define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__SHIFT                              20
 543 #define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__WIDTH                               5
 544 #define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__MASK                      0x01f00000U
 545 #define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__READ(src) \
 546                     (((u_int32_t)(src)\
 547                     & 0x01f00000U) >> 20)
 548 #define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__WRITE(src) \
 549                     (((u_int32_t)(src)\
 550                     << 20) & 0x01f00000U)
 551 #define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__MODIFY(dst, src) \
 552                     (dst) = ((dst) &\
 553                     ~0x01f00000U) | (((u_int32_t)(src) <<\
 554                     20) & 0x01f00000U)
 555 #define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__VERIFY(src) \
 556                     (!((((u_int32_t)(src)\
 557                     << 20) & ~0x01f00000U)))
 558
 559 /* macros for field rf_gain_drop_db_high_1 */
 560 #define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__SHIFT                             25
 561 #define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__WIDTH                              5
 562 #define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__MASK                     0x3e000000U
 563 #define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__READ(src) \
 564                     (((u_int32_t)(src)\
 565                     & 0x3e000000U) >> 25)
 566 #define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__WRITE(src) \
 567                     (((u_int32_t)(src)\
 568                     << 25) & 0x3e000000U)
 569 #define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__MODIFY(dst, src) \
 570                     (dst) = ((dst) &\
 571                     ~0x3e000000U) | (((u_int32_t)(src) <<\
 572                     25) & 0x3e000000U)
 573 #define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__VERIFY(src) \
 574                     (!((((u_int32_t)(src)\
 575                     << 25) & ~0x3e000000U)))
 576
 577 /* macros for field bt_tx_disable_NF_cal */
 578 #define BT_COEX_1__BT_TX_DISABLE_NF_CAL__SHIFT                               30
 579 #define BT_COEX_1__BT_TX_DISABLE_NF_CAL__WIDTH                                1
 580 #define BT_COEX_1__BT_TX_DISABLE_NF_CAL__MASK                       0x40000000U
 581 #define BT_COEX_1__BT_TX_DISABLE_NF_CAL__READ(src) \
 582                     (((u_int32_t)(src)\
 583                     & 0x40000000U) >> 30)
 584 #define BT_COEX_1__BT_TX_DISABLE_NF_CAL__WRITE(src) \
 585                     (((u_int32_t)(src)\
 586                     << 30) & 0x40000000U)
 587 #define BT_COEX_1__BT_TX_DISABLE_NF_CAL__MODIFY(dst, src) \
 588                     (dst) = ((dst) &\
 589                     ~0x40000000U) | (((u_int32_t)(src) <<\
 590                     30) & 0x40000000U)
 591 #define BT_COEX_1__BT_TX_DISABLE_NF_CAL__VERIFY(src) \
 592                     (!((((u_int32_t)(src)\
 593                     << 30) & ~0x40000000U)))
 594 #define BT_COEX_1__BT_TX_DISABLE_NF_CAL__SET(dst) \
 595                     (dst) = ((dst) &\
 596                     ~0x40000000U) | ((u_int32_t)(1) << 30)
 597 #define BT_COEX_1__BT_TX_DISABLE_NF_CAL__CLR(dst) \
 598                     (dst) = ((dst) &\
 599                     ~0x40000000U) | ((u_int32_t)(0) << 30)
 600 #define BT_COEX_1__TYPE                                               u_int32_t
 601 #define BT_COEX_1__READ                                             0x7fffffffU
 602 #define BT_COEX_1__WRITE                                            0x7fffffffU
 603
 604 #endif /* __BT_COEX_1_MACRO__ */
 605
 606
 607 /* macros for bb_reg_block.bb_agc_reg_map.BB_bt_coex_1 */
 608 #define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_BT_COEX_1__NUM                  1
 609
 610 /* macros for BlueprintGlobalNameSpace::bt_coex_2 */
 611 #ifndef __BT_COEX_2_MACRO__
 612 #define __BT_COEX_2_MACRO__
 613
 614 /* macros for field peak_det_tally_thr_low_2 */
 615 #define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__SHIFT                            0
 616 #define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__WIDTH                            5
 617 #define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__MASK                   0x0000001fU
 618 #define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__READ(src) \
 619                     (u_int32_t)(src)\
 620                     & 0x0000001fU
 621 #define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__WRITE(src) \
 622                     ((u_int32_t)(src)\
 623                     & 0x0000001fU)
 624 #define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__MODIFY(dst, src) \
 625                     (dst) = ((dst) &\
 626                     ~0x0000001fU) | ((u_int32_t)(src) &\
 627                     0x0000001fU)
 628 #define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__VERIFY(src) \
 629                     (!(((u_int32_t)(src)\
 630                     & ~0x0000001fU)))
 631
 632 /* macros for field peak_det_tally_thr_med_2 */
 633 #define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__SHIFT                            5
 634 #define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__WIDTH                            5
 635 #define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__MASK                   0x000003e0U
 636 #define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__READ(src) \
 637                     (((u_int32_t)(src)\
 638                     & 0x000003e0U) >> 5)
 639 #define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__WRITE(src) \
 640                     (((u_int32_t)(src)\
 641                     << 5) & 0x000003e0U)
 642 #define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__MODIFY(dst, src) \
 643                     (dst) = ((dst) &\
 644                     ~0x000003e0U) | (((u_int32_t)(src) <<\
 645                     5) & 0x000003e0U)
 646 #define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__VERIFY(src) \
 647                     (!((((u_int32_t)(src)\
 648                     << 5) & ~0x000003e0U)))
 649
 650 /* macros for field peak_det_tally_thr_high_2 */
 651 #define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__SHIFT                          10
 652 #define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__WIDTH                           5
 653 #define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__MASK                  0x00007c00U
 654 #define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__READ(src) \
 655                     (((u_int32_t)(src)\
 656                     & 0x00007c00U) >> 10)
 657 #define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__WRITE(src) \
 658                     (((u_int32_t)(src)\
 659                     << 10) & 0x00007c00U)
 660 #define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__MODIFY(dst, src) \
 661                     (dst) = ((dst) &\
 662                     ~0x00007c00U) | (((u_int32_t)(src) <<\
 663                     10) & 0x00007c00U)
 664 #define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__VERIFY(src) \
 665                     (!((((u_int32_t)(src)\
 666                     << 10) & ~0x00007c00U)))
 667
 668 /* macros for field rf_gain_drop_db_low_2 */
 669 #define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__SHIFT                              15
 670 #define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__WIDTH                               5
 671 #define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__MASK                      0x000f8000U
 672 #define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__READ(src) \
 673                     (((u_int32_t)(src)\
 674                     & 0x000f8000U) >> 15)
 675 #define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__WRITE(src) \
 676                     (((u_int32_t)(src)\
 677                     << 15) & 0x000f8000U)
 678 #define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__MODIFY(dst, src) \
 679                     (dst) = ((dst) &\
 680                     ~0x000f8000U) | (((u_int32_t)(src) <<\
 681                     15) & 0x000f8000U)
 682 #define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__VERIFY(src) \
 683                     (!((((u_int32_t)(src)\
 684                     << 15) & ~0x000f8000U)))
 685
 686 /* macros for field rf_gain_drop_db_med_2 */
 687 #define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__SHIFT                              20
 688 #define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__WIDTH                               5
 689 #define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__MASK                      0x01f00000U
 690 #define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__READ(src) \
 691                     (((u_int32_t)(src)\
 692                     & 0x01f00000U) >> 20)
 693 #define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__WRITE(src) \
 694                     (((u_int32_t)(src)\
 695                     << 20) & 0x01f00000U)
 696 #define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__MODIFY(dst, src) \
 697                     (dst) = ((dst) &\
 698                     ~0x01f00000U) | (((u_int32_t)(src) <<\
 699                     20) & 0x01f00000U)
 700 #define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__VERIFY(src) \
 701                     (!((((u_int32_t)(src)\
 702                     << 20) & ~0x01f00000U)))
 703
 704 /* macros for field rf_gain_drop_db_high_2 */
 705 #define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__SHIFT                             25
 706 #define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__WIDTH                              5
 707 #define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__MASK                     0x3e000000U
 708 #define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__READ(src) \
 709                     (((u_int32_t)(src)\
 710                     & 0x3e000000U) >> 25)
 711 #define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__WRITE(src) \
 712                     (((u_int32_t)(src)\
 713                     << 25) & 0x3e000000U)
 714 #define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__MODIFY(dst, src) \
 715                     (dst) = ((dst) &\
 716                     ~0x3e000000U) | (((u_int32_t)(src) <<\
 717                     25) & 0x3e000000U)
 718 #define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__VERIFY(src) \
 719                     (!((((u_int32_t)(src)\
 720                     << 25) & ~0x3e000000U)))
 721
 722 /* macros for field rfsat_rx_rx */
 723 #define BT_COEX_2__RFSAT_RX_RX__SHIFT                                        30
 724 #define BT_COEX_2__RFSAT_RX_RX__WIDTH                                         2
 725 #define BT_COEX_2__RFSAT_RX_RX__MASK                                0xc0000000U
 726 #define BT_COEX_2__RFSAT_RX_RX__READ(src) \
 727                     (((u_int32_t)(src)\
 728                     & 0xc0000000U) >> 30)
 729 #define BT_COEX_2__RFSAT_RX_RX__WRITE(src) \
 730                     (((u_int32_t)(src)\
 731                     << 30) & 0xc0000000U)
 732 #define BT_COEX_2__RFSAT_RX_RX__MODIFY(dst, src) \
 733                     (dst) = ((dst) &\
 734                     ~0xc0000000U) | (((u_int32_t)(src) <<\
 735                     30) & 0xc0000000U)
 736 #define BT_COEX_2__RFSAT_RX_RX__VERIFY(src) \
 737                     (!((((u_int32_t)(src)\
 738                     << 30) & ~0xc0000000U)))
 739 #define BT_COEX_2__TYPE                                               u_int32_t
 740 #define BT_COEX_2__READ                                             0xffffffffU
 741 #define BT_COEX_2__WRITE                                            0xffffffffU
 742
 743 #endif /* __BT_COEX_2_MACRO__ */
 744
 745
 746 /* macros for bb_reg_block.bb_agc_reg_map.BB_bt_coex_2 */
 747 #define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_BT_COEX_2__NUM                  1
 748
 749 /* macros for BlueprintGlobalNameSpace::bt_coex_3 */
 750 #ifndef __BT_COEX_3_MACRO__
 751 #define __BT_COEX_3_MACRO__
 752
 753 /* macros for field rfsat_bt_srch_srch */
 754 #define BT_COEX_3__RFSAT_BT_SRCH_SRCH__SHIFT                                  0
 755 #define BT_COEX_3__RFSAT_BT_SRCH_SRCH__WIDTH                                  2
 756 #define BT_COEX_3__RFSAT_BT_SRCH_SRCH__MASK                         0x00000003U
 757 #define BT_COEX_3__RFSAT_BT_SRCH_SRCH__READ(src) (u_int32_t)(src) & 0x00000003U
 758 #define BT_COEX_3__RFSAT_BT_SRCH_SRCH__WRITE(src) \
 759                     ((u_int32_t)(src)\
 760                     & 0x00000003U)
 761 #define BT_COEX_3__RFSAT_BT_SRCH_SRCH__MODIFY(dst, src) \
 762                     (dst) = ((dst) &\
 763                     ~0x00000003U) | ((u_int32_t)(src) &\
 764                     0x00000003U)
 765 #define BT_COEX_3__RFSAT_BT_SRCH_SRCH__VERIFY(src) \
 766                     (!(((u_int32_t)(src)\
 767                     & ~0x00000003U)))
 768
 769 /* macros for field rfsat_bt_rx_srch */
 770 #define BT_COEX_3__RFSAT_BT_RX_SRCH__SHIFT                                    2
 771 #define BT_COEX_3__RFSAT_BT_RX_SRCH__WIDTH                                    2
 772 #define BT_COEX_3__RFSAT_BT_RX_SRCH__MASK                           0x0000000cU
 773 #define BT_COEX_3__RFSAT_BT_RX_SRCH__READ(src) \
 774                     (((u_int32_t)(src)\
 775                     & 0x0000000cU) >> 2)
 776 #define BT_COEX_3__RFSAT_BT_RX_SRCH__WRITE(src) \
 777                     (((u_int32_t)(src)\
 778                     << 2) & 0x0000000cU)
 779 #define BT_COEX_3__RFSAT_BT_RX_SRCH__MODIFY(dst, src) \
 780                     (dst) = ((dst) &\
 781                     ~0x0000000cU) | (((u_int32_t)(src) <<\
 782                     2) & 0x0000000cU)
 783 #define BT_COEX_3__RFSAT_BT_RX_SRCH__VERIFY(src) \
 784                     (!((((u_int32_t)(src)\
 785                     << 2) & ~0x0000000cU)))
 786
 787 /* macros for field rfsat_bt_srch_rx */
 788 #define BT_COEX_3__RFSAT_BT_SRCH_RX__SHIFT                                    4
 789 #define BT_COEX_3__RFSAT_BT_SRCH_RX__WIDTH                                    2
 790 #define BT_COEX_3__RFSAT_BT_SRCH_RX__MASK                           0x00000030U
 791 #define BT_COEX_3__RFSAT_BT_SRCH_RX__READ(src) \
 792                     (((u_int32_t)(src)\
 793                     & 0x00000030U) >> 4)
 794 #define BT_COEX_3__RFSAT_BT_SRCH_RX__WRITE(src) \
 795                     (((u_int32_t)(src)\
 796                     << 4) & 0x00000030U)
 797 #define BT_COEX_3__RFSAT_BT_SRCH_RX__MODIFY(dst, src) \
 798                     (dst) = ((dst) &\
 799                     ~0x00000030U) | (((u_int32_t)(src) <<\
 800                     4) & 0x00000030U)
 801 #define BT_COEX_3__RFSAT_BT_SRCH_RX__VERIFY(src) \
 802                     (!((((u_int32_t)(src)\
 803                     << 4) & ~0x00000030U)))
 804
 805 /* macros for field rfsat_wlan_srch_srch */
 806 #define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__SHIFT                                6
 807 #define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__WIDTH                                2
 808 #define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__MASK                       0x000000c0U
 809 #define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__READ(src) \
 810                     (((u_int32_t)(src)\
 811                     & 0x000000c0U) >> 6)
 812 #define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__WRITE(src) \
 813                     (((u_int32_t)(src)\
 814                     << 6) & 0x000000c0U)
 815 #define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__MODIFY(dst, src) \
 816                     (dst) = ((dst) &\
 817                     ~0x000000c0U) | (((u_int32_t)(src) <<\
 818                     6) & 0x000000c0U)
 819 #define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__VERIFY(src) \
 820                     (!((((u_int32_t)(src)\
 821                     << 6) & ~0x000000c0U)))
 822
 823 /* macros for field rfsat_wlan_rx_srch */
 824 #define BT_COEX_3__RFSAT_WLAN_RX_SRCH__SHIFT                                  8
 825 #define BT_COEX_3__RFSAT_WLAN_RX_SRCH__WIDTH                                  2
 826 #define BT_COEX_3__RFSAT_WLAN_RX_SRCH__MASK                         0x00000300U
 827 #define BT_COEX_3__RFSAT_WLAN_RX_SRCH__READ(src) \
 828                     (((u_int32_t)(src)\
 829                     & 0x00000300U) >> 8)
 830 #define BT_COEX_3__RFSAT_WLAN_RX_SRCH__WRITE(src) \
 831                     (((u_int32_t)(src)\
 832                     << 8) & 0x00000300U)
 833 #define BT_COEX_3__RFSAT_WLAN_RX_SRCH__MODIFY(dst, src) \
 834                     (dst) = ((dst) &\
 835                     ~0x00000300U) | (((u_int32_t)(src) <<\
 836                     8) & 0x00000300U)
 837 #define BT_COEX_3__RFSAT_WLAN_RX_SRCH__VERIFY(src) \
 838                     (!((((u_int32_t)(src)\
 839                     << 8) & ~0x00000300U)))
 840
 841 /* macros for field rfsat_wlan_srch_rx */
 842 #define BT_COEX_3__RFSAT_WLAN_SRCH_RX__SHIFT                                 10
 843 #define BT_COEX_3__RFSAT_WLAN_SRCH_RX__WIDTH                                  2
 844 #define BT_COEX_3__RFSAT_WLAN_SRCH_RX__MASK                         0x00000c00U
 845 #define BT_COEX_3__RFSAT_WLAN_SRCH_RX__READ(src) \
 846                     (((u_int32_t)(src)\
 847                     & 0x00000c00U) >> 10)
 848 #define BT_COEX_3__RFSAT_WLAN_SRCH_RX__WRITE(src) \
 849                     (((u_int32_t)(src)\
 850                     << 10) & 0x00000c00U)
 851 #define BT_COEX_3__RFSAT_WLAN_SRCH_RX__MODIFY(dst, src) \
 852                     (dst) = ((dst) &\
 853                     ~0x00000c00U) | (((u_int32_t)(src) <<\
 854                     10) & 0x00000c00U)
 855 #define BT_COEX_3__RFSAT_WLAN_SRCH_RX__VERIFY(src) \
 856                     (!((((u_int32_t)(src)\
 857                     << 10) & ~0x00000c00U)))
 858
 859 /* macros for field rfsat_eq_srch_srch */
 860 #define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__SHIFT                                 12
 861 #define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__WIDTH                                  2
 862 #define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__MASK                         0x00003000U
 863 #define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__READ(src) \
 864                     (((u_int32_t)(src)\
 865                     & 0x00003000U) >> 12)
 866 #define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__WRITE(src) \
 867                     (((u_int32_t)(src)\
 868                     << 12) & 0x00003000U)
 869 #define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__MODIFY(dst, src) \
 870                     (dst) = ((dst) &\
 871                     ~0x00003000U) | (((u_int32_t)(src) <<\
 872                     12) & 0x00003000U)
 873 #define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__VERIFY(src) \
 874                     (!((((u_int32_t)(src)\
 875                     << 12) & ~0x00003000U)))
 876
 877 /* macros for field rfsat_eq_rx_srch */
 878 #define BT_COEX_3__RFSAT_EQ_RX_SRCH__SHIFT                                   14
 879 #define BT_COEX_3__RFSAT_EQ_RX_SRCH__WIDTH                                    2
 880 #define BT_COEX_3__RFSAT_EQ_RX_SRCH__MASK                           0x0000c000U
 881 #define BT_COEX_3__RFSAT_EQ_RX_SRCH__READ(src) \
 882                     (((u_int32_t)(src)\
 883                     & 0x0000c000U) >> 14)
 884 #define BT_COEX_3__RFSAT_EQ_RX_SRCH__WRITE(src) \
 885                     (((u_int32_t)(src)\
 886                     << 14) & 0x0000c000U)
 887 #define BT_COEX_3__RFSAT_EQ_RX_SRCH__MODIFY(dst, src) \
 888                     (dst) = ((dst) &\
 889                     ~0x0000c000U) | (((u_int32_t)(src) <<\
 890                     14) & 0x0000c000U)
 891 #define BT_COEX_3__RFSAT_EQ_RX_SRCH__VERIFY(src) \
 892                     (!((((u_int32_t)(src)\
 893                     << 14) & ~0x0000c000U)))
 894
 895 /* macros for field rfsat_eq_srch_rx */
 896 #define BT_COEX_3__RFSAT_EQ_SRCH_RX__SHIFT                                   16
 897 #define BT_COEX_3__RFSAT_EQ_SRCH_RX__WIDTH                                    2
 898 #define BT_COEX_3__RFSAT_EQ_SRCH_RX__MASK                           0x00030000U
 899 #define BT_COEX_3__RFSAT_EQ_SRCH_RX__READ(src) \
 900                     (((u_int32_t)(src)\
 901                     & 0x00030000U) >> 16)
 902 #define BT_COEX_3__RFSAT_EQ_SRCH_RX__WRITE(src) \
 903                     (((u_int32_t)(src)\
 904                     << 16) & 0x00030000U)
 905 #define BT_COEX_3__RFSAT_EQ_SRCH_RX__MODIFY(dst, src) \
 906                     (dst) = ((dst) &\
 907                     ~0x00030000U) | (((u_int32_t)(src) <<\
 908                     16) & 0x00030000U)
 909 #define BT_COEX_3__RFSAT_EQ_SRCH_RX__VERIFY(src) \
 910                     (!((((u_int32_t)(src)\
 911                     << 16) & ~0x00030000U)))
 912
 913 /* macros for field rf_gain_drop_db_non_1 */
 914 #define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__SHIFT                              18
 915 #define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__WIDTH                               5
 916 #define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__MASK                      0x007c0000U
 917 #define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__READ(src) \
 918                     (((u_int32_t)(src)\
 919                     & 0x007c0000U) >> 18)
 920 #define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__WRITE(src) \
 921                     (((u_int32_t)(src)\
 922                     << 18) & 0x007c0000U)
 923 #define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__MODIFY(dst, src) \
 924                     (dst) = ((dst) &\
 925                     ~0x007c0000U) | (((u_int32_t)(src) <<\
 926                     18) & 0x007c0000U)
 927 #define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__VERIFY(src) \
 928                     (!((((u_int32_t)(src)\
 929                     << 18) & ~0x007c0000U)))
 930
 931 /* macros for field rf_gain_drop_db_non_2 */
 932 #define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__SHIFT                              23
 933 #define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__WIDTH                               5
 934 #define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__MASK                      0x0f800000U
 935 #define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__READ(src) \
 936                     (((u_int32_t)(src)\
 937                     & 0x0f800000U) >> 23)
 938 #define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__WRITE(src) \
 939                     (((u_int32_t)(src)\
 940                     << 23) & 0x0f800000U)
 941 #define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__MODIFY(dst, src) \
 942                     (dst) = ((dst) &\
 943                     ~0x0f800000U) | (((u_int32_t)(src) <<\
 944                     23) & 0x0f800000U)
 945 #define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__VERIFY(src) \
 946                     (!((((u_int32_t)(src)\
 947                     << 23) & ~0x0f800000U)))
 948
 949 /* macros for field bt_rx_firpwr_incr */
 950 #define BT_COEX_3__BT_RX_FIRPWR_INCR__SHIFT                                  28
 951 #define BT_COEX_3__BT_RX_FIRPWR_INCR__WIDTH                                   4
 952 #define BT_COEX_3__BT_RX_FIRPWR_INCR__MASK                          0xf0000000U
 953 #define BT_COEX_3__BT_RX_FIRPWR_INCR__READ(src) \
 954                     (((u_int32_t)(src)\
 955                     & 0xf0000000U) >> 28)
 956 #define BT_COEX_3__BT_RX_FIRPWR_INCR__WRITE(src) \
 957                     (((u_int32_t)(src)\
 958                     << 28) & 0xf0000000U)
 959 #define BT_COEX_3__BT_RX_FIRPWR_INCR__MODIFY(dst, src) \
 960                     (dst) = ((dst) &\
 961                     ~0xf0000000U) | (((u_int32_t)(src) <<\
 962                     28) & 0xf0000000U)
 963 #define BT_COEX_3__BT_RX_FIRPWR_INCR__VERIFY(src) \
 964                     (!((((u_int32_t)(src)\
 965                     << 28) & ~0xf0000000U)))
 966 #define BT_COEX_3__TYPE                                               u_int32_t
 967 #define BT_COEX_3__READ                                             0xffffffffU
 968 #define BT_COEX_3__WRITE                                            0xffffffffU
 969
 970 #endif /* __BT_COEX_3_MACRO__ */
 971
 972
 973 /* macros for bb_reg_block.bb_agc_reg_map.BB_bt_coex_3 */
 974 #define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_BT_COEX_3__NUM                  1
 975
 976 /* macros for BlueprintGlobalNameSpace::bt_coex_4 */
 977 #ifndef __BT_COEX_4_MACRO__
 978 #define __BT_COEX_4_MACRO__
 979
 980 /* macros for field rfgain_eqv_lna_0 */
 981 #define BT_COEX_4__RFGAIN_EQV_LNA_0__SHIFT                                    0
 982 #define BT_COEX_4__RFGAIN_EQV_LNA_0__WIDTH                                    8
 983 #define BT_COEX_4__RFGAIN_EQV_LNA_0__MASK                           0x000000ffU
 984 #define BT_COEX_4__RFGAIN_EQV_LNA_0__READ(src)   (u_int32_t)(src) & 0x000000ffU
 985 #define BT_COEX_4__RFGAIN_EQV_LNA_0__WRITE(src) \
 986                     ((u_int32_t)(src)\
 987                     & 0x000000ffU)
 988 #define BT_COEX_4__RFGAIN_EQV_LNA_0__MODIFY(dst, src) \
 989                     (dst) = ((dst) &\
 990                     ~0x000000ffU) | ((u_int32_t)(src) &\
 991                     0x000000ffU)
 992 #define BT_COEX_4__RFGAIN_EQV_LNA_0__VERIFY(src) \
 993                     (!(((u_int32_t)(src)\
 994                     & ~0x000000ffU)))
 995
 996 /* macros for field rfgain_eqv_lna_1 */
 997 #define BT_COEX_4__RFGAIN_EQV_LNA_1__SHIFT                                    8
 998 #define BT_COEX_4__RFGAIN_EQV_LNA_1__WIDTH                                    8
 999 #define BT_COEX_4__RFGAIN_EQV_LNA_1__MASK                           0x0000ff00U
1000 #define BT_COEX_4__RFGAIN_EQV_LNA_1__READ(src) \
1001                     (((u_int32_t)(src)\
1002                     & 0x0000ff00U) >> 8)
1003 #define BT_COEX_4__RFGAIN_EQV_LNA_1__WRITE(src) \
1004                     (((u_int32_t)(src)\
1005                     << 8) & 0x0000ff00U)
1006 #define BT_COEX_4__RFGAIN_EQV_LNA_1__MODIFY(dst, src) \
1007                     (dst) = ((dst) &\
1008                     ~0x0000ff00U) | (((u_int32_t)(src) <<\
1009                     8) & 0x0000ff00U)
1010 #define BT_COEX_4__RFGAIN_EQV_LNA_1__VERIFY(src) \
1011                     (!((((u_int32_t)(src)\
1012                     << 8) & ~0x0000ff00U)))
1013
1014 /* macros for field rfgain_eqv_lna_2 */
1015 #define BT_COEX_4__RFGAIN_EQV_LNA_2__SHIFT                                   16
1016 #define BT_COEX_4__RFGAIN_EQV_LNA_2__WIDTH                                    8
1017 #define BT_COEX_4__RFGAIN_EQV_LNA_2__MASK                           0x00ff0000U
1018 #define BT_COEX_4__RFGAIN_EQV_LNA_2__READ(src) \
1019                     (((u_int32_t)(src)\
1020                     & 0x00ff0000U) >> 16)
1021 #define BT_COEX_4__RFGAIN_EQV_LNA_2__WRITE(src) \
1022                     (((u_int32_t)(src)\
1023                     << 16) & 0x00ff0000U)
1024 #define BT_COEX_4__RFGAIN_EQV_LNA_2__MODIFY(dst, src) \
1025                     (dst) = ((dst) &\
1026                     ~0x00ff0000U) | (((u_int32_t)(src) <<\
1027                     16) & 0x00ff0000U)
1028 #define BT_COEX_4__RFGAIN_EQV_LNA_2__VERIFY(src) \
1029                     (!((((u_int32_t)(src)\
1030                     << 16) & ~0x00ff0000U)))
1031
1032 /* macros for field rfgain_eqv_lna_3 */
1033 #define BT_COEX_4__RFGAIN_EQV_LNA_3__SHIFT                                   24
1034 #define BT_COEX_4__RFGAIN_EQV_LNA_3__WIDTH                                    8
1035 #define BT_COEX_4__RFGAIN_EQV_LNA_3__MASK                           0xff000000U
1036 #define BT_COEX_4__RFGAIN_EQV_LNA_3__READ(src) \
1037                     (((u_int32_t)(src)\
1038                     & 0xff000000U) >> 24)
1039 #define BT_COEX_4__RFGAIN_EQV_LNA_3__WRITE(src) \
1040                     (((u_int32_t)(src)\
1041                     << 24) & 0xff000000U)
1042 #define BT_COEX_4__RFGAIN_EQV_LNA_3__MODIFY(dst, src) \
1043                     (dst) = ((dst) &\
1044                     ~0xff000000U) | (((u_int32_t)(src) <<\
1045                     24) & 0xff000000U)
1046 #define BT_COEX_4__RFGAIN_EQV_LNA_3__VERIFY(src) \
1047                     (!((((u_int32_t)(src)\
1048                     << 24) & ~0xff000000U)))
1049 #define BT_COEX_4__TYPE                                               u_int32_t
1050 #define BT_COEX_4__READ                                             0xffffffffU
1051 #define BT_COEX_4__WRITE                                            0xffffffffU
1052
1053 #endif /* __BT_COEX_4_MACRO__ */
1054
1055
1056 /* macros for bb_reg_block.bb_agc_reg_map.BB_bt_coex_4 */
1057 #define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_BT_COEX_4__NUM                  1
1058
1059 /* macros for BlueprintGlobalNameSpace::bt_coex_5 */
1060 #ifndef __BT_COEX_5_MACRO__
1061 #define __BT_COEX_5_MACRO__
1062
1063 /* macros for field rfgain_eqv_lna_4 */
1064 #define BT_COEX_5__RFGAIN_EQV_LNA_4__SHIFT                                    0
1065 #define BT_COEX_5__RFGAIN_EQV_LNA_4__WIDTH                                    8
1066 #define BT_COEX_5__RFGAIN_EQV_LNA_4__MASK                           0x000000ffU
1067 #define BT_COEX_5__RFGAIN_EQV_LNA_4__READ(src)   (u_int32_t)(src) & 0x000000ffU
1068 #define BT_COEX_5__RFGAIN_EQV_LNA_4__WRITE(src) \
1069                     ((u_int32_t)(src)\
1070                     & 0x000000ffU)
1071 #define BT_COEX_5__RFGAIN_EQV_LNA_4__MODIFY(dst, src) \
1072                     (dst) = ((dst) &\
1073                     ~0x000000ffU) | ((u_int32_t)(src) &\
1074                     0x000000ffU)
1075 #define BT_COEX_5__RFGAIN_EQV_LNA_4__VERIFY(src) \
1076                     (!(((u_int32_t)(src)\
1077                     & ~0x000000ffU)))
1078
1079 /* macros for field rfgain_eqv_lna_5 */
1080 #define BT_COEX_5__RFGAIN_EQV_LNA_5__SHIFT                                    8
1081 #define BT_COEX_5__RFGAIN_EQV_LNA_5__WIDTH                                    8
1082 #define BT_COEX_5__RFGAIN_EQV_LNA_5__MASK                           0x0000ff00U
1083 #define BT_COEX_5__RFGAIN_EQV_LNA_5__READ(src) \
1084                     (((u_int32_t)(src)\
1085                     & 0x0000ff00U) >> 8)
1086 #define BT_COEX_5__RFGAIN_EQV_LNA_5__WRITE(src) \
1087                     (((u_int32_t)(src)\
1088                     << 8) & 0x0000ff00U)
1089 #define BT_COEX_5__RFGAIN_EQV_LNA_5__MODIFY(dst, src) \
1090                     (dst) = ((dst) &\
1091                     ~0x0000ff00U) | (((u_int32_t)(src) <<\
1092                     8) & 0x0000ff00U)
1093 #define BT_COEX_5__RFGAIN_EQV_LNA_5__VERIFY(src) \
1094                     (!((((u_int32_t)(src)\
1095                     << 8) & ~0x0000ff00U)))
1096
1097 /* macros for field rfgain_eqv_lna_6 */
1098 #define BT_COEX_5__RFGAIN_EQV_LNA_6__SHIFT                                   16
1099 #define BT_COEX_5__RFGAIN_EQV_LNA_6__WIDTH                                    8
1100 #define BT_COEX_5__RFGAIN_EQV_LNA_6__MASK                           0x00ff0000U
1101 #define BT_COEX_5__RFGAIN_EQV_LNA_6__READ(src) \
1102                     (((u_int32_t)(src)\
1103                     & 0x00ff0000U) >> 16)
1104 #define BT_COEX_5__RFGAIN_EQV_LNA_6__WRITE(src) \
1105                     (((u_int32_t)(src)\
1106                     << 16) & 0x00ff0000U)
1107 #define BT_COEX_5__RFGAIN_EQV_LNA_6__MODIFY(dst, src) \
1108                     (dst) = ((dst) &\
1109                     ~0x00ff0000U) | (((u_int32_t)(src) <<\
1110                     16) & 0x00ff0000U)
1111 #define BT_COEX_5__RFGAIN_EQV_LNA_6__VERIFY(src) \
1112                     (!((((u_int32_t)(src)\
1113                     << 16) & ~0x00ff0000U)))
1114
1115 /* macros for field rfgain_eqv_lna_7 */
1116 #define BT_COEX_5__RFGAIN_EQV_LNA_7__SHIFT                                   24
1117 #define BT_COEX_5__RFGAIN_EQV_LNA_7__WIDTH                                    8
1118 #define BT_COEX_5__RFGAIN_EQV_LNA_7__MASK                           0xff000000U
1119 #define BT_COEX_5__RFGAIN_EQV_LNA_7__READ(src) \
1120                     (((u_int32_t)(src)\
1121                     & 0xff000000U) >> 24)
1122 #define BT_COEX_5__RFGAIN_EQV_LNA_7__WRITE(src) \
1123                     (((u_int32_t)(src)\
1124                     << 24) & 0xff000000U)
1125 #define BT_COEX_5__RFGAIN_EQV_LNA_7__MODIFY(dst, src) \
1126                     (dst) = ((dst) &\
1127                     ~0xff000000U) | (((u_int32_t)(src) <<\
1128                     24) & 0xff000000U)
1129 #define BT_COEX_5__RFGAIN_EQV_LNA_7__VERIFY(src) \
1130                     (!((((u_int32_t)(src)\
1131                     << 24) & ~0xff000000U)))
1132 #define BT_COEX_5__TYPE                                               u_int32_t
1133 #define BT_COEX_5__READ                                             0xffffffffU
1134 #define BT_COEX_5__WRITE                                            0xffffffffU
1135
1136 #endif /* __BT_COEX_5_MACRO__ */
1137
1138
1139 /* macros for bb_reg_block.bb_agc_reg_map.BB_bt_coex_5 */
1140 #define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_BT_COEX_5__NUM                  1
1141
1142 /* macros for BlueprintGlobalNameSpace::dc_cal_status_b0 */
1143 #ifndef __DC_CAL_STATUS_B0_MACRO__
1144 #define __DC_CAL_STATUS_B0_MACRO__
1145
1146 /* macros for field offsetC1I_0 */
1147 #define DC_CAL_STATUS_B0__OFFSETC1I_0__SHIFT                                  0
1148 #define DC_CAL_STATUS_B0__OFFSETC1I_0__WIDTH                                  5
1149 #define DC_CAL_STATUS_B0__OFFSETC1I_0__MASK                         0x0000001fU
1150 #define DC_CAL_STATUS_B0__OFFSETC1I_0__READ(src) (u_int32_t)(src) & 0x0000001fU
1151
1152 /* macros for field offsetC1Q_0 */
1153 #define DC_CAL_STATUS_B0__OFFSETC1Q_0__SHIFT                                  5
1154 #define DC_CAL_STATUS_B0__OFFSETC1Q_0__WIDTH                                  5
1155 #define DC_CAL_STATUS_B0__OFFSETC1Q_0__MASK                         0x000003e0U
1156 #define DC_CAL_STATUS_B0__OFFSETC1Q_0__READ(src) \
1157                     (((u_int32_t)(src)\
1158                     & 0x000003e0U) >> 5)
1159
1160 /* macros for field offsetC2I_0 */
1161 #define DC_CAL_STATUS_B0__OFFSETC2I_0__SHIFT                                 10
1162 #define DC_CAL_STATUS_B0__OFFSETC2I_0__WIDTH                                  5
1163 #define DC_CAL_STATUS_B0__OFFSETC2I_0__MASK                         0x00007c00U
1164 #define DC_CAL_STATUS_B0__OFFSETC2I_0__READ(src) \
1165                     (((u_int32_t)(src)\
1166                     & 0x00007c00U) >> 10)
1167
1168 /* macros for field offsetC2Q_0 */
1169 #define DC_CAL_STATUS_B0__OFFSETC2Q_0__SHIFT                                 15
1170 #define DC_CAL_STATUS_B0__OFFSETC2Q_0__WIDTH                                  5
1171 #define DC_CAL_STATUS_B0__OFFSETC2Q_0__MASK                         0x000f8000U
1172 #define DC_CAL_STATUS_B0__OFFSETC2Q_0__READ(src) \
1173                     (((u_int32_t)(src)\
1174                     & 0x000f8000U) >> 15)
1175
1176 /* macros for field offsetC3I_0 */
1177 #define DC_CAL_STATUS_B0__OFFSETC3I_0__SHIFT                                 20
1178 #define DC_CAL_STATUS_B0__OFFSETC3I_0__WIDTH                                  5
1179 #define DC_CAL_STATUS_B0__OFFSETC3I_0__MASK                         0x01f00000U
1180 #define DC_CAL_STATUS_B0__OFFSETC3I_0__READ(src) \
1181                     (((u_int32_t)(src)\
1182                     & 0x01f00000U) >> 20)
1183
1184 /* macros for field offsetC3Q_0 */
1185 #define DC_CAL_STATUS_B0__OFFSETC3Q_0__SHIFT                                 25
1186 #define DC_CAL_STATUS_B0__OFFSETC3Q_0__WIDTH                                  5
1187 #define DC_CAL_STATUS_B0__OFFSETC3Q_0__MASK                         0x3e000000U
1188 #define DC_CAL_STATUS_B0__OFFSETC3Q_0__READ(src) \
1189                     (((u_int32_t)(src)\
1190                     & 0x3e000000U) >> 25)
1191 #define DC_CAL_STATUS_B0__TYPE                                        u_int32_t
1192 #define DC_CAL_STATUS_B0__READ                                      0x3fffffffU
1193
1194 #endif /* __DC_CAL_STATUS_B0_MACRO__ */
1195
1196
1197 /* macros for bb_reg_block.bb_agc_reg_map.BB_dc_cal_status_b0 */
1198 #define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_DC_CAL_STATUS_B0__NUM           1
1199
1200 /* macros for BlueprintGlobalNameSpace::bbb_sig_detect */
1201
1202 /* macros for field bbb_mrc_off_no_swap */
1203 #define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__SHIFT                           23
1204 #define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__WIDTH                            1
1205 #define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__MASK                   0x00800000U
1206 #define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__READ(src) \
1207                     (((u_int32_t)(src)\
1208                     & 0x00800000U) >> 23)
1209 #define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__WRITE(src) \
1210                     (((u_int32_t)(src)\
1211                     << 23) & 0x00800000U)
1212 #define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__MODIFY(dst, src) \
1213                     (dst) = ((dst) &\
1214                     ~0x00800000U) | (((u_int32_t)(src) <<\
1215                     23) & 0x00800000U)
1216 #define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__VERIFY(src) \
1217                     (!((((u_int32_t)(src)\
1218                     << 23) & ~0x00800000U)))
1219 #define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__SET(dst) \
1220                     (dst) = ((dst) &\
1221                     ~0x00800000U) | ((u_int32_t)(1) << 23)
1222 #define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__CLR(dst) \
1223                     (dst) = ((dst) &\
1224                     ~0x00800000U) | ((u_int32_t)(0) << 23)
1225
1226 #define BBB_SIG_DETECT__TYPE                                          u_int32_t
1227 #define BBB_SIG_DETECT__READ                                        0x80ffffffU
1228 #define BBB_SIG_DETECT__WRITE                                       0x80ffffffU
1229
1230 /* macros for BlueprintGlobalNameSpace::gen_controls */
1231
1232 /* macros for field enable_dac_async_fifo */
1233 #define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__SHIFT                           11
1234 #define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__WIDTH                            1
1235 #define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__MASK                   0x00000800U
1236 #define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__READ(src) \
1237                     (((u_int32_t)(src)\
1238                     & 0x00000800U) >> 11)
1239 #define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__WRITE(src) \
1240                     (((u_int32_t)(src)\
1241                     << 11) & 0x00000800U)
1242 #define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__MODIFY(dst, src) \
1243                     (dst) = ((dst) &\
1244                     ~0x00000800U) | (((u_int32_t)(src) <<\
1245                     11) & 0x00000800U)
1246 #define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__VERIFY(src) \
1247                     (!((((u_int32_t)(src)\
1248                     << 11) & ~0x00000800U)))
1249 #define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__SET(dst) \
1250                     (dst) = ((dst) &\
1251                     ~0x00000800U) | ((u_int32_t)(1) << 11)
1252 #define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__CLR(dst) \
1253                     (dst) = ((dst) &\
1254                     ~0x00000800U) | ((u_int32_t)(0) << 11)
1255
1256
1257 /* macros for field static20_mode_ht40_packet_handling */
1258 #define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__SHIFT              15
1259 #define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__WIDTH               1
1260 #define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__MASK      0x00008000U
1261 #define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__READ(src) \
1262                     (((u_int32_t)(src)\
1263                     & 0x00008000U) >> 15)
1264 #define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__WRITE(src) \
1265                     (((u_int32_t)(src)\
1266                     << 15) & 0x00008000U)
1267 #define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__MODIFY(dst, src) \
1268                     (dst) = ((dst) &\
1269                     ~0x00008000U) | (((u_int32_t)(src) <<\
1270                     15) & 0x00008000U)
1271 #define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__VERIFY(src) \
1272                     (!((((u_int32_t)(src)\
1273                     << 15) & ~0x00008000U)))
1274 #define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__SET(dst) \
1275                     (dst) = ((dst) &\
1276                     ~0x00008000U) | ((u_int32_t)(1) << 15)
1277 #define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__CLR(dst) \
1278                     (dst) = ((dst) &\
1279                     ~0x00008000U) | ((u_int32_t)(0) << 15)
1280
1281 /* macros for field static20_mode_ht40_packet_error_rpt */
1282 #define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__SHIFT             16
1283 #define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__WIDTH              1
1284 #define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__MASK     0x00010000U
1285 #define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__READ(src) \
1286                     (((u_int32_t)(src)\
1287                     & 0x00010000U) >> 16)
1288 #define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__WRITE(src) \
1289                     (((u_int32_t)(src)\
1290                     << 16) & 0x00010000U)
1291 #define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__MODIFY(dst, src) \
1292                     (dst) = ((dst) &\
1293                     ~0x00010000U) | (((u_int32_t)(src) <<\
1294                     16) & 0x00010000U)
1295 #define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__VERIFY(src) \
1296                     (!((((u_int32_t)(src)\
1297                     << 16) & ~0x00010000U)))
1298 #define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__SET(dst) \
1299                     (dst) = ((dst) &\
1300                     ~0x00010000U) | ((u_int32_t)(1) << 16)
1301 #define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__CLR(dst) \
1302                     (dst) = ((dst) &\
1303                     ~0x00010000U) | ((u_int32_t)(0) << 16)
1304
1305 /* macros for field unsupp_ht_rate_threshold */
1306 #define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__SHIFT                        18
1307 #define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__WIDTH                         7
1308 #define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__MASK                0x01fc0000U
1309 #define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__READ(src) \
1310                     (((u_int32_t)(src)\
1311                     & 0x01fc0000U) >> 18)
1312 #define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__WRITE(src) \
1313                     (((u_int32_t)(src)\
1314                     << 18) & 0x01fc0000U)
1315 #define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__MODIFY(dst, src) \
1316                     (dst) = ((dst) &\
1317                     ~0x01fc0000U) | (((u_int32_t)(src) <<\
1318                     18) & 0x01fc0000U)
1319 #define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__VERIFY(src) \
1320                     (!((((u_int32_t)(src)\
1321                     << 18) & ~0x01fc0000U)))
1322 #define GEN_CONTROLS__TYPE                                            u_int32_t
1323 #define GEN_CONTROLS__READ                                          0x01fdffffU
1324 #define GEN_CONTROLS__WRITE                                         0x01fdffffU
1325
1326 /* macros for bb_reg_block.bb_sm_reg_map.BB_gen_controls */
1327
1328 /* macros for BlueprintGlobalNameSpace::bb_reg_page_control */
1329 #ifndef __BB_REG_PAGE_CONTROL_MACRO__
1330 #define __BB_REG_PAGE_CONTROL_MACRO__
1331
1332 /* macros for field disable_bb_reg_page */
1333 #define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__SHIFT                       0
1334 #define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__WIDTH                       1
1335 #define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__MASK              0x00000001U
1336 #define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__READ(src) \
1337                     (u_int32_t)(src)\
1338                     & 0x00000001U
1339 #define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__WRITE(src) \
1340                     ((u_int32_t)(src)\
1341                     & 0x00000001U)
1342 #define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__MODIFY(dst, src) \
1343                     (dst) = ((dst) &\
1344                     ~0x00000001U) | ((u_int32_t)(src) &\
1345                     0x00000001U)
1346 #define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__VERIFY(src) \
1347                     (!(((u_int32_t)(src)\
1348                     & ~0x00000001U)))
1349 #define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__SET(dst) \
1350                     (dst) = ((dst) &\
1351                     ~0x00000001U) | (u_int32_t)(1)
1352 #define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__CLR(dst) \
1353                     (dst) = ((dst) &\
1354                     ~0x00000001U) | (u_int32_t)(0)
1355
1356 /* macros for field bb_register_page */
1357 #define BB_REG_PAGE_CONTROL__BB_REGISTER_PAGE__SHIFT                          1
1358 #define BB_REG_PAGE_CONTROL__BB_REGISTER_PAGE__WIDTH                          3
1359 #define BB_REG_PAGE_CONTROL__BB_REGISTER_PAGE__MASK                 0x0000000eU
1360 #define BB_REG_PAGE_CONTROL__BB_REGISTER_PAGE__READ(src) \
1361                     (((u_int32_t)(src)\
1362                     & 0x0000000eU) >> 1)
1363 #define BB_REG_PAGE_CONTROL__BB_REGISTER_PAGE__WRITE(src) \
1364                     (((u_int32_t)(src)\
1365                     << 1) & 0x0000000eU)
1366 #define BB_REG_PAGE_CONTROL__BB_REGISTER_PAGE__MODIFY(dst, src) \
1367                     (dst) = ((dst) &\
1368                     ~0x0000000eU) | (((u_int32_t)(src) <<\
1369                     1) & 0x0000000eU)
1370 #define BB_REG_PAGE_CONTROL__BB_REGISTER_PAGE__VERIFY(src) \
1371                     (!((((u_int32_t)(src)\
1372                     << 1) & ~0x0000000eU)))
1373
1374 /* macros for field direct_access_page */
1375 #define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__SHIFT                        4
1376 #define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__WIDTH                        1
1377 #define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__MASK               0x00000010U
1378 #define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__READ(src) \
1379                     (((u_int32_t)(src)\
1380                     & 0x00000010U) >> 4)
1381 #define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__WRITE(src) \
1382                     (((u_int32_t)(src)\
1383                     << 4) & 0x00000010U)
1384 #define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__MODIFY(dst, src) \
1385                     (dst) = ((dst) &\
1386                     ~0x00000010U) | (((u_int32_t)(src) <<\
1387                     4) & 0x00000010U)
1388 #define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__VERIFY(src) \
1389                     (!((((u_int32_t)(src)\
1390                     << 4) & ~0x00000010U)))
1391 #define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__SET(dst) \
1392                     (dst) = ((dst) &\
1393                     ~0x00000010U) | ((u_int32_t)(1) << 4)
1394 #define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__CLR(dst) \
1395                     (dst) = ((dst) &\
1396                     ~0x00000010U) | ((u_int32_t)(0) << 4)
1397 #define BB_REG_PAGE_CONTROL__TYPE                                     u_int32_t
1398 #define BB_REG_PAGE_CONTROL__READ                                   0x0000001fU
1399 #define BB_REG_PAGE_CONTROL__WRITE                                  0x0000001fU
1400
1401 #endif /* __BB_REG_PAGE_CONTROL_MACRO__ */
1402
1403
1404 /* macros for bb_reg_block.bb_bbb_reg_map.BB_bb_reg_page_control */
1405 #define INST_BB_REG_BLOCK__BB_BBB_REG_MAP__BB_BB_REG_PAGE_CONTROL__NUM        1
1406
1407 /* macros for BlueprintGlobalNameSpace::spectral_scan */
1408
1409
1410 /* macros for field spectral_scan_compressed_rpt */
1411 #define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__SHIFT                   31
1412 #define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__WIDTH                    1
1413 #define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__MASK           0x80000000U
1414 #define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__READ(src) \
1415                     (((u_int32_t)(src)\
1416                     & 0x80000000U) >> 31)
1417 #define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__WRITE(src) \
1418                     (((u_int32_t)(src)\
1419                     << 31) & 0x80000000U)
1420 #define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__MODIFY(dst, src) \
1421                     (dst) = ((dst) &\
1422                     ~0x80000000U) | (((u_int32_t)(src) <<\
1423                     31) & 0x80000000U)
1424 #define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__VERIFY(src) \
1425                     (!((((u_int32_t)(src)\
1426                     << 31) & ~0x80000000U)))
1427 #define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__SET(dst) \
1428                     (dst) = ((dst) &\
1429                     ~0x80000000U) | ((u_int32_t)(1) << 31)
1430 #define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__CLR(dst) \
1431                     (dst) = ((dst) &\
1432                     ~0x80000000U) | ((u_int32_t)(0) << 31)
1433 #define SPECTRAL_SCAN__TYPE                                           u_int32_t
1434 #define SPECTRAL_SCAN__READ                                         0xffffffffU
1435 #define SPECTRAL_SCAN__WRITE                                        0xffffffffU
1436
1437 /* macros for bb_reg_block.bb_sm_reg_map.BB_spectral_scan */
1438
1439 /* macros for BlueprintGlobalNameSpace::search_start_delay */
1440
1441
1442 /* macros for field rx_sounding_enable */
1443 #define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__SHIFT                        14
1444 #define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__WIDTH                         1
1445 #define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__MASK                0x00004000U
1446 #define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__READ(src) \
1447                     (((u_int32_t)(src)\
1448                     & 0x00004000U) >> 14)
1449 #define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__WRITE(src) \
1450                     (((u_int32_t)(src)\
1451                     << 14) & 0x00004000U)
1452 #define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__MODIFY(dst, src) \
1453                     (dst) = ((dst) &\
1454                     ~0x00004000U) | (((u_int32_t)(src) <<\
1455                     14) & 0x00004000U)
1456 #define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__VERIFY(src) \
1457                     (!((((u_int32_t)(src)\
1458                     << 14) & ~0x00004000U)))
1459 #define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__SET(dst) \
1460                     (dst) = ((dst) &\
1461                     ~0x00004000U) | ((u_int32_t)(1) << 14)
1462 #define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__CLR(dst) \
1463                     (dst) = ((dst) &\
1464                     ~0x00004000U) | ((u_int32_t)(0) << 14)
1465
1466 /* macros for field rm_hcsd4svd */
1467 #define SEARCH_START_DELAY__RM_HCSD4SVD__SHIFT                               15
1468 #define SEARCH_START_DELAY__RM_HCSD4SVD__WIDTH                                1
1469 #define SEARCH_START_DELAY__RM_HCSD4SVD__MASK                       0x00008000U
1470 #define SEARCH_START_DELAY__RM_HCSD4SVD__READ(src) \
1471                     (((u_int32_t)(src)\
1472                     & 0x00008000U) >> 15)
1473 #define SEARCH_START_DELAY__RM_HCSD4SVD__WRITE(src) \
1474                     (((u_int32_t)(src)\
1475                     << 15) & 0x00008000U)
1476 #define SEARCH_START_DELAY__RM_HCSD4SVD__MODIFY(dst, src) \
1477                     (dst) = ((dst) &\
1478                     ~0x00008000U) | (((u_int32_t)(src) <<\
1479                     15) & 0x00008000U)
1480 #define SEARCH_START_DELAY__RM_HCSD4SVD__VERIFY(src) \
1481                     (!((((u_int32_t)(src)\
1482                     << 15) & ~0x00008000U)))
1483 #define SEARCH_START_DELAY__RM_HCSD4SVD__SET(dst) \
1484                     (dst) = ((dst) &\
1485                     ~0x00008000U) | ((u_int32_t)(1) << 15)
1486 #define SEARCH_START_DELAY__RM_HCSD4SVD__CLR(dst) \
1487                     (dst) = ((dst) &\
1488                     ~0x00008000U) | ((u_int32_t)(0) << 15)
1489 #define SEARCH_START_DELAY__TYPE                                      u_int32_t
1490 #define SEARCH_START_DELAY__READ                                    0x0000ffffU
1491 #define SEARCH_START_DELAY__WRITE                                   0x0000ffffU
1492
1493 /* macros for bb_reg_block.bb_sm_reg_map.BB_search_start_delay */
1494
1495 /* macros for BlueprintGlobalNameSpace::frame_control */
1496
1497 /* macros for field en_err_static20_mode_ht40_packet */
1498 #define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__SHIFT               19
1499 #define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__WIDTH                1
1500 #define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__MASK       0x00080000U
1501 #define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__READ(src) \
1502                     (((u_int32_t)(src)\
1503                     & 0x00080000U) >> 19)
1504 #define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__WRITE(src) \
1505                     (((u_int32_t)(src)\
1506                     << 19) & 0x00080000U)
1507 #define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__MODIFY(dst, src) \
1508                     (dst) = ((dst) &\
1509                     ~0x00080000U) | (((u_int32_t)(src) <<\
1510                     19) & 0x00080000U)
1511 #define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__VERIFY(src) \
1512                     (!((((u_int32_t)(src)\
1513                     << 19) & ~0x00080000U)))
1514 #define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__SET(dst) \
1515                     (dst) = ((dst) &\
1516                     ~0x00080000U) | ((u_int32_t)(1) << 19)
1517 #define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__CLR(dst) \
1518                     (dst) = ((dst) &\
1519                     ~0x00080000U) | ((u_int32_t)(0) << 19)
1520
1521 /* macros for bb_reg_block.bb_sm_reg_map.BB_frame_control */
1522
1523 /* macros for BlueprintGlobalNameSpace::switch_table_com1 */
1524
1525 /* macros for field switch_table_com_spdt */
1526 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_SPDT__SHIFT                      20
1527 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_SPDT__WIDTH                       4
1528 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_SPDT__MASK              0x00f00000U
1529 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_SPDT__READ(src) \
1530                     (((u_int32_t)(src)\
1531                     & 0x00f00000U) >> 20)
1532 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_SPDT__WRITE(src) \
1533                     (((u_int32_t)(src)\
1534                     << 20) & 0x00f00000U)
1535 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_SPDT__MODIFY(dst, src) \
1536                     (dst) = ((dst) &\
1537                     ~0x00f00000U) | (((u_int32_t)(src) <<\
1538                     20) & 0x00f00000U)
1539 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_SPDT__VERIFY(src) \
1540                     (!((((u_int32_t)(src)\
1541                     << 20) & ~0x00f00000U)))
1542 #define SWITCH_TABLE_COM1__TYPE                                       u_int32_t
1543 #define SWITCH_TABLE_COM1__READ                                     0x00ffffffU
1544 #define SWITCH_TABLE_COM1__WRITE                                    0x00ffffffU
1545
1546 /* macros for bb_reg_block.bb_sm_reg_map.BB_switch_table_com1 */
1547
1548 /* macros for bb_reg_block.bb_sm_reg_map.BB_powertx_rate12 */
1549
1550 /* macros for field use_per_packet_olpc_gain_delta_adj */
1551 #define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__SHIFT                7
1552 #define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__WIDTH                1
1553 #define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__MASK       0x00000080U
1554 #define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__READ(src) \
1555                     (((u_int32_t)(src)\
1556                     & 0x00000080U) >> 7)
1557 #define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__WRITE(src) \
1558                     (((u_int32_t)(src)\
1559                     << 7) & 0x00000080U)
1560 #define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__MODIFY(dst, src) \
1561                     (dst) = ((dst) &\
1562                     ~0x00000080U) | (((u_int32_t)(src) <<\
1563                     7) & 0x00000080U)
1564 #define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__VERIFY(src) \
1565                     (!((((u_int32_t)(src)\
1566                     << 7) & ~0x00000080U)))
1567 #define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__SET(dst) \
1568                     (dst) = ((dst) &\
1569                     ~0x00000080U) | ((u_int32_t)(1) << 7)
1570 #define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__CLR(dst) \
1571                     (dst) = ((dst) &\
1572                     ~0x00000080U) | ((u_int32_t)(0) << 7)
1573 #define POWERTX_MAX__TYPE                                             u_int32_t
1574 #define POWERTX_MAX__READ                                           0x000000c0U
1575 #define POWERTX_MAX__WRITE                                          0x000000c0U
1576
1577 /* macros for bb_reg_block.bb_sm_reg_map.BB_powertx_max */
1578
1579 /* macros for BlueprintGlobalNameSpace::tx_forced_gain */
1580
1581
1582 /* macros for field forced_ob2G */
1583 #define TX_FORCED_GAIN__FORCED_OB2G__SHIFT                                   25
1584 #define TX_FORCED_GAIN__FORCED_OB2G__WIDTH                                    3
1585 #define TX_FORCED_GAIN__FORCED_OB2G__MASK                           0x0e000000U
1586 #define TX_FORCED_GAIN__FORCED_OB2G__READ(src) \
1587                     (((u_int32_t)(src)\
1588                     & 0x0e000000U) >> 25)
1589 #define TX_FORCED_GAIN__FORCED_OB2G__WRITE(src) \
1590                     (((u_int32_t)(src)\
1591                     << 25) & 0x0e000000U)
1592 #define TX_FORCED_GAIN__FORCED_OB2G__MODIFY(dst, src) \
1593                     (dst) = ((dst) &\
1594                     ~0x0e000000U) | (((u_int32_t)(src) <<\
1595                     25) & 0x0e000000U)
1596 #define TX_FORCED_GAIN__FORCED_OB2G__VERIFY(src) \
1597                     (!((((u_int32_t)(src)\
1598                     << 25) & ~0x0e000000U)))
1599
1600 /* macros for field forced_db2G */
1601 #define TX_FORCED_GAIN__FORCED_DB2G__SHIFT                                   28
1602 #define TX_FORCED_GAIN__FORCED_DB2G__WIDTH                                    3
1603 #define TX_FORCED_GAIN__FORCED_DB2G__MASK                           0x70000000U
1604 #define TX_FORCED_GAIN__FORCED_DB2G__READ(src) \
1605                     (((u_int32_t)(src)\
1606                     & 0x70000000U) >> 28)
1607 #define TX_FORCED_GAIN__FORCED_DB2G__WRITE(src) \
1608                     (((u_int32_t)(src)\
1609                     << 28) & 0x70000000U)
1610 #define TX_FORCED_GAIN__FORCED_DB2G__MODIFY(dst, src) \
1611                     (dst) = ((dst) &\
1612                     ~0x70000000U) | (((u_int32_t)(src) <<\
1613                     28) & 0x70000000U)
1614 #define TX_FORCED_GAIN__FORCED_DB2G__VERIFY(src) \
1615                     (!((((u_int32_t)(src)\
1616                     << 28) & ~0x70000000U)))
1617
1618 /* macros for field forced_green_paprd_enable */
1619 #define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__SHIFT                     31
1620 #define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__WIDTH                      1
1621 #define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__MASK             0x80000000U
1622 #define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__READ(src) \
1623                     (((u_int32_t)(src)\
1624                     & 0x80000000U) >> 31)
1625 #define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__WRITE(src) \
1626                     (((u_int32_t)(src)\
1627                     << 31) & 0x80000000U)
1628 #define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__MODIFY(dst, src) \
1629                     (dst) = ((dst) &\
1630                     ~0x80000000U) | (((u_int32_t)(src) <<\
1631                     31) & 0x80000000U)
1632 #define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__VERIFY(src) \
1633                     (!((((u_int32_t)(src)\
1634                     << 31) & ~0x80000000U)))
1635 #define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__SET(dst) \
1636                     (dst) = ((dst) &\
1637                     ~0x80000000U) | ((u_int32_t)(1) << 31)
1638 #define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__CLR(dst) \
1639                     (dst) = ((dst) &\
1640                     ~0x80000000U) | ((u_int32_t)(0) << 31)
1641 #define TX_FORCED_GAIN__TYPE                                          u_int32_t
1642 #define TX_FORCED_GAIN__READ                                        0xffffffffU
1643 #define TX_FORCED_GAIN__WRITE                                       0xffffffffU
1644
1645 /* macros for bb_reg_block.bb_sm_reg_map.BB_tx_forced_gain */
1646
1647 /* macros for BlueprintGlobalNameSpace::txiqcal_control_0 */
1648
1649
1650 /* macros for field enable_txiq_calibrate */
1651 #define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__SHIFT                      31
1652 #define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__WIDTH                       1
1653 #define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__MASK              0x80000000U
1654 #define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__READ(src) \
1655                     (((u_int32_t)(src)\
1656                     & 0x80000000U) >> 31)
1657 #define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__WRITE(src) \
1658                     (((u_int32_t)(src)\
1659                     << 31) & 0x80000000U)
1660 #define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__MODIFY(dst, src) \
1661                     (dst) = ((dst) &\
1662                     ~0x80000000U) | (((u_int32_t)(src) <<\
1663                     31) & 0x80000000U)
1664 #define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__VERIFY(src) \
1665                     (!((((u_int32_t)(src)\
1666                     << 31) & ~0x80000000U)))
1667 #define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__SET(dst) \
1668                     (dst) = ((dst) &\
1669                     ~0x80000000U) | ((u_int32_t)(1) << 31)
1670 #define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__CLR(dst) \
1671                     (dst) = ((dst) &\
1672                     ~0x80000000U) | ((u_int32_t)(0) << 31)
1673 #define TXIQCAL_CONTROL_0__TYPE                                       u_int32_t
1674 #define TXIQCAL_CONTROL_0__READ                                     0xffffffffU
1675 #define TXIQCAL_CONTROL_0__WRITE                                    0xffffffffU
1676
1677 /* macros for bb_reg_block.bb_sm_reg_map.BB_txiqcal_control_0 */
1678
1679 /* macros for BlueprintGlobalNameSpace::txiqcal_control_0 */
1680
1681 /* macros for field enable_txiq_calibrate */
1682 #define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__SHIFT                      31
1683 #define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__WIDTH                       1
1684 #define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__MASK              0x80000000U
1685 #define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__READ(src) \
1686                     (((u_int32_t)(src)\
1687                     & 0x80000000U) >> 31)
1688 #define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__WRITE(src) \
1689                     (((u_int32_t)(src)\
1690                     << 31) & 0x80000000U)
1691 #define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__MODIFY(dst, src) \
1692                     (dst) = ((dst) &\
1693                     ~0x80000000U) | (((u_int32_t)(src) <<\
1694                     31) & 0x80000000U)
1695 #define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__VERIFY(src) \
1696                     (!((((u_int32_t)(src)\
1697                     << 31) & ~0x80000000U)))
1698 #define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__SET(dst) \
1699                     (dst) = ((dst) &\
1700                     ~0x80000000U) | ((u_int32_t)(1) << 31)
1701 #define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__CLR(dst) \
1702                     (dst) = ((dst) &\
1703                     ~0x80000000U) | ((u_int32_t)(0) << 31)
1704 #define TXIQCAL_CONTROL_0__TYPE                                       u_int32_t
1705 #define TXIQCAL_CONTROL_0__READ                                     0xffffffffU
1706 #define TXIQCAL_CONTROL_0__WRITE                                    0xffffffffU
1707
1708 /* macros for bb_reg_block.bb_sm_reg_map.BB_txiqcal_control_0 */
1709
1710 /* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_0_1_b0 */
1711 #ifndef __PAPRD_PRE_POST_SCALE_0_1_B0_MACRO__
1712 #define __PAPRD_PRE_POST_SCALE_0_1_B0_MACRO__
1713
1714 /* macros for field paprd_pre_post_scaling_0_1_b0 */
1715 #define PAPRD_PRE_POST_SCALE_0_1_B0__PAPRD_PRE_POST_SCALING_0_1_B0__SHIFT     0
1716 #define PAPRD_PRE_POST_SCALE_0_1_B0__PAPRD_PRE_POST_SCALING_0_1_B0__WIDTH    18
1717 #define PAPRD_PRE_POST_SCALE_0_1_B0__PAPRD_PRE_POST_SCALING_0_1_B0__MASK \
1718                     0x0003ffffU
1719 #define PAPRD_PRE_POST_SCALE_0_1_B0__PAPRD_PRE_POST_SCALING_0_1_B0__READ(src) \
1720                     (u_int32_t)(src)\
1721                     & 0x0003ffffU
1722 #define PAPRD_PRE_POST_SCALE_0_1_B0__PAPRD_PRE_POST_SCALING_0_1_B0__WRITE(src) \
1723                     ((u_int32_t)(src)\
1724                     & 0x0003ffffU)
1725 #define PAPRD_PRE_POST_SCALE_0_1_B0__PAPRD_PRE_POST_SCALING_0_1_B0__MODIFY(dst, src) \
1726                     (dst) = ((dst) &\
1727                     ~0x0003ffffU) | ((u_int32_t)(src) &\
1728                     0x0003ffffU)
1729 #define PAPRD_PRE_POST_SCALE_0_1_B0__PAPRD_PRE_POST_SCALING_0_1_B0__VERIFY(src) \
1730                     (!(((u_int32_t)(src)\
1731                     & ~0x0003ffffU)))
1732 #define PAPRD_PRE_POST_SCALE_0_1_B0__TYPE                             u_int32_t
1733 #define PAPRD_PRE_POST_SCALE_0_1_B0__READ                           0x0003ffffU
1734 #define PAPRD_PRE_POST_SCALE_0_1_B0__WRITE                          0x0003ffffU
1735
1736 #endif /* __PAPRD_PRE_POST_SCALE_0_1_B0_MACRO__ */
1737
1738
1739 /* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_0_1_b0 */
1740 #define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_0_1_B0__NUM \
1741                     1
1742
1743 /* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_1_1_b0 */
1744 #ifndef __PAPRD_PRE_POST_SCALE_1_1_B0_MACRO__
1745 #define __PAPRD_PRE_POST_SCALE_1_1_B0_MACRO__
1746
1747 /* macros for field paprd_pre_post_scaling_1_1_b0 */
1748 #define PAPRD_PRE_POST_SCALE_1_1_B0__PAPRD_PRE_POST_SCALING_1_1_B0__SHIFT     0
1749 #define PAPRD_PRE_POST_SCALE_1_1_B0__PAPRD_PRE_POST_SCALING_1_1_B0__WIDTH    18
1750 #define PAPRD_PRE_POST_SCALE_1_1_B0__PAPRD_PRE_POST_SCALING_1_1_B0__MASK \
1751                     0x0003ffffU
1752 #define PAPRD_PRE_POST_SCALE_1_1_B0__PAPRD_PRE_POST_SCALING_1_1_B0__READ(src) \
1753                     (u_int32_t)(src)\
1754                     & 0x0003ffffU
1755 #define PAPRD_PRE_POST_SCALE_1_1_B0__PAPRD_PRE_POST_SCALING_1_1_B0__WRITE(src) \
1756                     ((u_int32_t)(src)\
1757                     & 0x0003ffffU)
1758 #define PAPRD_PRE_POST_SCALE_1_1_B0__PAPRD_PRE_POST_SCALING_1_1_B0__MODIFY(dst, src) \
1759                     (dst) = ((dst) &\
1760                     ~0x0003ffffU) | ((u_int32_t)(src) &\
1761                     0x0003ffffU)
1762 #define PAPRD_PRE_POST_SCALE_1_1_B0__PAPRD_PRE_POST_SCALING_1_1_B0__VERIFY(src) \
1763                     (!(((u_int32_t)(src)\
1764                     & ~0x0003ffffU)))
1765 #define PAPRD_PRE_POST_SCALE_1_1_B0__TYPE                             u_int32_t
1766 #define PAPRD_PRE_POST_SCALE_1_1_B0__READ                           0x0003ffffU
1767 #define PAPRD_PRE_POST_SCALE_1_1_B0__WRITE                          0x0003ffffU
1768
1769 #endif /* __PAPRD_PRE_POST_SCALE_1_1_B0_MACRO__ */
1770
1771
1772 /* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_1_1_b0 */
1773 #define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_1_1_B0__NUM \
1774                     1
1775
1776 /* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_2_1_b0 */
1777 #ifndef __PAPRD_PRE_POST_SCALE_2_1_B0_MACRO__
1778 #define __PAPRD_PRE_POST_SCALE_2_1_B0_MACRO__
1779
1780 /* macros for field paprd_pre_post_scaling_2_1_b0 */
1781 #define PAPRD_PRE_POST_SCALE_2_1_B0__PAPRD_PRE_POST_SCALING_2_1_B0__SHIFT     0
1782 #define PAPRD_PRE_POST_SCALE_2_1_B0__PAPRD_PRE_POST_SCALING_2_1_B0__WIDTH    18
1783 #define PAPRD_PRE_POST_SCALE_2_1_B0__PAPRD_PRE_POST_SCALING_2_1_B0__MASK \
1784                     0x0003ffffU
1785 #define PAPRD_PRE_POST_SCALE_2_1_B0__PAPRD_PRE_POST_SCALING_2_1_B0__READ(src) \
1786                     (u_int32_t)(src)\
1787                     & 0x0003ffffU
1788 #define PAPRD_PRE_POST_SCALE_2_1_B0__PAPRD_PRE_POST_SCALING_2_1_B0__WRITE(src) \
1789                     ((u_int32_t)(src)\
1790                     & 0x0003ffffU)
1791 #define PAPRD_PRE_POST_SCALE_2_1_B0__PAPRD_PRE_POST_SCALING_2_1_B0__MODIFY(dst, src) \
1792                     (dst) = ((dst) &\
1793                     ~0x0003ffffU) | ((u_int32_t)(src) &\
1794                     0x0003ffffU)
1795 #define PAPRD_PRE_POST_SCALE_2_1_B0__PAPRD_PRE_POST_SCALING_2_1_B0__VERIFY(src) \
1796                     (!(((u_int32_t)(src)\
1797                     & ~0x0003ffffU)))
1798 #define PAPRD_PRE_POST_SCALE_2_1_B0__TYPE                             u_int32_t
1799 #define PAPRD_PRE_POST_SCALE_2_1_B0__READ                           0x0003ffffU
1800 #define PAPRD_PRE_POST_SCALE_2_1_B0__WRITE                          0x0003ffffU
1801
1802 #endif /* __PAPRD_PRE_POST_SCALE_2_1_B0_MACRO__ */
1803
1804
1805 /* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_2_1_b0 */
1806 #define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_2_1_B0__NUM \
1807                     1
1808
1809 /* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_3_1_b0 */
1810 #ifndef __PAPRD_PRE_POST_SCALE_3_1_B0_MACRO__
1811 #define __PAPRD_PRE_POST_SCALE_3_1_B0_MACRO__
1812
1813 /* macros for field paprd_pre_post_scaling_3_1_b0 */
1814 #define PAPRD_PRE_POST_SCALE_3_1_B0__PAPRD_PRE_POST_SCALING_3_1_B0__SHIFT     0
1815 #define PAPRD_PRE_POST_SCALE_3_1_B0__PAPRD_PRE_POST_SCALING_3_1_B0__WIDTH    18
1816 #define PAPRD_PRE_POST_SCALE_3_1_B0__PAPRD_PRE_POST_SCALING_3_1_B0__MASK \
1817                     0x0003ffffU
1818 #define PAPRD_PRE_POST_SCALE_3_1_B0__PAPRD_PRE_POST_SCALING_3_1_B0__READ(src) \
1819                     (u_int32_t)(src)\
1820                     & 0x0003ffffU
1821 #define PAPRD_PRE_POST_SCALE_3_1_B0__PAPRD_PRE_POST_SCALING_3_1_B0__WRITE(src) \
1822                     ((u_int32_t)(src)\
1823                     & 0x0003ffffU)
1824 #define PAPRD_PRE_POST_SCALE_3_1_B0__PAPRD_PRE_POST_SCALING_3_1_B0__MODIFY(dst, src) \
1825                     (dst) = ((dst) &\
1826                     ~0x0003ffffU) | ((u_int32_t)(src) &\
1827                     0x0003ffffU)
1828 #define PAPRD_PRE_POST_SCALE_3_1_B0__PAPRD_PRE_POST_SCALING_3_1_B0__VERIFY(src) \
1829                     (!(((u_int32_t)(src)\
1830                     & ~0x0003ffffU)))
1831 #define PAPRD_PRE_POST_SCALE_3_1_B0__TYPE                             u_int32_t
1832 #define PAPRD_PRE_POST_SCALE_3_1_B0__READ                           0x0003ffffU
1833 #define PAPRD_PRE_POST_SCALE_3_1_B0__WRITE                          0x0003ffffU
1834
1835 #endif /* __PAPRD_PRE_POST_SCALE_3_1_B0_MACRO__ */
1836
1837
1838 /* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_3_1_b0 */
1839 #define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_3_1_B0__NUM \
1840                     1
1841
1842 /* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_4_1_b0 */
1843 #ifndef __PAPRD_PRE_POST_SCALE_4_1_B0_MACRO__
1844 #define __PAPRD_PRE_POST_SCALE_4_1_B0_MACRO__
1845
1846 /* macros for field paprd_pre_post_scaling_4_1_b0 */
1847 #define PAPRD_PRE_POST_SCALE_4_1_B0__PAPRD_PRE_POST_SCALING_4_1_B0__SHIFT     0
1848 #define PAPRD_PRE_POST_SCALE_4_1_B0__PAPRD_PRE_POST_SCALING_4_1_B0__WIDTH    18
1849 #define PAPRD_PRE_POST_SCALE_4_1_B0__PAPRD_PRE_POST_SCALING_4_1_B0__MASK \
1850                     0x0003ffffU
1851 #define PAPRD_PRE_POST_SCALE_4_1_B0__PAPRD_PRE_POST_SCALING_4_1_B0__READ(src) \
1852                     (u_int32_t)(src)\
1853                     & 0x0003ffffU
1854 #define PAPRD_PRE_POST_SCALE_4_1_B0__PAPRD_PRE_POST_SCALING_4_1_B0__WRITE(src) \
1855                     ((u_int32_t)(src)\
1856                     & 0x0003ffffU)
1857 #define PAPRD_PRE_POST_SCALE_4_1_B0__PAPRD_PRE_POST_SCALING_4_1_B0__MODIFY(dst, src) \
1858                     (dst) = ((dst) &\
1859                     ~0x0003ffffU) | ((u_int32_t)(src) &\
1860                     0x0003ffffU)
1861 #define PAPRD_PRE_POST_SCALE_4_1_B0__PAPRD_PRE_POST_SCALING_4_1_B0__VERIFY(src) \
1862                     (!(((u_int32_t)(src)\
1863                     & ~0x0003ffffU)))
1864 #define PAPRD_PRE_POST_SCALE_4_1_B0__TYPE                             u_int32_t
1865 #define PAPRD_PRE_POST_SCALE_4_1_B0__READ                           0x0003ffffU
1866 #define PAPRD_PRE_POST_SCALE_4_1_B0__WRITE                          0x0003ffffU
1867
1868 #endif /* __PAPRD_PRE_POST_SCALE_4_1_B0_MACRO__ */
1869
1870
1871 /* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_4_1_b0 */
1872 #define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_4_1_B0__NUM \
1873                     1
1874
1875 /* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_5_1_b0 */
1876 #ifndef __PAPRD_PRE_POST_SCALE_5_1_B0_MACRO__
1877 #define __PAPRD_PRE_POST_SCALE_5_1_B0_MACRO__
1878
1879 /* macros for field paprd_pre_post_scaling_5_1_b0 */
1880 #define PAPRD_PRE_POST_SCALE_5_1_B0__PAPRD_PRE_POST_SCALING_5_1_B0__SHIFT     0
1881 #define PAPRD_PRE_POST_SCALE_5_1_B0__PAPRD_PRE_POST_SCALING_5_1_B0__WIDTH    18
1882 #define PAPRD_PRE_POST_SCALE_5_1_B0__PAPRD_PRE_POST_SCALING_5_1_B0__MASK \
1883                     0x0003ffffU
1884 #define PAPRD_PRE_POST_SCALE_5_1_B0__PAPRD_PRE_POST_SCALING_5_1_B0__READ(src) \
1885                     (u_int32_t)(src)\
1886                     & 0x0003ffffU
1887 #define PAPRD_PRE_POST_SCALE_5_1_B0__PAPRD_PRE_POST_SCALING_5_1_B0__WRITE(src) \
1888                     ((u_int32_t)(src)\
1889                     & 0x0003ffffU)
1890 #define PAPRD_PRE_POST_SCALE_5_1_B0__PAPRD_PRE_POST_SCALING_5_1_B0__MODIFY(dst, src) \
1891                     (dst) = ((dst) &\
1892                     ~0x0003ffffU) | ((u_int32_t)(src) &\
1893                     0x0003ffffU)
1894 #define PAPRD_PRE_POST_SCALE_5_1_B0__PAPRD_PRE_POST_SCALING_5_1_B0__VERIFY(src) \
1895                     (!(((u_int32_t)(src)\
1896                     & ~0x0003ffffU)))
1897 #define PAPRD_PRE_POST_SCALE_5_1_B0__TYPE                             u_int32_t
1898 #define PAPRD_PRE_POST_SCALE_5_1_B0__READ                           0x0003ffffU
1899 #define PAPRD_PRE_POST_SCALE_5_1_B0__WRITE                          0x0003ffffU
1900
1901 #endif /* __PAPRD_PRE_POST_SCALE_5_1_B0_MACRO__ */
1902
1903
1904 /* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_5_1_b0 */
1905 #define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_5_1_B0__NUM \
1906                     1
1907
1908 /* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_6_1_b0 */
1909 #ifndef __PAPRD_PRE_POST_SCALE_6_1_B0_MACRO__
1910 #define __PAPRD_PRE_POST_SCALE_6_1_B0_MACRO__
1911
1912 /* macros for field paprd_pre_post_scaling_6_1_b0 */
1913 #define PAPRD_PRE_POST_SCALE_6_1_B0__PAPRD_PRE_POST_SCALING_6_1_B0__SHIFT     0
1914 #define PAPRD_PRE_POST_SCALE_6_1_B0__PAPRD_PRE_POST_SCALING_6_1_B0__WIDTH    18
1915 #define PAPRD_PRE_POST_SCALE_6_1_B0__PAPRD_PRE_POST_SCALING_6_1_B0__MASK \
1916                     0x0003ffffU
1917 #define PAPRD_PRE_POST_SCALE_6_1_B0__PAPRD_PRE_POST_SCALING_6_1_B0__READ(src) \
1918                     (u_int32_t)(src)\
1919                     & 0x0003ffffU
1920 #define PAPRD_PRE_POST_SCALE_6_1_B0__PAPRD_PRE_POST_SCALING_6_1_B0__WRITE(src) \
1921                     ((u_int32_t)(src)\
1922                     & 0x0003ffffU)
1923 #define PAPRD_PRE_POST_SCALE_6_1_B0__PAPRD_PRE_POST_SCALING_6_1_B0__MODIFY(dst, src) \
1924                     (dst) = ((dst) &\
1925                     ~0x0003ffffU) | ((u_int32_t)(src) &\
1926                     0x0003ffffU)
1927 #define PAPRD_PRE_POST_SCALE_6_1_B0__PAPRD_PRE_POST_SCALING_6_1_B0__VERIFY(src) \
1928                     (!(((u_int32_t)(src)\
1929                     & ~0x0003ffffU)))
1930 #define PAPRD_PRE_POST_SCALE_6_1_B0__TYPE                             u_int32_t
1931 #define PAPRD_PRE_POST_SCALE_6_1_B0__READ                           0x0003ffffU
1932 #define PAPRD_PRE_POST_SCALE_6_1_B0__WRITE                          0x0003ffffU
1933
1934 #endif /* __PAPRD_PRE_POST_SCALE_6_1_B0_MACRO__ */
1935
1936
1937 /* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_6_1_b0 */
1938 #define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_6_1_B0__NUM \
1939                     1
1940
1941 /* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_7_1_b0 */
1942 #ifndef __PAPRD_PRE_POST_SCALE_7_1_B0_MACRO__
1943 #define __PAPRD_PRE_POST_SCALE_7_1_B0_MACRO__
1944
1945 /* macros for field paprd_pre_post_scaling_7_1_b0 */
1946 #define PAPRD_PRE_POST_SCALE_7_1_B0__PAPRD_PRE_POST_SCALING_7_1_B0__SHIFT     0
1947 #define PAPRD_PRE_POST_SCALE_7_1_B0__PAPRD_PRE_POST_SCALING_7_1_B0__WIDTH    18
1948 #define PAPRD_PRE_POST_SCALE_7_1_B0__PAPRD_PRE_POST_SCALING_7_1_B0__MASK \
1949                     0x0003ffffU
1950 #define PAPRD_PRE_POST_SCALE_7_1_B0__PAPRD_PRE_POST_SCALING_7_1_B0__READ(src) \
1951                     (u_int32_t)(src)\
1952                     & 0x0003ffffU
1953 #define PAPRD_PRE_POST_SCALE_7_1_B0__PAPRD_PRE_POST_SCALING_7_1_B0__WRITE(src) \
1954                     ((u_int32_t)(src)\
1955                     & 0x0003ffffU)
1956 #define PAPRD_PRE_POST_SCALE_7_1_B0__PAPRD_PRE_POST_SCALING_7_1_B0__MODIFY(dst, src) \
1957                     (dst) = ((dst) &\
1958                     ~0x0003ffffU) | ((u_int32_t)(src) &\
1959                     0x0003ffffU)
1960 #define PAPRD_PRE_POST_SCALE_7_1_B0__PAPRD_PRE_POST_SCALING_7_1_B0__VERIFY(src) \
1961                     (!(((u_int32_t)(src)\
1962                     & ~0x0003ffffU)))
1963 #define PAPRD_PRE_POST_SCALE_7_1_B0__TYPE                             u_int32_t
1964 #define PAPRD_PRE_POST_SCALE_7_1_B0__READ                           0x0003ffffU
1965 #define PAPRD_PRE_POST_SCALE_7_1_B0__WRITE                          0x0003ffffU
1966
1967 #endif /* __PAPRD_PRE_POST_SCALE_7_1_B0_MACRO__ */
1968
1969
1970 /* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_7_1_b0 */
1971 #define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_7_1_B0__NUM \
1972                     1
1973
1974 /* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_0_2_b0 */
1975 #ifndef __PAPRD_PRE_POST_SCALE_0_2_B0_MACRO__
1976 #define __PAPRD_PRE_POST_SCALE_0_2_B0_MACRO__
1977
1978 /* macros for field paprd_pre_post_scaling_0_2_b0 */
1979 #define PAPRD_PRE_POST_SCALE_0_2_B0__PAPRD_PRE_POST_SCALING_0_2_B0__SHIFT     0
1980 #define PAPRD_PRE_POST_SCALE_0_2_B0__PAPRD_PRE_POST_SCALING_0_2_B0__WIDTH    18
1981 #define PAPRD_PRE_POST_SCALE_0_2_B0__PAPRD_PRE_POST_SCALING_0_2_B0__MASK \
1982                     0x0003ffffU
1983 #define PAPRD_PRE_POST_SCALE_0_2_B0__PAPRD_PRE_POST_SCALING_0_2_B0__READ(src) \
1984                     (u_int32_t)(src)\
1985                     & 0x0003ffffU
1986 #define PAPRD_PRE_POST_SCALE_0_2_B0__PAPRD_PRE_POST_SCALING_0_2_B0__WRITE(src) \
1987                     ((u_int32_t)(src)\
1988                     & 0x0003ffffU)
1989 #define PAPRD_PRE_POST_SCALE_0_2_B0__PAPRD_PRE_POST_SCALING_0_2_B0__MODIFY(dst, src) \
1990                     (dst) = ((dst) &\
1991                     ~0x0003ffffU) | ((u_int32_t)(src) &\
1992                     0x0003ffffU)
1993 #define PAPRD_PRE_POST_SCALE_0_2_B0__PAPRD_PRE_POST_SCALING_0_2_B0__VERIFY(src) \
1994                     (!(((u_int32_t)(src)\
1995                     & ~0x0003ffffU)))
1996 #define PAPRD_PRE_POST_SCALE_0_2_B0__TYPE                             u_int32_t
1997 #define PAPRD_PRE_POST_SCALE_0_2_B0__READ                           0x0003ffffU
1998 #define PAPRD_PRE_POST_SCALE_0_2_B0__WRITE                          0x0003ffffU
1999
2000 #endif /* __PAPRD_PRE_POST_SCALE_0_2_B0_MACRO__ */
2001
2002
2003 /* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_0_2_b0 */
2004 #define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_0_2_B0__NUM \
2005                     1
2006
2007 /* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_1_2_b0 */
2008 #ifndef __PAPRD_PRE_POST_SCALE_1_2_B0_MACRO__
2009 #define __PAPRD_PRE_POST_SCALE_1_2_B0_MACRO__
2010
2011 /* macros for field paprd_pre_post_scaling_1_2_b0 */
2012 #define PAPRD_PRE_POST_SCALE_1_2_B0__PAPRD_PRE_POST_SCALING_1_2_B0__SHIFT     0
2013 #define PAPRD_PRE_POST_SCALE_1_2_B0__PAPRD_PRE_POST_SCALING_1_2_B0__WIDTH    18
2014 #define PAPRD_PRE_POST_SCALE_1_2_B0__PAPRD_PRE_POST_SCALING_1_2_B0__MASK \
2015                     0x0003ffffU
2016 #define PAPRD_PRE_POST_SCALE_1_2_B0__PAPRD_PRE_POST_SCALING_1_2_B0__READ(src) \
2017                     (u_int32_t)(src)\
2018                     & 0x0003ffffU
2019 #define PAPRD_PRE_POST_SCALE_1_2_B0__PAPRD_PRE_POST_SCALING_1_2_B0__WRITE(src) \
2020                     ((u_int32_t)(src)\
2021                     & 0x0003ffffU)
2022 #define PAPRD_PRE_POST_SCALE_1_2_B0__PAPRD_PRE_POST_SCALING_1_2_B0__MODIFY(dst, src) \
2023                     (dst) = ((dst) &\
2024                     ~0x0003ffffU) | ((u_int32_t)(src) &\
2025                     0x0003ffffU)
2026 #define PAPRD_PRE_POST_SCALE_1_2_B0__PAPRD_PRE_POST_SCALING_1_2_B0__VERIFY(src) \
2027                     (!(((u_int32_t)(src)\
2028                     & ~0x0003ffffU)))
2029 #define PAPRD_PRE_POST_SCALE_1_2_B0__TYPE                             u_int32_t
2030 #define PAPRD_PRE_POST_SCALE_1_2_B0__READ                           0x0003ffffU
2031 #define PAPRD_PRE_POST_SCALE_1_2_B0__WRITE                          0x0003ffffU
2032
2033 #endif /* __PAPRD_PRE_POST_SCALE_1_2_B0_MACRO__ */
2034
2035
2036 /* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_1_2_b0 */
2037 #define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_1_2_B0__NUM \
2038                     1
2039
2040 /* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_2_2_b0 */
2041 #ifndef __PAPRD_PRE_POST_SCALE_2_2_B0_MACRO__
2042 #define __PAPRD_PRE_POST_SCALE_2_2_B0_MACRO__
2043
2044 /* macros for field paprd_pre_post_scaling_2_2_b0 */
2045 #define PAPRD_PRE_POST_SCALE_2_2_B0__PAPRD_PRE_POST_SCALING_2_2_B0__SHIFT     0
2046 #define PAPRD_PRE_POST_SCALE_2_2_B0__PAPRD_PRE_POST_SCALING_2_2_B0__WIDTH    18
2047 #define PAPRD_PRE_POST_SCALE_2_2_B0__PAPRD_PRE_POST_SCALING_2_2_B0__MASK \
2048                     0x0003ffffU
2049 #define PAPRD_PRE_POST_SCALE_2_2_B0__PAPRD_PRE_POST_SCALING_2_2_B0__READ(src) \
2050                     (u_int32_t)(src)\
2051                     & 0x0003ffffU
2052 #define PAPRD_PRE_POST_SCALE_2_2_B0__PAPRD_PRE_POST_SCALING_2_2_B0__WRITE(src) \
2053                     ((u_int32_t)(src)\
2054                     & 0x0003ffffU)
2055 #define PAPRD_PRE_POST_SCALE_2_2_B0__PAPRD_PRE_POST_SCALING_2_2_B0__MODIFY(dst, src) \
2056                     (dst) = ((dst) &\
2057                     ~0x0003ffffU) | ((u_int32_t)(src) &\
2058                     0x0003ffffU)
2059 #define PAPRD_PRE_POST_SCALE_2_2_B0__PAPRD_PRE_POST_SCALING_2_2_B0__VERIFY(src) \
2060                     (!(((u_int32_t)(src)\
2061                     & ~0x0003ffffU)))
2062 #define PAPRD_PRE_POST_SCALE_2_2_B0__TYPE                             u_int32_t
2063 #define PAPRD_PRE_POST_SCALE_2_2_B0__READ                           0x0003ffffU
2064 #define PAPRD_PRE_POST_SCALE_2_2_B0__WRITE                          0x0003ffffU
2065
2066 #endif /* __PAPRD_PRE_POST_SCALE_2_2_B0_MACRO__ */
2067
2068
2069 /* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_2_2_b0 */
2070 #define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_2_2_B0__NUM \
2071                     1
2072
2073 /* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_3_2_b0 */
2074 #ifndef __PAPRD_PRE_POST_SCALE_3_2_B0_MACRO__
2075 #define __PAPRD_PRE_POST_SCALE_3_2_B0_MACRO__
2076
2077 /* macros for field paprd_pre_post_scaling_3_2_b0 */
2078 #define PAPRD_PRE_POST_SCALE_3_2_B0__PAPRD_PRE_POST_SCALING_3_2_B0__SHIFT     0
2079 #define PAPRD_PRE_POST_SCALE_3_2_B0__PAPRD_PRE_POST_SCALING_3_2_B0__WIDTH    18
2080 #define PAPRD_PRE_POST_SCALE_3_2_B0__PAPRD_PRE_POST_SCALING_3_2_B0__MASK \
2081                     0x0003ffffU
2082 #define PAPRD_PRE_POST_SCALE_3_2_B0__PAPRD_PRE_POST_SCALING_3_2_B0__READ(src) \
2083                     (u_int32_t)(src)\
2084                     & 0x0003ffffU
2085 #define PAPRD_PRE_POST_SCALE_3_2_B0__PAPRD_PRE_POST_SCALING_3_2_B0__WRITE(src) \
2086                     ((u_int32_t)(src)\
2087                     & 0x0003ffffU)
2088 #define PAPRD_PRE_POST_SCALE_3_2_B0__PAPRD_PRE_POST_SCALING_3_2_B0__MODIFY(dst, src) \
2089                     (dst) = ((dst) &\
2090                     ~0x0003ffffU) | ((u_int32_t)(src) &\
2091                     0x0003ffffU)
2092 #define PAPRD_PRE_POST_SCALE_3_2_B0__PAPRD_PRE_POST_SCALING_3_2_B0__VERIFY(src) \
2093                     (!(((u_int32_t)(src)\
2094                     & ~0x0003ffffU)))
2095 #define PAPRD_PRE_POST_SCALE_3_2_B0__TYPE                             u_int32_t
2096 #define PAPRD_PRE_POST_SCALE_3_2_B0__READ                           0x0003ffffU
2097 #define PAPRD_PRE_POST_SCALE_3_2_B0__WRITE                          0x0003ffffU
2098
2099 #endif /* __PAPRD_PRE_POST_SCALE_3_2_B0_MACRO__ */
2100
2101
2102 /* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_3_2_b0 */
2103 #define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_3_2_B0__NUM \
2104                     1
2105
2106 /* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_4_2_b0 */
2107 #ifndef __PAPRD_PRE_POST_SCALE_4_2_B0_MACRO__
2108 #define __PAPRD_PRE_POST_SCALE_4_2_B0_MACRO__
2109
2110 /* macros for field paprd_pre_post_scaling_4_2_b0 */
2111 #define PAPRD_PRE_POST_SCALE_4_2_B0__PAPRD_PRE_POST_SCALING_4_2_B0__SHIFT     0
2112 #define PAPRD_PRE_POST_SCALE_4_2_B0__PAPRD_PRE_POST_SCALING_4_2_B0__WIDTH    18
2113 #define PAPRD_PRE_POST_SCALE_4_2_B0__PAPRD_PRE_POST_SCALING_4_2_B0__MASK \
2114                     0x0003ffffU
2115 #define PAPRD_PRE_POST_SCALE_4_2_B0__PAPRD_PRE_POST_SCALING_4_2_B0__READ(src) \
2116                     (u_int32_t)(src)\
2117                     & 0x0003ffffU
2118 #define PAPRD_PRE_POST_SCALE_4_2_B0__PAPRD_PRE_POST_SCALING_4_2_B0__WRITE(src) \
2119                     ((u_int32_t)(src)\
2120                     & 0x0003ffffU)
2121 #define PAPRD_PRE_POST_SCALE_4_2_B0__PAPRD_PRE_POST_SCALING_4_2_B0__MODIFY(dst, src) \
2122                     (dst) = ((dst) &\
2123                     ~0x0003ffffU) | ((u_int32_t)(src) &\
2124                     0x0003ffffU)
2125 #define PAPRD_PRE_POST_SCALE_4_2_B0__PAPRD_PRE_POST_SCALING_4_2_B0__VERIFY(src) \
2126                     (!(((u_int32_t)(src)\
2127                     & ~0x0003ffffU)))
2128 #define PAPRD_PRE_POST_SCALE_4_2_B0__TYPE                             u_int32_t
2129 #define PAPRD_PRE_POST_SCALE_4_2_B0__READ                           0x0003ffffU
2130 #define PAPRD_PRE_POST_SCALE_4_2_B0__WRITE                          0x0003ffffU
2131
2132 #endif /* __PAPRD_PRE_POST_SCALE_4_2_B0_MACRO__ */
2133
2134
2135 /* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_4_2_b0 */
2136 #define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_4_2_B0__NUM \
2137                     1
2138
2139 /* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_5_2_b0 */
2140 #ifndef __PAPRD_PRE_POST_SCALE_5_2_B0_MACRO__
2141 #define __PAPRD_PRE_POST_SCALE_5_2_B0_MACRO__
2142
2143 /* macros for field paprd_pre_post_scaling_5_2_b0 */
2144 #define PAPRD_PRE_POST_SCALE_5_2_B0__PAPRD_PRE_POST_SCALING_5_2_B0__SHIFT     0
2145 #define PAPRD_PRE_POST_SCALE_5_2_B0__PAPRD_PRE_POST_SCALING_5_2_B0__WIDTH    18
2146 #define PAPRD_PRE_POST_SCALE_5_2_B0__PAPRD_PRE_POST_SCALING_5_2_B0__MASK \
2147                     0x0003ffffU
2148 #define PAPRD_PRE_POST_SCALE_5_2_B0__PAPRD_PRE_POST_SCALING_5_2_B0__READ(src) \
2149                     (u_int32_t)(src)\
2150                     & 0x0003ffffU
2151 #define PAPRD_PRE_POST_SCALE_5_2_B0__PAPRD_PRE_POST_SCALING_5_2_B0__WRITE(src) \
2152                     ((u_int32_t)(src)\
2153                     & 0x0003ffffU)
2154 #define PAPRD_PRE_POST_SCALE_5_2_B0__PAPRD_PRE_POST_SCALING_5_2_B0__MODIFY(dst, src) \
2155                     (dst) = ((dst) &\
2156                     ~0x0003ffffU) | ((u_int32_t)(src) &\
2157                     0x0003ffffU)
2158 #define PAPRD_PRE_POST_SCALE_5_2_B0__PAPRD_PRE_POST_SCALING_5_2_B0__VERIFY(src) \
2159                     (!(((u_int32_t)(src)\
2160                     & ~0x0003ffffU)))
2161 #define PAPRD_PRE_POST_SCALE_5_2_B0__TYPE                             u_int32_t
2162 #define PAPRD_PRE_POST_SCALE_5_2_B0__READ                           0x0003ffffU
2163 #define PAPRD_PRE_POST_SCALE_5_2_B0__WRITE                          0x0003ffffU
2164
2165 #endif /* __PAPRD_PRE_POST_SCALE_5_2_B0_MACRO__ */
2166
2167
2168 /* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_5_2_b0 */
2169 #define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_5_2_B0__NUM \
2170                     1
2171
2172 /* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_6_2_b0 */
2173 #ifndef __PAPRD_PRE_POST_SCALE_6_2_B0_MACRO__
2174 #define __PAPRD_PRE_POST_SCALE_6_2_B0_MACRO__
2175
2176 /* macros for field paprd_pre_post_scaling_6_2_b0 */
2177 #define PAPRD_PRE_POST_SCALE_6_2_B0__PAPRD_PRE_POST_SCALING_6_2_B0__SHIFT     0
2178 #define PAPRD_PRE_POST_SCALE_6_2_B0__PAPRD_PRE_POST_SCALING_6_2_B0__WIDTH    18
2179 #define PAPRD_PRE_POST_SCALE_6_2_B0__PAPRD_PRE_POST_SCALING_6_2_B0__MASK \
2180                     0x0003ffffU
2181 #define PAPRD_PRE_POST_SCALE_6_2_B0__PAPRD_PRE_POST_SCALING_6_2_B0__READ(src) \
2182                     (u_int32_t)(src)\
2183                     & 0x0003ffffU
2184 #define PAPRD_PRE_POST_SCALE_6_2_B0__PAPRD_PRE_POST_SCALING_6_2_B0__WRITE(src) \
2185                     ((u_int32_t)(src)\
2186                     & 0x0003ffffU)
2187 #define PAPRD_PRE_POST_SCALE_6_2_B0__PAPRD_PRE_POST_SCALING_6_2_B0__MODIFY(dst, src) \
2188                     (dst) = ((dst) &\
2189                     ~0x0003ffffU) | ((u_int32_t)(src) &\
2190                     0x0003ffffU)
2191 #define PAPRD_PRE_POST_SCALE_6_2_B0__PAPRD_PRE_POST_SCALING_6_2_B0__VERIFY(src) \
2192                     (!(((u_int32_t)(src)\
2193                     & ~0x0003ffffU)))
2194 #define PAPRD_PRE_POST_SCALE_6_2_B0__TYPE                             u_int32_t
2195 #define PAPRD_PRE_POST_SCALE_6_2_B0__READ                           0x0003ffffU
2196 #define PAPRD_PRE_POST_SCALE_6_2_B0__WRITE                          0x0003ffffU
2197
2198 #endif /* __PAPRD_PRE_POST_SCALE_6_2_B0_MACRO__ */
2199
2200
2201 /* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_6_2_b0 */
2202 #define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_6_2_B0__NUM \
2203                     1
2204
2205 /* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_7_2_b0 */
2206 #ifndef __PAPRD_PRE_POST_SCALE_7_2_B0_MACRO__
2207 #define __PAPRD_PRE_POST_SCALE_7_2_B0_MACRO__
2208
2209 /* macros for field paprd_pre_post_scaling_7_2_b0 */
2210 #define PAPRD_PRE_POST_SCALE_7_2_B0__PAPRD_PRE_POST_SCALING_7_2_B0__SHIFT     0
2211 #define PAPRD_PRE_POST_SCALE_7_2_B0__PAPRD_PRE_POST_SCALING_7_2_B0__WIDTH    18
2212 #define PAPRD_PRE_POST_SCALE_7_2_B0__PAPRD_PRE_POST_SCALING_7_2_B0__MASK \
2213                     0x0003ffffU
2214 #define PAPRD_PRE_POST_SCALE_7_2_B0__PAPRD_PRE_POST_SCALING_7_2_B0__READ(src) \
2215                     (u_int32_t)(src)\
2216                     & 0x0003ffffU
2217 #define PAPRD_PRE_POST_SCALE_7_2_B0__PAPRD_PRE_POST_SCALING_7_2_B0__WRITE(src) \
2218                     ((u_int32_t)(src)\
2219                     & 0x0003ffffU)
2220 #define PAPRD_PRE_POST_SCALE_7_2_B0__PAPRD_PRE_POST_SCALING_7_2_B0__MODIFY(dst, src) \
2221                     (dst) = ((dst) &\
2222                     ~0x0003ffffU) | ((u_int32_t)(src) &\
2223                     0x0003ffffU)
2224 #define PAPRD_PRE_POST_SCALE_7_2_B0__PAPRD_PRE_POST_SCALING_7_2_B0__VERIFY(src) \
2225                     (!(((u_int32_t)(src)\
2226                     & ~0x0003ffffU)))
2227 #define PAPRD_PRE_POST_SCALE_7_2_B0__TYPE                             u_int32_t
2228 #define PAPRD_PRE_POST_SCALE_7_2_B0__READ                           0x0003ffffU
2229 #define PAPRD_PRE_POST_SCALE_7_2_B0__WRITE                          0x0003ffffU
2230
2231 #endif /* __PAPRD_PRE_POST_SCALE_7_2_B0_MACRO__ */
2232
2233
2234 /* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_7_2_b0 */
2235 #define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_7_2_B0__NUM \
2236                     1
2237
2238 /* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_0_3_b0 */
2239 #ifndef __PAPRD_PRE_POST_SCALE_0_3_B0_MACRO__
2240 #define __PAPRD_PRE_POST_SCALE_0_3_B0_MACRO__
2241
2242 /* macros for field paprd_pre_post_scaling_0_3_b0 */
2243 #define PAPRD_PRE_POST_SCALE_0_3_B0__PAPRD_PRE_POST_SCALING_0_3_B0__SHIFT     0
2244 #define PAPRD_PRE_POST_SCALE_0_3_B0__PAPRD_PRE_POST_SCALING_0_3_B0__WIDTH    18
2245 #define PAPRD_PRE_POST_SCALE_0_3_B0__PAPRD_PRE_POST_SCALING_0_3_B0__MASK \
2246                     0x0003ffffU
2247 #define PAPRD_PRE_POST_SCALE_0_3_B0__PAPRD_PRE_POST_SCALING_0_3_B0__READ(src) \
2248                     (u_int32_t)(src)\
2249                     & 0x0003ffffU
2250 #define PAPRD_PRE_POST_SCALE_0_3_B0__PAPRD_PRE_POST_SCALING_0_3_B0__WRITE(src) \
2251                     ((u_int32_t)(src)\
2252                     & 0x0003ffffU)
2253 #define PAPRD_PRE_POST_SCALE_0_3_B0__PAPRD_PRE_POST_SCALING_0_3_B0__MODIFY(dst, src) \
2254                     (dst) = ((dst) &\
2255                     ~0x0003ffffU) | ((u_int32_t)(src) &\
2256                     0x0003ffffU)
2257 #define PAPRD_PRE_POST_SCALE_0_3_B0__PAPRD_PRE_POST_SCALING_0_3_B0__VERIFY(src) \
2258                     (!(((u_int32_t)(src)\
2259                     & ~0x0003ffffU)))
2260 #define PAPRD_PRE_POST_SCALE_0_3_B0__TYPE                             u_int32_t
2261 #define PAPRD_PRE_POST_SCALE_0_3_B0__READ                           0x0003ffffU
2262 #define PAPRD_PRE_POST_SCALE_0_3_B0__WRITE                          0x0003ffffU
2263
2264 #endif /* __PAPRD_PRE_POST_SCALE_0_3_B0_MACRO__ */
2265
2266
2267 /* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_0_3_b0 */
2268 #define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_0_3_B0__NUM \
2269                     1
2270
2271 /* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_1_3_b0 */
2272 #ifndef __PAPRD_PRE_POST_SCALE_1_3_B0_MACRO__
2273 #define __PAPRD_PRE_POST_SCALE_1_3_B0_MACRO__
2274
2275 /* macros for field paprd_pre_post_scaling_1_3_b0 */
2276 #define PAPRD_PRE_POST_SCALE_1_3_B0__PAPRD_PRE_POST_SCALING_1_3_B0__SHIFT     0
2277 #define PAPRD_PRE_POST_SCALE_1_3_B0__PAPRD_PRE_POST_SCALING_1_3_B0__WIDTH    18
2278 #define PAPRD_PRE_POST_SCALE_1_3_B0__PAPRD_PRE_POST_SCALING_1_3_B0__MASK \
2279                     0x0003ffffU
2280 #define PAPRD_PRE_POST_SCALE_1_3_B0__PAPRD_PRE_POST_SCALING_1_3_B0__READ(src) \
2281                     (u_int32_t)(src)\
2282                     & 0x0003ffffU
2283 #define PAPRD_PRE_POST_SCALE_1_3_B0__PAPRD_PRE_POST_SCALING_1_3_B0__WRITE(src) \
2284                     ((u_int32_t)(src)\
2285                     & 0x0003ffffU)
2286 #define PAPRD_PRE_POST_SCALE_1_3_B0__PAPRD_PRE_POST_SCALING_1_3_B0__MODIFY(dst, src) \
2287                     (dst) = ((dst) &\
2288                     ~0x0003ffffU) | ((u_int32_t)(src) &\
2289                     0x0003ffffU)
2290 #define PAPRD_PRE_POST_SCALE_1_3_B0__PAPRD_PRE_POST_SCALING_1_3_B0__VERIFY(src) \
2291                     (!(((u_int32_t)(src)\
2292                     & ~0x0003ffffU)))
2293 #define PAPRD_PRE_POST_SCALE_1_3_B0__TYPE                             u_int32_t
2294 #define PAPRD_PRE_POST_SCALE_1_3_B0__READ                           0x0003ffffU
2295 #define PAPRD_PRE_POST_SCALE_1_3_B0__WRITE                          0x0003ffffU
2296
2297 #endif /* __PAPRD_PRE_POST_SCALE_1_3_B0_MACRO__ */
2298
2299
2300 /* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_1_3_b0 */
2301 #define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_1_3_B0__NUM \
2302                     1
2303
2304 /* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_2_3_b0 */
2305 #ifndef __PAPRD_PRE_POST_SCALE_2_3_B0_MACRO__
2306 #define __PAPRD_PRE_POST_SCALE_2_3_B0_MACRO__
2307
2308 /* macros for field paprd_pre_post_scaling_2_3_b0 */
2309 #define PAPRD_PRE_POST_SCALE_2_3_B0__PAPRD_PRE_POST_SCALING_2_3_B0__SHIFT     0
2310 #define PAPRD_PRE_POST_SCALE_2_3_B0__PAPRD_PRE_POST_SCALING_2_3_B0__WIDTH    18
2311 #define PAPRD_PRE_POST_SCALE_2_3_B0__PAPRD_PRE_POST_SCALING_2_3_B0__MASK \
2312                     0x0003ffffU
2313 #define PAPRD_PRE_POST_SCALE_2_3_B0__PAPRD_PRE_POST_SCALING_2_3_B0__READ(src) \
2314                     (u_int32_t)(src)\
2315                     & 0x0003ffffU
2316 #define PAPRD_PRE_POST_SCALE_2_3_B0__PAPRD_PRE_POST_SCALING_2_3_B0__WRITE(src) \
2317                     ((u_int32_t)(src)\
2318                     & 0x0003ffffU)
2319 #define PAPRD_PRE_POST_SCALE_2_3_B0__PAPRD_PRE_POST_SCALING_2_3_B0__MODIFY(dst, src) \
2320                     (dst) = ((dst) &\
2321                     ~0x0003ffffU) | ((u_int32_t)(src) &\
2322                     0x0003ffffU)
2323 #define PAPRD_PRE_POST_SCALE_2_3_B0__PAPRD_PRE_POST_SCALING_2_3_B0__VERIFY(src) \
2324                     (!(((u_int32_t)(src)\
2325                     & ~0x0003ffffU)))
2326 #define PAPRD_PRE_POST_SCALE_2_3_B0__TYPE                             u_int32_t
2327 #define PAPRD_PRE_POST_SCALE_2_3_B0__READ                           0x0003ffffU
2328 #define PAPRD_PRE_POST_SCALE_2_3_B0__WRITE                          0x0003ffffU
2329
2330 #endif /* __PAPRD_PRE_POST_SCALE_2_3_B0_MACRO__ */
2331
2332
2333 /* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_2_3_b0 */
2334 #define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_2_3_B0__NUM \
2335                     1
2336
2337 /* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_3_3_b0 */
2338 #ifndef __PAPRD_PRE_POST_SCALE_3_3_B0_MACRO__
2339 #define __PAPRD_PRE_POST_SCALE_3_3_B0_MACRO__
2340
2341 /* macros for field paprd_pre_post_scaling_3_3_b0 */
2342 #define PAPRD_PRE_POST_SCALE_3_3_B0__PAPRD_PRE_POST_SCALING_3_3_B0__SHIFT     0
2343 #define PAPRD_PRE_POST_SCALE_3_3_B0__PAPRD_PRE_POST_SCALING_3_3_B0__WIDTH    18
2344 #define PAPRD_PRE_POST_SCALE_3_3_B0__PAPRD_PRE_POST_SCALING_3_3_B0__MASK \
2345                     0x0003ffffU
2346 #define PAPRD_PRE_POST_SCALE_3_3_B0__PAPRD_PRE_POST_SCALING_3_3_B0__READ(src) \
2347                     (u_int32_t)(src)\
2348                     & 0x0003ffffU
2349 #define PAPRD_PRE_POST_SCALE_3_3_B0__PAPRD_PRE_POST_SCALING_3_3_B0__WRITE(src) \
2350                     ((u_int32_t)(src)\
2351                     & 0x0003ffffU)
2352 #define PAPRD_PRE_POST_SCALE_3_3_B0__PAPRD_PRE_POST_SCALING_3_3_B0__MODIFY(dst, src) \
2353                     (dst) = ((dst) &\
2354                     ~0x0003ffffU) | ((u_int32_t)(src) &\
2355                     0x0003ffffU)
2356 #define PAPRD_PRE_POST_SCALE_3_3_B0__PAPRD_PRE_POST_SCALING_3_3_B0__VERIFY(src) \
2357                     (!(((u_int32_t)(src)\
2358                     & ~0x0003ffffU)))
2359 #define PAPRD_PRE_POST_SCALE_3_3_B0__TYPE                             u_int32_t
2360 #define PAPRD_PRE_POST_SCALE_3_3_B0__READ                           0x0003ffffU
2361 #define PAPRD_PRE_POST_SCALE_3_3_B0__WRITE                          0x0003ffffU
2362
2363 #endif /* __PAPRD_PRE_POST_SCALE_3_3_B0_MACRO__ */
2364
2365
2366 /* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_3_3_b0 */
2367 #define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_3_3_B0__NUM \
2368                     1
2369
2370 /* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_4_3_b0 */
2371 #ifndef __PAPRD_PRE_POST_SCALE_4_3_B0_MACRO__
2372 #define __PAPRD_PRE_POST_SCALE_4_3_B0_MACRO__
2373
2374 /* macros for field paprd_pre_post_scaling_4_3_b0 */
2375 #define PAPRD_PRE_POST_SCALE_4_3_B0__PAPRD_PRE_POST_SCALING_4_3_B0__SHIFT     0
2376 #define PAPRD_PRE_POST_SCALE_4_3_B0__PAPRD_PRE_POST_SCALING_4_3_B0__WIDTH    18
2377 #define PAPRD_PRE_POST_SCALE_4_3_B0__PAPRD_PRE_POST_SCALING_4_3_B0__MASK \
2378                     0x0003ffffU
2379 #define PAPRD_PRE_POST_SCALE_4_3_B0__PAPRD_PRE_POST_SCALING_4_3_B0__READ(src) \
2380                     (u_int32_t)(src)\
2381                     & 0x0003ffffU
2382 #define PAPRD_PRE_POST_SCALE_4_3_B0__PAPRD_PRE_POST_SCALING_4_3_B0__WRITE(src) \
2383                     ((u_int32_t)(src)\
2384                     & 0x0003ffffU)
2385 #define PAPRD_PRE_POST_SCALE_4_3_B0__PAPRD_PRE_POST_SCALING_4_3_B0__MODIFY(dst, src) \
2386                     (dst) = ((dst) &\
2387                     ~0x0003ffffU) | ((u_int32_t)(src) &\
2388                     0x0003ffffU)
2389 #define PAPRD_PRE_POST_SCALE_4_3_B0__PAPRD_PRE_POST_SCALING_4_3_B0__VERIFY(src) \
2390                     (!(((u_int32_t)(src)\
2391                     & ~0x0003ffffU)))
2392 #define PAPRD_PRE_POST_SCALE_4_3_B0__TYPE                             u_int32_t
2393 #define PAPRD_PRE_POST_SCALE_4_3_B0__READ                           0x0003ffffU
2394 #define PAPRD_PRE_POST_SCALE_4_3_B0__WRITE                          0x0003ffffU
2395
2396 #endif /* __PAPRD_PRE_POST_SCALE_4_3_B0_MACRO__ */
2397
2398
2399 /* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_4_3_b0 */
2400 #define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_4_3_B0__NUM \
2401                     1
2402
2403 /* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_5_3_b0 */
2404 #ifndef __PAPRD_PRE_POST_SCALE_5_3_B0_MACRO__
2405 #define __PAPRD_PRE_POST_SCALE_5_3_B0_MACRO__
2406
2407 /* macros for field paprd_pre_post_scaling_5_3_b0 */
2408 #define PAPRD_PRE_POST_SCALE_5_3_B0__PAPRD_PRE_POST_SCALING_5_3_B0__SHIFT     0
2409 #define PAPRD_PRE_POST_SCALE_5_3_B0__PAPRD_PRE_POST_SCALING_5_3_B0__WIDTH    18
2410 #define PAPRD_PRE_POST_SCALE_5_3_B0__PAPRD_PRE_POST_SCALING_5_3_B0__MASK \
2411                     0x0003ffffU
2412 #define PAPRD_PRE_POST_SCALE_5_3_B0__PAPRD_PRE_POST_SCALING_5_3_B0__READ(src) \
2413                     (u_int32_t)(src)\
2414                     & 0x0003ffffU
2415 #define PAPRD_PRE_POST_SCALE_5_3_B0__PAPRD_PRE_POST_SCALING_5_3_B0__WRITE(src) \
2416                     ((u_int32_t)(src)\
2417                     & 0x0003ffffU)
2418 #define PAPRD_PRE_POST_SCALE_5_3_B0__PAPRD_PRE_POST_SCALING_5_3_B0__MODIFY(dst, src) \
2419                     (dst) = ((dst) &\
2420                     ~0x0003ffffU) | ((u_int32_t)(src) &\
2421                     0x0003ffffU)
2422 #define PAPRD_PRE_POST_SCALE_5_3_B0__PAPRD_PRE_POST_SCALING_5_3_B0__VERIFY(src) \
2423                     (!(((u_int32_t)(src)\
2424                     & ~0x0003ffffU)))
2425 #define PAPRD_PRE_POST_SCALE_5_3_B0__TYPE                             u_int32_t
2426 #define PAPRD_PRE_POST_SCALE_5_3_B0__READ                           0x0003ffffU
2427 #define PAPRD_PRE_POST_SCALE_5_3_B0__WRITE                          0x0003ffffU
2428
2429 #endif /* __PAPRD_PRE_POST_SCALE_5_3_B0_MACRO__ */
2430
2431
2432 /* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_5_3_b0 */
2433 #define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_5_3_B0__NUM \
2434                     1
2435
2436 /* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_6_3_b0 */
2437 #ifndef __PAPRD_PRE_POST_SCALE_6_3_B0_MACRO__
2438 #define __PAPRD_PRE_POST_SCALE_6_3_B0_MACRO__
2439
2440 /* macros for field paprd_pre_post_scaling_6_3_b0 */
2441 #define PAPRD_PRE_POST_SCALE_6_3_B0__PAPRD_PRE_POST_SCALING_6_3_B0__SHIFT     0
2442 #define PAPRD_PRE_POST_SCALE_6_3_B0__PAPRD_PRE_POST_SCALING_6_3_B0__WIDTH    18
2443 #define PAPRD_PRE_POST_SCALE_6_3_B0__PAPRD_PRE_POST_SCALING_6_3_B0__MASK \
2444                     0x0003ffffU
2445 #define PAPRD_PRE_POST_SCALE_6_3_B0__PAPRD_PRE_POST_SCALING_6_3_B0__READ(src) \
2446                     (u_int32_t)(src)\
2447                     & 0x0003ffffU
2448 #define PAPRD_PRE_POST_SCALE_6_3_B0__PAPRD_PRE_POST_SCALING_6_3_B0__WRITE(src) \
2449                     ((u_int32_t)(src)\
2450                     & 0x0003ffffU)
2451 #define PAPRD_PRE_POST_SCALE_6_3_B0__PAPRD_PRE_POST_SCALING_6_3_B0__MODIFY(dst, src) \
2452                     (dst) = ((dst) &\
2453                     ~0x0003ffffU) | ((u_int32_t)(src) &\
2454                     0x0003ffffU)
2455 #define PAPRD_PRE_POST_SCALE_6_3_B0__PAPRD_PRE_POST_SCALING_6_3_B0__VERIFY(src) \
2456                     (!(((u_int32_t)(src)\
2457                     & ~0x0003ffffU)))
2458 #define PAPRD_PRE_POST_SCALE_6_3_B0__TYPE                             u_int32_t
2459 #define PAPRD_PRE_POST_SCALE_6_3_B0__READ                           0x0003ffffU
2460 #define PAPRD_PRE_POST_SCALE_6_3_B0__WRITE                          0x0003ffffU
2461
2462 #endif /* __PAPRD_PRE_POST_SCALE_6_3_B0_MACRO__ */
2463
2464
2465 /* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_6_3_b0 */
2466 #define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_6_3_B0__NUM \
2467                     1
2468
2469 /* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_7_3_b0 */
2470 #ifndef __PAPRD_PRE_POST_SCALE_7_3_B0_MACRO__
2471 #define __PAPRD_PRE_POST_SCALE_7_3_B0_MACRO__
2472
2473 /* macros for field paprd_pre_post_scaling_7_3_b0 */
2474 #define PAPRD_PRE_POST_SCALE_7_3_B0__PAPRD_PRE_POST_SCALING_7_3_B0__SHIFT     0
2475 #define PAPRD_PRE_POST_SCALE_7_3_B0__PAPRD_PRE_POST_SCALING_7_3_B0__WIDTH    18
2476 #define PAPRD_PRE_POST_SCALE_7_3_B0__PAPRD_PRE_POST_SCALING_7_3_B0__MASK \
2477                     0x0003ffffU
2478 #define PAPRD_PRE_POST_SCALE_7_3_B0__PAPRD_PRE_POST_SCALING_7_3_B0__READ(src) \
2479                     (u_int32_t)(src)\
2480                     & 0x0003ffffU
2481 #define PAPRD_PRE_POST_SCALE_7_3_B0__PAPRD_PRE_POST_SCALING_7_3_B0__WRITE(src) \
2482                     ((u_int32_t)(src)\
2483                     & 0x0003ffffU)
2484 #define PAPRD_PRE_POST_SCALE_7_3_B0__PAPRD_PRE_POST_SCALING_7_3_B0__MODIFY(dst, src) \
2485                     (dst) = ((dst) &\
2486                     ~0x0003ffffU) | ((u_int32_t)(src) &\
2487                     0x0003ffffU)
2488 #define PAPRD_PRE_POST_SCALE_7_3_B0__PAPRD_PRE_POST_SCALING_7_3_B0__VERIFY(src) \
2489                     (!(((u_int32_t)(src)\
2490                     & ~0x0003ffffU)))
2491 #define PAPRD_PRE_POST_SCALE_7_3_B0__TYPE                             u_int32_t
2492 #define PAPRD_PRE_POST_SCALE_7_3_B0__READ                           0x0003ffffU
2493 #define PAPRD_PRE_POST_SCALE_7_3_B0__WRITE                          0x0003ffffU
2494
2495 #endif /* __PAPRD_PRE_POST_SCALE_7_3_B0_MACRO__ */
2496
2497
2498 /* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_7_3_b0 */
2499 #define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_7_3_B0__NUM \
2500                     1
2501
2502 /* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_0_4_b0 */
2503 #ifndef __PAPRD_PRE_POST_SCALE_0_4_B0_MACRO__
2504 #define __PAPRD_PRE_POST_SCALE_0_4_B0_MACRO__
2505
2506 /* macros for field paprd_pre_post_scaling_0_4_b0 */
2507 #define PAPRD_PRE_POST_SCALE_0_4_B0__PAPRD_PRE_POST_SCALING_0_4_B0__SHIFT     0
2508 #define PAPRD_PRE_POST_SCALE_0_4_B0__PAPRD_PRE_POST_SCALING_0_4_B0__WIDTH    18
2509 #define PAPRD_PRE_POST_SCALE_0_4_B0__PAPRD_PRE_POST_SCALING_0_4_B0__MASK \
2510                     0x0003ffffU
2511 #define PAPRD_PRE_POST_SCALE_0_4_B0__PAPRD_PRE_POST_SCALING_0_4_B0__READ(src) \
2512                     (u_int32_t)(src)\
2513                     & 0x0003ffffU
2514 #define PAPRD_PRE_POST_SCALE_0_4_B0__PAPRD_PRE_POST_SCALING_0_4_B0__WRITE(src) \
2515                     ((u_int32_t)(src)\
2516                     & 0x0003ffffU)
2517 #define PAPRD_PRE_POST_SCALE_0_4_B0__PAPRD_PRE_POST_SCALING_0_4_B0__MODIFY(dst, src) \
2518                     (dst) = ((dst) &\
2519                     ~0x0003ffffU) | ((u_int32_t)(src) &\
2520                     0x0003ffffU)
2521 #define PAPRD_PRE_POST_SCALE_0_4_B0__PAPRD_PRE_POST_SCALING_0_4_B0__VERIFY(src) \
2522                     (!(((u_int32_t)(src)\
2523                     & ~0x0003ffffU)))
2524 #define PAPRD_PRE_POST_SCALE_0_4_B0__TYPE                             u_int32_t
2525 #define PAPRD_PRE_POST_SCALE_0_4_B0__READ                           0x0003ffffU
2526 #define PAPRD_PRE_POST_SCALE_0_4_B0__WRITE                          0x0003ffffU
2527
2528 #endif /* __PAPRD_PRE_POST_SCALE_0_4_B0_MACRO__ */
2529
2530
2531 /* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_0_4_b0 */
2532 #define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_0_4_B0__NUM \
2533                     1
2534
2535 /* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_1_4_b0 */
2536 #ifndef __PAPRD_PRE_POST_SCALE_1_4_B0_MACRO__
2537 #define __PAPRD_PRE_POST_SCALE_1_4_B0_MACRO__
2538
2539 /* macros for field paprd_pre_post_scaling_1_4_b0 */
2540 #define PAPRD_PRE_POST_SCALE_1_4_B0__PAPRD_PRE_POST_SCALING_1_4_B0__SHIFT     0
2541 #define PAPRD_PRE_POST_SCALE_1_4_B0__PAPRD_PRE_POST_SCALING_1_4_B0__WIDTH    18
2542 #define PAPRD_PRE_POST_SCALE_1_4_B0__PAPRD_PRE_POST_SCALING_1_4_B0__MASK \
2543                     0x0003ffffU
2544 #define PAPRD_PRE_POST_SCALE_1_4_B0__PAPRD_PRE_POST_SCALING_1_4_B0__READ(src) \
2545                     (u_int32_t)(src)\
2546                     & 0x0003ffffU
2547 #define PAPRD_PRE_POST_SCALE_1_4_B0__PAPRD_PRE_POST_SCALING_1_4_B0__WRITE(src) \
2548                     ((u_int32_t)(src)\
2549                     & 0x0003ffffU)
2550 #define PAPRD_PRE_POST_SCALE_1_4_B0__PAPRD_PRE_POST_SCALING_1_4_B0__MODIFY(dst, src) \
2551                     (dst) = ((dst) &\
2552                     ~0x0003ffffU) | ((u_int32_t)(src) &\
2553                     0x0003ffffU)
2554 #define PAPRD_PRE_POST_SCALE_1_4_B0__PAPRD_PRE_POST_SCALING_1_4_B0__VERIFY(src) \
2555                     (!(((u_int32_t)(src)\
2556                     & ~0x0003ffffU)))
2557 #define PAPRD_PRE_POST_SCALE_1_4_B0__TYPE                             u_int32_t
2558 #define PAPRD_PRE_POST_SCALE_1_4_B0__READ                           0x0003ffffU
2559 #define PAPRD_PRE_POST_SCALE_1_4_B0__WRITE                          0x0003ffffU
2560
2561 #endif /* __PAPRD_PRE_POST_SCALE_1_4_B0_MACRO__ */
2562
2563
2564 /* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_1_4_b0 */
2565 #define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_1_4_B0__NUM \
2566                     1
2567
2568 /* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_2_4_b0 */
2569 #ifndef __PAPRD_PRE_POST_SCALE_2_4_B0_MACRO__
2570 #define __PAPRD_PRE_POST_SCALE_2_4_B0_MACRO__
2571
2572 /* macros for field paprd_pre_post_scaling_2_4_b0 */
2573 #define PAPRD_PRE_POST_SCALE_2_4_B0__PAPRD_PRE_POST_SCALING_2_4_B0__SHIFT     0
2574 #define PAPRD_PRE_POST_SCALE_2_4_B0__PAPRD_PRE_POST_SCALING_2_4_B0__WIDTH    18
2575 #define PAPRD_PRE_POST_SCALE_2_4_B0__PAPRD_PRE_POST_SCALING_2_4_B0__MASK \
2576                     0x0003ffffU
2577 #define PAPRD_PRE_POST_SCALE_2_4_B0__PAPRD_PRE_POST_SCALING_2_4_B0__READ(src) \
2578                     (u_int32_t)(src)\
2579                     & 0x0003ffffU
2580 #define PAPRD_PRE_POST_SCALE_2_4_B0__PAPRD_PRE_POST_SCALING_2_4_B0__WRITE(src) \
2581                     ((u_int32_t)(src)\
2582                     & 0x0003ffffU)
2583 #define PAPRD_PRE_POST_SCALE_2_4_B0__PAPRD_PRE_POST_SCALING_2_4_B0__MODIFY(dst, src) \
2584                     (dst) = ((dst) &\
2585                     ~0x0003ffffU) | ((u_int32_t)(src) &\
2586                     0x0003ffffU)
2587 #define PAPRD_PRE_POST_SCALE_2_4_B0__PAPRD_PRE_POST_SCALING_2_4_B0__VERIFY(src) \
2588                     (!(((u_int32_t)(src)\
2589                     & ~0x0003ffffU)))
2590 #define PAPRD_PRE_POST_SCALE_2_4_B0__TYPE                             u_int32_t
2591 #define PAPRD_PRE_POST_SCALE_2_4_B0__READ                           0x0003ffffU
2592 #define PAPRD_PRE_POST_SCALE_2_4_B0__WRITE                          0x0003ffffU
2593
2594 #endif /* __PAPRD_PRE_POST_SCALE_2_4_B0_MACRO__ */
2595
2596
2597 /* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_2_4_b0 */
2598 #define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_2_4_B0__NUM \
2599                     1
2600
2601 /* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_3_4_b0 */
2602 #ifndef __PAPRD_PRE_POST_SCALE_3_4_B0_MACRO__
2603 #define __PAPRD_PRE_POST_SCALE_3_4_B0_MACRO__
2604
2605 /* macros for field paprd_pre_post_scaling_3_4_b0 */
2606 #define PAPRD_PRE_POST_SCALE_3_4_B0__PAPRD_PRE_POST_SCALING_3_4_B0__SHIFT     0
2607 #define PAPRD_PRE_POST_SCALE_3_4_B0__PAPRD_PRE_POST_SCALING_3_4_B0__WIDTH    18
2608 #define PAPRD_PRE_POST_SCALE_3_4_B0__PAPRD_PRE_POST_SCALING_3_4_B0__MASK \
2609                     0x0003ffffU
2610 #define PAPRD_PRE_POST_SCALE_3_4_B0__PAPRD_PRE_POST_SCALING_3_4_B0__READ(src) \
2611                     (u_int32_t)(src)\
2612                     & 0x0003ffffU
2613 #define PAPRD_PRE_POST_SCALE_3_4_B0__PAPRD_PRE_POST_SCALING_3_4_B0__WRITE(src) \
2614                     ((u_int32_t)(src)\
2615                     & 0x0003ffffU)
2616 #define PAPRD_PRE_POST_SCALE_3_4_B0__PAPRD_PRE_POST_SCALING_3_4_B0__MODIFY(dst, src) \
2617                     (dst) = ((dst) &\
2618                     ~0x0003ffffU) | ((u_int32_t)(src) &\
2619                     0x0003ffffU)
2620 #define PAPRD_PRE_POST_SCALE_3_4_B0__PAPRD_PRE_POST_SCALING_3_4_B0__VERIFY(src) \
2621                     (!(((u_int32_t)(src)\
2622                     & ~0x0003ffffU)))
2623 #define PAPRD_PRE_POST_SCALE_3_4_B0__TYPE                             u_int32_t
2624 #define PAPRD_PRE_POST_SCALE_3_4_B0__READ                           0x0003ffffU
2625 #define PAPRD_PRE_POST_SCALE_3_4_B0__WRITE                          0x0003ffffU
2626
2627 #endif /* __PAPRD_PRE_POST_SCALE_3_4_B0_MACRO__ */
2628
2629
2630 /* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_3_4_b0 */
2631 #define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_3_4_B0__NUM \
2632                     1
2633
2634 /* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_4_4_b0 */
2635 #ifndef __PAPRD_PRE_POST_SCALE_4_4_B0_MACRO__
2636 #define __PAPRD_PRE_POST_SCALE_4_4_B0_MACRO__
2637
2638 /* macros for field paprd_pre_post_scaling_4_4_b0 */
2639 #define PAPRD_PRE_POST_SCALE_4_4_B0__PAPRD_PRE_POST_SCALING_4_4_B0__SHIFT     0
2640 #define PAPRD_PRE_POST_SCALE_4_4_B0__PAPRD_PRE_POST_SCALING_4_4_B0__WIDTH    18
2641 #define PAPRD_PRE_POST_SCALE_4_4_B0__PAPRD_PRE_POST_SCALING_4_4_B0__MASK \
2642                     0x0003ffffU
2643 #define PAPRD_PRE_POST_SCALE_4_4_B0__PAPRD_PRE_POST_SCALING_4_4_B0__READ(src) \
2644                     (u_int32_t)(src)\
2645                     & 0x0003ffffU
2646 #define PAPRD_PRE_POST_SCALE_4_4_B0__PAPRD_PRE_POST_SCALING_4_4_B0__WRITE(src) \
2647                     ((u_int32_t)(src)\
2648                     & 0x0003ffffU)
2649 #define PAPRD_PRE_POST_SCALE_4_4_B0__PAPRD_PRE_POST_SCALING_4_4_B0__MODIFY(dst, src) \
2650                     (dst) = ((dst) &\
2651                     ~0x0003ffffU) | ((u_int32_t)(src) &\
2652                     0x0003ffffU)
2653 #define PAPRD_PRE_POST_SCALE_4_4_B0__PAPRD_PRE_POST_SCALING_4_4_B0__VERIFY(src) \
2654                     (!(((u_int32_t)(src)\
2655                     & ~0x0003ffffU)))
2656 #define PAPRD_PRE_POST_SCALE_4_4_B0__TYPE                             u_int32_t
2657 #define PAPRD_PRE_POST_SCALE_4_4_B0__READ                           0x0003ffffU
2658 #define PAPRD_PRE_POST_SCALE_4_4_B0__WRITE                          0x0003ffffU
2659
2660 #endif /* __PAPRD_PRE_POST_SCALE_4_4_B0_MACRO__ */
2661
2662
2663 /* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_4_4_b0 */
2664 #define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_4_4_B0__NUM \
2665                     1
2666
2667 /* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_5_4_b0 */
2668 #ifndef __PAPRD_PRE_POST_SCALE_5_4_B0_MACRO__
2669 #define __PAPRD_PRE_POST_SCALE_5_4_B0_MACRO__
2670
2671 /* macros for field paprd_pre_post_scaling_5_4_b0 */
2672 #define PAPRD_PRE_POST_SCALE_5_4_B0__PAPRD_PRE_POST_SCALING_5_4_B0__SHIFT     0
2673 #define PAPRD_PRE_POST_SCALE_5_4_B0__PAPRD_PRE_POST_SCALING_5_4_B0__WIDTH    18
2674 #define PAPRD_PRE_POST_SCALE_5_4_B0__PAPRD_PRE_POST_SCALING_5_4_B0__MASK \
2675                     0x0003ffffU
2676 #define PAPRD_PRE_POST_SCALE_5_4_B0__PAPRD_PRE_POST_SCALING_5_4_B0__READ(src) \
2677                     (u_int32_t)(src)\
2678                     & 0x0003ffffU
2679 #define PAPRD_PRE_POST_SCALE_5_4_B0__PAPRD_PRE_POST_SCALING_5_4_B0__WRITE(src) \
2680                     ((u_int32_t)(src)\
2681                     & 0x0003ffffU)
2682 #define PAPRD_PRE_POST_SCALE_5_4_B0__PAPRD_PRE_POST_SCALING_5_4_B0__MODIFY(dst, src) \
2683                     (dst) = ((dst) &\
2684                     ~0x0003ffffU) | ((u_int32_t)(src) &\
2685                     0x0003ffffU)
2686 #define PAPRD_PRE_POST_SCALE_5_4_B0__PAPRD_PRE_POST_SCALING_5_4_B0__VERIFY(src) \
2687                     (!(((u_int32_t)(src)\
2688                     & ~0x0003ffffU)))
2689 #define PAPRD_PRE_POST_SCALE_5_4_B0__TYPE                             u_int32_t
2690 #define PAPRD_PRE_POST_SCALE_5_4_B0__READ                           0x0003ffffU
2691 #define PAPRD_PRE_POST_SCALE_5_4_B0__WRITE                          0x0003ffffU
2692
2693 #endif /* __PAPRD_PRE_POST_SCALE_5_4_B0_MACRO__ */
2694
2695
2696 /* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_5_4_b0 */
2697 #define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_5_4_B0__NUM \
2698                     1
2699
2700 /* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_6_4_b0 */
2701 #ifndef __PAPRD_PRE_POST_SCALE_6_4_B0_MACRO__
2702 #define __PAPRD_PRE_POST_SCALE_6_4_B0_MACRO__
2703
2704 /* macros for field paprd_pre_post_scaling_6_4_b0 */
2705 #define PAPRD_PRE_POST_SCALE_6_4_B0__PAPRD_PRE_POST_SCALING_6_4_B0__SHIFT     0
2706 #define PAPRD_PRE_POST_SCALE_6_4_B0__PAPRD_PRE_POST_SCALING_6_4_B0__WIDTH    18
2707 #define PAPRD_PRE_POST_SCALE_6_4_B0__PAPRD_PRE_POST_SCALING_6_4_B0__MASK \
2708                     0x0003ffffU
2709 #define PAPRD_PRE_POST_SCALE_6_4_B0__PAPRD_PRE_POST_SCALING_6_4_B0__READ(src) \
2710                     (u_int32_t)(src)\
2711                     & 0x0003ffffU
2712 #define PAPRD_PRE_POST_SCALE_6_4_B0__PAPRD_PRE_POST_SCALING_6_4_B0__WRITE(src) \
2713                     ((u_int32_t)(src)\
2714                     & 0x0003ffffU)
2715 #define PAPRD_PRE_POST_SCALE_6_4_B0__PAPRD_PRE_POST_SCALING_6_4_B0__MODIFY(dst, src) \
2716                     (dst) = ((dst) &\
2717                     ~0x0003ffffU) | ((u_int32_t)(src) &\
2718                     0x0003ffffU)
2719 #define PAPRD_PRE_POST_SCALE_6_4_B0__PAPRD_PRE_POST_SCALING_6_4_B0__VERIFY(src) \
2720                     (!(((u_int32_t)(src)\
2721                     & ~0x0003ffffU)))
2722 #define PAPRD_PRE_POST_SCALE_6_4_B0__TYPE                             u_int32_t
2723 #define PAPRD_PRE_POST_SCALE_6_4_B0__READ                           0x0003ffffU
2724 #define PAPRD_PRE_POST_SCALE_6_4_B0__WRITE                          0x0003ffffU
2725
2726 #endif /* __PAPRD_PRE_POST_SCALE_6_4_B0_MACRO__ */
2727
2728
2729 /* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_6_4_b0 */
2730 #define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_6_4_B0__NUM \
2731                     1
2732
2733 /* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_7_4_b0 */
2734 #ifndef __PAPRD_PRE_POST_SCALE_7_4_B0_MACRO__
2735 #define __PAPRD_PRE_POST_SCALE_7_4_B0_MACRO__
2736
2737 /* macros for field paprd_pre_post_scaling_7_4_b0 */
2738 #define PAPRD_PRE_POST_SCALE_7_4_B0__PAPRD_PRE_POST_SCALING_7_4_B0__SHIFT     0
2739 #define PAPRD_PRE_POST_SCALE_7_4_B0__PAPRD_PRE_POST_SCALING_7_4_B0__WIDTH    18
2740 #define PAPRD_PRE_POST_SCALE_7_4_B0__PAPRD_PRE_POST_SCALING_7_4_B0__MASK \
2741                     0x0003ffffU
2742 #define PAPRD_PRE_POST_SCALE_7_4_B0__PAPRD_PRE_POST_SCALING_7_4_B0__READ(src) \
2743                     (u_int32_t)(src)\
2744                     & 0x0003ffffU
2745 #define PAPRD_PRE_POST_SCALE_7_4_B0__PAPRD_PRE_POST_SCALING_7_4_B0__WRITE(src) \
2746                     ((u_int32_t)(src)\
2747                     & 0x0003ffffU)
2748 #define PAPRD_PRE_POST_SCALE_7_4_B0__PAPRD_PRE_POST_SCALING_7_4_B0__MODIFY(dst, src) \
2749                     (dst) = ((dst) &\
2750                     ~0x0003ffffU) | ((u_int32_t)(src) &\
2751                     0x0003ffffU)
2752 #define PAPRD_PRE_POST_SCALE_7_4_B0__PAPRD_PRE_POST_SCALING_7_4_B0__VERIFY(src) \
2753                     (!(((u_int32_t)(src)\
2754                     & ~0x0003ffffU)))
2755 #define PAPRD_PRE_POST_SCALE_7_4_B0__TYPE                             u_int32_t
2756 #define PAPRD_PRE_POST_SCALE_7_4_B0__READ                           0x0003ffffU
2757 #define PAPRD_PRE_POST_SCALE_7_4_B0__WRITE                          0x0003ffffU
2758
2759 #endif /* __PAPRD_PRE_POST_SCALE_7_4_B0_MACRO__ */
2760
2761
2762 /* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_7_4_b0 */
2763 #define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_7_4_B0__NUM \
2764                     1
2765
2766 /* macros for BlueprintGlobalNameSpace::paprd_power_at_am2am_cal_b0 */
2767 #ifndef __PAPRD_POWER_AT_AM2AM_CAL_B0_MACRO__
2768 #define __PAPRD_POWER_AT_AM2AM_CAL_B0_MACRO__
2769
2770 /* macros for field paprd_power_at_am2am_cal_1_b0 */
2771 #define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_1_B0__SHIFT     0
2772 #define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_1_B0__WIDTH     6
2773 #define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_1_B0__MASK \
2774                     0x0000003fU
2775 #define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_1_B0__READ(src) \
2776                     (u_int32_t)(src)\
2777                     & 0x0000003fU
2778 #define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_1_B0__WRITE(src) \
2779                     ((u_int32_t)(src)\
2780                     & 0x0000003fU)
2781 #define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_1_B0__MODIFY(dst, src) \
2782                     (dst) = ((dst) &\
2783                     ~0x0000003fU) | ((u_int32_t)(src) &\
2784                     0x0000003fU)
2785 #define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_1_B0__VERIFY(src) \
2786                     (!(((u_int32_t)(src)\
2787                     & ~0x0000003fU)))
2788
2789 /* macros for field paprd_power_at_am2am_cal_2_b0 */
2790 #define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_2_B0__SHIFT     6
2791 #define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_2_B0__WIDTH     6
2792 #define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_2_B0__MASK \
2793                     0x00000fc0U
2794 #define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_2_B0__READ(src) \
2795                     (((u_int32_t)(src)\
2796                     & 0x00000fc0U) >> 6)
2797 #define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_2_B0__WRITE(src) \
2798                     (((u_int32_t)(src)\
2799                     << 6) & 0x00000fc0U)
2800 #define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_2_B0__MODIFY(dst, src) \
2801                     (dst) = ((dst) &\
2802                     ~0x00000fc0U) | (((u_int32_t)(src) <<\
2803                     6) & 0x00000fc0U)
2804 #define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_2_B0__VERIFY(src) \
2805                     (!((((u_int32_t)(src)\
2806                     << 6) & ~0x00000fc0U)))
2807
2808 /* macros for field paprd_power_at_am2am_cal_3_b0 */
2809 #define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_3_B0__SHIFT    12
2810 #define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_3_B0__WIDTH     6
2811 #define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_3_B0__MASK \
2812                     0x0003f000U
2813 #define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_3_B0__READ(src) \
2814                     (((u_int32_t)(src)\
2815                     & 0x0003f000U) >> 12)
2816 #define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_3_B0__WRITE(src) \
2817                     (((u_int32_t)(src)\
2818                     << 12) & 0x0003f000U)
2819 #define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_3_B0__MODIFY(dst, src) \
2820                     (dst) = ((dst) &\
2821                     ~0x0003f000U) | (((u_int32_t)(src) <<\
2822                     12) & 0x0003f000U)
2823 #define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_3_B0__VERIFY(src) \
2824                     (!((((u_int32_t)(src)\
2825                     << 12) & ~0x0003f000U)))
2826
2827 /* macros for field paprd_power_at_am2am_cal_4_b0 */
2828 #define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_4_B0__SHIFT    18
2829 #define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_4_B0__WIDTH     6
2830 #define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_4_B0__MASK \
2831                     0x00fc0000U
2832 #define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_4_B0__READ(src) \
2833                     (((u_int32_t)(src)\
2834                     & 0x00fc0000U) >> 18)
2835 #define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_4_B0__WRITE(src) \
2836                     (((u_int32_t)(src)\
2837                     << 18) & 0x00fc0000U)
2838 #define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_4_B0__MODIFY(dst, src) \
2839                     (dst) = ((dst) &\
2840                     ~0x00fc0000U) | (((u_int32_t)(src) <<\
2841                     18) & 0x00fc0000U)
2842 #define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_4_B0__VERIFY(src) \
2843                     (!((((u_int32_t)(src)\
2844                     << 18) & ~0x00fc0000U)))
2845 #define PAPRD_POWER_AT_AM2AM_CAL_B0__TYPE                             u_int32_t
2846 #define PAPRD_POWER_AT_AM2AM_CAL_B0__READ                           0x00ffffffU
2847 #define PAPRD_POWER_AT_AM2AM_CAL_B0__WRITE                          0x00ffffffU
2848
2849 #endif /* __PAPRD_POWER_AT_AM2AM_CAL_B0_MACRO__ */
2850
2851
2852 /* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_power_at_am2am_cal_b0 */
2853 #define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_POWER_AT_AM2AM_CAL_B0__NUM \
2854                     1
2855
2856 /* macros for BlueprintGlobalNameSpace::paprd_valid_obdb_b0 */
2857 #ifndef __PAPRD_VALID_OBDB_B0_MACRO__
2858 #define __PAPRD_VALID_OBDB_B0_MACRO__
2859
2860 /* macros for field paprd_valid_obdb_0_b0 */
2861 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_0_B0__SHIFT                     0
2862 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_0_B0__WIDTH                     6
2863 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_0_B0__MASK            0x0000003fU
2864 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_0_B0__READ(src) \
2865                     (u_int32_t)(src)\
2866                     & 0x0000003fU
2867 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_0_B0__WRITE(src) \
2868                     ((u_int32_t)(src)\
2869                     & 0x0000003fU)
2870 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_0_B0__MODIFY(dst, src) \
2871                     (dst) = ((dst) &\
2872                     ~0x0000003fU) | ((u_int32_t)(src) &\
2873                     0x0000003fU)
2874 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_0_B0__VERIFY(src) \
2875                     (!(((u_int32_t)(src)\
2876                     & ~0x0000003fU)))
2877
2878 /* macros for field paprd_valid_obdb_1_b0 */
2879 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_1_B0__SHIFT                     6
2880 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_1_B0__WIDTH                     6
2881 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_1_B0__MASK            0x00000fc0U
2882 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_1_B0__READ(src) \
2883                     (((u_int32_t)(src)\
2884                     & 0x00000fc0U) >> 6)
2885 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_1_B0__WRITE(src) \
2886                     (((u_int32_t)(src)\
2887                     << 6) & 0x00000fc0U)
2888 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_1_B0__MODIFY(dst, src) \
2889                     (dst) = ((dst) &\
2890                     ~0x00000fc0U) | (((u_int32_t)(src) <<\
2891                     6) & 0x00000fc0U)
2892 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_1_B0__VERIFY(src) \
2893                     (!((((u_int32_t)(src)\
2894                     << 6) & ~0x00000fc0U)))
2895
2896 /* macros for field paprd_valid_obdb_2_b0 */
2897 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_2_B0__SHIFT                    12
2898 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_2_B0__WIDTH                     6
2899 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_2_B0__MASK            0x0003f000U
2900 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_2_B0__READ(src) \
2901                     (((u_int32_t)(src)\
2902                     & 0x0003f000U) >> 12)
2903 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_2_B0__WRITE(src) \
2904                     (((u_int32_t)(src)\
2905                     << 12) & 0x0003f000U)
2906 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_2_B0__MODIFY(dst, src) \
2907                     (dst) = ((dst) &\
2908                     ~0x0003f000U) | (((u_int32_t)(src) <<\
2909                     12) & 0x0003f000U)
2910 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_2_B0__VERIFY(src) \
2911                     (!((((u_int32_t)(src)\
2912                     << 12) & ~0x0003f000U)))
2913
2914 /* macros for field paprd_valid_obdb_3_b0 */
2915 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_3_B0__SHIFT                    18
2916 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_3_B0__WIDTH                     6
2917 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_3_B0__MASK            0x00fc0000U
2918 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_3_B0__READ(src) \
2919                     (((u_int32_t)(src)\
2920                     & 0x00fc0000U) >> 18)
2921 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_3_B0__WRITE(src) \
2922                     (((u_int32_t)(src)\
2923                     << 18) & 0x00fc0000U)
2924 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_3_B0__MODIFY(dst, src) \
2925                     (dst) = ((dst) &\
2926                     ~0x00fc0000U) | (((u_int32_t)(src) <<\
2927                     18) & 0x00fc0000U)
2928 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_3_B0__VERIFY(src) \
2929                     (!((((u_int32_t)(src)\
2930                     << 18) & ~0x00fc0000U)))
2931
2932 /* macros for field paprd_valid_obdb_4_b0 */
2933 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_4_B0__SHIFT                    24
2934 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_4_B0__WIDTH                     6
2935 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_4_B0__MASK            0x3f000000U
2936 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_4_B0__READ(src) \
2937                     (((u_int32_t)(src)\
2938                     & 0x3f000000U) >> 24)
2939 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_4_B0__WRITE(src) \
2940                     (((u_int32_t)(src)\
2941                     << 24) & 0x3f000000U)
2942 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_4_B0__MODIFY(dst, src) \
2943                     (dst) = ((dst) &\
2944                     ~0x3f000000U) | (((u_int32_t)(src) <<\
2945                     24) & 0x3f000000U)
2946 #define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_4_B0__VERIFY(src) \
2947                     (!((((u_int32_t)(src)\
2948                     << 24) & ~0x3f000000U)))
2949 #define PAPRD_VALID_OBDB_B0__TYPE                                     u_int32_t
2950 #define PAPRD_VALID_OBDB_B0__READ                                   0x3fffffffU
2951 #define PAPRD_VALID_OBDB_B0__WRITE                                  0x3fffffffU
2952
2953 #endif /* __PAPRD_VALID_OBDB_B0_MACRO__ */
2954
2955
2956 /* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_valid_obdb_b0 */
2957 #define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_VALID_OBDB_B0__NUM    1
2958
2959 /* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_1 */
2960 #ifndef __GREEN_TX_GAIN_TAB_1_MACRO__
2961 #define __GREEN_TX_GAIN_TAB_1_MACRO__
2962
2963 /* macros for field green_tg_table1 */
2964 #define GREEN_TX_GAIN_TAB_1__GREEN_TG_TABLE1__SHIFT                           0
2965 #define GREEN_TX_GAIN_TAB_1__GREEN_TG_TABLE1__WIDTH                           7
2966 #define GREEN_TX_GAIN_TAB_1__GREEN_TG_TABLE1__MASK                  0x0000007fU
2967 #define GREEN_TX_GAIN_TAB_1__GREEN_TG_TABLE1__READ(src) \
2968                     (u_int32_t)(src)\
2969                     & 0x0000007fU
2970 #define GREEN_TX_GAIN_TAB_1__GREEN_TG_TABLE1__WRITE(src) \
2971                     ((u_int32_t)(src)\
2972                     & 0x0000007fU)
2973 #define GREEN_TX_GAIN_TAB_1__GREEN_TG_TABLE1__MODIFY(dst, src) \
2974                     (dst) = ((dst) &\
2975                     ~0x0000007fU) | ((u_int32_t)(src) &\
2976                     0x0000007fU)
2977 #define GREEN_TX_GAIN_TAB_1__GREEN_TG_TABLE1__VERIFY(src) \
2978                     (!(((u_int32_t)(src)\
2979                     & ~0x0000007fU)))
2980 #define GREEN_TX_GAIN_TAB_1__TYPE                                     u_int32_t
2981 #define GREEN_TX_GAIN_TAB_1__READ                                   0x0000007fU
2982 #define GREEN_TX_GAIN_TAB_1__WRITE                                  0x0000007fU
2983
2984 #endif /* __GREEN_TX_GAIN_TAB_1_MACRO__ */
2985
2986
2987 /* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_1 */
2988 #define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_1__NUM     1
2989
2990 /* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_2 */
2991 #ifndef __GREEN_TX_GAIN_TAB_2_MACRO__
2992 #define __GREEN_TX_GAIN_TAB_2_MACRO__
2993
2994 /* macros for field green_tg_table2 */
2995 #define GREEN_TX_GAIN_TAB_2__GREEN_TG_TABLE2__SHIFT                           0
2996 #define GREEN_TX_GAIN_TAB_2__GREEN_TG_TABLE2__WIDTH                           7
2997 #define GREEN_TX_GAIN_TAB_2__GREEN_TG_TABLE2__MASK                  0x0000007fU
2998 #define GREEN_TX_GAIN_TAB_2__GREEN_TG_TABLE2__READ(src) \
2999                     (u_int32_t)(src)\
3000                     & 0x0000007fU
3001 #define GREEN_TX_GAIN_TAB_2__GREEN_TG_TABLE2__WRITE(src) \
3002                     ((u_int32_t)(src)\
3003                     & 0x0000007fU)
3004 #define GREEN_TX_GAIN_TAB_2__GREEN_TG_TABLE2__MODIFY(dst, src) \
3005                     (dst) = ((dst) &\
3006                     ~0x0000007fU) | ((u_int32_t)(src) &\
3007                     0x0000007fU)
3008 #define GREEN_TX_GAIN_TAB_2__GREEN_TG_TABLE2__VERIFY(src) \
3009                     (!(((u_int32_t)(src)\
3010                     & ~0x0000007fU)))
3011 #define GREEN_TX_GAIN_TAB_2__TYPE                                     u_int32_t
3012 #define GREEN_TX_GAIN_TAB_2__READ                                   0x0000007fU
3013 #define GREEN_TX_GAIN_TAB_2__WRITE                                  0x0000007fU
3014
3015 #endif /* __GREEN_TX_GAIN_TAB_2_MACRO__ */
3016
3017
3018 /* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_2 */
3019 #define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_2__NUM     1
3020
3021 /* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_3 */
3022 #ifndef __GREEN_TX_GAIN_TAB_3_MACRO__
3023 #define __GREEN_TX_GAIN_TAB_3_MACRO__
3024
3025 /* macros for field green_tg_table3 */
3026 #define GREEN_TX_GAIN_TAB_3__GREEN_TG_TABLE3__SHIFT                           0
3027 #define GREEN_TX_GAIN_TAB_3__GREEN_TG_TABLE3__WIDTH                           7
3028 #define GREEN_TX_GAIN_TAB_3__GREEN_TG_TABLE3__MASK                  0x0000007fU
3029 #define GREEN_TX_GAIN_TAB_3__GREEN_TG_TABLE3__READ(src) \
3030                     (u_int32_t)(src)\
3031                     & 0x0000007fU
3032 #define GREEN_TX_GAIN_TAB_3__GREEN_TG_TABLE3__WRITE(src) \
3033                     ((u_int32_t)(src)\
3034                     & 0x0000007fU)
3035 #define GREEN_TX_GAIN_TAB_3__GREEN_TG_TABLE3__MODIFY(dst, src) \
3036                     (dst) = ((dst) &\
3037                     ~0x0000007fU) | ((u_int32_t)(src) &\
3038                     0x0000007fU)
3039 #define GREEN_TX_GAIN_TAB_3__GREEN_TG_TABLE3__VERIFY(src) \
3040                     (!(((u_int32_t)(src)\
3041                     & ~0x0000007fU)))
3042 #define GREEN_TX_GAIN_TAB_3__TYPE                                     u_int32_t
3043 #define GREEN_TX_GAIN_TAB_3__READ                                   0x0000007fU
3044 #define GREEN_TX_GAIN_TAB_3__WRITE                                  0x0000007fU
3045
3046 #endif /* __GREEN_TX_GAIN_TAB_3_MACRO__ */
3047
3048
3049 /* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_3 */
3050 #define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_3__NUM     1
3051
3052 /* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_4 */
3053 #ifndef __GREEN_TX_GAIN_TAB_4_MACRO__
3054 #define __GREEN_TX_GAIN_TAB_4_MACRO__
3055
3056 /* macros for field green_tg_table4 */
3057 #define GREEN_TX_GAIN_TAB_4__GREEN_TG_TABLE4__SHIFT                           0
3058 #define GREEN_TX_GAIN_TAB_4__GREEN_TG_TABLE4__WIDTH                           7
3059 #define GREEN_TX_GAIN_TAB_4__GREEN_TG_TABLE4__MASK                  0x0000007fU
3060 #define GREEN_TX_GAIN_TAB_4__GREEN_TG_TABLE4__READ(src) \
3061                     (u_int32_t)(src)\
3062                     & 0x0000007fU
3063 #define GREEN_TX_GAIN_TAB_4__GREEN_TG_TABLE4__WRITE(src) \
3064                     ((u_int32_t)(src)\
3065                     & 0x0000007fU)
3066 #define GREEN_TX_GAIN_TAB_4__GREEN_TG_TABLE4__MODIFY(dst, src) \
3067                     (dst) = ((dst) &\
3068                     ~0x0000007fU) | ((u_int32_t)(src) &\
3069                     0x0000007fU)
3070 #define GREEN_TX_GAIN_TAB_4__GREEN_TG_TABLE4__VERIFY(src) \
3071                     (!(((u_int32_t)(src)\
3072                     & ~0x0000007fU)))
3073 #define GREEN_TX_GAIN_TAB_4__TYPE                                     u_int32_t
3074 #define GREEN_TX_GAIN_TAB_4__READ                                   0x0000007fU
3075 #define GREEN_TX_GAIN_TAB_4__WRITE                                  0x0000007fU
3076
3077 #endif /* __GREEN_TX_GAIN_TAB_4_MACRO__ */
3078
3079
3080 /* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_4 */
3081 #define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_4__NUM     1
3082
3083 /* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_5 */
3084 #ifndef __GREEN_TX_GAIN_TAB_5_MACRO__
3085 #define __GREEN_TX_GAIN_TAB_5_MACRO__
3086
3087 /* macros for field green_tg_table5 */
3088 #define GREEN_TX_GAIN_TAB_5__GREEN_TG_TABLE5__SHIFT                           0
3089 #define GREEN_TX_GAIN_TAB_5__GREEN_TG_TABLE5__WIDTH                           7
3090 #define GREEN_TX_GAIN_TAB_5__GREEN_TG_TABLE5__MASK                  0x0000007fU
3091 #define GREEN_TX_GAIN_TAB_5__GREEN_TG_TABLE5__READ(src) \
3092                     (u_int32_t)(src)\
3093                     & 0x0000007fU
3094 #define GREEN_TX_GAIN_TAB_5__GREEN_TG_TABLE5__WRITE(src) \
3095                     ((u_int32_t)(src)\
3096                     & 0x0000007fU)
3097 #define GREEN_TX_GAIN_TAB_5__GREEN_TG_TABLE5__MODIFY(dst, src) \
3098                     (dst) = ((dst) &\
3099                     ~0x0000007fU) | ((u_int32_t)(src) &\
3100                     0x0000007fU)
3101 #define GREEN_TX_GAIN_TAB_5__GREEN_TG_TABLE5__VERIFY(src) \
3102                     (!(((u_int32_t)(src)\
3103                     & ~0x0000007fU)))
3104 #define GREEN_TX_GAIN_TAB_5__TYPE                                     u_int32_t
3105 #define GREEN_TX_GAIN_TAB_5__READ                                   0x0000007fU
3106 #define GREEN_TX_GAIN_TAB_5__WRITE                                  0x0000007fU
3107
3108 #endif /* __GREEN_TX_GAIN_TAB_5_MACRO__ */
3109
3110
3111 /* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_5 */
3112 #define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_5__NUM     1
3113
3114 /* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_6 */
3115 #ifndef __GREEN_TX_GAIN_TAB_6_MACRO__
3116 #define __GREEN_TX_GAIN_TAB_6_MACRO__
3117
3118 /* macros for field green_tg_table6 */
3119 #define GREEN_TX_GAIN_TAB_6__GREEN_TG_TABLE6__SHIFT                           0
3120 #define GREEN_TX_GAIN_TAB_6__GREEN_TG_TABLE6__WIDTH                           7
3121 #define GREEN_TX_GAIN_TAB_6__GREEN_TG_TABLE6__MASK                  0x0000007fU
3122 #define GREEN_TX_GAIN_TAB_6__GREEN_TG_TABLE6__READ(src) \
3123                     (u_int32_t)(src)\
3124                     & 0x0000007fU
3125 #define GREEN_TX_GAIN_TAB_6__GREEN_TG_TABLE6__WRITE(src) \
3126                     ((u_int32_t)(src)\
3127                     & 0x0000007fU)
3128 #define GREEN_TX_GAIN_TAB_6__GREEN_TG_TABLE6__MODIFY(dst, src) \
3129                     (dst) = ((dst) &\
3130                     ~0x0000007fU) | ((u_int32_t)(src) &\
3131                     0x0000007fU)
3132 #define GREEN_TX_GAIN_TAB_6__GREEN_TG_TABLE6__VERIFY(src) \
3133                     (!(((u_int32_t)(src)\
3134                     & ~0x0000007fU)))
3135 #define GREEN_TX_GAIN_TAB_6__TYPE                                     u_int32_t
3136 #define GREEN_TX_GAIN_TAB_6__READ                                   0x0000007fU
3137 #define GREEN_TX_GAIN_TAB_6__WRITE                                  0x0000007fU
3138
3139 #endif /* __GREEN_TX_GAIN_TAB_6_MACRO__ */
3140
3141
3142 /* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_6 */
3143 #define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_6__NUM     1
3144
3145 /* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_7 */
3146 #ifndef __GREEN_TX_GAIN_TAB_7_MACRO__
3147 #define __GREEN_TX_GAIN_TAB_7_MACRO__
3148
3149 /* macros for field green_tg_table7 */
3150 #define GREEN_TX_GAIN_TAB_7__GREEN_TG_TABLE7__SHIFT                           0
3151 #define GREEN_TX_GAIN_TAB_7__GREEN_TG_TABLE7__WIDTH                           7
3152 #define GREEN_TX_GAIN_TAB_7__GREEN_TG_TABLE7__MASK                  0x0000007fU
3153 #define GREEN_TX_GAIN_TAB_7__GREEN_TG_TABLE7__READ(src) \
3154                     (u_int32_t)(src)\
3155                     & 0x0000007fU
3156 #define GREEN_TX_GAIN_TAB_7__GREEN_TG_TABLE7__WRITE(src) \
3157                     ((u_int32_t)(src)\
3158                     & 0x0000007fU)
3159 #define GREEN_TX_GAIN_TAB_7__GREEN_TG_TABLE7__MODIFY(dst, src) \
3160                     (dst) = ((dst) &\
3161                     ~0x0000007fU) | ((u_int32_t)(src) &\
3162                     0x0000007fU)
3163 #define GREEN_TX_GAIN_TAB_7__GREEN_TG_TABLE7__VERIFY(src) \
3164                     (!(((u_int32_t)(src)\
3165                     & ~0x0000007fU)))
3166 #define GREEN_TX_GAIN_TAB_7__TYPE                                     u_int32_t
3167 #define GREEN_TX_GAIN_TAB_7__READ                                   0x0000007fU
3168 #define GREEN_TX_GAIN_TAB_7__WRITE                                  0x0000007fU
3169
3170 #endif /* __GREEN_TX_GAIN_TAB_7_MACRO__ */
3171
3172
3173 /* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_7 */
3174 #define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_7__NUM     1
3175
3176 /* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_8 */
3177 #ifndef __GREEN_TX_GAIN_TAB_8_MACRO__
3178 #define __GREEN_TX_GAIN_TAB_8_MACRO__
3179
3180 /* macros for field green_tg_table8 */
3181 #define GREEN_TX_GAIN_TAB_8__GREEN_TG_TABLE8__SHIFT                           0
3182 #define GREEN_TX_GAIN_TAB_8__GREEN_TG_TABLE8__WIDTH                           7
3183 #define GREEN_TX_GAIN_TAB_8__GREEN_TG_TABLE8__MASK                  0x0000007fU
3184 #define GREEN_TX_GAIN_TAB_8__GREEN_TG_TABLE8__READ(src) \
3185                     (u_int32_t)(src)\
3186                     & 0x0000007fU
3187 #define GREEN_TX_GAIN_TAB_8__GREEN_TG_TABLE8__WRITE(src) \
3188                     ((u_int32_t)(src)\
3189                     & 0x0000007fU)
3190 #define GREEN_TX_GAIN_TAB_8__GREEN_TG_TABLE8__MODIFY(dst, src) \
3191                     (dst) = ((dst) &\
3192                     ~0x0000007fU) | ((u_int32_t)(src) &\
3193                     0x0000007fU)
3194 #define GREEN_TX_GAIN_TAB_8__GREEN_TG_TABLE8__VERIFY(src) \
3195                     (!(((u_int32_t)(src)\
3196                     & ~0x0000007fU)))
3197 #define GREEN_TX_GAIN_TAB_8__TYPE                                     u_int32_t
3198 #define GREEN_TX_GAIN_TAB_8__READ                                   0x0000007fU
3199 #define GREEN_TX_GAIN_TAB_8__WRITE                                  0x0000007fU
3200
3201 #endif /* __GREEN_TX_GAIN_TAB_8_MACRO__ */
3202
3203
3204 /* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_8 */
3205 #define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_8__NUM     1
3206
3207 /* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_9 */
3208 #ifndef __GREEN_TX_GAIN_TAB_9_MACRO__
3209 #define __GREEN_TX_GAIN_TAB_9_MACRO__
3210
3211 /* macros for field green_tg_table9 */
3212 #define GREEN_TX_GAIN_TAB_9__GREEN_TG_TABLE9__SHIFT                           0
3213 #define GREEN_TX_GAIN_TAB_9__GREEN_TG_TABLE9__WIDTH                           7
3214 #define GREEN_TX_GAIN_TAB_9__GREEN_TG_TABLE9__MASK                  0x0000007fU
3215 #define GREEN_TX_GAIN_TAB_9__GREEN_TG_TABLE9__READ(src) \
3216                     (u_int32_t)(src)\
3217                     & 0x0000007fU
3218 #define GREEN_TX_GAIN_TAB_9__GREEN_TG_TABLE9__WRITE(src) \
3219                     ((u_int32_t)(src)\
3220                     & 0x0000007fU)
3221 #define GREEN_TX_GAIN_TAB_9__GREEN_TG_TABLE9__MODIFY(dst, src) \
3222                     (dst) = ((dst) &\
3223                     ~0x0000007fU) | ((u_int32_t)(src) &\
3224                     0x0000007fU)
3225 #define GREEN_TX_GAIN_TAB_9__GREEN_TG_TABLE9__VERIFY(src) \
3226                     (!(((u_int32_t)(src)\
3227                     & ~0x0000007fU)))
3228 #define GREEN_TX_GAIN_TAB_9__TYPE                                     u_int32_t
3229 #define GREEN_TX_GAIN_TAB_9__READ                                   0x0000007fU
3230 #define GREEN_TX_GAIN_TAB_9__WRITE                                  0x0000007fU
3231
3232 #endif /* __GREEN_TX_GAIN_TAB_9_MACRO__ */
3233
3234
3235 /* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_9 */
3236 #define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_9__NUM     1
3237
3238 /* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_10 */
3239 #ifndef __GREEN_TX_GAIN_TAB_10_MACRO__
3240 #define __GREEN_TX_GAIN_TAB_10_MACRO__
3241
3242 /* macros for field green_tg_table10 */
3243 #define GREEN_TX_GAIN_TAB_10__GREEN_TG_TABLE10__SHIFT                         0
3244 #define GREEN_TX_GAIN_TAB_10__GREEN_TG_TABLE10__WIDTH                         7
3245 #define GREEN_TX_GAIN_TAB_10__GREEN_TG_TABLE10__MASK                0x0000007fU
3246 #define GREEN_TX_GAIN_TAB_10__GREEN_TG_TABLE10__READ(src) \
3247                     (u_int32_t)(src)\
3248                     & 0x0000007fU
3249 #define GREEN_TX_GAIN_TAB_10__GREEN_TG_TABLE10__WRITE(src) \
3250                     ((u_int32_t)(src)\
3251                     & 0x0000007fU)
3252 #define GREEN_TX_GAIN_TAB_10__GREEN_TG_TABLE10__MODIFY(dst, src) \
3253                     (dst) = ((dst) &\
3254                     ~0x0000007fU) | ((u_int32_t)(src) &\
3255                     0x0000007fU)
3256 #define GREEN_TX_GAIN_TAB_10__GREEN_TG_TABLE10__VERIFY(src) \
3257                     (!(((u_int32_t)(src)\
3258                     & ~0x0000007fU)))
3259 #define GREEN_TX_GAIN_TAB_10__TYPE                                    u_int32_t
3260 #define GREEN_TX_GAIN_TAB_10__READ                                  0x0000007fU
3261 #define GREEN_TX_GAIN_TAB_10__WRITE                                 0x0000007fU
3262
3263 #endif /* __GREEN_TX_GAIN_TAB_10_MACRO__ */
3264
3265
3266 /* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_10 */
3267 #define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_10__NUM    1
3268
3269 /* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_11 */
3270 #ifndef __GREEN_TX_GAIN_TAB_11_MACRO__
3271 #define __GREEN_TX_GAIN_TAB_11_MACRO__
3272
3273 /* macros for field green_tg_table11 */
3274 #define GREEN_TX_GAIN_TAB_11__GREEN_TG_TABLE11__SHIFT                         0
3275 #define GREEN_TX_GAIN_TAB_11__GREEN_TG_TABLE11__WIDTH                         7
3276 #define GREEN_TX_GAIN_TAB_11__GREEN_TG_TABLE11__MASK                0x0000007fU
3277 #define GREEN_TX_GAIN_TAB_11__GREEN_TG_TABLE11__READ(src) \
3278                     (u_int32_t)(src)\
3279                     & 0x0000007fU
3280 #define GREEN_TX_GAIN_TAB_11__GREEN_TG_TABLE11__WRITE(src) \
3281                     ((u_int32_t)(src)\
3282                     & 0x0000007fU)
3283 #define GREEN_TX_GAIN_TAB_11__GREEN_TG_TABLE11__MODIFY(dst, src) \
3284                     (dst) = ((dst) &\
3285                     ~0x0000007fU) | ((u_int32_t)(src) &\
3286                     0x0000007fU)
3287 #define GREEN_TX_GAIN_TAB_11__GREEN_TG_TABLE11__VERIFY(src) \
3288                     (!(((u_int32_t)(src)\
3289                     & ~0x0000007fU)))
3290 #define GREEN_TX_GAIN_TAB_11__TYPE                                    u_int32_t
3291 #define GREEN_TX_GAIN_TAB_11__READ                                  0x0000007fU
3292 #define GREEN_TX_GAIN_TAB_11__WRITE                                 0x0000007fU
3293
3294 #endif /* __GREEN_TX_GAIN_TAB_11_MACRO__ */
3295
3296
3297 /* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_11 */
3298 #define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_11__NUM    1
3299
3300 /* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_12 */
3301 #ifndef __GREEN_TX_GAIN_TAB_12_MACRO__
3302 #define __GREEN_TX_GAIN_TAB_12_MACRO__
3303
3304 /* macros for field green_tg_table12 */
3305 #define GREEN_TX_GAIN_TAB_12__GREEN_TG_TABLE12__SHIFT                         0
3306 #define GREEN_TX_GAIN_TAB_12__GREEN_TG_TABLE12__WIDTH                         7
3307 #define GREEN_TX_GAIN_TAB_12__GREEN_TG_TABLE12__MASK                0x0000007fU
3308 #define GREEN_TX_GAIN_TAB_12__GREEN_TG_TABLE12__READ(src) \
3309                     (u_int32_t)(src)\
3310                     & 0x0000007fU
3311 #define GREEN_TX_GAIN_TAB_12__GREEN_TG_TABLE12__WRITE(src) \
3312                     ((u_int32_t)(src)\
3313                     & 0x0000007fU)
3314 #define GREEN_TX_GAIN_TAB_12__GREEN_TG_TABLE12__MODIFY(dst, src) \
3315                     (dst) = ((dst) &\
3316                     ~0x0000007fU) | ((u_int32_t)(src) &\
3317                     0x0000007fU)
3318 #define GREEN_TX_GAIN_TAB_12__GREEN_TG_TABLE12__VERIFY(src) \
3319                     (!(((u_int32_t)(src)\
3320                     & ~0x0000007fU)))
3321 #define GREEN_TX_GAIN_TAB_12__TYPE                                    u_int32_t
3322 #define GREEN_TX_GAIN_TAB_12__READ                                  0x0000007fU
3323 #define GREEN_TX_GAIN_TAB_12__WRITE                                 0x0000007fU
3324
3325 #endif /* __GREEN_TX_GAIN_TAB_12_MACRO__ */
3326
3327
3328 /* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_12 */
3329 #define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_12__NUM    1
3330
3331 /* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_13 */
3332 #ifndef __GREEN_TX_GAIN_TAB_13_MACRO__
3333 #define __GREEN_TX_GAIN_TAB_13_MACRO__
3334
3335 /* macros for field green_tg_table13 */
3336 #define GREEN_TX_GAIN_TAB_13__GREEN_TG_TABLE13__SHIFT                         0
3337 #define GREEN_TX_GAIN_TAB_13__GREEN_TG_TABLE13__WIDTH                         7
3338 #define GREEN_TX_GAIN_TAB_13__GREEN_TG_TABLE13__MASK                0x0000007fU
3339 #define GREEN_TX_GAIN_TAB_13__GREEN_TG_TABLE13__READ(src) \
3340                     (u_int32_t)(src)\
3341                     & 0x0000007fU
3342 #define GREEN_TX_GAIN_TAB_13__GREEN_TG_TABLE13__WRITE(src) \
3343                     ((u_int32_t)(src)\
3344                     & 0x0000007fU)
3345 #define GREEN_TX_GAIN_TAB_13__GREEN_TG_TABLE13__MODIFY(dst, src) \
3346                     (dst) = ((dst) &\
3347                     ~0x0000007fU) | ((u_int32_t)(src) &\
3348                     0x0000007fU)
3349 #define GREEN_TX_GAIN_TAB_13__GREEN_TG_TABLE13__VERIFY(src) \
3350                     (!(((u_int32_t)(src)\
3351                     & ~0x0000007fU)))
3352 #define GREEN_TX_GAIN_TAB_13__TYPE                                    u_int32_t
3353 #define GREEN_TX_GAIN_TAB_13__READ                                  0x0000007fU
3354 #define GREEN_TX_GAIN_TAB_13__WRITE                                 0x0000007fU
3355
3356 #endif /* __GREEN_TX_GAIN_TAB_13_MACRO__ */
3357
3358
3359 /* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_13 */
3360 #define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_13__NUM    1
3361
3362 /* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_14 */
3363 #ifndef __GREEN_TX_GAIN_TAB_14_MACRO__
3364 #define __GREEN_TX_GAIN_TAB_14_MACRO__
3365
3366 /* macros for field green_tg_table14 */
3367 #define GREEN_TX_GAIN_TAB_14__GREEN_TG_TABLE14__SHIFT                         0
3368 #define GREEN_TX_GAIN_TAB_14__GREEN_TG_TABLE14__WIDTH                         7
3369 #define GREEN_TX_GAIN_TAB_14__GREEN_TG_TABLE14__MASK                0x0000007fU
3370 #define GREEN_TX_GAIN_TAB_14__GREEN_TG_TABLE14__READ(src) \
3371                     (u_int32_t)(src)\
3372                     & 0x0000007fU
3373 #define GREEN_TX_GAIN_TAB_14__GREEN_TG_TABLE14__WRITE(src) \
3374                     ((u_int32_t)(src)\
3375                     & 0x0000007fU)
3376 #define GREEN_TX_GAIN_TAB_14__GREEN_TG_TABLE14__MODIFY(dst, src) \
3377                     (dst) = ((dst) &\
3378                     ~0x0000007fU) | ((u_int32_t)(src) &\
3379                     0x0000007fU)
3380 #define GREEN_TX_GAIN_TAB_14__GREEN_TG_TABLE14__VERIFY(src) \
3381                     (!(((u_int32_t)(src)\
3382                     & ~0x0000007fU)))
3383 #define GREEN_TX_GAIN_TAB_14__TYPE                                    u_int32_t
3384 #define GREEN_TX_GAIN_TAB_14__READ                                  0x0000007fU
3385 #define GREEN_TX_GAIN_TAB_14__WRITE                                 0x0000007fU
3386
3387 #endif /* __GREEN_TX_GAIN_TAB_14_MACRO__ */
3388
3389
3390 /* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_14 */
3391 #define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_14__NUM    1
3392
3393 /* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_15 */
3394 #ifndef __GREEN_TX_GAIN_TAB_15_MACRO__
3395 #define __GREEN_TX_GAIN_TAB_15_MACRO__
3396
3397 /* macros for field green_tg_table15 */
3398 #define GREEN_TX_GAIN_TAB_15__GREEN_TG_TABLE15__SHIFT                         0
3399 #define GREEN_TX_GAIN_TAB_15__GREEN_TG_TABLE15__WIDTH                         7
3400 #define GREEN_TX_GAIN_TAB_15__GREEN_TG_TABLE15__MASK                0x0000007fU
3401 #define GREEN_TX_GAIN_TAB_15__GREEN_TG_TABLE15__READ(src) \
3402                     (u_int32_t)(src)\
3403                     & 0x0000007fU
3404 #define GREEN_TX_GAIN_TAB_15__GREEN_TG_TABLE15__WRITE(src) \
3405                     ((u_int32_t)(src)\
3406                     & 0x0000007fU)
3407 #define GREEN_TX_GAIN_TAB_15__GREEN_TG_TABLE15__MODIFY(dst, src) \
3408                     (dst) = ((dst) &\
3409                     ~0x0000007fU) | ((u_int32_t)(src) &\
3410                     0x0000007fU)
3411 #define GREEN_TX_GAIN_TAB_15__GREEN_TG_TABLE15__VERIFY(src) \
3412                     (!(((u_int32_t)(src)\
3413                     & ~0x0000007fU)))
3414 #define GREEN_TX_GAIN_TAB_15__TYPE                                    u_int32_t
3415 #define GREEN_TX_GAIN_TAB_15__READ                                  0x0000007fU
3416 #define GREEN_TX_GAIN_TAB_15__WRITE                                 0x0000007fU
3417
3418 #endif /* __GREEN_TX_GAIN_TAB_15_MACRO__ */
3419
3420
3421 /* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_15 */
3422 #define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_15__NUM    1
3423
3424 /* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_16 */
3425 #ifndef __GREEN_TX_GAIN_TAB_16_MACRO__
3426 #define __GREEN_TX_GAIN_TAB_16_MACRO__
3427
3428 /* macros for field green_tg_table16 */
3429 #define GREEN_TX_GAIN_TAB_16__GREEN_TG_TABLE16__SHIFT                         0
3430 #define GREEN_TX_GAIN_TAB_16__GREEN_TG_TABLE16__WIDTH                         7
3431 #define GREEN_TX_GAIN_TAB_16__GREEN_TG_TABLE16__MASK                0x0000007fU
3432 #define GREEN_TX_GAIN_TAB_16__GREEN_TG_TABLE16__READ(src) \
3433                     (u_int32_t)(src)\
3434                     & 0x0000007fU
3435 #define GREEN_TX_GAIN_TAB_16__GREEN_TG_TABLE16__WRITE(src) \
3436                     ((u_int32_t)(src)\
3437                     & 0x0000007fU)
3438 #define GREEN_TX_GAIN_TAB_16__GREEN_TG_TABLE16__MODIFY(dst, src) \
3439                     (dst) = ((dst) &\
3440                     ~0x0000007fU) | ((u_int32_t)(src) &\
3441                     0x0000007fU)
3442 #define GREEN_TX_GAIN_TAB_16__GREEN_TG_TABLE16__VERIFY(src) \
3443                     (!(((u_int32_t)(src)\
3444                     & ~0x0000007fU)))
3445 #define GREEN_TX_GAIN_TAB_16__TYPE                                    u_int32_t
3446 #define GREEN_TX_GAIN_TAB_16__READ                                  0x0000007fU
3447 #define GREEN_TX_GAIN_TAB_16__WRITE                                 0x0000007fU
3448
3449 #endif /* __GREEN_TX_GAIN_TAB_16_MACRO__ */
3450
3451
3452 /* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_16 */
3453 #define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_16__NUM    1
3454
3455 /* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_17 */
3456 #ifndef __GREEN_TX_GAIN_TAB_17_MACRO__
3457 #define __GREEN_TX_GAIN_TAB_17_MACRO__
3458
3459 /* macros for field green_tg_table17 */
3460 #define GREEN_TX_GAIN_TAB_17__GREEN_TG_TABLE17__SHIFT                         0
3461 #define GREEN_TX_GAIN_TAB_17__GREEN_TG_TABLE17__WIDTH                         7
3462 #define GREEN_TX_GAIN_TAB_17__GREEN_TG_TABLE17__MASK                0x0000007fU
3463 #define GREEN_TX_GAIN_TAB_17__GREEN_TG_TABLE17__READ(src) \
3464                     (u_int32_t)(src)\
3465                     & 0x0000007fU
3466 #define GREEN_TX_GAIN_TAB_17__GREEN_TG_TABLE17__WRITE(src) \
3467                     ((u_int32_t)(src)\
3468                     & 0x0000007fU)
3469 #define GREEN_TX_GAIN_TAB_17__GREEN_TG_TABLE17__MODIFY(dst, src) \
3470                     (dst) = ((dst) &\
3471                     ~0x0000007fU) | ((u_int32_t)(src) &\
3472                     0x0000007fU)
3473 #define GREEN_TX_GAIN_TAB_17__GREEN_TG_TABLE17__VERIFY(src) \
3474                     (!(((u_int32_t)(src)\
3475                     & ~0x0000007fU)))
3476 #define GREEN_TX_GAIN_TAB_17__TYPE                                    u_int32_t
3477 #define GREEN_TX_GAIN_TAB_17__READ                                  0x0000007fU
3478 #define GREEN_TX_GAIN_TAB_17__WRITE                                 0x0000007fU
3479
3480 #endif /* __GREEN_TX_GAIN_TAB_17_MACRO__ */
3481
3482
3483 /* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_17 */
3484 #define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_17__NUM    1
3485
3486 /* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_18 */
3487 #ifndef __GREEN_TX_GAIN_TAB_18_MACRO__
3488 #define __GREEN_TX_GAIN_TAB_18_MACRO__
3489
3490 /* macros for field green_tg_table18 */
3491 #define GREEN_TX_GAIN_TAB_18__GREEN_TG_TABLE18__SHIFT                         0
3492 #define GREEN_TX_GAIN_TAB_18__GREEN_TG_TABLE18__WIDTH                         7
3493 #define GREEN_TX_GAIN_TAB_18__GREEN_TG_TABLE18__MASK                0x0000007fU
3494 #define GREEN_TX_GAIN_TAB_18__GREEN_TG_TABLE18__READ(src) \
3495                     (u_int32_t)(src)\
3496                     & 0x0000007fU
3497 #define GREEN_TX_GAIN_TAB_18__GREEN_TG_TABLE18__WRITE(src) \
3498                     ((u_int32_t)(src)\
3499                     & 0x0000007fU)
3500 #define GREEN_TX_GAIN_TAB_18__GREEN_TG_TABLE18__MODIFY(dst, src) \
3501                     (dst) = ((dst) &\
3502                     ~0x0000007fU) | ((u_int32_t)(src) &\
3503                     0x0000007fU)
3504 #define GREEN_TX_GAIN_TAB_18__GREEN_TG_TABLE18__VERIFY(src) \
3505                     (!(((u_int32_t)(src)\
3506                     & ~0x0000007fU)))
3507 #define GREEN_TX_GAIN_TAB_18__TYPE                                    u_int32_t
3508 #define GREEN_TX_GAIN_TAB_18__READ                                  0x0000007fU
3509 #define GREEN_TX_GAIN_TAB_18__WRITE                                 0x0000007fU
3510
3511 #endif /* __GREEN_TX_GAIN_TAB_18_MACRO__ */
3512
3513
3514 /* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_18 */
3515 #define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_18__NUM    1
3516
3517 /* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_19 */
3518 #ifndef __GREEN_TX_GAIN_TAB_19_MACRO__
3519 #define __GREEN_TX_GAIN_TAB_19_MACRO__
3520
3521 /* macros for field green_tg_table19 */
3522 #define GREEN_TX_GAIN_TAB_19__GREEN_TG_TABLE19__SHIFT                         0
3523 #define GREEN_TX_GAIN_TAB_19__GREEN_TG_TABLE19__WIDTH                         7
3524 #define GREEN_TX_GAIN_TAB_19__GREEN_TG_TABLE19__MASK                0x0000007fU
3525 #define GREEN_TX_GAIN_TAB_19__GREEN_TG_TABLE19__READ(src) \
3526                     (u_int32_t)(src)\
3527                     & 0x0000007fU
3528 #define GREEN_TX_GAIN_TAB_19__GREEN_TG_TABLE19__WRITE(src) \
3529                     ((u_int32_t)(src)\
3530                     & 0x0000007fU)
3531 #define GREEN_TX_GAIN_TAB_19__GREEN_TG_TABLE19__MODIFY(dst, src) \
3532                     (dst) = ((dst) &\
3533                     ~0x0000007fU) | ((u_int32_t)(src) &\
3534                     0x0000007fU)
3535 #define GREEN_TX_GAIN_TAB_19__GREEN_TG_TABLE19__VERIFY(src) \
3536                     (!(((u_int32_t)(src)\
3537                     & ~0x0000007fU)))
3538 #define GREEN_TX_GAIN_TAB_19__TYPE                                    u_int32_t
3539 #define GREEN_TX_GAIN_TAB_19__READ                                  0x0000007fU
3540 #define GREEN_TX_GAIN_TAB_19__WRITE                                 0x0000007fU
3541
3542 #endif /* __GREEN_TX_GAIN_TAB_19_MACRO__ */
3543
3544
3545 /* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_19 */
3546 #define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_19__NUM    1
3547
3548 /* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_20 */
3549 #ifndef __GREEN_TX_GAIN_TAB_20_MACRO__
3550 #define __GREEN_TX_GAIN_TAB_20_MACRO__
3551
3552 /* macros for field green_tg_table20 */
3553 #define GREEN_TX_GAIN_TAB_20__GREEN_TG_TABLE20__SHIFT                         0
3554 #define GREEN_TX_GAIN_TAB_20__GREEN_TG_TABLE20__WIDTH                         7
3555 #define GREEN_TX_GAIN_TAB_20__GREEN_TG_TABLE20__MASK                0x0000007fU
3556 #define GREEN_TX_GAIN_TAB_20__GREEN_TG_TABLE20__READ(src) \
3557                     (u_int32_t)(src)\
3558                     & 0x0000007fU
3559 #define GREEN_TX_GAIN_TAB_20__GREEN_TG_TABLE20__WRITE(src) \
3560                     ((u_int32_t)(src)\
3561                     & 0x0000007fU)
3562 #define GREEN_TX_GAIN_TAB_20__GREEN_TG_TABLE20__MODIFY(dst, src) \
3563                     (dst) = ((dst) &\
3564                     ~0x0000007fU) | ((u_int32_t)(src) &\
3565                     0x0000007fU)
3566 #define GREEN_TX_GAIN_TAB_20__GREEN_TG_TABLE20__VERIFY(src) \
3567                     (!(((u_int32_t)(src)\
3568                     & ~0x0000007fU)))
3569 #define GREEN_TX_GAIN_TAB_20__TYPE                                    u_int32_t
3570 #define GREEN_TX_GAIN_TAB_20__READ                                  0x0000007fU
3571 #define GREEN_TX_GAIN_TAB_20__WRITE                                 0x0000007fU
3572
3573 #endif /* __GREEN_TX_GAIN_TAB_20_MACRO__ */
3574
3575
3576 /* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_20 */
3577 #define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_20__NUM    1
3578
3579 /* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_21 */
3580 #ifndef __GREEN_TX_GAIN_TAB_21_MACRO__
3581 #define __GREEN_TX_GAIN_TAB_21_MACRO__
3582
3583 /* macros for field green_tg_table21 */
3584 #define GREEN_TX_GAIN_TAB_21__GREEN_TG_TABLE21__SHIFT                         0
3585 #define GREEN_TX_GAIN_TAB_21__GREEN_TG_TABLE21__WIDTH                         7
3586 #define GREEN_TX_GAIN_TAB_21__GREEN_TG_TABLE21__MASK                0x0000007fU
3587 #define GREEN_TX_GAIN_TAB_21__GREEN_TG_TABLE21__READ(src) \
3588                     (u_int32_t)(src)\
3589                     & 0x0000007fU
3590 #define GREEN_TX_GAIN_TAB_21__GREEN_TG_TABLE21__WRITE(src) \
3591                     ((u_int32_t)(src)\
3592                     & 0x0000007fU)
3593 #define GREEN_TX_GAIN_TAB_21__GREEN_TG_TABLE21__MODIFY(dst, src) \
3594                     (dst) = ((dst) &\
3595                     ~0x0000007fU) | ((u_int32_t)(src) &\
3596                     0x0000007fU)
3597 #define GREEN_TX_GAIN_TAB_21__GREEN_TG_TABLE21__VERIFY(src) \
3598                     (!(((u_int32_t)(src)\
3599                     & ~0x0000007fU)))
3600 #define GREEN_TX_GAIN_TAB_21__TYPE                                    u_int32_t
3601 #define GREEN_TX_GAIN_TAB_21__READ                                  0x0000007fU
3602 #define GREEN_TX_GAIN_TAB_21__WRITE                                 0x0000007fU
3603
3604 #endif /* __GREEN_TX_GAIN_TAB_21_MACRO__ */
3605
3606
3607 /* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_21 */
3608 #define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_21__NUM    1
3609
3610 /* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_22 */
3611 #ifndef __GREEN_TX_GAIN_TAB_22_MACRO__
3612 #define __GREEN_TX_GAIN_TAB_22_MACRO__
3613
3614 /* macros for field green_tg_table22 */
3615 #define GREEN_TX_GAIN_TAB_22__GREEN_TG_TABLE22__SHIFT                         0
3616 #define GREEN_TX_GAIN_TAB_22__GREEN_TG_TABLE22__WIDTH                         7
3617 #define GREEN_TX_GAIN_TAB_22__GREEN_TG_TABLE22__MASK                0x0000007fU
3618 #define GREEN_TX_GAIN_TAB_22__GREEN_TG_TABLE22__READ(src) \
3619                     (u_int32_t)(src)\
3620                     & 0x0000007fU
3621 #define GREEN_TX_GAIN_TAB_22__GREEN_TG_TABLE22__WRITE(src) \
3622                     ((u_int32_t)(src)\
3623                     & 0x0000007fU)
3624 #define GREEN_TX_GAIN_TAB_22__GREEN_TG_TABLE22__MODIFY(dst, src) \
3625                     (dst) = ((dst) &\
3626                     ~0x0000007fU) | ((u_int32_t)(src) &\
3627                     0x0000007fU)
3628 #define GREEN_TX_GAIN_TAB_22__GREEN_TG_TABLE22__VERIFY(src) \
3629                     (!(((u_int32_t)(src)\
3630                     & ~0x0000007fU)))
3631 #define GREEN_TX_GAIN_TAB_22__TYPE                                    u_int32_t
3632 #define GREEN_TX_GAIN_TAB_22__READ                                  0x0000007fU
3633 #define GREEN_TX_GAIN_TAB_22__WRITE                                 0x0000007fU
3634
3635 #endif /* __GREEN_TX_GAIN_TAB_22_MACRO__ */
3636
3637
3638 /* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_22 */
3639 #define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_22__NUM    1
3640
3641 /* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_23 */
3642 #ifndef __GREEN_TX_GAIN_TAB_23_MACRO__
3643 #define __GREEN_TX_GAIN_TAB_23_MACRO__
3644
3645 /* macros for field green_tg_table23 */
3646 #define GREEN_TX_GAIN_TAB_23__GREEN_TG_TABLE23__SHIFT                         0
3647 #define GREEN_TX_GAIN_TAB_23__GREEN_TG_TABLE23__WIDTH                         7
3648 #define GREEN_TX_GAIN_TAB_23__GREEN_TG_TABLE23__MASK                0x0000007fU
3649 #define GREEN_TX_GAIN_TAB_23__GREEN_TG_TABLE23__READ(src) \
3650                     (u_int32_t)(src)\
3651                     & 0x0000007fU
3652 #define GREEN_TX_GAIN_TAB_23__GREEN_TG_TABLE23__WRITE(src) \
3653                     ((u_int32_t)(src)\
3654                     & 0x0000007fU)
3655 #define GREEN_TX_GAIN_TAB_23__GREEN_TG_TABLE23__MODIFY(dst, src) \
3656                     (dst) = ((dst) &\
3657                     ~0x0000007fU) | ((u_int32_t)(src) &\
3658                     0x0000007fU)
3659 #define GREEN_TX_GAIN_TAB_23__GREEN_TG_TABLE23__VERIFY(src) \
3660                     (!(((u_int32_t)(src)\
3661                     & ~0x0000007fU)))
3662 #define GREEN_TX_GAIN_TAB_23__TYPE                                    u_int32_t
3663 #define GREEN_TX_GAIN_TAB_23__READ                                  0x0000007fU
3664 #define GREEN_TX_GAIN_TAB_23__WRITE                                 0x0000007fU
3665
3666 #endif /* __GREEN_TX_GAIN_TAB_23_MACRO__ */
3667
3668
3669 /* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_23 */
3670 #define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_23__NUM    1
3671
3672 /* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_24 */
3673 #ifndef __GREEN_TX_GAIN_TAB_24_MACRO__
3674 #define __GREEN_TX_GAIN_TAB_24_MACRO__
3675
3676 /* macros for field green_tg_table24 */
3677 #define GREEN_TX_GAIN_TAB_24__GREEN_TG_TABLE24__SHIFT                         0
3678 #define GREEN_TX_GAIN_TAB_24__GREEN_TG_TABLE24__WIDTH                         7
3679 #define GREEN_TX_GAIN_TAB_24__GREEN_TG_TABLE24__MASK                0x0000007fU
3680 #define GREEN_TX_GAIN_TAB_24__GREEN_TG_TABLE24__READ(src) \
3681                     (u_int32_t)(src)\
3682                     & 0x0000007fU
3683 #define GREEN_TX_GAIN_TAB_24__GREEN_TG_TABLE24__WRITE(src) \
3684                     ((u_int32_t)(src)\
3685                     & 0x0000007fU)
3686 #define GREEN_TX_GAIN_TAB_24__GREEN_TG_TABLE24__MODIFY(dst, src) \
3687                     (dst) = ((dst) &\
3688                     ~0x0000007fU) | ((u_int32_t)(src) &\
3689                     0x0000007fU)
3690 #define GREEN_TX_GAIN_TAB_24__GREEN_TG_TABLE24__VERIFY(src) \
3691                     (!(((u_int32_t)(src)\
3692                     & ~0x0000007fU)))
3693 #define GREEN_TX_GAIN_TAB_24__TYPE                                    u_int32_t
3694 #define GREEN_TX_GAIN_TAB_24__READ                                  0x0000007fU
3695 #define GREEN_TX_GAIN_TAB_24__WRITE                                 0x0000007fU
3696
3697 #endif /* __GREEN_TX_GAIN_TAB_24_MACRO__ */
3698
3699
3700 /* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_24 */
3701 #define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_24__NUM    1
3702
3703 /* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_25 */
3704 #ifndef __GREEN_TX_GAIN_TAB_25_MACRO__
3705 #define __GREEN_TX_GAIN_TAB_25_MACRO__
3706
3707 /* macros for field green_tg_table25 */
3708 #define GREEN_TX_GAIN_TAB_25__GREEN_TG_TABLE25__SHIFT                         0
3709 #define GREEN_TX_GAIN_TAB_25__GREEN_TG_TABLE25__WIDTH                         7
3710 #define GREEN_TX_GAIN_TAB_25__GREEN_TG_TABLE25__MASK                0x0000007fU
3711 #define GREEN_TX_GAIN_TAB_25__GREEN_TG_TABLE25__READ(src) \
3712                     (u_int32_t)(src)\
3713                     & 0x0000007fU
3714 #define GREEN_TX_GAIN_TAB_25__GREEN_TG_TABLE25__WRITE(src) \
3715                     ((u_int32_t)(src)\
3716                     & 0x0000007fU)
3717 #define GREEN_TX_GAIN_TAB_25__GREEN_TG_TABLE25__MODIFY(dst, src) \
3718                     (dst) = ((dst) &\
3719                     ~0x0000007fU) | ((u_int32_t)(src) &\
3720                     0x0000007fU)
3721 #define GREEN_TX_GAIN_TAB_25__GREEN_TG_TABLE25__VERIFY(src) \
3722                     (!(((u_int32_t)(src)\
3723                     & ~0x0000007fU)))
3724 #define GREEN_TX_GAIN_TAB_25__TYPE                                    u_int32_t
3725 #define GREEN_TX_GAIN_TAB_25__READ                                  0x0000007fU
3726 #define GREEN_TX_GAIN_TAB_25__WRITE                                 0x0000007fU
3727
3728 #endif /* __GREEN_TX_GAIN_TAB_25_MACRO__ */
3729
3730
3731 /* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_25 */
3732 #define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_25__NUM    1
3733
3734 /* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_26 */
3735 #ifndef __GREEN_TX_GAIN_TAB_26_MACRO__
3736 #define __GREEN_TX_GAIN_TAB_26_MACRO__
3737
3738 /* macros for field green_tg_table26 */
3739 #define GREEN_TX_GAIN_TAB_26__GREEN_TG_TABLE26__SHIFT                         0
3740 #define GREEN_TX_GAIN_TAB_26__GREEN_TG_TABLE26__WIDTH                         7
3741 #define GREEN_TX_GAIN_TAB_26__GREEN_TG_TABLE26__MASK                0x0000007fU
3742 #define GREEN_TX_GAIN_TAB_26__GREEN_TG_TABLE26__READ(src) \
3743                     (u_int32_t)(src)\
3744                     & 0x0000007fU
3745 #define GREEN_TX_GAIN_TAB_26__GREEN_TG_TABLE26__WRITE(src) \
3746                     ((u_int32_t)(src)\
3747                     & 0x0000007fU)
3748 #define GREEN_TX_GAIN_TAB_26__GREEN_TG_TABLE26__MODIFY(dst, src) \
3749                     (dst) = ((dst) &\
3750                     ~0x0000007fU) | ((u_int32_t)(src) &\
3751                     0x0000007fU)
3752 #define GREEN_TX_GAIN_TAB_26__GREEN_TG_TABLE26__VERIFY(src) \
3753                     (!(((u_int32_t)(src)\
3754                     & ~0x0000007fU)))
3755 #define GREEN_TX_GAIN_TAB_26__TYPE                                    u_int32_t
3756 #define GREEN_TX_GAIN_TAB_26__READ                                  0x0000007fU
3757 #define GREEN_TX_GAIN_TAB_26__WRITE                                 0x0000007fU
3758
3759 #endif /* __GREEN_TX_GAIN_TAB_26_MACRO__ */
3760
3761
3762 /* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_26 */
3763 #define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_26__NUM    1
3764
3765 /* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_27 */
3766 #ifndef __GREEN_TX_GAIN_TAB_27_MACRO__
3767 #define __GREEN_TX_GAIN_TAB_27_MACRO__
3768
3769 /* macros for field green_tg_table27 */
3770 #define GREEN_TX_GAIN_TAB_27__GREEN_TG_TABLE27__SHIFT                         0
3771 #define GREEN_TX_GAIN_TAB_27__GREEN_TG_TABLE27__WIDTH                         7
3772 #define GREEN_TX_GAIN_TAB_27__GREEN_TG_TABLE27__MASK                0x0000007fU
3773 #define GREEN_TX_GAIN_TAB_27__GREEN_TG_TABLE27__READ(src) \
3774                     (u_int32_t)(src)\
3775                     & 0x0000007fU
3776 #define GREEN_TX_GAIN_TAB_27__GREEN_TG_TABLE27__WRITE(src) \
3777                     ((u_int32_t)(src)\
3778                     & 0x0000007fU)
3779 #define GREEN_TX_GAIN_TAB_27__GREEN_TG_TABLE27__MODIFY(dst, src) \
3780                     (dst) = ((dst) &\
3781                     ~0x0000007fU) | ((u_int32_t)(src) &\
3782                     0x0000007fU)
3783 #define GREEN_TX_GAIN_TAB_27__GREEN_TG_TABLE27__VERIFY(src) \
3784                     (!(((u_int32_t)(src)\
3785                     & ~0x0000007fU)))
3786 #define GREEN_TX_GAIN_TAB_27__TYPE                                    u_int32_t
3787 #define GREEN_TX_GAIN_TAB_27__READ                                  0x0000007fU
3788 #define GREEN_TX_GAIN_TAB_27__WRITE                                 0x0000007fU
3789
3790 #endif /* __GREEN_TX_GAIN_TAB_27_MACRO__ */
3791
3792
3793 /* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_27 */
3794 #define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_27__NUM    1
3795
3796 /* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_28 */
3797 #ifndef __GREEN_TX_GAIN_TAB_28_MACRO__
3798 #define __GREEN_TX_GAIN_TAB_28_MACRO__
3799
3800 /* macros for field green_tg_table28 */
3801 #define GREEN_TX_GAIN_TAB_28__GREEN_TG_TABLE28__SHIFT                         0
3802 #define GREEN_TX_GAIN_TAB_28__GREEN_TG_TABLE28__WIDTH                         7
3803 #define GREEN_TX_GAIN_TAB_28__GREEN_TG_TABLE28__MASK                0x0000007fU
3804 #define GREEN_TX_GAIN_TAB_28__GREEN_TG_TABLE28__READ(src) \
3805                     (u_int32_t)(src)\
3806                     & 0x0000007fU
3807 #define GREEN_TX_GAIN_TAB_28__GREEN_TG_TABLE28__WRITE(src) \
3808                     ((u_int32_t)(src)\
3809                     & 0x0000007fU)
3810 #define GREEN_TX_GAIN_TAB_28__GREEN_TG_TABLE28__MODIFY(dst, src) \
3811                     (dst) = ((dst) &\
3812                     ~0x0000007fU) | ((u_int32_t)(src) &\
3813                     0x0000007fU)
3814 #define GREEN_TX_GAIN_TAB_28__GREEN_TG_TABLE28__VERIFY(src) \
3815                     (!(((u_int32_t)(src)\
3816                     & ~0x0000007fU)))
3817 #define GREEN_TX_GAIN_TAB_28__TYPE                                    u_int32_t
3818 #define GREEN_TX_GAIN_TAB_28__READ                                  0x0000007fU
3819 #define GREEN_TX_GAIN_TAB_28__WRITE                                 0x0000007fU
3820
3821 #endif /* __GREEN_TX_GAIN_TAB_28_MACRO__ */
3822
3823
3824 /* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_28 */
3825 #define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_28__NUM    1
3826
3827 /* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_29 */
3828 #ifndef __GREEN_TX_GAIN_TAB_29_MACRO__
3829 #define __GREEN_TX_GAIN_TAB_29_MACRO__
3830
3831 /* macros for field green_tg_table29 */
3832 #define GREEN_TX_GAIN_TAB_29__GREEN_TG_TABLE29__SHIFT                         0
3833 #define GREEN_TX_GAIN_TAB_29__GREEN_TG_TABLE29__WIDTH                         7
3834 #define GREEN_TX_GAIN_TAB_29__GREEN_TG_TABLE29__MASK                0x0000007fU
3835 #define GREEN_TX_GAIN_TAB_29__GREEN_TG_TABLE29__READ(src) \
3836                     (u_int32_t)(src)\
3837                     & 0x0000007fU
3838 #define GREEN_TX_GAIN_TAB_29__GREEN_TG_TABLE29__WRITE(src) \
3839                     ((u_int32_t)(src)\
3840                     & 0x0000007fU)
3841 #define GREEN_TX_GAIN_TAB_29__GREEN_TG_TABLE29__MODIFY(dst, src) \
3842                     (dst) = ((dst) &\
3843                     ~0x0000007fU) | ((u_int32_t)(src) &\
3844                     0x0000007fU)
3845 #define GREEN_TX_GAIN_TAB_29__GREEN_TG_TABLE29__VERIFY(src) \
3846                     (!(((u_int32_t)(src)\
3847                     & ~0x0000007fU)))
3848 #define GREEN_TX_GAIN_TAB_29__TYPE                                    u_int32_t
3849 #define GREEN_TX_GAIN_TAB_29__READ                                  0x0000007fU
3850 #define GREEN_TX_GAIN_TAB_29__WRITE                                 0x0000007fU
3851
3852 #endif /* __GREEN_TX_GAIN_TAB_29_MACRO__ */
3853
3854
3855 /* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_29 */
3856 #define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_29__NUM    1
3857
3858 /* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_30 */
3859 #ifndef __GREEN_TX_GAIN_TAB_30_MACRO__
3860 #define __GREEN_TX_GAIN_TAB_30_MACRO__
3861
3862 /* macros for field green_tg_table30 */
3863 #define GREEN_TX_GAIN_TAB_30__GREEN_TG_TABLE30__SHIFT                         0
3864 #define GREEN_TX_GAIN_TAB_30__GREEN_TG_TABLE30__WIDTH                         7
3865 #define GREEN_TX_GAIN_TAB_30__GREEN_TG_TABLE30__MASK                0x0000007fU
3866 #define GREEN_TX_GAIN_TAB_30__GREEN_TG_TABLE30__READ(src) \
3867                     (u_int32_t)(src)\
3868                     & 0x0000007fU
3869 #define GREEN_TX_GAIN_TAB_30__GREEN_TG_TABLE30__WRITE(src) \
3870                     ((u_int32_t)(src)\
3871                     & 0x0000007fU)
3872 #define GREEN_TX_GAIN_TAB_30__GREEN_TG_TABLE30__MODIFY(dst, src) \
3873                     (dst) = ((dst) &\
3874                     ~0x0000007fU) | ((u_int32_t)(src) &\
3875                     0x0000007fU)
3876 #define GREEN_TX_GAIN_TAB_30__GREEN_TG_TABLE30__VERIFY(src) \
3877                     (!(((u_int32_t)(src)\
3878                     & ~0x0000007fU)))
3879 #define GREEN_TX_GAIN_TAB_30__TYPE                                    u_int32_t
3880 #define GREEN_TX_GAIN_TAB_30__READ                                  0x0000007fU
3881 #define GREEN_TX_GAIN_TAB_30__WRITE                                 0x0000007fU
3882
3883 #endif /* __GREEN_TX_GAIN_TAB_30_MACRO__ */
3884
3885
3886 /* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_30 */
3887 #define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_30__NUM    1
3888
3889 /* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_31 */
3890 #ifndef __GREEN_TX_GAIN_TAB_31_MACRO__
3891 #define __GREEN_TX_GAIN_TAB_31_MACRO__
3892
3893 /* macros for field green_tg_table31 */
3894 #define GREEN_TX_GAIN_TAB_31__GREEN_TG_TABLE31__SHIFT                         0
3895 #define GREEN_TX_GAIN_TAB_31__GREEN_TG_TABLE31__WIDTH                         7
3896 #define GREEN_TX_GAIN_TAB_31__GREEN_TG_TABLE31__MASK                0x0000007fU
3897 #define GREEN_TX_GAIN_TAB_31__GREEN_TG_TABLE31__READ(src) \
3898                     (u_int32_t)(src)\
3899                     & 0x0000007fU
3900 #define GREEN_TX_GAIN_TAB_31__GREEN_TG_TABLE31__WRITE(src) \
3901                     ((u_int32_t)(src)\
3902                     & 0x0000007fU)
3903 #define GREEN_TX_GAIN_TAB_31__GREEN_TG_TABLE31__MODIFY(dst, src) \
3904                     (dst) = ((dst) &\
3905                     ~0x0000007fU) | ((u_int32_t)(src) &\
3906                     0x0000007fU)
3907 #define GREEN_TX_GAIN_TAB_31__GREEN_TG_TABLE31__VERIFY(src) \
3908                     (!(((u_int32_t)(src)\
3909                     & ~0x0000007fU)))
3910 #define GREEN_TX_GAIN_TAB_31__TYPE                                    u_int32_t
3911 #define GREEN_TX_GAIN_TAB_31__READ                                  0x0000007fU
3912 #define GREEN_TX_GAIN_TAB_31__WRITE                                 0x0000007fU
3913
3914 #endif /* __GREEN_TX_GAIN_TAB_31_MACRO__ */
3915
3916
3917 /* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_31 */
3918 #define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_31__NUM    1
3919
3920 /* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_32 */
3921 #ifndef __GREEN_TX_GAIN_TAB_32_MACRO__
3922 #define __GREEN_TX_GAIN_TAB_32_MACRO__
3923
3924 /* macros for field green_tg_table32 */
3925 #define GREEN_TX_GAIN_TAB_32__GREEN_TG_TABLE32__SHIFT                         0
3926 #define GREEN_TX_GAIN_TAB_32__GREEN_TG_TABLE32__WIDTH                         7
3927 #define GREEN_TX_GAIN_TAB_32__GREEN_TG_TABLE32__MASK                0x0000007fU
3928 #define GREEN_TX_GAIN_TAB_32__GREEN_TG_TABLE32__READ(src) \
3929                     (u_int32_t)(src)\
3930                     & 0x0000007fU
3931 #define GREEN_TX_GAIN_TAB_32__GREEN_TG_TABLE32__WRITE(src) \
3932                     ((u_int32_t)(src)\
3933                     & 0x0000007fU)
3934 #define GREEN_TX_GAIN_TAB_32__GREEN_TG_TABLE32__MODIFY(dst, src) \
3935                     (dst) = ((dst) &\
3936                     ~0x0000007fU) | ((u_int32_t)(src) &\
3937                     0x0000007fU)
3938 #define GREEN_TX_GAIN_TAB_32__GREEN_TG_TABLE32__VERIFY(src) \
3939                     (!(((u_int32_t)(src)\
3940                     & ~0x0000007fU)))
3941 #define GREEN_TX_GAIN_TAB_32__TYPE                                    u_int32_t
3942 #define GREEN_TX_GAIN_TAB_32__READ                                  0x0000007fU
3943 #define GREEN_TX_GAIN_TAB_32__WRITE                                 0x0000007fU
3944
3945 #endif /* __GREEN_TX_GAIN_TAB_32_MACRO__ */
3946
3947
3948 /* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_32 */
3949 #define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_32__NUM    1
3950
3951
3952 /* macros for BlueprintGlobalNameSpace::PMU1 */
3953 #ifndef __PMU1_MACRO__
3954 #define __PMU1_MACRO__
3955
3956 /* macros for field pwd */
3957 #define PMU1__PWD__SHIFT                                                      0
3958 #define PMU1__PWD__WIDTH                                                      3
3959 #define PMU1__PWD__MASK                                             0x00000007U
3960 #define PMU1__PWD__READ(src)                     (u_int32_t)(src) & 0x00000007U
3961 #define PMU1__PWD__WRITE(src)                  ((u_int32_t)(src) & 0x00000007U)
3962 #define PMU1__PWD__MODIFY(dst, src) \
3963                     (dst) = ((dst) &\
3964                     ~0x00000007U) | ((u_int32_t)(src) &\
3965                     0x00000007U)
3966 #define PMU1__PWD__VERIFY(src)           (!(((u_int32_t)(src) & ~0x00000007U)))
3967
3968 /* macros for field Nfdiv */
3969 #define PMU1__NFDIV__SHIFT                                                    3
3970 #define PMU1__NFDIV__WIDTH                                                    1
3971 #define PMU1__NFDIV__MASK                                           0x00000008U
3972 #define PMU1__NFDIV__READ(src)          (((u_int32_t)(src) & 0x00000008U) >> 3)
3973 #define PMU1__NFDIV__WRITE(src)         (((u_int32_t)(src) << 3) & 0x00000008U)
3974 #define PMU1__NFDIV__MODIFY(dst, src) \
3975                     (dst) = ((dst) &\
3976                     ~0x00000008U) | (((u_int32_t)(src) <<\
3977                     3) & 0x00000008U)
3978 #define PMU1__NFDIV__VERIFY(src)  (!((((u_int32_t)(src) << 3) & ~0x00000008U)))
3979 #define PMU1__NFDIV__SET(dst) \
3980                     (dst) = ((dst) &\
3981                     ~0x00000008U) | ((u_int32_t)(1) << 3)
3982 #define PMU1__NFDIV__CLR(dst) \
3983                     (dst) = ((dst) &\
3984                     ~0x00000008U) | ((u_int32_t)(0) << 3)
3985
3986 /* macros for field Refv */
3987 #define PMU1__REFV__SHIFT                                                     4
3988 #define PMU1__REFV__WIDTH                                                     4
3989 #define PMU1__REFV__MASK                                            0x000000f0U
3990 #define PMU1__REFV__READ(src)           (((u_int32_t)(src) & 0x000000f0U) >> 4)
3991 #define PMU1__REFV__WRITE(src)          (((u_int32_t)(src) << 4) & 0x000000f0U)
3992 #define PMU1__REFV__MODIFY(dst, src) \
3993                     (dst) = ((dst) &\
3994                     ~0x000000f0U) | (((u_int32_t)(src) <<\
3995                     4) & 0x000000f0U)
3996 #define PMU1__REFV__VERIFY(src)   (!((((u_int32_t)(src) << 4) & ~0x000000f0U)))
3997
3998 /* macros for field Gm1 */
3999 #define PMU1__GM1__SHIFT                                                      8
4000 #define PMU1__GM1__WIDTH                                                      3
4001 #define PMU1__GM1__MASK                                             0x00000700U
4002 #define PMU1__GM1__READ(src)            (((u_int32_t)(src) & 0x00000700U) >> 8)
4003 #define PMU1__GM1__WRITE(src)           (((u_int32_t)(src) << 8) & 0x00000700U)
4004 #define PMU1__GM1__MODIFY(dst, src) \
4005                     (dst) = ((dst) &\
4006                     ~0x00000700U) | (((u_int32_t)(src) <<\
4007                     8) & 0x00000700U)
4008 #define PMU1__GM1__VERIFY(src)    (!((((u_int32_t)(src) << 8) & ~0x00000700U)))
4009
4010 /* macros for field Classb */
4011 #define PMU1__CLASSB__SHIFT                                                  11
4012 #define PMU1__CLASSB__WIDTH                                                   3
4013 #define PMU1__CLASSB__MASK                                          0x00003800U
4014 #define PMU1__CLASSB__READ(src)        (((u_int32_t)(src) & 0x00003800U) >> 11)
4015 #define PMU1__CLASSB__WRITE(src)       (((u_int32_t)(src) << 11) & 0x00003800U)
4016 #define PMU1__CLASSB__MODIFY(dst, src) \
4017                     (dst) = ((dst) &\
4018                     ~0x00003800U) | (((u_int32_t)(src) <<\
4019                     11) & 0x00003800U)
4020 #define PMU1__CLASSB__VERIFY(src) \
4021                     (!((((u_int32_t)(src)\
4022                     << 11) & ~0x00003800U)))
4023
4024 /* macros for field Cc */
4025 #define PMU1__CC__SHIFT                                                      14
4026 #define PMU1__CC__WIDTH                                                       3
4027 #define PMU1__CC__MASK                                              0x0001c000U
4028 #define PMU1__CC__READ(src)            (((u_int32_t)(src) & 0x0001c000U) >> 14)
4029 #define PMU1__CC__WRITE(src)           (((u_int32_t)(src) << 14) & 0x0001c000U)
4030 #define PMU1__CC__MODIFY(dst, src) \
4031                     (dst) = ((dst) &\
4032                     ~0x0001c000U) | (((u_int32_t)(src) <<\
4033                     14) & 0x0001c000U)
4034 #define PMU1__CC__VERIFY(src)    (!((((u_int32_t)(src) << 14) & ~0x0001c000U)))
4035
4036 /* macros for field Rc */
4037 #define PMU1__RC__SHIFT                                                      17
4038 #define PMU1__RC__WIDTH                                                       3
4039 #define PMU1__RC__MASK                                              0x000e0000U
4040 #define PMU1__RC__READ(src)            (((u_int32_t)(src) & 0x000e0000U) >> 17)
4041 #define PMU1__RC__WRITE(src)           (((u_int32_t)(src) << 17) & 0x000e0000U)
4042 #define PMU1__RC__MODIFY(dst, src) \
4043                     (dst) = ((dst) &\
4044                     ~0x000e0000U) | (((u_int32_t)(src) <<\
4045                     17) & 0x000e0000U)
4046 #define PMU1__RC__VERIFY(src)    (!((((u_int32_t)(src) << 17) & ~0x000e0000U)))
4047
4048 /* macros for field Rampslope */
4049 #define PMU1__RAMPSLOPE__SHIFT                                               20
4050 #define PMU1__RAMPSLOPE__WIDTH                                                4
4051 #define PMU1__RAMPSLOPE__MASK                                       0x00f00000U
4052 #define PMU1__RAMPSLOPE__READ(src)     (((u_int32_t)(src) & 0x00f00000U) >> 20)
4053 #define PMU1__RAMPSLOPE__WRITE(src)    (((u_int32_t)(src) << 20) & 0x00f00000U)
4054 #define PMU1__RAMPSLOPE__MODIFY(dst, src) \
4055                     (dst) = ((dst) &\
4056                     ~0x00f00000U) | (((u_int32_t)(src) <<\
4057                     20) & 0x00f00000U)
4058 #define PMU1__RAMPSLOPE__VERIFY(src) \
4059                     (!((((u_int32_t)(src)\
4060                     << 20) & ~0x00f00000U)))
4061
4062 /* macros for field Segm */
4063 #define PMU1__SEGM__SHIFT                                                    24
4064 #define PMU1__SEGM__WIDTH                                                     2
4065 #define PMU1__SEGM__MASK                                            0x03000000U
4066 #define PMU1__SEGM__READ(src)          (((u_int32_t)(src) & 0x03000000U) >> 24)
4067 #define PMU1__SEGM__WRITE(src)         (((u_int32_t)(src) << 24) & 0x03000000U)
4068 #define PMU1__SEGM__MODIFY(dst, src) \
4069                     (dst) = ((dst) &\
4070                     ~0x03000000U) | (((u_int32_t)(src) <<\
4071                     24) & 0x03000000U)
4072 #define PMU1__SEGM__VERIFY(src)  (!((((u_int32_t)(src) << 24) & ~0x03000000U)))
4073
4074 /* macros for field UseLocalOsc */
4075 #define PMU1__USELOCALOSC__SHIFT                                             26
4076 #define PMU1__USELOCALOSC__WIDTH                                              1
4077 #define PMU1__USELOCALOSC__MASK                                     0x04000000U
4078 #define PMU1__USELOCALOSC__READ(src)   (((u_int32_t)(src) & 0x04000000U) >> 26)
4079 #define PMU1__USELOCALOSC__WRITE(src)  (((u_int32_t)(src) << 26) & 0x04000000U)
4080 #define PMU1__USELOCALOSC__MODIFY(dst, src) \
4081                     (dst) = ((dst) &\
4082                     ~0x04000000U) | (((u_int32_t)(src) <<\
4083                     26) & 0x04000000U)
4084 #define PMU1__USELOCALOSC__VERIFY(src) \
4085                     (!((((u_int32_t)(src)\
4086                     << 26) & ~0x04000000U)))
4087 #define PMU1__USELOCALOSC__SET(dst) \
4088                     (dst) = ((dst) &\
4089                     ~0x04000000U) | ((u_int32_t)(1) << 26)
4090 #define PMU1__USELOCALOSC__CLR(dst) \
4091                     (dst) = ((dst) &\
4092                     ~0x04000000U) | ((u_int32_t)(0) << 26)
4093
4094 /* macros for field ForceXoscStable */
4095 #define PMU1__FORCEXOSCSTABLE__SHIFT                                         27
4096 #define PMU1__FORCEXOSCSTABLE__WIDTH                                          1
4097 #define PMU1__FORCEXOSCSTABLE__MASK                                 0x08000000U
4098 #define PMU1__FORCEXOSCSTABLE__READ(src) \
4099                     (((u_int32_t)(src)\
4100                     & 0x08000000U) >> 27)
4101 #define PMU1__FORCEXOSCSTABLE__WRITE(src) \
4102                     (((u_int32_t)(src)\
4103                     << 27) & 0x08000000U)
4104 #define PMU1__FORCEXOSCSTABLE__MODIFY(dst, src) \
4105                     (dst) = ((dst) &\
4106                     ~0x08000000U) | (((u_int32_t)(src) <<\
4107                     27) & 0x08000000U)
4108 #define PMU1__FORCEXOSCSTABLE__VERIFY(src) \
4109                     (!((((u_int32_t)(src)\
4110                     << 27) & ~0x08000000U)))
4111 #define PMU1__FORCEXOSCSTABLE__SET(dst) \
4112                     (dst) = ((dst) &\
4113                     ~0x08000000U) | ((u_int32_t)(1) << 27)
4114 #define PMU1__FORCEXOSCSTABLE__CLR(dst) \
4115                     (dst) = ((dst) &\
4116                     ~0x08000000U) | ((u_int32_t)(0) << 27)
4117
4118 /* macros for field SelFb */
4119 #define PMU1__SELFB__SHIFT                                                   28
4120 #define PMU1__SELFB__WIDTH                                                    1
4121 #define PMU1__SELFB__MASK                                           0x10000000U
4122 #define PMU1__SELFB__READ(src)         (((u_int32_t)(src) & 0x10000000U) >> 28)
4123 #define PMU1__SELFB__WRITE(src)        (((u_int32_t)(src) << 28) & 0x10000000U)
4124 #define PMU1__SELFB__MODIFY(dst, src) \
4125                     (dst) = ((dst) &\
4126                     ~0x10000000U) | (((u_int32_t)(src) <<\
4127                     28) & 0x10000000U)
4128 #define PMU1__SELFB__VERIFY(src) (!((((u_int32_t)(src) << 28) & ~0x10000000U)))
4129 #define PMU1__SELFB__SET(dst) \
4130                     (dst) = ((dst) &\
4131                     ~0x10000000U) | ((u_int32_t)(1) << 28)
4132 #define PMU1__SELFB__CLR(dst) \
4133                     (dst) = ((dst) &\
4134                     ~0x10000000U) | ((u_int32_t)(0) << 28)
4135
4136 /* macros for field FilterFb */
4137 #define PMU1__FILTERFB__SHIFT                                                29
4138 #define PMU1__FILTERFB__WIDTH                                                 3
4139 #define PMU1__FILTERFB__MASK                                        0xe0000000U
4140 #define PMU1__FILTERFB__READ(src)      (((u_int32_t)(src) & 0xe0000000U) >> 29)
4141 #define PMU1__FILTERFB__WRITE(src)     (((u_int32_t)(src) << 29) & 0xe0000000U)
4142 #define PMU1__FILTERFB__MODIFY(dst, src) \
4143                     (dst) = ((dst) &\
4144                     ~0xe0000000U) | (((u_int32_t)(src) <<\
4145                     29) & 0xe0000000U)
4146 #define PMU1__FILTERFB__VERIFY(src) \
4147                     (!((((u_int32_t)(src)\
4148                     << 29) & ~0xe0000000U)))
4149 #define PMU1__TYPE                                                    u_int32_t
4150 #define PMU1__READ                                                  0xffffffffU
4151 #define PMU1__WRITE                                                 0xffffffffU
4152
4153 #endif /* __PMU1_MACRO__ */
4154
4155
4156 /* macros for radio65_reg_block.ch0_PMU1 */
4157 #define INST_RADIO65_REG_BLOCK__CH0_PMU1__NUM                                 1
4158
4159 /* macros for BlueprintGlobalNameSpace::PMU2 */
4160 #ifndef __PMU2_MACRO__
4161 #define __PMU2_MACRO__
4162
4163 /* macros for field SPARE2 */
4164 #define PMU2__SPARE2__SHIFT                                                   0
4165 #define PMU2__SPARE2__WIDTH                                                  19
4166 #define PMU2__SPARE2__MASK                                          0x0007ffffU
4167 #define PMU2__SPARE2__READ(src)                  (u_int32_t)(src) & 0x0007ffffU
4168 #define PMU2__SPARE2__WRITE(src)               ((u_int32_t)(src) & 0x0007ffffU)
4169 #define PMU2__SPARE2__MODIFY(dst, src) \
4170                     (dst) = ((dst) &\
4171                     ~0x0007ffffU) | ((u_int32_t)(src) &\
4172                     0x0007ffffU)
4173 #define PMU2__SPARE2__VERIFY(src)        (!(((u_int32_t)(src) & ~0x0007ffffU)))
4174
4175 /* macros for field pwdlpo_pwd */
4176 #define PMU2__PWDLPO_PWD__SHIFT                                              19
4177 #define PMU2__PWDLPO_PWD__WIDTH                                               1
4178 #define PMU2__PWDLPO_PWD__MASK                                      0x00080000U
4179 #define PMU2__PWDLPO_PWD__READ(src)    (((u_int32_t)(src) & 0x00080000U) >> 19)
4180 #define PMU2__PWDLPO_PWD__WRITE(src)   (((u_int32_t)(src) << 19) & 0x00080000U)
4181 #define PMU2__PWDLPO_PWD__MODIFY(dst, src) \
4182                     (dst) = ((dst) &\
4183                     ~0x00080000U) | (((u_int32_t)(src) <<\
4184                     19) & 0x00080000U)
4185 #define PMU2__PWDLPO_PWD__VERIFY(src) \
4186                     (!((((u_int32_t)(src)\
4187                     << 19) & ~0x00080000U)))
4188 #define PMU2__PWDLPO_PWD__SET(dst) \
4189                     (dst) = ((dst) &\
4190                     ~0x00080000U) | ((u_int32_t)(1) << 19)
4191 #define PMU2__PWDLPO_PWD__CLR(dst) \
4192                     (dst) = ((dst) &\
4193                     ~0x00080000U) | ((u_int32_t)(0) << 19)
4194
4195 /* macros for field disc_ovr */
4196 #define PMU2__DISC_OVR__SHIFT                                                20
4197 #define PMU2__DISC_OVR__WIDTH                                                 1
4198 #define PMU2__DISC_OVR__MASK                                        0x00100000U
4199 #define PMU2__DISC_OVR__READ(src)      (((u_int32_t)(src) & 0x00100000U) >> 20)
4200 #define PMU2__DISC_OVR__WRITE(src)     (((u_int32_t)(src) << 20) & 0x00100000U)
4201 #define PMU2__DISC_OVR__MODIFY(dst, src) \
4202                     (dst) = ((dst) &\
4203                     ~0x00100000U) | (((u_int32_t)(src) <<\
4204                     20) & 0x00100000U)
4205 #define PMU2__DISC_OVR__VERIFY(src) \
4206                     (!((((u_int32_t)(src)\
4207                     << 20) & ~0x00100000U)))
4208 #define PMU2__DISC_OVR__SET(dst) \
4209                     (dst) = ((dst) &\
4210                     ~0x00100000U) | ((u_int32_t)(1) << 20)
4211 #define PMU2__DISC_OVR__CLR(dst) \
4212                     (dst) = ((dst) &\
4213                     ~0x00100000U) | ((u_int32_t)(0) << 20)
4214
4215 /* macros for field pgm */
4216 #define PMU2__PGM__SHIFT                                                     21
4217 #define PMU2__PGM__WIDTH                                                      1
4218 #define PMU2__PGM__MASK                                             0x00200000U
4219 #define PMU2__PGM__READ(src)           (((u_int32_t)(src) & 0x00200000U) >> 21)
4220 #define PMU2__PGM__WRITE(src)          (((u_int32_t)(src) << 21) & 0x00200000U)
4221 #define PMU2__PGM__MODIFY(dst, src) \
4222                     (dst) = ((dst) &\
4223                     ~0x00200000U) | (((u_int32_t)(src) <<\
4224                     21) & 0x00200000U)
4225 #define PMU2__PGM__VERIFY(src)   (!((((u_int32_t)(src) << 21) & ~0x00200000U)))
4226 #define PMU2__PGM__SET(dst) \
4227                     (dst) = ((dst) &\
4228                     ~0x00200000U) | ((u_int32_t)(1) << 21)
4229 #define PMU2__PGM__CLR(dst) \
4230                     (dst) = ((dst) &\
4231                     ~0x00200000U) | ((u_int32_t)(0) << 21)
4232
4233 /* macros for field FilterVc */
4234 #define PMU2__FILTERVC__SHIFT                                                22
4235 #define PMU2__FILTERVC__WIDTH                                                 3
4236 #define PMU2__FILTERVC__MASK                                        0x01c00000U
4237 #define PMU2__FILTERVC__READ(src)      (((u_int32_t)(src) & 0x01c00000U) >> 22)
4238 #define PMU2__FILTERVC__WRITE(src)     (((u_int32_t)(src) << 22) & 0x01c00000U)
4239 #define PMU2__FILTERVC__MODIFY(dst, src) \
4240                     (dst) = ((dst) &\
4241                     ~0x01c00000U) | (((u_int32_t)(src) <<\
4242                     22) & 0x01c00000U)
4243 #define PMU2__FILTERVC__VERIFY(src) \
4244                     (!((((u_int32_t)(src)\
4245                     << 22) & ~0x01c00000U)))
4246
4247 /* macros for field Disc */
4248 #define PMU2__DISC__SHIFT                                                    25
4249 #define PMU2__DISC__WIDTH                                                     1
4250 #define PMU2__DISC__MASK                                            0x02000000U
4251 #define PMU2__DISC__READ(src)          (((u_int32_t)(src) & 0x02000000U) >> 25)
4252 #define PMU2__DISC__WRITE(src)         (((u_int32_t)(src) << 25) & 0x02000000U)
4253 #define PMU2__DISC__MODIFY(dst, src) \
4254                     (dst) = ((dst) &\
4255                     ~0x02000000U) | (((u_int32_t)(src) <<\
4256                     25) & 0x02000000U)
4257 #define PMU2__DISC__VERIFY(src)  (!((((u_int32_t)(src) << 25) & ~0x02000000U)))
4258 #define PMU2__DISC__SET(dst) \
4259                     (dst) = ((dst) &\
4260                     ~0x02000000U) | ((u_int32_t)(1) << 25)
4261 #define PMU2__DISC__CLR(dst) \
4262                     (dst) = ((dst) &\
4263                     ~0x02000000U) | ((u_int32_t)(0) << 25)
4264
4265 /* macros for field DiscDel */
4266 #define PMU2__DISCDEL__SHIFT                                                 26
4267 #define PMU2__DISCDEL__WIDTH                                                  3
4268 #define PMU2__DISCDEL__MASK                                         0x1c000000U
4269 #define PMU2__DISCDEL__READ(src)       (((u_int32_t)(src) & 0x1c000000U) >> 26)
4270 #define PMU2__DISCDEL__WRITE(src)      (((u_int32_t)(src) << 26) & 0x1c000000U)
4271 #define PMU2__DISCDEL__MODIFY(dst, src) \
4272                     (dst) = ((dst) &\
4273                     ~0x1c000000U) | (((u_int32_t)(src) <<\
4274                     26) & 0x1c000000U)
4275 #define PMU2__DISCDEL__VERIFY(src) \
4276                     (!((((u_int32_t)(src)\
4277                     << 26) & ~0x1c000000U)))
4278
4279 /* macros for field SPARE1 */
4280 #define PMU2__SPARE1__SHIFT                                                  29
4281 #define PMU2__SPARE1__WIDTH                                                   3
4282 #define PMU2__SPARE1__MASK                                          0xe0000000U
4283 #define PMU2__SPARE1__READ(src)        (((u_int32_t)(src) & 0xe0000000U) >> 29)
4284 #define PMU2__SPARE1__WRITE(src)       (((u_int32_t)(src) << 29) & 0xe0000000U)
4285 #define PMU2__SPARE1__MODIFY(dst, src) \
4286                     (dst) = ((dst) &\
4287                     ~0xe0000000U) | (((u_int32_t)(src) <<\
4288                     29) & 0xe0000000U)
4289 #define PMU2__SPARE1__VERIFY(src) \
4290                     (!((((u_int32_t)(src)\
4291                     << 29) & ~0xe0000000U)))
4292 #define PMU2__TYPE                                                    u_int32_t
4293 #define PMU2__READ                                                  0xffffffffU
4294 #define PMU2__WRITE                                                 0xffffffffU
4295
4296 #endif /* __PMU2_MACRO__ */
4297
4298
4299 /* macros for radio65_reg_block.ch0_PMU2 */
4300 #define INST_RADIO65_REG_BLOCK__CH0_PMU2__NUM                                 1
4301
4302 #define POSEIDON_REG_MAP__VERSION \
4303                     "/cad/local/lib/perl/Pinfo.pm\n\
4304                     /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/analog_intf_reg_sysconfig.rdl\n\
4305                     /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/bb_reg_map_sysconfig.rdl\n\
4306                     /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/efuse_reg_sysconfig.rdl\n\
4307                     /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/mac_dcu_reg_sysconfig.rdl\n\
4308                     /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/mac_dma_reg_sysconfig.rdl\n\
4309                     /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/mac_pcu_reg_sysconfig.rdl\n\
4310                     /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/mac_qcu_reg_sysconfig.rdl\n\
4311                     /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/merlin2_0_radio_reg_sysconfig.rdl\n\
4312                     /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/pcie_phy_reg_csr_sysconfig.rdl\n\
4313                     /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/radio_65_reg_sysconfig.rdl\n\
4314                     /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/rtc_reg_sysconfig.rdl\n\
4315                     /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/rtc_sync_reg_sysconfig.rdl\n\
4316                     /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/svd_reg_sysconfig.rdl\n\
4317                     /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/top/emulation_misc.rdl\n\
4318                     /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/top/merlin2_0_radio_reg_map.rdl\n\
4319                     /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/top/pcie_phy_reg_csr.rdl\n\
4320                     /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/top/poseidon_radio_reg.rdl\n\
4321                     /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/top/poseidon_reg.rdl\n\
4322                     /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/env/blueprint/ath_ansic.pm\n\
4323                     /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/amba_mac/blueprint/rtc_sync_reg.rdl\n\
4324                     /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/amba_mac/svd/blueprint/svd_reg.rdl\n\
4325                     /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/apb_analog/analog_intf_reg.rdl\n\
4326                     /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/bb/blueprint/bb_reg_map.rdl\n\
4327                     /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/host_intf/rtl/blueprint/efuse_reg.rdl\n\
4328                     /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/host_intf/rtl/blueprint/host_intf_reg.rdl\n\
4329                     /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/mac/rtl/mac_dma/blueprint/mac_dcu_reg.rdl\n\
4330                     /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/mac/rtl/mac_dma/blueprint/mac_dma_reg.rdl\n\
4331                     /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/mac/rtl/mac_dma/blueprint/mac_qcu_reg.rdl\n\
4332                     /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/mac/rtl/mac_pcu/blueprint/mac_pcu_reg.rdl\n\
4333                     /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/rtc/blueprint/rtc_reg.rdl"
4334 #endif /* __REG_POSEIDON_REG_MAP_MACRO_H__ */