sys/contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map.h

   1 /*
   2  * Copyright (c) 2013 Qualcomm Atheros, Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
   9  * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
  10  * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
  11  * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
  12  * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
  13  * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  14  * PERFORMANCE OF THIS SOFTWARE.
  15  */
  16 /*                                                                           */
  17 /* File:       /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top/scorpion_reg_map.h*/
  18 /* Creator:    irshad                                                        */
  19 /* Time:       Wednesday Feb 15, 2012 [5:06:37 pm]                           */
  20 /*                                                                           */
  21 /* Path:       /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top*/
  22 /* Arguments:  /cad/denali/blueprint/3.7.3//Linux-64bit/blueprint -dump      */
  23 /*             -codegen                                                      */
  24 /*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/flow/blueprint/ath_ansic.codegen*/
  25 /*             -ath_ansic -Wdesc -I                                          */
  26 /*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top*/
  27 /*             -I /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint */
  28 /*             -I                                                            */
  29 /*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/flow/blueprint*/
  30 /*             -I                                                            */
  31 /*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig*/
  32 /*             -odir                                                         */
  33 /*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top*/
  34 /*             -eval {$INCLUDE_SYSCONFIG_FILES=1} -eval                      */
  35 /*             $WAR_EV58615_for_ansic_codegen=1 scorpion_reg.rdl             */
  36 /*                                                                           */
  37 /* Sources:    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/mac_dcu_reg_sysconfig.rdl*/
  38 /*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/rtc/rtc_reg.rdl*/
  39 /*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/mac/rtl/mac_dma/blueprint/mac_dma_reg.rdl*/
  40 /*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/rtc_reg_sysconfig.rdl*/
  41 /*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/mac_pcu_reg_sysconfig.rdl*/
  42 /*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/mac/rtl/mac_dma/blueprint/mac_dcu_reg.rdl*/
  43 /*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/mac/rtl/mac_pcu/blueprint/mac_pcu_reg.rdl*/
  44 /*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/wmac_wrap/rtc_sync_reg.rdl*/
  45 /*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/mac/rtl/mac_dma/blueprint/mac_qcu_reg.rdl*/
  46 /*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/mac_dma_reg_sysconfig.rdl*/
  47 /*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top/scorpion_reg.rdl*/
  48 /*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/bb_reg_map_sysconfig.rdl*/
  49 /*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top/scorpion_radio_reg.rdl*/
  50 /*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/svd_reg_sysconfig.rdl*/
  51 /*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/radio_65_reg_sysconfig.rdl*/
  52 /*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/bb/blueprint/bb_reg_map.rdl*/
  53 /*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/rtc_sync_reg_sysconfig.rdl*/
  54 /*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/svd/svd_reg.rdl*/
  55 /*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/mac_qcu_reg_sysconfig.rdl*/
  56 /*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/flow/blueprint/ath_ansic.pm*/
  57 /*             /cad/local/lib/perl/Pinfo.pm                                  */
  58 /*                                                                           */
  59 /* Blueprint:   3.7.3 (Fri Aug 29 12:39:16 PDT 2008)                         */
  60 /* Machine:    rupavathi.users.atheros.com                                   */
  61 /* OS:         Linux 2.6.9-89.ELsmp                                          */
  62 /* Description:                                                              */
  63 /*                                                                           */
  64 /*This Register Map contains the complete register set for scorpion.         */
  65 /*                                                                           */
  66 /* Copyright (C) 2012 Denali Software Inc.  All rights reserved              */
  67 /* THIS FILE IS AUTOMATICALLY GENERATED BY DENALI BLUEPRINT, DO NOT EDIT     */
  68 /*                                                                           */
  69
  70
  71 #ifndef __REG_SCORPION_REG_MAP_H__
  72 #define __REG_SCORPION_REG_MAP_H__
  73
  74 #include "scorpion_reg_map_macro.h"
  75
  76 struct mac_dma_reg {
  77   volatile char pad__0[0x8];                      /*        0x0 - 0x8        */
  78   volatile u_int32_t MAC_DMA_CR;                  /*        0x8 - 0xc        */
  79   volatile char pad__1[0x8];                      /*        0xc - 0x14       */
  80   volatile u_int32_t MAC_DMA_CFG;                 /*       0x14 - 0x18       */
  81   volatile u_int32_t MAC_DMA_RXBUFPTR_THRESH;     /*       0x18 - 0x1c       */
  82   volatile u_int32_t MAC_DMA_TXDPPTR_THRESH;      /*       0x1c - 0x20       */
  83   volatile u_int32_t MAC_DMA_MIRT;                /*       0x20 - 0x24       */
  84   volatile u_int32_t MAC_DMA_GLOBAL_IER;          /*       0x24 - 0x28       */
  85   volatile u_int32_t MAC_DMA_TIMT;                /*       0x28 - 0x2c       */
  86   volatile u_int32_t MAC_DMA_RIMT;                /*       0x2c - 0x30       */
  87   volatile u_int32_t MAC_DMA_TXCFG;               /*       0x30 - 0x34       */
  88   volatile u_int32_t MAC_DMA_RXCFG;               /*       0x34 - 0x38       */
  89   volatile u_int32_t MAC_DMA_RXJLA;               /*       0x38 - 0x3c       */
  90   volatile char pad__2[0x4];                      /*       0x3c - 0x40       */
  91   volatile u_int32_t MAC_DMA_MIBC;                /*       0x40 - 0x44       */
  92   volatile u_int32_t MAC_DMA_TOPS;                /*       0x44 - 0x48       */
  93   volatile u_int32_t MAC_DMA_RXNPTO;              /*       0x48 - 0x4c       */
  94   volatile u_int32_t MAC_DMA_TXNPTO;              /*       0x4c - 0x50       */
  95   volatile u_int32_t MAC_DMA_RPGTO;               /*       0x50 - 0x54       */
  96   volatile char pad__3[0x4];                      /*       0x54 - 0x58       */
  97   volatile u_int32_t MAC_DMA_MACMISC;             /*       0x58 - 0x5c       */
  98   volatile u_int32_t MAC_DMA_INTER;               /*       0x5c - 0x60       */
  99   volatile u_int32_t MAC_DMA_DATABUF;             /*       0x60 - 0x64       */
 100   volatile u_int32_t MAC_DMA_GTT;                 /*       0x64 - 0x68       */
 101   volatile u_int32_t MAC_DMA_GTTM;                /*       0x68 - 0x6c       */
 102   volatile u_int32_t MAC_DMA_CST;                 /*       0x6c - 0x70       */
 103   volatile u_int32_t MAC_DMA_RXDP_SIZE;           /*       0x70 - 0x74       */
 104   volatile u_int32_t MAC_DMA_RX_QUEUE_HP_RXDP;    /*       0x74 - 0x78       */
 105   volatile u_int32_t MAC_DMA_RX_QUEUE_LP_RXDP;    /*       0x78 - 0x7c       */
 106   volatile char pad__4[0x4];                      /*       0x7c - 0x80       */
 107   volatile u_int32_t MAC_DMA_ISR_P;               /*       0x80 - 0x84       */
 108   volatile u_int32_t MAC_DMA_ISR_S0;              /*       0x84 - 0x88       */
 109   volatile u_int32_t MAC_DMA_ISR_S1;              /*       0x88 - 0x8c       */
 110   volatile u_int32_t MAC_DMA_ISR_S2;              /*       0x8c - 0x90       */
 111   volatile u_int32_t MAC_DMA_ISR_S3;              /*       0x90 - 0x94       */
 112   volatile u_int32_t MAC_DMA_ISR_S4;              /*       0x94 - 0x98       */
 113   volatile u_int32_t MAC_DMA_ISR_S5;              /*       0x98 - 0x9c       */
 114   volatile char pad__5[0x4];                      /*       0x9c - 0xa0       */
 115   volatile u_int32_t MAC_DMA_IMR_P;               /*       0xa0 - 0xa4       */
 116   volatile u_int32_t MAC_DMA_IMR_S0;              /*       0xa4 - 0xa8       */
 117   volatile u_int32_t MAC_DMA_IMR_S1;              /*       0xa8 - 0xac       */
 118   volatile u_int32_t MAC_DMA_IMR_S2;              /*       0xac - 0xb0       */
 119   volatile u_int32_t MAC_DMA_IMR_S3;              /*       0xb0 - 0xb4       */
 120   volatile u_int32_t MAC_DMA_IMR_S4;              /*       0xb4 - 0xb8       */
 121   volatile u_int32_t MAC_DMA_IMR_S5;              /*       0xb8 - 0xbc       */
 122   volatile char pad__6[0x4];                      /*       0xbc - 0xc0       */
 123   volatile u_int32_t MAC_DMA_ISR_P_RAC;           /*       0xc0 - 0xc4       */
 124   volatile u_int32_t MAC_DMA_ISR_S0_S;            /*       0xc4 - 0xc8       */
 125   volatile u_int32_t MAC_DMA_ISR_S1_S;            /*       0xc8 - 0xcc       */
 126   volatile char pad__7[0x4];                      /*       0xcc - 0xd0       */
 127   volatile u_int32_t MAC_DMA_ISR_S2_S;            /*       0xd0 - 0xd4       */
 128   volatile u_int32_t MAC_DMA_ISR_S3_S;            /*       0xd4 - 0xd8       */
 129   volatile u_int32_t MAC_DMA_ISR_S4_S;            /*       0xd8 - 0xdc       */
 130   volatile u_int32_t MAC_DMA_ISR_S5_S;            /*       0xdc - 0xe0       */
 131   volatile u_int32_t MAC_DMA_DMADBG_0;            /*       0xe0 - 0xe4       */
 132   volatile u_int32_t MAC_DMA_DMADBG_1;            /*       0xe4 - 0xe8       */
 133   volatile u_int32_t MAC_DMA_DMADBG_2;            /*       0xe8 - 0xec       */
 134   volatile u_int32_t MAC_DMA_DMADBG_3;            /*       0xec - 0xf0       */
 135   volatile u_int32_t MAC_DMA_DMADBG_4;            /*       0xf0 - 0xf4       */
 136   volatile u_int32_t MAC_DMA_DMADBG_5;            /*       0xf4 - 0xf8       */
 137   volatile u_int32_t MAC_DMA_DMADBG_6;            /*       0xf8 - 0xfc       */
 138   volatile u_int32_t MAC_DMA_DMADBG_7;            /*       0xfc - 0x100      */
 139   volatile u_int32_t MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0;
 140                                                   /*      0x100 - 0x104      */
 141   volatile u_int32_t MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8;
 142                                                   /*      0x104 - 0x108      */
 143   volatile u_int32_t MAC_DMA_TIMT_0;              /*      0x108 - 0x10c      */
 144   volatile u_int32_t MAC_DMA_TIMT_1;              /*      0x10c - 0x110      */
 145   volatile u_int32_t MAC_DMA_TIMT_2;              /*      0x110 - 0x114      */
 146   volatile u_int32_t MAC_DMA_TIMT_3;              /*      0x114 - 0x118      */
 147   volatile u_int32_t MAC_DMA_TIMT_4;              /*      0x118 - 0x11c      */
 148   volatile u_int32_t MAC_DMA_TIMT_5;              /*      0x11c - 0x120      */
 149   volatile u_int32_t MAC_DMA_TIMT_6;              /*      0x120 - 0x124      */
 150   volatile u_int32_t MAC_DMA_TIMT_7;              /*      0x124 - 0x128      */
 151   volatile u_int32_t MAC_DMA_TIMT_8;              /*      0x128 - 0x12c      */
 152   volatile u_int32_t MAC_DMA_TIMT_9;              /*      0x12c - 0x130      */
 153 };
 154
 155 struct mac_qcu_reg {
 156   volatile u_int32_t MAC_QCU_TXDP[10];            /*        0x0 - 0x28       */
 157   volatile char pad__0[0x8];                      /*       0x28 - 0x30       */
 158   volatile u_int32_t MAC_QCU_STATUS_RING_START;   /*       0x30 - 0x34       */
 159   volatile u_int32_t MAC_QCU_STATUS_RING_END;     /*       0x34 - 0x38       */
 160   volatile u_int32_t MAC_QCU_STATUS_RING_CURRENT; /*       0x38 - 0x3c       */
 161   volatile char pad__1[0x4];                      /*       0x3c - 0x40       */
 162   volatile u_int32_t MAC_QCU_TXE;                 /*       0x40 - 0x44       */
 163   volatile char pad__2[0x3c];                     /*       0x44 - 0x80       */
 164   volatile u_int32_t MAC_QCU_TXD;                 /*       0x80 - 0x84       */
 165   volatile char pad__3[0x3c];                     /*       0x84 - 0xc0       */
 166   volatile u_int32_t MAC_QCU_CBR[10];             /*       0xc0 - 0xe8       */
 167   volatile char pad__4[0x18];                     /*       0xe8 - 0x100      */
 168   volatile u_int32_t MAC_QCU_RDYTIME[10];         /*      0x100 - 0x128      */
 169   volatile char pad__5[0x18];                     /*      0x128 - 0x140      */
 170   volatile u_int32_t MAC_QCU_ONESHOT_ARM_SC;      /*      0x140 - 0x144      */
 171   volatile char pad__6[0x3c];                     /*      0x144 - 0x180      */
 172   volatile u_int32_t MAC_QCU_ONESHOT_ARM_CC;      /*      0x180 - 0x184      */
 173   volatile char pad__7[0x3c];                     /*      0x184 - 0x1c0      */
 174   volatile u_int32_t MAC_QCU_MISC[10];            /*      0x1c0 - 0x1e8      */
 175   volatile char pad__8[0x18];                     /*      0x1e8 - 0x200      */
 176   volatile u_int32_t MAC_QCU_CNT[10];             /*      0x200 - 0x228      */
 177   volatile char pad__9[0x18];                     /*      0x228 - 0x240      */
 178   volatile u_int32_t MAC_QCU_RDYTIME_SHDN;        /*      0x240 - 0x244      */
 179   volatile u_int32_t MAC_QCU_DESC_CRC_CHK;        /*      0x244 - 0x248      */
 180 };
 181
 182 struct mac_dcu_reg {
 183   volatile u_int32_t MAC_DCU_QCUMASK[10];         /*        0x0 - 0x28       */
 184   volatile char pad__0[0x8];                      /*       0x28 - 0x30       */
 185   volatile u_int32_t MAC_DCU_GBL_IFS_SIFS;        /*       0x30 - 0x34       */
 186   volatile char pad__1[0x4];                      /*       0x34 - 0x38       */
 187   volatile u_int32_t MAC_DCU_TXFILTER_DCU0_31_0;  /*       0x38 - 0x3c       */
 188   volatile u_int32_t MAC_DCU_TXFILTER_DCU8_31_0;  /*       0x3c - 0x40       */
 189   volatile u_int32_t MAC_DCU_LCL_IFS[10];         /*       0x40 - 0x68       */
 190   volatile char pad__2[0x8];                      /*       0x68 - 0x70       */
 191   volatile u_int32_t MAC_DCU_GBL_IFS_SLOT;        /*       0x70 - 0x74       */
 192   volatile char pad__3[0x4];                      /*       0x74 - 0x78       */
 193   volatile u_int32_t MAC_DCU_TXFILTER_DCU0_63_32; /*       0x78 - 0x7c       */
 194   volatile u_int32_t MAC_DCU_TXFILTER_DCU8_63_32; /*       0x7c - 0x80       */
 195   volatile u_int32_t MAC_DCU_RETRY_LIMIT[10];     /*       0x80 - 0xa8       */
 196   volatile char pad__4[0x8];                      /*       0xa8 - 0xb0       */
 197   volatile u_int32_t MAC_DCU_GBL_IFS_EIFS;        /*       0xb0 - 0xb4       */
 198   volatile char pad__5[0x4];                      /*       0xb4 - 0xb8       */
 199   volatile u_int32_t MAC_DCU_TXFILTER_DCU0_95_64; /*       0xb8 - 0xbc       */
 200   volatile u_int32_t MAC_DCU_TXFILTER_DCU8_95_64; /*       0xbc - 0xc0       */
 201   volatile u_int32_t MAC_DCU_CHANNEL_TIME[10];    /*       0xc0 - 0xe8       */
 202   volatile char pad__6[0x8];                      /*       0xe8 - 0xf0       */
 203   volatile u_int32_t MAC_DCU_GBL_IFS_MISC;        /*       0xf0 - 0xf4       */
 204   volatile char pad__7[0x4];                      /*       0xf4 - 0xf8       */
 205   volatile u_int32_t MAC_DCU_TXFILTER_DCU0_127_96;
 206                                                   /*       0xf8 - 0xfc       */
 207   volatile u_int32_t MAC_DCU_TXFILTER_DCU8_127_96;
 208                                                   /*       0xfc - 0x100      */
 209   volatile u_int32_t MAC_DCU_MISC[10];            /*      0x100 - 0x128      */
 210   volatile char pad__8[0x10];                     /*      0x128 - 0x138      */
 211   volatile u_int32_t MAC_DCU_TXFILTER_DCU1_31_0;  /*      0x138 - 0x13c      */
 212   volatile u_int32_t MAC_DCU_TXFILTER_DCU9_31_0;  /*      0x13c - 0x140      */
 213   volatile u_int32_t MAC_DCU_SEQ;                 /*      0x140 - 0x144      */
 214   volatile char pad__9[0x34];                     /*      0x144 - 0x178      */
 215   volatile u_int32_t MAC_DCU_TXFILTER_DCU1_63_32; /*      0x178 - 0x17c      */
 216   volatile u_int32_t MAC_DCU_TXFILTER_DCU9_63_32; /*      0x17c - 0x180      */
 217   volatile char pad__10[0x38];                    /*      0x180 - 0x1b8      */
 218   volatile u_int32_t MAC_DCU_TXFILTER_DCU1_95_64; /*      0x1b8 - 0x1bc      */
 219   volatile u_int32_t MAC_DCU_TXFILTER_DCU9_95_64; /*      0x1bc - 0x1c0      */
 220   volatile char pad__11[0x38];                    /*      0x1c0 - 0x1f8      */
 221   volatile u_int32_t MAC_DCU_TXFILTER_DCU1_127_96;
 222                                                   /*      0x1f8 - 0x1fc      */
 223   volatile u_int32_t MAC_DCU_TXFILTER_DCU9_127_96;
 224                                                   /*      0x1fc - 0x200      */
 225   volatile char pad__12[0x38];                    /*      0x200 - 0x238      */
 226   volatile u_int32_t MAC_DCU_TXFILTER_DCU2_31_0;  /*      0x238 - 0x23c      */
 227   volatile char pad__13[0x34];                    /*      0x23c - 0x270      */
 228   volatile u_int32_t MAC_DCU_PAUSE;               /*      0x270 - 0x274      */
 229   volatile char pad__14[0x4];                     /*      0x274 - 0x278      */
 230   volatile u_int32_t MAC_DCU_TXFILTER_DCU2_63_32; /*      0x278 - 0x27c      */
 231   volatile char pad__15[0x34];                    /*      0x27c - 0x2b0      */
 232   volatile u_int32_t MAC_DCU_WOW_KACFG;           /*      0x2b0 - 0x2b4      */
 233   volatile char pad__16[0x4];                     /*      0x2b4 - 0x2b8      */
 234   volatile u_int32_t MAC_DCU_TXFILTER_DCU2_95_64; /*      0x2b8 - 0x2bc      */
 235   volatile char pad__17[0x34];                    /*      0x2bc - 0x2f0      */
 236   volatile u_int32_t MAC_DCU_TXSLOT;              /*      0x2f0 - 0x2f4      */
 237   volatile char pad__18[0x4];                     /*      0x2f4 - 0x2f8      */
 238   volatile u_int32_t MAC_DCU_TXFILTER_DCU2_127_96;
 239                                                   /*      0x2f8 - 0x2fc      */
 240   volatile char pad__19[0x3c];                    /*      0x2fc - 0x338      */
 241   volatile u_int32_t MAC_DCU_TXFILTER_DCU3_31_0;  /*      0x338 - 0x33c      */
 242   volatile char pad__20[0x3c];                    /*      0x33c - 0x378      */
 243   volatile u_int32_t MAC_DCU_TXFILTER_DCU3_63_32; /*      0x378 - 0x37c      */
 244   volatile char pad__21[0x3c];                    /*      0x37c - 0x3b8      */
 245   volatile u_int32_t MAC_DCU_TXFILTER_DCU3_95_64; /*      0x3b8 - 0x3bc      */
 246   volatile char pad__22[0x3c];                    /*      0x3bc - 0x3f8      */
 247   volatile u_int32_t MAC_DCU_TXFILTER_DCU3_127_96;
 248                                                   /*      0x3f8 - 0x3fc      */
 249   volatile char pad__23[0x3c];                    /*      0x3fc - 0x438      */
 250   volatile u_int32_t MAC_DCU_TXFILTER_DCU4_31_0;  /*      0x438 - 0x43c      */
 251   volatile u_int32_t MAC_DCU_TXFILTER_CLEAR;      /*      0x43c - 0x440      */
 252   volatile char pad__24[0x38];                    /*      0x440 - 0x478      */
 253   volatile u_int32_t MAC_DCU_TXFILTER_DCU4_63_32; /*      0x478 - 0x47c      */
 254   volatile u_int32_t MAC_DCU_TXFILTER_SET;        /*      0x47c - 0x480      */
 255   volatile char pad__25[0x38];                    /*      0x480 - 0x4b8      */
 256   volatile u_int32_t MAC_DCU_TXFILTER_DCU4_95_64; /*      0x4b8 - 0x4bc      */
 257   volatile char pad__26[0x3c];                    /*      0x4bc - 0x4f8      */
 258   volatile u_int32_t MAC_DCU_TXFILTER_DCU4_127_96;
 259                                                   /*      0x4f8 - 0x4fc      */
 260   volatile char pad__27[0x3c];                    /*      0x4fc - 0x538      */
 261   volatile u_int32_t MAC_DCU_TXFILTER_DCU5_31_0;  /*      0x538 - 0x53c      */
 262   volatile char pad__28[0x3c];                    /*      0x53c - 0x578      */
 263   volatile u_int32_t MAC_DCU_TXFILTER_DCU5_63_32; /*      0x578 - 0x57c      */
 264   volatile char pad__29[0x3c];                    /*      0x57c - 0x5b8      */
 265   volatile u_int32_t MAC_DCU_TXFILTER_DCU5_95_64; /*      0x5b8 - 0x5bc      */
 266   volatile char pad__30[0x3c];                    /*      0x5bc - 0x5f8      */
 267   volatile u_int32_t MAC_DCU_TXFILTER_DCU5_127_96;
 268                                                   /*      0x5f8 - 0x5fc      */
 269   volatile char pad__31[0x3c];                    /*      0x5fc - 0x638      */
 270   volatile u_int32_t MAC_DCU_TXFILTER_DCU6_31_0;  /*      0x638 - 0x63c      */
 271   volatile char pad__32[0x3c];                    /*      0x63c - 0x678      */
 272   volatile u_int32_t MAC_DCU_TXFILTER_DCU6_63_32; /*      0x678 - 0x67c      */
 273   volatile char pad__33[0x3c];                    /*      0x67c - 0x6b8      */
 274   volatile u_int32_t MAC_DCU_TXFILTER_DCU6_95_64; /*      0x6b8 - 0x6bc      */
 275   volatile char pad__34[0x3c];                    /*      0x6bc - 0x6f8      */
 276   volatile u_int32_t MAC_DCU_TXFILTER_DCU6_127_96;
 277                                                   /*      0x6f8 - 0x6fc      */
 278   volatile char pad__35[0x3c];                    /*      0x6fc - 0x738      */
 279   volatile u_int32_t MAC_DCU_TXFILTER_DCU7_31_0;  /*      0x738 - 0x73c      */
 280   volatile char pad__36[0x3c];                    /*      0x73c - 0x778      */
 281   volatile u_int32_t MAC_DCU_TXFILTER_DCU7_63_32; /*      0x778 - 0x77c      */
 282   volatile char pad__37[0x3c];                    /*      0x77c - 0x7b8      */
 283   volatile u_int32_t MAC_DCU_TXFILTER_DCU7_95_64; /*      0x7b8 - 0x7bc      */
 284   volatile char pad__38[0x3c];                    /*      0x7bc - 0x7f8      */
 285   volatile u_int32_t MAC_DCU_TXFILTER_DCU7_127_96;
 286                                                   /*      0x7f8 - 0x7fc      */
 287   volatile char pad__39[0x704];                   /*      0x7fc - 0xf00      */
 288   volatile u_int32_t MAC_SLEEP_STATUS;            /*      0xf00 - 0xf04      */
 289   volatile u_int32_t MAC_LED_CONFIG;              /*      0xf04 - 0xf08      */
 290 };
 291
 292 struct rtc_reg {
 293   volatile u_int32_t RESET_CONTROL;               /*        0x0 - 0x4        */
 294   volatile u_int32_t XTAL_CONTROL;                /*        0x4 - 0x8        */
 295   volatile u_int32_t REG_CONTROL0;                /*        0x8 - 0xc        */
 296   volatile u_int32_t REG_CONTROL1;                /*        0xc - 0x10       */
 297   volatile u_int32_t QUADRATURE;                  /*       0x10 - 0x14       */
 298   volatile u_int32_t PLL_CONTROL;                 /*       0x14 - 0x18       */
 299   volatile u_int32_t PLL_SETTLE;                  /*       0x18 - 0x1c       */
 300   volatile u_int32_t XTAL_SETTLE;                 /*       0x1c - 0x20       */
 301   volatile u_int32_t CLOCK_OUT;                   /*       0x20 - 0x24       */
 302   volatile u_int32_t BIAS_OVERRIDE;               /*       0x24 - 0x28       */
 303   volatile u_int32_t RESET_CAUSE;                 /*       0x28 - 0x2c       */
 304   volatile u_int32_t SYSTEM_SLEEP;                /*       0x2c - 0x30       */
 305   volatile u_int32_t MAC_SLEEP_CONTROL;           /*       0x30 - 0x34       */
 306   volatile u_int32_t KEEP_AWAKE;                  /*       0x34 - 0x38       */
 307   volatile u_int32_t DERIVED_RTC_CLK;             /*       0x38 - 0x3c       */
 308   volatile u_int32_t PLL_CONTROL2;                /*       0x3c - 0x40       */
 309 };
 310
 311 struct rtc_sync_reg {
 312   volatile u_int32_t RTC_SYNC_RESET;              /*        0x0 - 0x4        */
 313   volatile u_int32_t RTC_SYNC_STATUS;             /*        0x4 - 0x8        */
 314   volatile u_int32_t RTC_SYNC_DERIVED;            /*        0x8 - 0xc        */
 315   volatile u_int32_t RTC_SYNC_FORCE_WAKE;         /*        0xc - 0x10       */
 316   volatile u_int32_t RTC_SYNC_INTR_CAUSE;         /*       0x10 - 0x14       */
 317   volatile u_int32_t RTC_SYNC_INTR_ENABLE;        /*       0x14 - 0x18       */
 318   volatile u_int32_t RTC_SYNC_INTR_MASK;          /*       0x18 - 0x1c       */
 319 };
 320
 321 struct mac_pcu_reg {
 322   volatile u_int32_t MAC_PCU_STA_ADDR_L32;        /*        0x0 - 0x4        */
 323   volatile u_int32_t MAC_PCU_STA_ADDR_U16;        /*        0x4 - 0x8        */
 324   volatile u_int32_t MAC_PCU_BSSID_L32;           /*        0x8 - 0xc        */
 325   volatile u_int32_t MAC_PCU_BSSID_U16;           /*        0xc - 0x10       */
 326   volatile u_int32_t MAC_PCU_BCN_RSSI_AVE;        /*       0x10 - 0x14       */
 327   volatile u_int32_t MAC_PCU_ACK_CTS_TIMEOUT;     /*       0x14 - 0x18       */
 328   volatile u_int32_t MAC_PCU_BCN_RSSI_CTL;        /*       0x18 - 0x1c       */
 329   volatile u_int32_t MAC_PCU_USEC_LATENCY;        /*       0x1c - 0x20       */
 330   volatile u_int32_t MAC_PCU_RESET_TSF;           /*       0x20 - 0x24       */
 331   volatile char pad__0[0x14];                     /*       0x24 - 0x38       */
 332   volatile u_int32_t MAC_PCU_MAX_CFP_DUR;         /*       0x38 - 0x3c       */
 333   volatile u_int32_t MAC_PCU_RX_FILTER;           /*       0x3c - 0x40       */
 334   volatile u_int32_t MAC_PCU_MCAST_FILTER_L32;    /*       0x40 - 0x44       */
 335   volatile u_int32_t MAC_PCU_MCAST_FILTER_U32;    /*       0x44 - 0x48       */
 336   volatile u_int32_t MAC_PCU_DIAG_SW;             /*       0x48 - 0x4c       */
 337   volatile u_int32_t MAC_PCU_TSF_L32;             /*       0x4c - 0x50       */
 338   volatile u_int32_t MAC_PCU_TSF_U32;             /*       0x50 - 0x54       */
 339   volatile u_int32_t MAC_PCU_TST_ADDAC;           /*       0x54 - 0x58       */
 340   volatile u_int32_t MAC_PCU_DEF_ANTENNA;         /*       0x58 - 0x5c       */
 341   volatile u_int32_t MAC_PCU_AES_MUTE_MASK_0;     /*       0x5c - 0x60       */
 342   volatile u_int32_t MAC_PCU_AES_MUTE_MASK_1;     /*       0x60 - 0x64       */
 343   volatile u_int32_t MAC_PCU_GATED_CLKS;          /*       0x64 - 0x68       */
 344   volatile u_int32_t MAC_PCU_OBS_BUS_2;           /*       0x68 - 0x6c       */
 345   volatile u_int32_t MAC_PCU_OBS_BUS_1;           /*       0x6c - 0x70       */
 346   volatile u_int32_t MAC_PCU_DYM_MIMO_PWR_SAVE;   /*       0x70 - 0x74       */
 347   volatile u_int32_t MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB;
 348                                                   /*       0x74 - 0x78       */
 349   volatile u_int32_t MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB;
 350                                                   /*       0x78 - 0x7c       */
 351   volatile char pad__1[0x4];                      /*       0x7c - 0x80       */
 352   volatile u_int32_t MAC_PCU_LAST_BEACON_TSF;     /*       0x80 - 0x84       */
 353   volatile u_int32_t MAC_PCU_NAV;                 /*       0x84 - 0x88       */
 354   volatile u_int32_t MAC_PCU_RTS_SUCCESS_CNT;     /*       0x88 - 0x8c       */
 355   volatile u_int32_t MAC_PCU_RTS_FAIL_CNT;        /*       0x8c - 0x90       */
 356   volatile u_int32_t MAC_PCU_ACK_FAIL_CNT;        /*       0x90 - 0x94       */
 357   volatile u_int32_t MAC_PCU_FCS_FAIL_CNT;        /*       0x94 - 0x98       */
 358   volatile u_int32_t MAC_PCU_BEACON_CNT;          /*       0x98 - 0x9c       */
 359   volatile u_int32_t MAC_PCU_TDMA_SLOT_ALERT_CNTL;
 360                                                   /*       0x9c - 0xa0       */
 361   volatile u_int32_t MAC_PCU_BASIC_SET;           /*       0xa0 - 0xa4       */
 362   volatile u_int32_t MAC_PCU_MGMT_SEQ;            /*       0xa4 - 0xa8       */
 363   volatile u_int32_t MAC_PCU_BF_RPT1;             /*       0xa8 - 0xac       */
 364   volatile u_int32_t MAC_PCU_BF_RPT2;             /*       0xac - 0xb0       */
 365   volatile u_int32_t MAC_PCU_TX_ANT_1;            /*       0xb0 - 0xb4       */
 366   volatile u_int32_t MAC_PCU_TX_ANT_2;            /*       0xb4 - 0xb8       */
 367   volatile u_int32_t MAC_PCU_TX_ANT_3;            /*       0xb8 - 0xbc       */
 368   volatile u_int32_t MAC_PCU_TX_ANT_4;            /*       0xbc - 0xc0       */
 369   volatile u_int32_t MAC_PCU_XRMODE;              /*       0xc0 - 0xc4       */
 370   volatile u_int32_t MAC_PCU_XRDEL;               /*       0xc4 - 0xc8       */
 371   volatile u_int32_t MAC_PCU_XRTO;                /*       0xc8 - 0xcc       */
 372   volatile u_int32_t MAC_PCU_XRCRP;               /*       0xcc - 0xd0       */
 373   volatile u_int32_t MAC_PCU_XRSTMP;              /*       0xd0 - 0xd4       */
 374   volatile u_int32_t MAC_PCU_SLP1;                /*       0xd4 - 0xd8       */
 375   volatile u_int32_t MAC_PCU_SLP2;                /*       0xd8 - 0xdc       */
 376   volatile u_int32_t MAC_PCU_SELF_GEN_DEFAULT;    /*       0xdc - 0xe0       */
 377   volatile u_int32_t MAC_PCU_ADDR1_MASK_L32;      /*       0xe0 - 0xe4       */
 378   volatile u_int32_t MAC_PCU_ADDR1_MASK_U16;      /*       0xe4 - 0xe8       */
 379   volatile u_int32_t MAC_PCU_TPC;                 /*       0xe8 - 0xec       */
 380   volatile u_int32_t MAC_PCU_TX_FRAME_CNT;        /*       0xec - 0xf0       */
 381   volatile u_int32_t MAC_PCU_RX_FRAME_CNT;        /*       0xf0 - 0xf4       */
 382   volatile u_int32_t MAC_PCU_RX_CLEAR_CNT;        /*       0xf4 - 0xf8       */
 383   volatile u_int32_t MAC_PCU_CYCLE_CNT;           /*       0xf8 - 0xfc       */
 384   volatile u_int32_t MAC_PCU_QUIET_TIME_1;        /*       0xfc - 0x100      */
 385   volatile u_int32_t MAC_PCU_QUIET_TIME_2;        /*      0x100 - 0x104      */
 386   volatile char pad__2[0x4];                      /*      0x104 - 0x108      */
 387   volatile u_int32_t MAC_PCU_QOS_NO_ACK;          /*      0x108 - 0x10c      */
 388   volatile u_int32_t MAC_PCU_PHY_ERROR_MASK;      /*      0x10c - 0x110      */
 389   volatile u_int32_t MAC_PCU_XRLAT;               /*      0x110 - 0x114      */
 390   volatile u_int32_t MAC_PCU_RXBUF;               /*      0x114 - 0x118      */
 391   volatile u_int32_t MAC_PCU_MIC_QOS_CONTROL;     /*      0x118 - 0x11c      */
 392   volatile u_int32_t MAC_PCU_MIC_QOS_SELECT;      /*      0x11c - 0x120      */
 393   volatile u_int32_t MAC_PCU_MISC_MODE;           /*      0x120 - 0x124      */
 394   volatile u_int32_t MAC_PCU_FILTER_OFDM_CNT;     /*      0x124 - 0x128      */
 395   volatile u_int32_t MAC_PCU_FILTER_CCK_CNT;      /*      0x128 - 0x12c      */
 396   volatile u_int32_t MAC_PCU_PHY_ERR_CNT_1;       /*      0x12c - 0x130      */
 397   volatile u_int32_t MAC_PCU_PHY_ERR_CNT_1_MASK;  /*      0x130 - 0x134      */
 398   volatile u_int32_t MAC_PCU_PHY_ERR_CNT_2;       /*      0x134 - 0x138      */
 399   volatile u_int32_t MAC_PCU_PHY_ERR_CNT_2_MASK;  /*      0x138 - 0x13c      */
 400   volatile u_int32_t MAC_PCU_TSF_THRESHOLD;       /*      0x13c - 0x140      */
 401   volatile u_int32_t MAC_PCU_MISC_MODE4;          /*      0x140 - 0x144      */
 402   volatile u_int32_t MAC_PCU_PHY_ERROR_EIFS_MASK; /*      0x144 - 0x148      */
 403   volatile char pad__3[0x20];                     /*      0x148 - 0x168      */
 404   volatile u_int32_t MAC_PCU_PHY_ERR_CNT_3;       /*      0x168 - 0x16c      */
 405   volatile u_int32_t MAC_PCU_PHY_ERR_CNT_3_MASK;  /*      0x16c - 0x170      */
 406   volatile u_int32_t MAC_PCU_BLUETOOTH_MODE;      /*      0x170 - 0x174      */
 407   volatile u_int32_t MAC_PCU_BLUETOOTH_WL_WEIGHTS0;
 408                                                   /*      0x174 - 0x178      */
 409   volatile u_int32_t MAC_PCU_HCF_TIMEOUT;         /*      0x178 - 0x17c      */
 410   volatile u_int32_t MAC_PCU_BLUETOOTH_MODE2;     /*      0x17c - 0x180      */
 411   volatile u_int32_t MAC_PCU_GENERIC_TIMERS2[16]; /*      0x180 - 0x1c0      */
 412   volatile u_int32_t MAC_PCU_GENERIC_TIMERS2_MODE;
 413                                                   /*      0x1c0 - 0x1c4      */
 414   volatile u_int32_t MAC_PCU_BLUETOOTH_WL_WEIGHTS1;
 415                                                   /*      0x1c4 - 0x1c8      */
 416   volatile u_int32_t MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE;
 417                                                   /*      0x1c8 - 0x1cc      */
 418   volatile u_int32_t MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY;
 419                                                   /*      0x1cc - 0x1d0      */
 420   volatile u_int32_t MAC_PCU_TXSIFS;              /*      0x1d0 - 0x1d4      */
 421   volatile u_int32_t MAC_PCU_BLUETOOTH_MODE3;     /*      0x1d4 - 0x1d8      */
 422   volatile char pad__4[0x14];                     /*      0x1d8 - 0x1ec      */
 423   volatile u_int32_t MAC_PCU_TXOP_X;              /*      0x1ec - 0x1f0      */
 424   volatile u_int32_t MAC_PCU_TXOP_0_3;            /*      0x1f0 - 0x1f4      */
 425   volatile u_int32_t MAC_PCU_TXOP_4_7;            /*      0x1f4 - 0x1f8      */
 426   volatile u_int32_t MAC_PCU_TXOP_8_11;           /*      0x1f8 - 0x1fc      */
 427   volatile u_int32_t MAC_PCU_TXOP_12_15;          /*      0x1fc - 0x200      */
 428   volatile u_int32_t MAC_PCU_GENERIC_TIMERS[16];  /*      0x200 - 0x240      */
 429   volatile u_int32_t MAC_PCU_GENERIC_TIMERS_MODE; /*      0x240 - 0x244      */
 430   volatile u_int32_t MAC_PCU_SLP32_MODE;          /*      0x244 - 0x248      */
 431   volatile u_int32_t MAC_PCU_SLP32_WAKE;          /*      0x248 - 0x24c      */
 432   volatile u_int32_t MAC_PCU_SLP32_INC;           /*      0x24c - 0x250      */
 433   volatile u_int32_t MAC_PCU_SLP_MIB1;            /*      0x250 - 0x254      */
 434   volatile u_int32_t MAC_PCU_SLP_MIB2;            /*      0x254 - 0x258      */
 435   volatile u_int32_t MAC_PCU_SLP_MIB3;            /*      0x258 - 0x25c      */
 436   volatile u_int32_t MAC_PCU_WOW1;                /*      0x25c - 0x260      */
 437   volatile u_int32_t MAC_PCU_WOW2;                /*      0x260 - 0x264      */
 438   volatile u_int32_t MAC_PCU_LOGIC_ANALYZER;      /*      0x264 - 0x268      */
 439   volatile u_int32_t MAC_PCU_LOGIC_ANALYZER_32L;  /*      0x268 - 0x26c      */
 440   volatile u_int32_t MAC_PCU_LOGIC_ANALYZER_16U;  /*      0x26c - 0x270      */
 441   volatile u_int32_t MAC_PCU_WOW3_BEACON_FAIL;    /*      0x270 - 0x274      */
 442   volatile u_int32_t MAC_PCU_WOW3_BEACON;         /*      0x274 - 0x278      */
 443   volatile u_int32_t MAC_PCU_WOW3_KEEP_ALIVE;     /*      0x278 - 0x27c      */
 444   volatile u_int32_t MAC_PCU_WOW_KA;              /*      0x27c - 0x280      */
 445   volatile char pad__5[0x4];                      /*      0x280 - 0x284      */
 446   volatile u_int32_t PCU_1US;                     /*      0x284 - 0x288      */
 447   volatile u_int32_t PCU_KA;                      /*      0x288 - 0x28c      */
 448   volatile u_int32_t WOW_EXACT;                   /*      0x28c - 0x290      */
 449   volatile char pad__6[0x4];                      /*      0x290 - 0x294      */
 450   volatile u_int32_t PCU_WOW4;                    /*      0x294 - 0x298      */
 451   volatile u_int32_t PCU_WOW5;                    /*      0x298 - 0x29c      */
 452   volatile u_int32_t MAC_PCU_PHY_ERR_CNT_MASK_CONT;
 453                                                   /*      0x29c - 0x2a0      */
 454   volatile char pad__7[0x60];                     /*      0x2a0 - 0x300      */
 455   volatile u_int32_t MAC_PCU_AZIMUTH_MODE;        /*      0x300 - 0x304      */
 456   volatile char pad__8[0x10];                     /*      0x304 - 0x314      */
 457   volatile u_int32_t MAC_PCU_AZIMUTH_TIME_STAMP;  /*      0x314 - 0x318      */
 458   volatile u_int32_t MAC_PCU_20_40_MODE;          /*      0x318 - 0x31c      */
 459   volatile u_int32_t MAC_PCU_H_XFER_TIMEOUT;      /*      0x31c - 0x320      */
 460   volatile char pad__9[0x8];                      /*      0x320 - 0x328      */
 461   volatile u_int32_t MAC_PCU_RX_CLEAR_DIFF_CNT;   /*      0x328 - 0x32c      */
 462   volatile u_int32_t MAC_PCU_SELF_GEN_ANTENNA_MASK;
 463                                                   /*      0x32c - 0x330      */
 464   volatile u_int32_t MAC_PCU_BA_BAR_CONTROL;      /*      0x330 - 0x334      */
 465   volatile u_int32_t MAC_PCU_LEGACY_PLCP_SPOOF;   /*      0x334 - 0x338      */
 466   volatile u_int32_t MAC_PCU_PHY_ERROR_MASK_CONT; /*      0x338 - 0x33c      */
 467   volatile u_int32_t MAC_PCU_TX_TIMER;            /*      0x33c - 0x340      */
 468   volatile u_int32_t MAC_PCU_TXBUF_CTRL;          /*      0x340 - 0x344      */
 469   volatile u_int32_t MAC_PCU_MISC_MODE2;          /*      0x344 - 0x348      */
 470   volatile u_int32_t MAC_PCU_ALT_AES_MUTE_MASK;   /*      0x348 - 0x34c      */
 471   volatile u_int32_t MAC_PCU_WOW6;                /*      0x34c - 0x350      */
 472   volatile u_int32_t ASYNC_FIFO_REG1;             /*      0x350 - 0x354      */
 473   volatile u_int32_t ASYNC_FIFO_REG2;             /*      0x354 - 0x358      */
 474   volatile u_int32_t ASYNC_FIFO_REG3;             /*      0x358 - 0x35c      */
 475   volatile u_int32_t MAC_PCU_WOW5;                /*      0x35c - 0x360      */
 476   volatile u_int32_t MAC_PCU_WOW_LENGTH1;         /*      0x360 - 0x364      */
 477   volatile u_int32_t MAC_PCU_WOW_LENGTH2;         /*      0x364 - 0x368      */
 478   volatile u_int32_t WOW_PATTERN_MATCH_LESS_THAN_256_BYTES;
 479                                                   /*      0x368 - 0x36c      */
 480   volatile char pad__10[0x4];                     /*      0x36c - 0x370      */
 481   volatile u_int32_t MAC_PCU_WOW4;                /*      0x370 - 0x374      */
 482   volatile u_int32_t WOW2_EXACT;                  /*      0x374 - 0x378      */
 483   volatile u_int32_t PCU_WOW6;                    /*      0x378 - 0x37c      */
 484   volatile u_int32_t PCU_WOW7;                    /*      0x37c - 0x380      */
 485   volatile u_int32_t MAC_PCU_WOW_LENGTH3;         /*      0x380 - 0x384      */
 486   volatile u_int32_t MAC_PCU_WOW_LENGTH4;         /*      0x384 - 0x388      */
 487   volatile u_int32_t MAC_PCU_LOCATION_MODE_CONTROL;
 488                                                   /*      0x388 - 0x38c      */
 489   volatile u_int32_t MAC_PCU_LOCATION_MODE_TIMER; /*      0x38c - 0x390      */
 490   volatile u_int32_t MAC_PCU_TSF2_L32;            /*      0x390 - 0x394      */
 491   volatile u_int32_t MAC_PCU_TSF2_U32;            /*      0x394 - 0x398      */
 492   volatile u_int32_t MAC_PCU_BSSID2_L32;          /*      0x398 - 0x39c      */
 493   volatile u_int32_t MAC_PCU_BSSID2_U16;          /*      0x39c - 0x3a0      */
 494   volatile u_int32_t MAC_PCU_DIRECT_CONNECT;      /*      0x3a0 - 0x3a4      */
 495   volatile u_int32_t MAC_PCU_TID_TO_AC;           /*      0x3a4 - 0x3a8      */
 496   volatile u_int32_t MAC_PCU_HP_QUEUE;            /*      0x3a8 - 0x3ac      */
 497   volatile u_int32_t MAC_PCU_BLUETOOTH_BT_WEIGHTS0;
 498                                                   /*      0x3ac - 0x3b0      */
 499   volatile u_int32_t MAC_PCU_BLUETOOTH_BT_WEIGHTS1;
 500                                                   /*      0x3b0 - 0x3b4      */
 501   volatile u_int32_t MAC_PCU_BLUETOOTH_BT_WEIGHTS2;
 502                                                   /*      0x3b4 - 0x3b8      */
 503   volatile u_int32_t MAC_PCU_BLUETOOTH_BT_WEIGHTS3;
 504                                                   /*      0x3b8 - 0x3bc      */
 505   volatile u_int32_t MAC_PCU_AGC_SATURATION_CNT0; /*      0x3bc - 0x3c0      */
 506   volatile u_int32_t MAC_PCU_AGC_SATURATION_CNT1; /*      0x3c0 - 0x3c4      */
 507   volatile u_int32_t MAC_PCU_AGC_SATURATION_CNT2; /*      0x3c4 - 0x3c8      */
 508   volatile u_int32_t MAC_PCU_HW_BCN_PROC1;        /*      0x3c8 - 0x3cc      */
 509   volatile u_int32_t MAC_PCU_HW_BCN_PROC2;        /*      0x3cc - 0x3d0      */
 510   volatile u_int32_t MAC_PCU_MISC_MODE3;          /*      0x3d0 - 0x3d4      */
 511   volatile u_int32_t MAC_PCU_FILTER_RSSI_AVE;     /*      0x3d4 - 0x3d8      */
 512   volatile u_int32_t MAC_PCU_PHY_ERROR_AIFS_MASK; /*      0x3d8 - 0x3dc      */
 513   volatile u_int32_t MAC_PCU_PS_FILTER;           /*      0x3dc - 0x3e0      */
 514   volatile char pad__11[0x20];                    /*      0x3e0 - 0x400      */
 515   volatile u_int32_t MAC_PCU_TXBUF_BA[64];        /*      0x400 - 0x500      */
 516   volatile char pad__12[0x300];                   /*      0x500 - 0x800      */
 517   volatile u_int32_t MAC_PCU_KEY_CACHE[1024];     /*      0x800 - 0x1800     */
 518 };
 519
 520 struct chn_reg_map {
 521   volatile u_int32_t BB_timing_controls_1;        /*        0x0 - 0x4        */
 522   volatile u_int32_t BB_timing_controls_2;        /*        0x4 - 0x8        */
 523   volatile u_int32_t BB_timing_controls_3;        /*        0x8 - 0xc        */
 524   volatile u_int32_t BB_timing_control_4;         /*        0xc - 0x10       */
 525   volatile u_int32_t BB_timing_control_5;         /*       0x10 - 0x14       */
 526   volatile u_int32_t BB_timing_control_6;         /*       0x14 - 0x18       */
 527   volatile u_int32_t BB_timing_control_11;        /*       0x18 - 0x1c       */
 528   volatile u_int32_t BB_spur_mask_controls;       /*       0x1c - 0x20       */
 529   volatile u_int32_t BB_find_signal_low;          /*       0x20 - 0x24       */
 530   volatile u_int32_t BB_sfcorr;                   /*       0x24 - 0x28       */
 531   volatile u_int32_t BB_self_corr_low;            /*       0x28 - 0x2c       */
 532   volatile u_int32_t BB_ext_chan_scorr_thr;       /*       0x2c - 0x30       */
 533   volatile u_int32_t BB_ext_chan_pwr_thr_2_b0;    /*       0x30 - 0x34       */
 534   volatile u_int32_t BB_radar_detection;          /*       0x34 - 0x38       */
 535   volatile u_int32_t BB_radar_detection_2;        /*       0x38 - 0x3c       */
 536   volatile u_int32_t BB_extension_radar;          /*       0x3c - 0x40       */
 537   volatile char pad__0[0x40];                     /*       0x40 - 0x80       */
 538   volatile u_int32_t BB_multichain_control;       /*       0x80 - 0x84       */
 539   volatile u_int32_t BB_per_chain_csd;            /*       0x84 - 0x88       */
 540   volatile char pad__1[0x18];                     /*       0x88 - 0xa0       */
 541   volatile u_int32_t BB_tx_crc;                   /*       0xa0 - 0xa4       */
 542   volatile u_int32_t BB_tstdac_constant;          /*       0xa4 - 0xa8       */
 543   volatile u_int32_t BB_spur_report_b0;           /*       0xa8 - 0xac       */
 544   volatile char pad__2[0x4];                      /*       0xac - 0xb0       */
 545   volatile u_int32_t BB_txiqcal_control_3;        /*       0xb0 - 0xb4       */
 546   volatile char pad__3[0x8];                      /*       0xb4 - 0xbc       */
 547   volatile u_int32_t BB_green_tx_control_1;       /*       0xbc - 0xc0       */
 548   volatile u_int32_t BB_iq_adc_meas_0_b0;         /*       0xc0 - 0xc4       */
 549   volatile u_int32_t BB_iq_adc_meas_1_b0;         /*       0xc4 - 0xc8       */
 550   volatile u_int32_t BB_iq_adc_meas_2_b0;         /*       0xc8 - 0xcc       */
 551   volatile u_int32_t BB_iq_adc_meas_3_b0;         /*       0xcc - 0xd0       */
 552   volatile u_int32_t BB_tx_phase_ramp_b0;         /*       0xd0 - 0xd4       */
 553   volatile u_int32_t BB_adc_gain_dc_corr_b0;      /*       0xd4 - 0xd8       */
 554   volatile char pad__4[0x4];                      /*       0xd8 - 0xdc       */
 555   volatile u_int32_t BB_rx_iq_corr_b0;            /*       0xdc - 0xe0       */
 556   volatile char pad__5[0x4];                      /*       0xe0 - 0xe4       */
 557   volatile u_int32_t BB_paprd_am2am_mask;         /*       0xe4 - 0xe8       */
 558   volatile u_int32_t BB_paprd_am2pm_mask;         /*       0xe8 - 0xec       */
 559   volatile u_int32_t BB_paprd_ht40_mask;          /*       0xec - 0xf0       */
 560   volatile u_int32_t BB_paprd_ctrl0_b0;           /*       0xf0 - 0xf4       */
 561   volatile u_int32_t BB_paprd_ctrl1_b0;           /*       0xf4 - 0xf8       */
 562   volatile u_int32_t BB_pa_gain123_b0;            /*       0xf8 - 0xfc       */
 563   volatile u_int32_t BB_pa_gain45_b0;             /*       0xfc - 0x100      */
 564   volatile u_int32_t BB_paprd_pre_post_scale_0_b0;
 565                                                   /*      0x100 - 0x104      */
 566   volatile u_int32_t BB_paprd_pre_post_scale_1_b0;
 567                                                   /*      0x104 - 0x108      */
 568   volatile u_int32_t BB_paprd_pre_post_scale_2_b0;
 569                                                   /*      0x108 - 0x10c      */
 570   volatile u_int32_t BB_paprd_pre_post_scale_3_b0;
 571                                                   /*      0x10c - 0x110      */
 572   volatile u_int32_t BB_paprd_pre_post_scale_4_b0;
 573                                                   /*      0x110 - 0x114      */
 574   volatile u_int32_t BB_paprd_pre_post_scale_5_b0;
 575                                                   /*      0x114 - 0x118      */
 576   volatile u_int32_t BB_paprd_pre_post_scale_6_b0;
 577                                                   /*      0x118 - 0x11c      */
 578   volatile u_int32_t BB_paprd_pre_post_scale_7_b0;
 579                                                   /*      0x11c - 0x120      */
 580   volatile u_int32_t BB_paprd_mem_tab_b0[120];    /*      0x120 - 0x300      */
 581   volatile u_int32_t BB_chan_info_chan_tab_b0[60];
 582                                                   /*      0x300 - 0x3f0      */
 583   volatile u_int32_t BB_chn_tables_intf_addr;     /*      0x3f0 - 0x3f4      */
 584   volatile u_int32_t BB_chn_tables_intf_data;     /*      0x3f4 - 0x3f8      */
 585 };
 586
 587 struct mrc_reg_map {
 588   volatile u_int32_t BB_timing_control_3a;        /*        0x0 - 0x4        */
 589   volatile u_int32_t BB_ldpc_cntl1;               /*        0x4 - 0x8        */
 590   volatile u_int32_t BB_ldpc_cntl2;               /*        0x8 - 0xc        */
 591   volatile u_int32_t BB_pilot_spur_mask;          /*        0xc - 0x10       */
 592   volatile u_int32_t BB_chan_spur_mask;           /*       0x10 - 0x14       */
 593   volatile u_int32_t BB_short_gi_delta_slope;     /*       0x14 - 0x18       */
 594   volatile u_int32_t BB_ml_cntl1;                 /*       0x18 - 0x1c       */
 595   volatile u_int32_t BB_ml_cntl2;                 /*       0x1c - 0x20       */
 596   volatile u_int32_t BB_tstadc;                   /*       0x20 - 0x24       */
 597 };
 598
 599 struct bbb_reg_map {
 600   volatile u_int32_t BB_bbb_rx_ctrl_1;            /*        0x0 - 0x4        */
 601   volatile u_int32_t BB_bbb_rx_ctrl_2;            /*        0x4 - 0x8        */
 602   volatile u_int32_t BB_bbb_rx_ctrl_3;            /*        0x8 - 0xc        */
 603   volatile u_int32_t BB_bbb_rx_ctrl_4;            /*        0xc - 0x10       */
 604   volatile u_int32_t BB_bbb_rx_ctrl_5;            /*       0x10 - 0x14       */
 605   volatile u_int32_t BB_bbb_rx_ctrl_6;            /*       0x14 - 0x18       */
 606   volatile u_int32_t BB_force_clken_cck;          /*       0x18 - 0x1c       */
 607 };
 608
 609 struct agc_reg_map {
 610   volatile u_int32_t BB_settling_time;            /*        0x0 - 0x4        */
 611   volatile u_int32_t BB_gain_force_max_gains_b0;  /*        0x4 - 0x8        */
 612   volatile u_int32_t BB_gains_min_offsets;        /*        0x8 - 0xc        */
 613   volatile u_int32_t BB_desired_sigsize;          /*        0xc - 0x10       */
 614   volatile u_int32_t BB_find_signal;              /*       0x10 - 0x14       */
 615   volatile u_int32_t BB_agc;                      /*       0x14 - 0x18       */
 616   volatile u_int32_t BB_ext_atten_switch_ctl_b0;  /*       0x18 - 0x1c       */
 617   volatile u_int32_t BB_cca_b0;                   /*       0x1c - 0x20       */
 618   volatile u_int32_t BB_cca_ctrl_2_b0;            /*       0x20 - 0x24       */
 619   volatile u_int32_t BB_restart;                  /*       0x24 - 0x28       */
 620   volatile u_int32_t BB_multichain_gain_ctrl;     /*       0x28 - 0x2c       */
 621   volatile u_int32_t BB_ext_chan_pwr_thr_1;       /*       0x2c - 0x30       */
 622   volatile u_int32_t BB_ext_chan_detect_win;      /*       0x30 - 0x34       */
 623   volatile u_int32_t BB_pwr_thr_20_40_det;        /*       0x34 - 0x38       */
 624   volatile u_int32_t BB_rifs_srch;                /*       0x38 - 0x3c       */
 625   volatile u_int32_t BB_peak_det_ctrl_1;          /*       0x3c - 0x40       */
 626   volatile u_int32_t BB_peak_det_ctrl_2;          /*       0x40 - 0x44       */
 627   volatile u_int32_t BB_rx_gain_bounds_1;         /*       0x44 - 0x48       */
 628   volatile u_int32_t BB_rx_gain_bounds_2;         /*       0x48 - 0x4c       */
 629   volatile u_int32_t BB_peak_det_cal_ctrl;        /*       0x4c - 0x50       */
 630   volatile u_int32_t BB_agc_dig_dc_ctrl;          /*       0x50 - 0x54       */
 631   volatile u_int32_t BB_bt_coex_1;                /*       0x54 - 0x58       */
 632   volatile u_int32_t BB_bt_coex_2;                /*       0x58 - 0x5c       */
 633   volatile u_int32_t BB_bt_coex_3;                /*       0x5c - 0x60       */
 634   volatile u_int32_t BB_bt_coex_4;                /*       0x60 - 0x64       */
 635   volatile u_int32_t BB_bt_coex_5;                /*       0x64 - 0x68       */
 636   volatile u_int32_t BB_redpwr_ctrl_1;            /*       0x68 - 0x6c       */
 637   volatile u_int32_t BB_redpwr_ctrl_2;            /*       0x6c - 0x70       */
 638   volatile char pad__0[0x110];                    /*       0x70 - 0x180      */
 639   volatile u_int32_t BB_rssi_b0;                  /*      0x180 - 0x184      */
 640   volatile u_int32_t BB_spur_est_cck_report_b0;   /*      0x184 - 0x188      */
 641   volatile u_int32_t BB_agc_dig_dc_status_i_b0;   /*      0x188 - 0x18c      */
 642   volatile u_int32_t BB_agc_dig_dc_status_q_b0;   /*      0x18c - 0x190      */
 643   volatile u_int32_t BB_dc_cal_status_b0;         /*      0x190 - 0x194      */
 644   volatile char pad__1[0x2c];                     /*      0x194 - 0x1c0      */
 645   volatile u_int32_t BB_bbb_sig_detect;           /*      0x1c0 - 0x1c4      */
 646   volatile u_int32_t BB_bbb_dagc_ctrl;            /*      0x1c4 - 0x1c8      */
 647   volatile u_int32_t BB_iqcorr_ctrl_cck;          /*      0x1c8 - 0x1cc      */
 648   volatile u_int32_t BB_cck_spur_mit;             /*      0x1cc - 0x1d0      */
 649   volatile u_int32_t BB_mrc_cck_ctrl;             /*      0x1d0 - 0x1d4      */
 650   volatile u_int32_t BB_cck_blocker_det;          /*      0x1d4 - 0x1d8      */
 651   volatile char pad__2[0x28];                     /*      0x1d8 - 0x200      */
 652   volatile u_int32_t BB_rx_ocgain[128];           /*      0x200 - 0x400      */
 653 };
 654
 655 struct sm_reg_map {
 656   volatile u_int32_t BB_D2_chip_id;               /*        0x0 - 0x4        */
 657   volatile u_int32_t BB_gen_controls;             /*        0x4 - 0x8        */
 658   volatile u_int32_t BB_modes_select;             /*        0x8 - 0xc        */
 659   volatile u_int32_t BB_active;                   /*        0xc - 0x10       */
 660   volatile char pad__0[0x10];                     /*       0x10 - 0x20       */
 661   volatile u_int32_t BB_vit_spur_mask_A;          /*       0x20 - 0x24       */
 662   volatile u_int32_t BB_vit_spur_mask_B;          /*       0x24 - 0x28       */
 663   volatile u_int32_t BB_spectral_scan;            /*       0x28 - 0x2c       */
 664   volatile u_int32_t BB_radar_bw_filter;          /*       0x2c - 0x30       */
 665   volatile u_int32_t BB_search_start_delay;       /*       0x30 - 0x34       */
 666   volatile u_int32_t BB_max_rx_length;            /*       0x34 - 0x38       */
 667   volatile u_int32_t BB_frame_control;            /*       0x38 - 0x3c       */
 668   volatile u_int32_t BB_rfbus_request;            /*       0x3c - 0x40       */
 669   volatile u_int32_t BB_rfbus_grant;              /*       0x40 - 0x44       */
 670   volatile u_int32_t BB_rifs;                     /*       0x44 - 0x48       */
 671   volatile u_int32_t BB_spectral_scan_2;          /*       0x48 - 0x4c       */
 672   volatile char pad__1[0x4];                      /*       0x4c - 0x50       */
 673   volatile u_int32_t BB_rx_clear_delay;           /*       0x50 - 0x54       */
 674   volatile u_int32_t BB_analog_power_on_time;     /*       0x54 - 0x58       */
 675   volatile u_int32_t BB_tx_timing_1;              /*       0x58 - 0x5c       */
 676   volatile u_int32_t BB_tx_timing_2;              /*       0x5c - 0x60       */
 677   volatile u_int32_t BB_tx_timing_3;              /*       0x60 - 0x64       */
 678   volatile u_int32_t BB_xpa_timing_control;       /*       0x64 - 0x68       */
 679   volatile char pad__2[0x18];                     /*       0x68 - 0x80       */
 680   volatile u_int32_t BB_misc_pa_control;          /*       0x80 - 0x84       */
 681   volatile u_int32_t BB_switch_table_chn_b0;      /*       0x84 - 0x88       */
 682   volatile u_int32_t BB_switch_table_com1;        /*       0x88 - 0x8c       */
 683   volatile u_int32_t BB_switch_table_com2;        /*       0x8c - 0x90       */
 684   volatile char pad__3[0x10];                     /*       0x90 - 0xa0       */
 685   volatile u_int32_t BB_multichain_enable;        /*       0xa0 - 0xa4       */
 686   volatile char pad__4[0x1c];                     /*       0xa4 - 0xc0       */
 687   volatile u_int32_t BB_cal_chain_mask;           /*       0xc0 - 0xc4       */
 688   volatile u_int32_t BB_agc_control;              /*       0xc4 - 0xc8       */
 689   volatile u_int32_t BB_iq_adc_cal_mode;          /*       0xc8 - 0xcc       */
 690   volatile u_int32_t BB_fcal_1;                   /*       0xcc - 0xd0       */
 691   volatile u_int32_t BB_fcal_2_b0;                /*       0xd0 - 0xd4       */
 692   volatile u_int32_t BB_dft_tone_ctrl_b0;         /*       0xd4 - 0xd8       */
 693   volatile u_int32_t BB_cl_cal_ctrl;              /*       0xd8 - 0xdc       */
 694   volatile u_int32_t BB_cl_map_0_b0;              /*       0xdc - 0xe0       */
 695   volatile u_int32_t BB_cl_map_1_b0;              /*       0xe0 - 0xe4       */
 696   volatile u_int32_t BB_cl_map_2_b0;              /*       0xe4 - 0xe8       */
 697   volatile u_int32_t BB_cl_map_3_b0;              /*       0xe8 - 0xec       */
 698   volatile u_int32_t BB_cl_map_pal_0_b0;          /*       0xec - 0xf0       */
 699   volatile u_int32_t BB_cl_map_pal_1_b0;          /*       0xf0 - 0xf4       */
 700   volatile u_int32_t BB_cl_map_pal_2_b0;          /*       0xf4 - 0xf8       */
 701   volatile u_int32_t BB_cl_map_pal_3_b0;          /*       0xf8 - 0xfc       */
 702   volatile char pad__5[0x4];                      /*       0xfc - 0x100      */
 703   volatile u_int32_t BB_cl_tab_b0[16];            /*      0x100 - 0x140      */
 704   volatile u_int32_t BB_synth_control;            /*      0x140 - 0x144      */
 705   volatile u_int32_t BB_addac_clk_select;         /*      0x144 - 0x148      */
 706   volatile u_int32_t BB_pll_cntl;                 /*      0x148 - 0x14c      */
 707   volatile u_int32_t BB_analog_swap;              /*      0x14c - 0x150      */
 708   volatile u_int32_t BB_addac_parallel_control;   /*      0x150 - 0x154      */
 709   volatile char pad__6[0x4];                      /*      0x154 - 0x158      */
 710   volatile u_int32_t BB_force_analog;             /*      0x158 - 0x15c      */
 711   volatile char pad__7[0x4];                      /*      0x15c - 0x160      */
 712   volatile u_int32_t BB_test_controls;            /*      0x160 - 0x164      */
 713   volatile u_int32_t BB_test_controls_status;     /*      0x164 - 0x168      */
 714   volatile u_int32_t BB_tstdac;                   /*      0x168 - 0x16c      */
 715   volatile u_int32_t BB_channel_status;           /*      0x16c - 0x170      */
 716   volatile u_int32_t BB_chaninfo_ctrl;            /*      0x170 - 0x174      */
 717   volatile u_int32_t BB_chan_info_noise_pwr;      /*      0x174 - 0x178      */
 718   volatile u_int32_t BB_chan_info_gain_diff;      /*      0x178 - 0x17c      */
 719   volatile u_int32_t BB_chan_info_fine_timing;    /*      0x17c - 0x180      */
 720   volatile u_int32_t BB_chan_info_gain_b0;        /*      0x180 - 0x184      */
 721   volatile char pad__8[0xc];                      /*      0x184 - 0x190      */
 722   volatile u_int32_t BB_scrambler_seed;           /*      0x190 - 0x194      */
 723   volatile u_int32_t BB_bbb_tx_ctrl;              /*      0x194 - 0x198      */
 724   volatile u_int32_t BB_bbb_txfir_0;              /*      0x198 - 0x19c      */
 725   volatile u_int32_t BB_bbb_txfir_1;              /*      0x19c - 0x1a0      */
 726   volatile u_int32_t BB_bbb_txfir_2;              /*      0x1a0 - 0x1a4      */
 727   volatile u_int32_t BB_heavy_clip_ctrl;          /*      0x1a4 - 0x1a8      */
 728   volatile u_int32_t BB_heavy_clip_20;            /*      0x1a8 - 0x1ac      */
 729   volatile u_int32_t BB_heavy_clip_40;            /*      0x1ac - 0x1b0      */
 730   volatile u_int32_t BB_illegal_tx_rate;          /*      0x1b0 - 0x1b4      */
 731   volatile char pad__9[0xc];                      /*      0x1b4 - 0x1c0      */
 732   volatile u_int32_t BB_powertx_rate1;            /*      0x1c0 - 0x1c4      */
 733   volatile u_int32_t BB_powertx_rate2;            /*      0x1c4 - 0x1c8      */
 734   volatile u_int32_t BB_powertx_rate3;            /*      0x1c8 - 0x1cc      */
 735   volatile u_int32_t BB_powertx_rate4;            /*      0x1cc - 0x1d0      */
 736   volatile u_int32_t BB_powertx_rate5;            /*      0x1d0 - 0x1d4      */
 737   volatile u_int32_t BB_powertx_rate6;            /*      0x1d4 - 0x1d8      */
 738   volatile u_int32_t BB_powertx_rate7;            /*      0x1d8 - 0x1dc      */
 739   volatile u_int32_t BB_powertx_rate8;            /*      0x1dc - 0x1e0      */
 740   volatile u_int32_t BB_powertx_rate9;            /*      0x1e0 - 0x1e4      */
 741   volatile u_int32_t BB_powertx_rate10;           /*      0x1e4 - 0x1e8      */
 742   volatile u_int32_t BB_powertx_rate11;           /*      0x1e8 - 0x1ec      */
 743   volatile u_int32_t BB_powertx_rate12;           /*      0x1ec - 0x1f0      */
 744   volatile u_int32_t BB_powertx_max;              /*      0x1f0 - 0x1f4      */
 745   volatile u_int32_t BB_powertx_sub;              /*      0x1f4 - 0x1f8      */
 746   volatile u_int32_t BB_tpc_1;                    /*      0x1f8 - 0x1fc      */
 747   volatile u_int32_t BB_tpc_2;                    /*      0x1fc - 0x200      */
 748   volatile u_int32_t BB_tpc_3;                    /*      0x200 - 0x204      */
 749   volatile u_int32_t BB_tpc_4_b0;                 /*      0x204 - 0x208      */
 750   volatile u_int32_t BB_tpc_5_b0;                 /*      0x208 - 0x20c      */
 751   volatile u_int32_t BB_tpc_6_b0;                 /*      0x20c - 0x210      */
 752   volatile u_int32_t BB_tpc_7;                    /*      0x210 - 0x214      */
 753   volatile u_int32_t BB_tpc_8;                    /*      0x214 - 0x218      */
 754   volatile u_int32_t BB_tpc_9;                    /*      0x218 - 0x21c      */
 755   volatile u_int32_t BB_tpc_10;                   /*      0x21c - 0x220      */
 756   volatile u_int32_t BB_tpc_11_b0;                /*      0x220 - 0x224      */
 757   volatile u_int32_t BB_tpc_12;                   /*      0x224 - 0x228      */
 758   volatile u_int32_t BB_tpc_13;                   /*      0x228 - 0x22c      */
 759   volatile u_int32_t BB_tpc_14;                   /*      0x22c - 0x230      */
 760   volatile u_int32_t BB_tpc_15;                   /*      0x230 - 0x234      */
 761   volatile u_int32_t BB_tpc_16;                   /*      0x234 - 0x238      */
 762   volatile u_int32_t BB_tpc_17;                   /*      0x238 - 0x23c      */
 763   volatile u_int32_t BB_tpc_18;                   /*      0x23c - 0x240      */
 764   volatile u_int32_t BB_tpc_19_b0;                /*      0x240 - 0x244      */
 765   volatile u_int32_t BB_tpc_20;                   /*      0x244 - 0x248      */
 766   volatile u_int32_t BB_therm_adc_1;              /*      0x248 - 0x24c      */
 767   volatile u_int32_t BB_therm_adc_2;              /*      0x24c - 0x250      */
 768   volatile u_int32_t BB_therm_adc_3;              /*      0x250 - 0x254      */
 769   volatile u_int32_t BB_therm_adc_4;              /*      0x254 - 0x258      */
 770   volatile u_int32_t BB_tx_forced_gain;           /*      0x258 - 0x25c      */
 771   volatile char pad__10[0x24];                    /*      0x25c - 0x280      */
 772   volatile u_int32_t BB_pdadc_tab_b0[32];         /*      0x280 - 0x300      */
 773   volatile u_int32_t BB_tx_gain_tab_1;            /*      0x300 - 0x304      */
 774   volatile u_int32_t BB_tx_gain_tab_2;            /*      0x304 - 0x308      */
 775   volatile u_int32_t BB_tx_gain_tab_3;            /*      0x308 - 0x30c      */
 776   volatile u_int32_t BB_tx_gain_tab_4;            /*      0x30c - 0x310      */
 777   volatile u_int32_t BB_tx_gain_tab_5;            /*      0x310 - 0x314      */
 778   volatile u_int32_t BB_tx_gain_tab_6;            /*      0x314 - 0x318      */
 779   volatile u_int32_t BB_tx_gain_tab_7;            /*      0x318 - 0x31c      */
 780   volatile u_int32_t BB_tx_gain_tab_8;            /*      0x31c - 0x320      */
 781   volatile u_int32_t BB_tx_gain_tab_9;            /*      0x320 - 0x324      */
 782   volatile u_int32_t BB_tx_gain_tab_10;           /*      0x324 - 0x328      */
 783   volatile u_int32_t BB_tx_gain_tab_11;           /*      0x328 - 0x32c      */
 784   volatile u_int32_t BB_tx_gain_tab_12;           /*      0x32c - 0x330      */
 785   volatile u_int32_t BB_tx_gain_tab_13;           /*      0x330 - 0x334      */
 786   volatile u_int32_t BB_tx_gain_tab_14;           /*      0x334 - 0x338      */
 787   volatile u_int32_t BB_tx_gain_tab_15;           /*      0x338 - 0x33c      */
 788   volatile u_int32_t BB_tx_gain_tab_16;           /*      0x33c - 0x340      */
 789   volatile u_int32_t BB_tx_gain_tab_17;           /*      0x340 - 0x344      */
 790   volatile u_int32_t BB_tx_gain_tab_18;           /*      0x344 - 0x348      */
 791   volatile u_int32_t BB_tx_gain_tab_19;           /*      0x348 - 0x34c      */
 792   volatile u_int32_t BB_tx_gain_tab_20;           /*      0x34c - 0x350      */
 793   volatile u_int32_t BB_tx_gain_tab_21;           /*      0x350 - 0x354      */
 794   volatile u_int32_t BB_tx_gain_tab_22;           /*      0x354 - 0x358      */
 795   volatile u_int32_t BB_tx_gain_tab_23;           /*      0x358 - 0x35c      */
 796   volatile u_int32_t BB_tx_gain_tab_24;           /*      0x35c - 0x360      */
 797   volatile u_int32_t BB_tx_gain_tab_25;           /*      0x360 - 0x364      */
 798   volatile u_int32_t BB_tx_gain_tab_26;           /*      0x364 - 0x368      */
 799   volatile u_int32_t BB_tx_gain_tab_27;           /*      0x368 - 0x36c      */
 800   volatile u_int32_t BB_tx_gain_tab_28;           /*      0x36c - 0x370      */
 801   volatile u_int32_t BB_tx_gain_tab_29;           /*      0x370 - 0x374      */
 802   volatile u_int32_t BB_tx_gain_tab_30;           /*      0x374 - 0x378      */
 803   volatile u_int32_t BB_tx_gain_tab_31;           /*      0x378 - 0x37c      */
 804   volatile u_int32_t BB_tx_gain_tab_32;           /*      0x37c - 0x380      */
 805   volatile u_int32_t BB_rtt_ctrl;                 /*      0x380 - 0x384      */
 806   volatile u_int32_t BB_rtt_table_sw_intf_b0;     /*      0x384 - 0x388      */
 807   volatile u_int32_t BB_rtt_table_sw_intf_1_b0;   /*      0x388 - 0x38c      */
 808   volatile char pad__11[0x74];                    /*      0x38c - 0x400      */
 809   volatile u_int32_t BB_caltx_gain_set_0;         /*      0x400 - 0x404      */
 810   volatile u_int32_t BB_caltx_gain_set_2;         /*      0x404 - 0x408      */
 811   volatile u_int32_t BB_caltx_gain_set_4;         /*      0x408 - 0x40c      */
 812   volatile u_int32_t BB_caltx_gain_set_6;         /*      0x40c - 0x410      */
 813   volatile u_int32_t BB_caltx_gain_set_8;         /*      0x410 - 0x414      */
 814   volatile u_int32_t BB_caltx_gain_set_10;        /*      0x414 - 0x418      */
 815   volatile u_int32_t BB_caltx_gain_set_12;        /*      0x418 - 0x41c      */
 816   volatile u_int32_t BB_caltx_gain_set_14;        /*      0x41c - 0x420      */
 817   volatile u_int32_t BB_caltx_gain_set_16;        /*      0x420 - 0x424      */
 818   volatile u_int32_t BB_caltx_gain_set_18;        /*      0x424 - 0x428      */
 819   volatile u_int32_t BB_caltx_gain_set_20;        /*      0x428 - 0x42c      */
 820   volatile u_int32_t BB_caltx_gain_set_22;        /*      0x42c - 0x430      */
 821   volatile u_int32_t BB_caltx_gain_set_24;        /*      0x430 - 0x434      */
 822   volatile u_int32_t BB_caltx_gain_set_26;        /*      0x434 - 0x438      */
 823   volatile u_int32_t BB_caltx_gain_set_28;        /*      0x438 - 0x43c      */
 824   volatile u_int32_t BB_caltx_gain_set_30;        /*      0x43c - 0x440      */
 825   volatile char pad__12[0x4];                     /*      0x440 - 0x444      */
 826   volatile u_int32_t BB_txiqcal_control_0;        /*      0x444 - 0x448      */
 827   volatile u_int32_t BB_txiqcal_control_1;        /*      0x448 - 0x44c      */
 828   volatile u_int32_t BB_txiqcal_control_2;        /*      0x44c - 0x450      */
 829   volatile u_int32_t BB_txiq_corr_coeff_01_b0;    /*      0x450 - 0x454      */
 830   volatile u_int32_t BB_txiq_corr_coeff_23_b0;    /*      0x454 - 0x458      */
 831   volatile u_int32_t BB_txiq_corr_coeff_45_b0;    /*      0x458 - 0x45c      */
 832   volatile u_int32_t BB_txiq_corr_coeff_67_b0;    /*      0x45c - 0x460      */
 833   volatile u_int32_t BB_txiq_corr_coeff_89_b0;    /*      0x460 - 0x464      */
 834   volatile u_int32_t BB_txiq_corr_coeff_ab_b0;    /*      0x464 - 0x468      */
 835   volatile u_int32_t BB_txiq_corr_coeff_cd_b0;    /*      0x468 - 0x46c      */
 836   volatile u_int32_t BB_txiq_corr_coeff_ef_b0;    /*      0x46c - 0x470      */
 837   volatile u_int32_t BB_cal_rxbb_gain_tbl_0;      /*      0x470 - 0x474      */
 838   volatile u_int32_t BB_cal_rxbb_gain_tbl_4;      /*      0x474 - 0x478      */
 839   volatile u_int32_t BB_cal_rxbb_gain_tbl_8;      /*      0x478 - 0x47c      */
 840   volatile u_int32_t BB_cal_rxbb_gain_tbl_12;     /*      0x47c - 0x480      */
 841   volatile u_int32_t BB_cal_rxbb_gain_tbl_16;     /*      0x480 - 0x484      */
 842   volatile u_int32_t BB_cal_rxbb_gain_tbl_20;     /*      0x484 - 0x488      */
 843   volatile u_int32_t BB_cal_rxbb_gain_tbl_24;     /*      0x488 - 0x48c      */
 844   volatile u_int32_t BB_txiqcal_status_b0;        /*      0x48c - 0x490      */
 845   volatile u_int32_t BB_paprd_trainer_cntl1;      /*      0x490 - 0x494      */
 846   volatile u_int32_t BB_paprd_trainer_cntl2;      /*      0x494 - 0x498      */
 847   volatile u_int32_t BB_paprd_trainer_cntl3;      /*      0x498 - 0x49c      */
 848   volatile u_int32_t BB_paprd_trainer_cntl4;      /*      0x49c - 0x4a0      */
 849   volatile u_int32_t BB_paprd_trainer_stat1;      /*      0x4a0 - 0x4a4      */
 850   volatile u_int32_t BB_paprd_trainer_stat2;      /*      0x4a4 - 0x4a8      */
 851   volatile u_int32_t BB_paprd_trainer_stat3;      /*      0x4a8 - 0x4ac      */
 852   volatile char pad__13[0x114];                   /*      0x4ac - 0x5c0      */
 853   volatile u_int32_t BB_watchdog_status;          /*      0x5c0 - 0x5c4      */
 854   volatile u_int32_t BB_watchdog_ctrl_1;          /*      0x5c4 - 0x5c8      */
 855   volatile u_int32_t BB_watchdog_ctrl_2;          /*      0x5c8 - 0x5cc      */
 856   volatile u_int32_t BB_bluetooth_cntl;           /*      0x5cc - 0x5d0      */
 857   volatile u_int32_t BB_phyonly_warm_reset;       /*      0x5d0 - 0x5d4      */
 858   volatile u_int32_t BB_phyonly_control;          /*      0x5d4 - 0x5d8      */
 859   volatile char pad__14[0x4];                     /*      0x5d8 - 0x5dc      */
 860   volatile u_int32_t BB_eco_ctrl;                 /*      0x5dc - 0x5e0      */
 861   volatile char pad__15[0x10];                    /*      0x5e0 - 0x5f0      */
 862   volatile u_int32_t BB_tables_intf_addr_b0;      /*      0x5f0 - 0x5f4      */
 863   volatile u_int32_t BB_tables_intf_data_b0;      /*      0x5f4 - 0x5f8      */
 864 };
 865
 866 struct chn1_reg_map {
 867   volatile char pad__0[0x30];                     /*        0x0 - 0x30       */
 868   volatile u_int32_t BB_ext_chan_pwr_thr_2_b1;    /*       0x30 - 0x34       */
 869   volatile char pad__1[0x74];                     /*       0x34 - 0xa8       */
 870   volatile u_int32_t BB_spur_report_b1;           /*       0xa8 - 0xac       */
 871   volatile char pad__2[0x14];                     /*       0xac - 0xc0       */
 872   volatile u_int32_t BB_iq_adc_meas_0_b1;         /*       0xc0 - 0xc4       */
 873   volatile u_int32_t BB_iq_adc_meas_1_b1;         /*       0xc4 - 0xc8       */
 874   volatile u_int32_t BB_iq_adc_meas_2_b1;         /*       0xc8 - 0xcc       */
 875   volatile u_int32_t BB_iq_adc_meas_3_b1;         /*       0xcc - 0xd0       */
 876   volatile u_int32_t BB_tx_phase_ramp_b1;         /*       0xd0 - 0xd4       */
 877   volatile u_int32_t BB_adc_gain_dc_corr_b1;      /*       0xd4 - 0xd8       */
 878   volatile char pad__3[0x4];                      /*       0xd8 - 0xdc       */
 879   volatile u_int32_t BB_rx_iq_corr_b1;            /*       0xdc - 0xe0       */
 880   volatile char pad__4[0x10];                     /*       0xe0 - 0xf0       */
 881   volatile u_int32_t BB_paprd_ctrl0_b1;           /*       0xf0 - 0xf4       */
 882   volatile u_int32_t BB_paprd_ctrl1_b1;           /*       0xf4 - 0xf8       */
 883   volatile u_int32_t BB_pa_gain123_b1;            /*       0xf8 - 0xfc       */
 884   volatile u_int32_t BB_pa_gain45_b1;             /*       0xfc - 0x100      */
 885   volatile u_int32_t BB_paprd_pre_post_scale_0_b1;
 886                                                   /*      0x100 - 0x104      */
 887   volatile u_int32_t BB_paprd_pre_post_scale_1_b1;
 888                                                   /*      0x104 - 0x108      */
 889   volatile u_int32_t BB_paprd_pre_post_scale_2_b1;
 890                                                   /*      0x108 - 0x10c      */
 891   volatile u_int32_t BB_paprd_pre_post_scale_3_b1;
 892                                                   /*      0x10c - 0x110      */
 893   volatile u_int32_t BB_paprd_pre_post_scale_4_b1;
 894                                                   /*      0x110 - 0x114      */
 895   volatile u_int32_t BB_paprd_pre_post_scale_5_b1;
 896                                                   /*      0x114 - 0x118      */
 897   volatile u_int32_t BB_paprd_pre_post_scale_6_b1;
 898                                                   /*      0x118 - 0x11c      */
 899   volatile u_int32_t BB_paprd_pre_post_scale_7_b1;
 900                                                   /*      0x11c - 0x120      */
 901   volatile u_int32_t BB_paprd_mem_tab_b1[120];    /*      0x120 - 0x300      */
 902   volatile u_int32_t BB_chan_info_chan_tab_b1[60];
 903                                                   /*      0x300 - 0x3f0      */
 904   volatile u_int32_t BB_chn1_tables_intf_addr;    /*      0x3f0 - 0x3f4      */
 905   volatile u_int32_t BB_chn1_tables_intf_data;    /*      0x3f4 - 0x3f8      */
 906 };
 907
 908 struct agc1_reg_map {
 909   volatile char pad__0[0x4];                      /*        0x0 - 0x4        */
 910   volatile u_int32_t BB_gain_force_max_gains_b1;  /*        0x4 - 0x8        */
 911   volatile char pad__1[0x10];                     /*        0x8 - 0x18       */
 912   volatile u_int32_t BB_ext_atten_switch_ctl_b1;  /*       0x18 - 0x1c       */
 913   volatile u_int32_t BB_cca_b1;                   /*       0x1c - 0x20       */
 914   volatile u_int32_t BB_cca_ctrl_2_b1;            /*       0x20 - 0x24       */
 915   volatile char pad__2[0x15c];                    /*       0x24 - 0x180      */
 916   volatile u_int32_t BB_rssi_b1;                  /*      0x180 - 0x184      */
 917   volatile u_int32_t BB_spur_est_cck_report_b1;   /*      0x184 - 0x188      */
 918   volatile u_int32_t BB_agc_dig_dc_status_i_b1;   /*      0x188 - 0x18c      */
 919   volatile u_int32_t BB_agc_dig_dc_status_q_b1;   /*      0x18c - 0x190      */
 920   volatile u_int32_t BB_dc_cal_status_b1;         /*      0x190 - 0x194      */
 921   volatile char pad__3[0x6c];                     /*      0x194 - 0x200      */
 922   volatile u_int32_t BB_rx_ocgain2[128];          /*      0x200 - 0x400      */
 923 };
 924
 925 struct sm1_reg_map {
 926   volatile char pad__0[0x84];                     /*        0x0 - 0x84       */
 927   volatile u_int32_t BB_switch_table_chn_b1;      /*       0x84 - 0x88       */
 928   volatile char pad__1[0x48];                     /*       0x88 - 0xd0       */
 929   volatile u_int32_t BB_fcal_2_b1;                /*       0xd0 - 0xd4       */
 930   volatile u_int32_t BB_dft_tone_ctrl_b1;         /*       0xd4 - 0xd8       */
 931   volatile char pad__2[0x4];                      /*       0xd8 - 0xdc       */
 932   volatile u_int32_t BB_cl_map_0_b1;              /*       0xdc - 0xe0       */
 933   volatile u_int32_t BB_cl_map_1_b1;              /*       0xe0 - 0xe4       */
 934   volatile u_int32_t BB_cl_map_2_b1;              /*       0xe4 - 0xe8       */
 935   volatile u_int32_t BB_cl_map_3_b1;              /*       0xe8 - 0xec       */
 936   volatile u_int32_t BB_cl_map_pal_0_b1;          /*       0xec - 0xf0       */
 937   volatile u_int32_t BB_cl_map_pal_1_b1;          /*       0xf0 - 0xf4       */
 938   volatile u_int32_t BB_cl_map_pal_2_b1;          /*       0xf4 - 0xf8       */
 939   volatile u_int32_t BB_cl_map_pal_3_b1;          /*       0xf8 - 0xfc       */
 940   volatile char pad__3[0x4];                      /*       0xfc - 0x100      */
 941   volatile u_int32_t BB_cl_tab_b1[16];            /*      0x100 - 0x140      */
 942   volatile char pad__4[0x40];                     /*      0x140 - 0x180      */
 943   volatile u_int32_t BB_chan_info_gain_b1;        /*      0x180 - 0x184      */
 944   volatile char pad__5[0x80];                     /*      0x184 - 0x204      */
 945   volatile u_int32_t BB_tpc_4_b1;                 /*      0x204 - 0x208      */
 946   volatile u_int32_t BB_tpc_5_b1;                 /*      0x208 - 0x20c      */
 947   volatile u_int32_t BB_tpc_6_b1;                 /*      0x20c - 0x210      */
 948   volatile char pad__6[0x10];                     /*      0x210 - 0x220      */
 949   volatile u_int32_t BB_tpc_11_b1;                /*      0x220 - 0x224      */
 950   volatile char pad__7[0x1c];                     /*      0x224 - 0x240      */
 951   volatile u_int32_t BB_tpc_19_b1;                /*      0x240 - 0x244      */
 952   volatile char pad__8[0x3c];                     /*      0x244 - 0x280      */
 953   volatile u_int32_t BB_pdadc_tab_b1[32];         /*      0x280 - 0x300      */
 954   volatile char pad__9[0x84];                     /*      0x300 - 0x384      */
 955   volatile u_int32_t BB_rtt_table_sw_intf_b1;     /*      0x384 - 0x388      */
 956   volatile u_int32_t BB_rtt_table_sw_intf_1_b1;   /*      0x388 - 0x38c      */
 957   volatile char pad__10[0xc4];                    /*      0x38c - 0x450      */
 958   volatile u_int32_t BB_txiq_corr_coeff_01_b1;    /*      0x450 - 0x454      */
 959   volatile u_int32_t BB_txiq_corr_coeff_23_b1;    /*      0x454 - 0x458      */
 960   volatile u_int32_t BB_txiq_corr_coeff_45_b1;    /*      0x458 - 0x45c      */
 961   volatile u_int32_t BB_txiq_corr_coeff_67_b1;    /*      0x45c - 0x460      */
 962   volatile u_int32_t BB_txiq_corr_coeff_89_b1;    /*      0x460 - 0x464      */
 963   volatile u_int32_t BB_txiq_corr_coeff_ab_b1;    /*      0x464 - 0x468      */
 964   volatile u_int32_t BB_txiq_corr_coeff_cd_b1;    /*      0x468 - 0x46c      */
 965   volatile u_int32_t BB_txiq_corr_coeff_ef_b1;    /*      0x46c - 0x470      */
 966   volatile char pad__11[0x1c];                    /*      0x470 - 0x48c      */
 967   volatile u_int32_t BB_txiqcal_status_b1;        /*      0x48c - 0x490      */
 968   volatile char pad__12[0x160];                   /*      0x490 - 0x5f0      */
 969   volatile u_int32_t BB_tables_intf_addr_b1;      /*      0x5f0 - 0x5f4      */
 970   volatile u_int32_t BB_tables_intf_data_b1;      /*      0x5f4 - 0x5f8      */
 971 };
 972
 973 struct chn2_reg_map {
 974   volatile char pad__0[0x30];                     /*        0x0 - 0x30       */
 975   volatile u_int32_t BB_ext_chan_pwr_thr_2_b2;    /*       0x30 - 0x34       */
 976   volatile char pad__1[0x74];                     /*       0x34 - 0xa8       */
 977   volatile u_int32_t BB_spur_report_b2;           /*       0xa8 - 0xac       */
 978   volatile char pad__2[0x14];                     /*       0xac - 0xc0       */
 979   volatile u_int32_t BB_iq_adc_meas_0_b2;         /*       0xc0 - 0xc4       */
 980   volatile u_int32_t BB_iq_adc_meas_1_b2;         /*       0xc4 - 0xc8       */
 981   volatile u_int32_t BB_iq_adc_meas_2_b2;         /*       0xc8 - 0xcc       */
 982   volatile u_int32_t BB_iq_adc_meas_3_b2;         /*       0xcc - 0xd0       */
 983   volatile u_int32_t BB_tx_phase_ramp_b2;         /*       0xd0 - 0xd4       */
 984   volatile u_int32_t BB_adc_gain_dc_corr_b2;      /*       0xd4 - 0xd8       */
 985   volatile char pad__3[0x4];                      /*       0xd8 - 0xdc       */
 986   volatile u_int32_t BB_rx_iq_corr_b2;            /*       0xdc - 0xe0       */
 987   volatile char pad__4[0x10];                     /*       0xe0 - 0xf0       */
 988   volatile u_int32_t BB_paprd_ctrl0_b2;           /*       0xf0 - 0xf4       */
 989   volatile u_int32_t BB_paprd_ctrl1_b2;           /*       0xf4 - 0xf8       */
 990   volatile u_int32_t BB_pa_gain123_b2;            /*       0xf8 - 0xfc       */
 991   volatile u_int32_t BB_pa_gain45_b2;             /*       0xfc - 0x100      */
 992   volatile u_int32_t BB_paprd_pre_post_scale_0_b2;
 993                                                   /*      0x100 - 0x104      */
 994   volatile u_int32_t BB_paprd_pre_post_scale_1_b2;
 995                                                   /*      0x104 - 0x108      */
 996   volatile u_int32_t BB_paprd_pre_post_scale_2_b2;
 997                                                   /*      0x108 - 0x10c      */
 998   volatile u_int32_t BB_paprd_pre_post_scale_3_b2;
 999                                                   /*      0x10c - 0x110      */
1000   volatile u_int32_t BB_paprd_pre_post_scale_4_b2;
1001                                                   /*      0x110 - 0x114      */
1002   volatile u_int32_t BB_paprd_pre_post_scale_5_b2;
1003                                                   /*      0x114 - 0x118      */
1004   volatile u_int32_t BB_paprd_pre_post_scale_6_b2;
1005                                                   /*      0x118 - 0x11c      */
1006   volatile u_int32_t BB_paprd_pre_post_scale_7_b2;
1007                                                   /*      0x11c - 0x120      */
1008   volatile u_int32_t BB_paprd_mem_tab_b2[120];    /*      0x120 - 0x300      */
1009   volatile u_int32_t BB_chan_info_chan_tab_b2[60];
1010                                                   /*      0x300 - 0x3f0      */
1011   volatile u_int32_t BB_chn2_tables_intf_addr;    /*      0x3f0 - 0x3f4      */
1012   volatile u_int32_t BB_chn2_tables_intf_data;    /*      0x3f4 - 0x3f8      */
1013 };
1014
1015 struct agc2_reg_map {
1016   volatile char pad__0[0x4];                      /*        0x0 - 0x4        */
1017   volatile u_int32_t BB_gain_force_max_gains_b2;  /*        0x4 - 0x8        */
1018   volatile char pad__1[0x10];                     /*        0x8 - 0x18       */
1019   volatile u_int32_t BB_ext_atten_switch_ctl_b2;  /*       0x18 - 0x1c       */
1020   volatile u_int32_t BB_cca_b2;                   /*       0x1c - 0x20       */
1021   volatile u_int32_t BB_cca_ctrl_2_b2;            /*       0x20 - 0x24       */
1022   volatile char pad__2[0x15c];                    /*       0x24 - 0x180      */
1023   volatile u_int32_t BB_rssi_b2;                  /*      0x180 - 0x184      */
1024   volatile char pad__3[0x4];                      /*      0x184 - 0x188      */
1025   volatile u_int32_t BB_agc_dig_dc_status_i_b2;   /*      0x188 - 0x18c      */
1026   volatile u_int32_t BB_agc_dig_dc_status_q_b2;   /*      0x18c - 0x190      */
1027   volatile u_int32_t BB_dc_cal_status_b2;         /*      0x190 - 0x194      */
1028 };
1029
1030 struct sm2_reg_map {
1031   volatile char pad__0[0x84];                     /*        0x0 - 0x84       */
1032   volatile u_int32_t BB_switch_table_chn_b2;      /*       0x84 - 0x88       */
1033   volatile char pad__1[0x48];                     /*       0x88 - 0xd0       */
1034   volatile u_int32_t BB_fcal_2_b2;                /*       0xd0 - 0xd4       */
1035   volatile u_int32_t BB_dft_tone_ctrl_b2;         /*       0xd4 - 0xd8       */
1036   volatile char pad__2[0x4];                      /*       0xd8 - 0xdc       */
1037   volatile u_int32_t BB_cl_map_0_b2;              /*       0xdc - 0xe0       */
1038   volatile u_int32_t BB_cl_map_1_b2;              /*       0xe0 - 0xe4       */
1039   volatile u_int32_t BB_cl_map_2_b2;              /*       0xe4 - 0xe8       */
1040   volatile u_int32_t BB_cl_map_3_b2;              /*       0xe8 - 0xec       */
1041   volatile u_int32_t BB_cl_map_pal_0_b2;          /*       0xec - 0xf0       */
1042   volatile u_int32_t BB_cl_map_pal_1_b2;          /*       0xf0 - 0xf4       */
1043   volatile u_int32_t BB_cl_map_pal_2_b2;          /*       0xf4 - 0xf8       */
1044   volatile u_int32_t BB_cl_map_pal_3_b2;          /*       0xf8 - 0xfc       */
1045   volatile char pad__3[0x4];                      /*       0xfc - 0x100      */
1046   volatile u_int32_t BB_cl_tab_b2[16];            /*      0x100 - 0x140      */
1047   volatile char pad__4[0x40];                     /*      0x140 - 0x180      */
1048   volatile u_int32_t BB_chan_info_gain_b2;        /*      0x180 - 0x184      */
1049   volatile char pad__5[0x80];                     /*      0x184 - 0x204      */
1050   volatile u_int32_t BB_tpc_4_b2;                 /*      0x204 - 0x208      */
1051   volatile u_int32_t BB_tpc_5_b2;                 /*      0x208 - 0x20c      */
1052   volatile u_int32_t BB_tpc_6_b2;                 /*      0x20c - 0x210      */
1053   volatile char pad__6[0x10];                     /*      0x210 - 0x220      */
1054   volatile u_int32_t BB_tpc_11_b2;                /*      0x220 - 0x224      */
1055   volatile char pad__7[0x1c];                     /*      0x224 - 0x240      */
1056   volatile u_int32_t BB_tpc_19_b2;                /*      0x240 - 0x244      */
1057   volatile char pad__8[0x3c];                     /*      0x244 - 0x280      */
1058   volatile u_int32_t BB_pdadc_tab_b2[32];         /*      0x280 - 0x300      */
1059   volatile char pad__9[0x84];                     /*      0x300 - 0x384      */
1060   volatile u_int32_t BB_rtt_table_sw_intf_b2;     /*      0x384 - 0x388      */
1061   volatile u_int32_t BB_rtt_table_sw_intf_1_b2;   /*      0x388 - 0x38c      */
1062   volatile char pad__10[0xc4];                    /*      0x38c - 0x450      */
1063   volatile u_int32_t BB_txiq_corr_coeff_01_b2;    /*      0x450 - 0x454      */
1064   volatile u_int32_t BB_txiq_corr_coeff_23_b2;    /*      0x454 - 0x458      */
1065   volatile u_int32_t BB_txiq_corr_coeff_45_b2;    /*      0x458 - 0x45c      */
1066   volatile u_int32_t BB_txiq_corr_coeff_67_b2;    /*      0x45c - 0x460      */
1067   volatile u_int32_t BB_txiq_corr_coeff_89_b2;    /*      0x460 - 0x464      */
1068   volatile u_int32_t BB_txiq_corr_coeff_ab_b2;    /*      0x464 - 0x468      */
1069   volatile u_int32_t BB_txiq_corr_coeff_cd_b2;    /*      0x468 - 0x46c      */
1070   volatile u_int32_t BB_txiq_corr_coeff_ef_b2;    /*      0x46c - 0x470      */
1071   volatile char pad__11[0x1c];                    /*      0x470 - 0x48c      */
1072   volatile u_int32_t BB_txiqcal_status_b2;        /*      0x48c - 0x490      */
1073   volatile char pad__12[0x160];                   /*      0x490 - 0x5f0      */
1074   volatile u_int32_t BB_tables_intf_addr_b2;      /*      0x5f0 - 0x5f4      */
1075   volatile u_int32_t BB_tables_intf_data_b2;      /*      0x5f4 - 0x5f8      */
1076 };
1077
1078 struct chn3_reg_map {
1079   volatile u_int32_t BB_dummy1[256];              /*        0x0 - 0x400      */
1080 };
1081
1082 struct agc3_reg_map {
1083   volatile u_int32_t BB_dummy;                    /*        0x0 - 0x4        */
1084   volatile char pad__0[0x17c];                    /*        0x4 - 0x180      */
1085   volatile u_int32_t BB_rssi_b3;                  /*      0x180 - 0x184      */
1086 };
1087
1088 struct sm3_reg_map {
1089   volatile u_int32_t BB_dummy2[384];              /*        0x0 - 0x600      */
1090 };
1091
1092 struct bb_reg_map {
1093   struct chn_reg_map bb_chn_reg_map;              /*        0x0 - 0x3f8      */
1094   volatile char pad__0[0x8];                      /*      0x3f8 - 0x400      */
1095   struct mrc_reg_map bb_mrc_reg_map;              /*      0x400 - 0x424      */
1096   volatile char pad__1[0xdc];                     /*      0x424 - 0x500      */
1097   struct bbb_reg_map bb_bbb_reg_map;              /*      0x500 - 0x51c      */
1098   volatile char pad__2[0xe4];                     /*      0x51c - 0x600      */
1099   struct agc_reg_map bb_agc_reg_map;              /*      0x600 - 0xa00      */
1100   struct sm_reg_map bb_sm_reg_map;                /*      0xa00 - 0xff8      */
1101   volatile char pad__3[0x8];                      /*      0xff8 - 0x1000     */
1102   struct chn1_reg_map bb_chn1_reg_map;            /*     0x1000 - 0x13c8     */
1103   volatile char pad__4[0x238];                    /*     0x13c8 - 0x1600     */
1104   struct agc1_reg_map bb_agc1_reg_map;            /*     0x1600 - 0x19fc     */
1105   volatile char pad__5[0x4];                      /*     0x19fc - 0x1a00     */
1106   struct sm1_reg_map bb_sm1_reg_map;              /*     0x1a00 - 0x1f74     */
1107   volatile char pad__6[0x8c];                     /*     0x1f74 - 0x2000     */
1108   struct chn2_reg_map bb_chn2_reg_map;            /*     0x2000 - 0x23c8     */
1109   volatile char pad__7[0x238];                    /*     0x23c8 - 0x2600     */
1110   struct agc2_reg_map bb_agc2_reg_map;            /*     0x2600 - 0x2790     */
1111   volatile char pad__8[0x270];                    /*     0x2790 - 0x2a00     */
1112   struct sm2_reg_map bb_sm2_reg_map;              /*     0x2a00 - 0x2f74     */
1113   volatile char pad__9[0x8c];                     /*     0x2f74 - 0x3000     */
1114   struct chn3_reg_map bb_chn3_reg_map;            /*     0x3000 - 0x3400     */
1115   volatile char pad__10[0x200];                   /*     0x3400 - 0x3600     */
1116   struct agc3_reg_map bb_agc3_reg_map;            /*     0x3600 - 0x3784     */
1117   volatile char pad__11[0x27c];                   /*     0x3784 - 0x3a00     */
1118   struct sm3_reg_map bb_sm3_reg_map;              /*     0x3a00 - 0x4000     */
1119 };
1120
1121 struct mac_pcu_buf_reg {
1122   volatile u_int32_t MAC_PCU_BUF[2048];           /*        0x0 - 0x2000     */
1123 };
1124
1125 struct svd_reg {
1126   volatile u_int32_t TXBF_DBG;                    /*        0x0 - 0x4        */
1127   volatile u_int32_t TXBF;                        /*        0x4 - 0x8        */
1128   volatile u_int32_t TXBF_TIMER;                  /*        0x8 - 0xc        */
1129   volatile u_int32_t TXBF_SW;                     /*        0xc - 0x10       */
1130   volatile u_int32_t TXBF_SM;                     /*       0x10 - 0x14       */
1131   volatile u_int32_t TXBF1_CNTL;                  /*       0x14 - 0x18       */
1132   volatile u_int32_t TXBF2_CNTL;                  /*       0x18 - 0x1c       */
1133   volatile u_int32_t TXBF3_CNTL;                  /*       0x1c - 0x20       */
1134   volatile u_int32_t TXBF4_CNTL;                  /*       0x20 - 0x24       */
1135   volatile u_int32_t TXBF5_CNTL;                  /*       0x24 - 0x28       */
1136   volatile u_int32_t TXBF6_CNTL;                  /*       0x28 - 0x2c       */
1137   volatile u_int32_t TXBF7_CNTL;                  /*       0x2c - 0x30       */
1138   volatile u_int32_t TXBF8_CNTL;                  /*       0x30 - 0x34       */
1139   volatile char pad__0[0xfcc];                    /*       0x34 - 0x1000     */
1140   volatile u_int32_t RC0[118];                    /*     0x1000 - 0x11d8     */
1141   volatile char pad__1[0x28];                     /*     0x11d8 - 0x1200     */
1142   volatile u_int32_t RC1[118];                    /*     0x1200 - 0x13d8     */
1143   volatile char pad__2[0x28];                     /*     0x13d8 - 0x1400     */
1144   volatile u_int32_t SVD_MEM0[114];               /*     0x1400 - 0x15c8     */
1145   volatile char pad__3[0x38];                     /*     0x15c8 - 0x1600     */
1146   volatile u_int32_t SVD_MEM1[114];               /*     0x1600 - 0x17c8     */
1147   volatile char pad__4[0x38];                     /*     0x17c8 - 0x1800     */
1148   volatile u_int32_t SVD_MEM2[114];               /*     0x1800 - 0x19c8     */
1149   volatile char pad__5[0x38];                     /*     0x19c8 - 0x1a00     */
1150   volatile u_int32_t SVD_MEM3[114];               /*     0x1a00 - 0x1bc8     */
1151   volatile char pad__6[0x38];                     /*     0x1bc8 - 0x1c00     */
1152   volatile u_int32_t SVD_MEM4[114];               /*     0x1c00 - 0x1dc8     */
1153   volatile char pad__7[0x638];                    /*     0x1dc8 - 0x2400     */
1154   volatile u_int32_t CVCACHE[512];                /*     0x2400 - 0x2c00     */
1155 };
1156
1157 struct radio65_reg {
1158   volatile u_int32_t ch0_RXRF_BIAS1;              /*        0x0 - 0x4        */
1159   volatile u_int32_t ch0_RXRF_BIAS2;              /*        0x4 - 0x8        */
1160   volatile u_int32_t ch0_RXRF_GAINSTAGES;         /*        0x8 - 0xc        */
1161   volatile u_int32_t ch0_RXRF_AGC;                /*        0xc - 0x10       */
1162   volatile char pad__0[0x30];                     /*       0x10 - 0x40       */
1163   volatile u_int32_t ch0_TXRF1;                   /*       0x40 - 0x44       */
1164   volatile u_int32_t ch0_TXRF2;                   /*       0x44 - 0x48       */
1165   volatile u_int32_t ch0_TXRF3;                   /*       0x48 - 0x4c       */
1166   volatile u_int32_t ch0_TXRF4;                   /*       0x4c - 0x50       */
1167   volatile u_int32_t ch0_TXRF5;                   /*       0x50 - 0x54       */
1168   volatile u_int32_t ch0_TXRF6;                   /*       0x54 - 0x58       */
1169   volatile char pad__1[0x28];                     /*       0x58 - 0x80       */
1170   volatile u_int32_t ch0_SYNTH1;                  /*       0x80 - 0x84       */
1171   volatile u_int32_t ch0_SYNTH2;                  /*       0x84 - 0x88       */
1172   volatile u_int32_t ch0_SYNTH3;                  /*       0x88 - 0x8c       */
1173   volatile u_int32_t ch0_SYNTH4;                  /*       0x8c - 0x90       */
1174   volatile u_int32_t ch0_SYNTH5;                  /*       0x90 - 0x94       */
1175   volatile u_int32_t ch0_SYNTH6;                  /*       0x94 - 0x98       */
1176   volatile u_int32_t ch0_SYNTH7;                  /*       0x98 - 0x9c       */
1177   volatile u_int32_t ch0_SYNTH8;                  /*       0x9c - 0xa0       */
1178   volatile u_int32_t ch0_SYNTH9;                  /*       0xa0 - 0xa4       */
1179   volatile u_int32_t ch0_SYNTH10;                 /*       0xa4 - 0xa8       */
1180   volatile u_int32_t ch0_SYNTH11;                 /*       0xa8 - 0xac       */
1181   volatile u_int32_t ch0_SYNTH12;                 /*       0xac - 0xb0       */
1182   volatile u_int32_t ch0_SYNTH13;                 /*       0xb0 - 0xb4       */
1183   volatile u_int32_t ch0_SYNTH14;                 /*       0xb4 - 0xb8       */
1184   volatile char pad__2[0x8];                      /*       0xb8 - 0xc0       */
1185   volatile u_int32_t ch0_BIAS1;                   /*       0xc0 - 0xc4       */
1186   volatile u_int32_t ch0_BIAS2;                   /*       0xc4 - 0xc8       */
1187   volatile u_int32_t ch0_BIAS3;                   /*       0xc8 - 0xcc       */
1188   volatile u_int32_t ch0_BIAS4;                   /*       0xcc - 0xd0       */
1189   volatile char pad__3[0x30];                     /*       0xd0 - 0x100      */
1190   volatile u_int32_t ch0_RXTX1;                   /*      0x100 - 0x104      */
1191   volatile u_int32_t ch0_RXTX2;                   /*      0x104 - 0x108      */
1192   volatile u_int32_t ch0_RXTX3;                   /*      0x108 - 0x10c      */
1193   volatile u_int32_t ch0_RXTX4;                   /*      0x10c - 0x110      */
1194   volatile char pad__4[0x30];                     /*      0x110 - 0x140      */
1195   volatile u_int32_t ch0_BB1;                     /*      0x140 - 0x144      */
1196   volatile u_int32_t ch0_BB2;                     /*      0x144 - 0x148      */
1197   volatile u_int32_t ch0_BB3;                     /*      0x148 - 0x14c      */
1198   volatile char pad__5[0x34];                     /*      0x14c - 0x180      */
1199   volatile u_int32_t ch0_BB_PLL;                  /*      0x180 - 0x184      */
1200   volatile u_int32_t ch0_BB_PLL2;                 /*      0x184 - 0x188      */
1201   volatile u_int32_t ch0_BB_PLL3;                 /*      0x188 - 0x18c      */
1202   volatile u_int32_t ch0_BB_PLL4;                 /*      0x18c - 0x190      */
1203   volatile char pad__6[0x30];                     /*      0x190 - 0x1c0      */
1204   volatile u_int32_t ch0_CPU_PLL;                 /*      0x1c0 - 0x1c4      */
1205   volatile u_int32_t ch0_CPU_PLL2;                /*      0x1c4 - 0x1c8      */
1206   volatile u_int32_t ch0_CPU_PLL3;                /*      0x1c8 - 0x1cc      */
1207   volatile u_int32_t ch0_CPU_PLL4;                /*      0x1cc - 0x1d0      */
1208   volatile char pad__7[0x30];                     /*      0x1d0 - 0x200      */
1209   volatile u_int32_t ch0_AUDIO_PLL;               /*      0x200 - 0x204      */
1210   volatile u_int32_t ch0_AUDIO_PLL2;              /*      0x204 - 0x208      */
1211   volatile u_int32_t ch0_AUDIO_PLL3;              /*      0x208 - 0x20c      */
1212   volatile u_int32_t ch0_AUDIO_PLL4;              /*      0x20c - 0x210      */
1213   volatile char pad__8[0x30];                     /*      0x210 - 0x240      */
1214   volatile u_int32_t ch0_DDR_PLL;                 /*      0x240 - 0x244      */
1215   volatile u_int32_t ch0_DDR_PLL2;                /*      0x244 - 0x248      */
1216   volatile u_int32_t ch0_DDR_PLL3;                /*      0x248 - 0x24c      */
1217   volatile u_int32_t ch0_DDR_PLL4;                /*      0x24c - 0x250      */
1218   volatile char pad__9[0x30];                     /*      0x250 - 0x280      */
1219   volatile u_int32_t ch0_TOP;                     /*      0x280 - 0x284      */
1220   volatile u_int32_t ch0_TOP2;                    /*      0x284 - 0x288      */
1221   volatile u_int32_t ch0_TOP3;                    /*      0x288 - 0x28c      */
1222   volatile u_int32_t ch0_THERM;                   /*      0x28c - 0x290      */
1223   volatile u_int32_t ch0_XTAL;                    /*      0x290 - 0x294      */
1224   volatile char pad__10[0xec];                    /*      0x294 - 0x380      */
1225   volatile u_int32_t ch0_rbist_cntrl;             /*      0x380 - 0x384      */
1226   volatile u_int32_t ch0_tx_dc_offset;            /*      0x384 - 0x388      */
1227   volatile u_int32_t ch0_tx_tonegen0;             /*      0x388 - 0x38c      */
1228   volatile u_int32_t ch0_tx_tonegen1;             /*      0x38c - 0x390      */
1229   volatile u_int32_t ch0_tx_lftonegen0;           /*      0x390 - 0x394      */
1230   volatile u_int32_t ch0_tx_linear_ramp_i;        /*      0x394 - 0x398      */
1231   volatile u_int32_t ch0_tx_linear_ramp_q;        /*      0x398 - 0x39c      */
1232   volatile u_int32_t ch0_tx_prbs_mag;             /*      0x39c - 0x3a0      */
1233   volatile u_int32_t ch0_tx_prbs_seed_i;          /*      0x3a0 - 0x3a4      */
1234   volatile u_int32_t ch0_tx_prbs_seed_q;          /*      0x3a4 - 0x3a8      */
1235   volatile u_int32_t ch0_cmac_dc_cancel;          /*      0x3a8 - 0x3ac      */
1236   volatile u_int32_t ch0_cmac_dc_offset;          /*      0x3ac - 0x3b0      */
1237   volatile u_int32_t ch0_cmac_corr;               /*      0x3b0 - 0x3b4      */
1238   volatile u_int32_t ch0_cmac_power;              /*      0x3b4 - 0x3b8      */
1239   volatile u_int32_t ch0_cmac_cross_corr;         /*      0x3b8 - 0x3bc      */
1240   volatile u_int32_t ch0_cmac_i2q2;               /*      0x3bc - 0x3c0      */
1241   volatile u_int32_t ch0_cmac_power_hpf;          /*      0x3c0 - 0x3c4      */
1242   volatile u_int32_t ch0_rxdac_set1;              /*      0x3c4 - 0x3c8      */
1243   volatile u_int32_t ch0_rxdac_set2;              /*      0x3c8 - 0x3cc      */
1244   volatile u_int32_t ch0_rxdac_long_shift;        /*      0x3cc - 0x3d0      */
1245   volatile u_int32_t ch0_cmac_results_i;          /*      0x3d0 - 0x3d4      */
1246   volatile u_int32_t ch0_cmac_results_q;          /*      0x3d4 - 0x3d8      */
1247   volatile char pad__11[0x28];                    /*      0x3d8 - 0x400      */
1248   volatile u_int32_t ch1_RXRF_BIAS1;              /*      0x400 - 0x404      */
1249   volatile u_int32_t ch1_RXRF_BIAS2;              /*      0x404 - 0x408      */
1250   volatile u_int32_t ch1_RXRF_GAINSTAGES;         /*      0x408 - 0x40c      */
1251   volatile u_int32_t ch1_RXRF_AGC;                /*      0x40c - 0x410      */
1252   volatile char pad__12[0x30];                    /*      0x410 - 0x440      */
1253   volatile u_int32_t ch1_TXRF1;                   /*      0x440 - 0x444      */
1254   volatile u_int32_t ch1_TXRF2;                   /*      0x444 - 0x448      */
1255   volatile u_int32_t ch1_TXRF3;                   /*      0x448 - 0x44c      */
1256   volatile u_int32_t ch1_TXRF4;                   /*      0x44c - 0x450      */
1257   volatile u_int32_t ch1_TXRF5;                   /*      0x450 - 0x454      */
1258   volatile u_int32_t ch1_TXRF6;                   /*      0x454 - 0x458      */
1259   volatile char pad__13[0xa8];                    /*      0x458 - 0x500      */
1260   volatile u_int32_t ch1_RXTX1;                   /*      0x500 - 0x504      */
1261   volatile u_int32_t ch1_RXTX2;                   /*      0x504 - 0x508      */
1262   volatile u_int32_t ch1_RXTX3;                   /*      0x508 - 0x50c      */
1263   volatile u_int32_t ch1_RXTX4;                   /*      0x50c - 0x510      */
1264   volatile char pad__14[0x30];                    /*      0x510 - 0x540      */
1265   volatile u_int32_t ch1_BB1;                     /*      0x540 - 0x544      */
1266   volatile u_int32_t ch1_BB2;                     /*      0x544 - 0x548      */
1267   volatile u_int32_t ch1_BB3;                     /*      0x548 - 0x54c      */
1268   volatile char pad__15[0x234];                   /*      0x54c - 0x780      */
1269   volatile u_int32_t ch1_rbist_cntrl;             /*      0x780 - 0x784      */
1270   volatile u_int32_t ch1_tx_dc_offset;            /*      0x784 - 0x788      */
1271   volatile u_int32_t ch1_tx_tonegen0;             /*      0x788 - 0x78c      */
1272   volatile u_int32_t ch1_tx_tonegen1;             /*      0x78c - 0x790      */
1273   volatile u_int32_t ch1_tx_lftonegen0;           /*      0x790 - 0x794      */
1274   volatile u_int32_t ch1_tx_linear_ramp_i;        /*      0x794 - 0x798      */
1275   volatile u_int32_t ch1_tx_linear_ramp_q;        /*      0x798 - 0x79c      */
1276   volatile u_int32_t ch1_tx_prbs_mag;             /*      0x79c - 0x7a0      */
1277   volatile u_int32_t ch1_tx_prbs_seed_i;          /*      0x7a0 - 0x7a4      */
1278   volatile u_int32_t ch1_tx_prbs_seed_q;          /*      0x7a4 - 0x7a8      */
1279   volatile u_int32_t ch1_cmac_dc_cancel;          /*      0x7a8 - 0x7ac      */
1280   volatile u_int32_t ch1_cmac_dc_offset;          /*      0x7ac - 0x7b0      */
1281   volatile u_int32_t ch1_cmac_corr;               /*      0x7b0 - 0x7b4      */
1282   volatile u_int32_t ch1_cmac_power;              /*      0x7b4 - 0x7b8      */
1283   volatile u_int32_t ch1_cmac_cross_corr;         /*      0x7b8 - 0x7bc      */
1284   volatile u_int32_t ch1_cmac_i2q2;               /*      0x7bc - 0x7c0      */
1285   volatile u_int32_t ch1_cmac_power_hpf;          /*      0x7c0 - 0x7c4      */
1286   volatile u_int32_t ch1_rxdac_set1;              /*      0x7c4 - 0x7c8      */
1287   volatile u_int32_t ch1_rxdac_set2;              /*      0x7c8 - 0x7cc      */
1288   volatile u_int32_t ch1_rxdac_long_shift;        /*      0x7cc - 0x7d0      */
1289   volatile u_int32_t ch1_cmac_results_i;          /*      0x7d0 - 0x7d4      */
1290   volatile u_int32_t ch1_cmac_results_q;          /*      0x7d4 - 0x7d8      */
1291   volatile char pad__16[0x28];                    /*      0x7d8 - 0x800      */
1292   volatile u_int32_t ch2_RXRF_BIAS1;              /*      0x800 - 0x804      */
1293   volatile u_int32_t ch2_RXRF_BIAS2;              /*      0x804 - 0x808      */
1294   volatile u_int32_t ch2_RXRF_GAINSTAGES;         /*      0x808 - 0x80c      */
1295   volatile u_int32_t ch2_RXRF_AGC;                /*      0x80c - 0x810      */
1296   volatile char pad__17[0x30];                    /*      0x810 - 0x840      */
1297   volatile u_int32_t ch2_TXRF1;                   /*      0x840 - 0x844      */
1298   volatile u_int32_t ch2_TXRF2;                   /*      0x844 - 0x848      */
1299   volatile u_int32_t ch2_TXRF3;                   /*      0x848 - 0x84c      */
1300   volatile u_int32_t ch2_TXRF4;                   /*      0x84c - 0x850      */
1301   volatile u_int32_t ch2_TXRF5;                   /*      0x850 - 0x854      */
1302   volatile u_int32_t ch2_TXRF6;                   /*      0x854 - 0x858      */
1303   volatile char pad__18[0xa8];                    /*      0x858 - 0x900      */
1304   volatile u_int32_t ch2_RXTX1;                   /*      0x900 - 0x904      */
1305   volatile u_int32_t ch2_RXTX2;                   /*      0x904 - 0x908      */
1306   volatile u_int32_t ch2_RXTX3;                   /*      0x908 - 0x90c      */
1307   volatile u_int32_t ch2_RXTX4;                   /*      0x90c - 0x910      */
1308   volatile char pad__19[0x30];                    /*      0x910 - 0x940      */
1309   volatile u_int32_t ch2_BB1;                     /*      0x940 - 0x944      */
1310   volatile u_int32_t ch2_BB2;                     /*      0x944 - 0x948      */
1311   volatile u_int32_t ch2_BB3;                     /*      0x948 - 0x94c      */
1312   volatile char pad__20[0x234];                   /*      0x94c - 0xb80      */
1313   volatile u_int32_t ch2_rbist_cntrl;             /*      0xb80 - 0xb84      */
1314   volatile u_int32_t ch2_tx_dc_offset;            /*      0xb84 - 0xb88      */
1315   volatile u_int32_t ch2_tx_tonegen0;             /*      0xb88 - 0xb8c      */
1316   volatile u_int32_t ch2_tx_tonegen1;             /*      0xb8c - 0xb90      */
1317   volatile u_int32_t ch2_tx_lftonegen0;           /*      0xb90 - 0xb94      */
1318   volatile u_int32_t ch2_tx_linear_ramp_i;        /*      0xb94 - 0xb98      */
1319   volatile u_int32_t ch2_tx_linear_ramp_q;        /*      0xb98 - 0xb9c      */
1320   volatile u_int32_t ch2_tx_prbs_mag;             /*      0xb9c - 0xba0      */
1321   volatile u_int32_t ch2_tx_prbs_seed_i;          /*      0xba0 - 0xba4      */
1322   volatile u_int32_t ch2_tx_prbs_seed_q;          /*      0xba4 - 0xba8      */
1323   volatile u_int32_t ch2_cmac_dc_cancel;          /*      0xba8 - 0xbac      */
1324   volatile u_int32_t ch2_cmac_dc_offset;          /*      0xbac - 0xbb0      */
1325   volatile u_int32_t ch2_cmac_corr;               /*      0xbb0 - 0xbb4      */
1326   volatile u_int32_t ch2_cmac_power;              /*      0xbb4 - 0xbb8      */
1327   volatile u_int32_t ch2_cmac_cross_corr;         /*      0xbb8 - 0xbbc      */
1328   volatile u_int32_t ch2_cmac_i2q2;               /*      0xbbc - 0xbc0      */
1329   volatile u_int32_t ch2_cmac_power_hpf;          /*      0xbc0 - 0xbc4      */
1330   volatile u_int32_t ch2_rxdac_set1;              /*      0xbc4 - 0xbc8      */
1331   volatile u_int32_t ch2_rxdac_set2;              /*      0xbc8 - 0xbcc      */
1332   volatile u_int32_t ch2_rxdac_long_shift;        /*      0xbcc - 0xbd0      */
1333   volatile u_int32_t ch2_cmac_results_i;          /*      0xbd0 - 0xbd4      */
1334   volatile u_int32_t ch2_cmac_results_q;          /*      0xbd4 - 0xbd8      */
1335 };
1336
1337 struct scorpion_reg_map {
1338   struct mac_dma_reg mac_dma_reg_map;             /*        0x0 - 0x128      */
1339   volatile char pad__0[0x6d8];                    /*      0x128 - 0x800      */
1340   struct mac_qcu_reg mac_qcu_reg_map;             /*      0x800 - 0xa48      */
1341   volatile char pad__1[0x5b8];                    /*      0xa48 - 0x1000     */
1342   struct mac_dcu_reg mac_dcu_reg_map;             /*     0x1000 - 0x1f08     */
1343   volatile char pad__2[0x50f8];                   /*     0x1f08 - 0x7000     */
1344   struct rtc_reg rtc_reg_map;                     /*     0x7000 - 0x7040     */
1345   struct rtc_sync_reg rtc_sync_reg_map;           /*     0x7040 - 0x705c     */
1346   volatile char pad__3[0xfa4];                    /*     0x705c - 0x8000     */
1347   struct mac_pcu_reg mac_pcu_reg_map;             /*     0x8000 - 0x9800     */
1348   struct bb_reg_map bb_reg_map;                   /*     0x9800 - 0xd800     */
1349   volatile char pad__4[0x800];                    /*     0xd800 - 0xe000     */
1350   struct mac_pcu_buf_reg mac_pcu_buf_reg_map;     /*     0xe000 - 0x10000    */
1351   struct svd_reg svd_reg_map;                     /*    0x10000 - 0x12c00    */
1352   volatile char pad__5[0x3400];                   /*    0x12c00 - 0x16000    */
1353   struct radio65_reg radio65_reg_map;             /*    0x16000 - 0x16bd8    */
1354 };
1355
1356 #endif /* __REG_SCORPION_REG_MAP_H__ */