sys/contrib/dev/ath/ath_hal/ar9300/wasp_reg_map.h

   1 /*
   2  * Copyright (c) 2013 Qualcomm Atheros, Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
   9  * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
  10  * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
  11  * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
  12  * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
  13  * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  14  * PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef __REG_WASP_REG_MAP_H__
  18
  19 struct host_intf_reg_ar9340 {
  20   volatile char pad__0[0x4000];                   /*        0x0 - 0x4000     */
  21   volatile u_int32_t HOST_INTF_RESET_CONTROL;     /*     0x4000 - 0x4004     */
  22   volatile u_int32_t HOST_INTF_PM_CTRL;           /*     0x4004 - 0x4008     */
  23   volatile u_int32_t HOST_INTF_TIMEOUT;           /*     0x4008 - 0x400c     */
  24   volatile u_int32_t HOST_INTF_SREV;              /*     0x400c - 0x4010     */
  25   volatile u_int32_t HOST_INTF_INTR_SYNC_CAUSE;   /*     0x4010 - 0x4014     */
  26   volatile u_int32_t HOST_INTF_INTR_SYNC_ENABLE;  /*     0x4014 - 0x4018     */
  27   volatile u_int32_t HOST_INTF_INTR_ASYNC_MASK;   /*     0x4018 - 0x401c     */
  28   volatile u_int32_t HOST_INTF_INTR_SYNC_MASK;    /*     0x401c - 0x4020     */
  29   volatile u_int32_t HOST_INTF_INTR_ASYNC_CAUSE;  /*     0x4020 - 0x4024     */
  30   volatile u_int32_t HOST_INTF_INTR_ASYNC_ENABLE; /*     0x4024 - 0x4028     */
  31   volatile u_int32_t HOST_INTF_GPIO_OUT;          /*     0x4028 - 0x402c     */
  32   volatile u_int32_t HOST_INTF_GPIO_IN;           /*     0x402c - 0x4030     */
  33   volatile u_int32_t HOST_INTF_GPIO_OE;           /*     0x4030 - 0x4034     */
  34   volatile u_int32_t HOST_INTF_GPIO_OE1;          /*     0x4034 - 0x4038     */
  35   volatile u_int32_t HOST_INTF_GPIO_INTR_POLAR;   /*     0x4038 - 0x403c     */
  36   volatile u_int32_t HOST_INTF_GPIO_INPUT_VALUE;  /*     0x403c - 0x4040     */
  37   volatile u_int32_t HOST_INTF_GPIO_INPUT_MUX1;   /*     0x4040 - 0x4044     */
  38   volatile u_int32_t HOST_INTF_GPIO_INPUT_MUX2;   /*     0x4044 - 0x4048     */
  39   volatile u_int32_t HOST_INTF_GPIO_OUTPUT_MUX1;  /*     0x4048 - 0x404c     */
  40   volatile u_int32_t HOST_INTF_GPIO_OUTPUT_MUX2;  /*     0x404c - 0x4050     */
  41   volatile u_int32_t HOST_INTF_GPIO_OUTPUT_MUX3;  /*     0x4050 - 0x4054     */
  42   volatile u_int32_t HOST_INTF_GPIO_INPUT_STATE;  /*     0x4054 - 0x4058     */
  43   volatile u_int32_t HOST_INTF_CLKRUN;            /*     0x4058 - 0x405c     */
  44   volatile u_int32_t HOST_INTF_OBS_CTRL;          /*     0x405c - 0x4060     */
  45   volatile u_int32_t HOST_INTF_RFSILENT;          /*     0x4060 - 0x4064     */
  46   volatile char pad__3[0x10];                     /*     0x4064 - 0x4074     */
  47   volatile u_int32_t HOST_INTF_MISC;              /*     0x4074 - 0x4078     */
  48   volatile u_int32_t HOST_INTF_MAC_TDMA_CCA_CNTL; /*     0x4078 - 0x407c     */
  49   volatile u_int32_t HOST_INTF_MAC_TXAPSYNC;      /*     0x407c - 0x4080     */
  50   volatile u_int32_t HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR;
  51                                                   /*     0x4080 - 0x4084     */
  52   volatile u_int32_t HOST_INTF_INTR_PRIORITY_SYNC_CAUSE;
  53                                                   /*     0x4084 - 0x4088     */
  54   volatile u_int32_t HOST_INTF_INTR_PRIORITY_SYNC_ENABLE;
  55                                                   /*     0x4088 - 0x408c     */
  56   volatile u_int32_t HOST_INTF_INTR_PRIORITY_ASYNC_MASK;
  57                                                   /*     0x408c - 0x4090     */
  58   volatile u_int32_t HOST_INTF_INTR_PRIORITY_SYNC_MASK;
  59                                                   /*     0x4090 - 0x4094     */
  60   volatile u_int32_t HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE;
  61                                                   /*     0x4094 - 0x4098     */
  62   volatile u_int32_t HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE;
  63                                                   /*     0x4098 - 0x409c     */
  64   volatile u_int32_t HOST_INTF_AXI_BYTE_SWAP;     /*     0x409c - 0x40a0     */
  65   volatile char pad__4[0x20];                     /*     0x40a4 - 0x40c4     */
  66   volatile u_int32_t HOST_INTF_WORK_AROUND;       /*     0x40c4 - 0x40c8     */
  67   volatile u_int32_t HOST_INTF_EEPROM_STS;        /*     0x40c8 - 0x40cc     */
  68   volatile u_int32_t HOST_INTF_PCIE_MSI;          /*     0x40d8 - 0x40dc     */
  69 };
  70
  71 #endif /* __REG_WASP_REG_MAP_H__ */