sys/contrib/octeon-sdk/cvmx-mixx-defs.h

   1 /***********************license start***************
   2  * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
   3  * reserved.
   4  *
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met:
   9  *
  10  *   * Redistributions of source code must retain the above copyright
  11  *     notice, this list of conditions and the following disclaimer.
  12  *
  13  *   * Redistributions in binary form must reproduce the above
  14  *     copyright notice, this list of conditions and the following
  15  *     disclaimer in the documentation and/or other materials provided
  16  *     with the distribution.
  17
  18  *   * Neither the name of Cavium Inc. nor the names of
  19  *     its contributors may be used to endorse or promote products
  20  *     derived from this software without specific prior written
  21  *     permission.
  22
  23  * This Software, including technical data, may be subject to U.S. export  control
  24  * laws, including the U.S. Export Administration Act and its  associated
  25  * regulations, and may be subject to export or import  regulations in other
  26  * countries.
  27
  28  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
  29  * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  30  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  31  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  32  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
  33  * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
  34  * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
  35  * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
  36  * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
  37  * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
  38  ***********************license end**************************************/
  39
  40
  41 /**
  42  * cvmx-mixx-defs.h
  43  *
  44  * Configuration and status register (CSR) type definitions for
  45  * Octeon mixx.
  46  *
  47  * This file is auto generated. Do not edit.
  48  *
  49  * <hr>$Revision$<hr>
  50  *
  51  */
  52 #ifndef __CVMX_MIXX_DEFS_H__
  53 #define __CVMX_MIXX_DEFS_H__
  54
  55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
  56 static inline uint64_t CVMX_MIXX_BIST(unsigned long offset)
  57 {
  58         if (!(
  59               (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
  60               (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
  61               (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
  62               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
  63               (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
  64               (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
  65                 cvmx_warn("CVMX_MIXX_BIST(%lu) is invalid on this chip\n", offset);
  66         return CVMX_ADD_IO_SEG(0x0001070000100078ull) + ((offset) & 1) * 2048;
  67 }
  68 #else
  69 #define CVMX_MIXX_BIST(offset) (CVMX_ADD_IO_SEG(0x0001070000100078ull) + ((offset) & 1) * 2048)
  70 #endif
  71 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
  72 static inline uint64_t CVMX_MIXX_CTL(unsigned long offset)
  73 {
  74         if (!(
  75               (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
  76               (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
  77               (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
  78               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
  79               (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
  80               (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
  81                 cvmx_warn("CVMX_MIXX_CTL(%lu) is invalid on this chip\n", offset);
  82         return CVMX_ADD_IO_SEG(0x0001070000100020ull) + ((offset) & 1) * 2048;
  83 }
  84 #else
  85 #define CVMX_MIXX_CTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100020ull) + ((offset) & 1) * 2048)
  86 #endif
  87 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
  88 static inline uint64_t CVMX_MIXX_INTENA(unsigned long offset)
  89 {
  90         if (!(
  91               (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
  92               (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
  93               (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
  94               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
  95               (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
  96               (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
  97                 cvmx_warn("CVMX_MIXX_INTENA(%lu) is invalid on this chip\n", offset);
  98         return CVMX_ADD_IO_SEG(0x0001070000100050ull) + ((offset) & 1) * 2048;
  99 }
 100 #else
 101 #define CVMX_MIXX_INTENA(offset) (CVMX_ADD_IO_SEG(0x0001070000100050ull) + ((offset) & 1) * 2048)
 102 #endif
 103 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 104 static inline uint64_t CVMX_MIXX_IRCNT(unsigned long offset)
 105 {
 106         if (!(
 107               (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 108               (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
 109               (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
 110               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
 111               (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
 112               (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 113                 cvmx_warn("CVMX_MIXX_IRCNT(%lu) is invalid on this chip\n", offset);
 114         return CVMX_ADD_IO_SEG(0x0001070000100030ull) + ((offset) & 1) * 2048;
 115 }
 116 #else
 117 #define CVMX_MIXX_IRCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100030ull) + ((offset) & 1) * 2048)
 118 #endif
 119 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 120 static inline uint64_t CVMX_MIXX_IRHWM(unsigned long offset)
 121 {
 122         if (!(
 123               (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 124               (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
 125               (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
 126               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
 127               (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
 128               (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 129                 cvmx_warn("CVMX_MIXX_IRHWM(%lu) is invalid on this chip\n", offset);
 130         return CVMX_ADD_IO_SEG(0x0001070000100028ull) + ((offset) & 1) * 2048;
 131 }
 132 #else
 133 #define CVMX_MIXX_IRHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100028ull) + ((offset) & 1) * 2048)
 134 #endif
 135 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 136 static inline uint64_t CVMX_MIXX_IRING1(unsigned long offset)
 137 {
 138         if (!(
 139               (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 140               (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
 141               (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
 142               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
 143               (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
 144               (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 145                 cvmx_warn("CVMX_MIXX_IRING1(%lu) is invalid on this chip\n", offset);
 146         return CVMX_ADD_IO_SEG(0x0001070000100010ull) + ((offset) & 1) * 2048;
 147 }
 148 #else
 149 #define CVMX_MIXX_IRING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100010ull) + ((offset) & 1) * 2048)
 150 #endif
 151 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 152 static inline uint64_t CVMX_MIXX_IRING2(unsigned long offset)
 153 {
 154         if (!(
 155               (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 156               (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
 157               (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
 158               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
 159               (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
 160               (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 161                 cvmx_warn("CVMX_MIXX_IRING2(%lu) is invalid on this chip\n", offset);
 162         return CVMX_ADD_IO_SEG(0x0001070000100018ull) + ((offset) & 1) * 2048;
 163 }
 164 #else
 165 #define CVMX_MIXX_IRING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100018ull) + ((offset) & 1) * 2048)
 166 #endif
 167 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 168 static inline uint64_t CVMX_MIXX_ISR(unsigned long offset)
 169 {
 170         if (!(
 171               (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 172               (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
 173               (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
 174               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
 175               (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
 176               (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 177                 cvmx_warn("CVMX_MIXX_ISR(%lu) is invalid on this chip\n", offset);
 178         return CVMX_ADD_IO_SEG(0x0001070000100048ull) + ((offset) & 1) * 2048;
 179 }
 180 #else
 181 #define CVMX_MIXX_ISR(offset) (CVMX_ADD_IO_SEG(0x0001070000100048ull) + ((offset) & 1) * 2048)
 182 #endif
 183 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 184 static inline uint64_t CVMX_MIXX_ORCNT(unsigned long offset)
 185 {
 186         if (!(
 187               (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 188               (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
 189               (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
 190               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
 191               (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
 192               (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 193                 cvmx_warn("CVMX_MIXX_ORCNT(%lu) is invalid on this chip\n", offset);
 194         return CVMX_ADD_IO_SEG(0x0001070000100040ull) + ((offset) & 1) * 2048;
 195 }
 196 #else
 197 #define CVMX_MIXX_ORCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100040ull) + ((offset) & 1) * 2048)
 198 #endif
 199 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 200 static inline uint64_t CVMX_MIXX_ORHWM(unsigned long offset)
 201 {
 202         if (!(
 203               (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 204               (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
 205               (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
 206               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
 207               (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
 208               (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 209                 cvmx_warn("CVMX_MIXX_ORHWM(%lu) is invalid on this chip\n", offset);
 210         return CVMX_ADD_IO_SEG(0x0001070000100038ull) + ((offset) & 1) * 2048;
 211 }
 212 #else
 213 #define CVMX_MIXX_ORHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100038ull) + ((offset) & 1) * 2048)
 214 #endif
 215 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 216 static inline uint64_t CVMX_MIXX_ORING1(unsigned long offset)
 217 {
 218         if (!(
 219               (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 220               (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
 221               (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
 222               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
 223               (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
 224               (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 225                 cvmx_warn("CVMX_MIXX_ORING1(%lu) is invalid on this chip\n", offset);
 226         return CVMX_ADD_IO_SEG(0x0001070000100000ull) + ((offset) & 1) * 2048;
 227 }
 228 #else
 229 #define CVMX_MIXX_ORING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100000ull) + ((offset) & 1) * 2048)
 230 #endif
 231 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 232 static inline uint64_t CVMX_MIXX_ORING2(unsigned long offset)
 233 {
 234         if (!(
 235               (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 236               (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
 237               (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
 238               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
 239               (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
 240               (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 241                 cvmx_warn("CVMX_MIXX_ORING2(%lu) is invalid on this chip\n", offset);
 242         return CVMX_ADD_IO_SEG(0x0001070000100008ull) + ((offset) & 1) * 2048;
 243 }
 244 #else
 245 #define CVMX_MIXX_ORING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100008ull) + ((offset) & 1) * 2048)
 246 #endif
 247 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 248 static inline uint64_t CVMX_MIXX_REMCNT(unsigned long offset)
 249 {
 250         if (!(
 251               (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
 252               (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
 253               (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
 254               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
 255               (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
 256               (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 257                 cvmx_warn("CVMX_MIXX_REMCNT(%lu) is invalid on this chip\n", offset);
 258         return CVMX_ADD_IO_SEG(0x0001070000100058ull) + ((offset) & 1) * 2048;
 259 }
 260 #else
 261 #define CVMX_MIXX_REMCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100058ull) + ((offset) & 1) * 2048)
 262 #endif
 263 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 264 static inline uint64_t CVMX_MIXX_TSCTL(unsigned long offset)
 265 {
 266         if (!(
 267               (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
 268               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
 269               (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
 270               (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 271                 cvmx_warn("CVMX_MIXX_TSCTL(%lu) is invalid on this chip\n", offset);
 272         return CVMX_ADD_IO_SEG(0x0001070000100068ull) + ((offset) & 1) * 2048;
 273 }
 274 #else
 275 #define CVMX_MIXX_TSCTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100068ull) + ((offset) & 1) * 2048)
 276 #endif
 277 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 278 static inline uint64_t CVMX_MIXX_TSTAMP(unsigned long offset)
 279 {
 280         if (!(
 281               (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
 282               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
 283               (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
 284               (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
 285                 cvmx_warn("CVMX_MIXX_TSTAMP(%lu) is invalid on this chip\n", offset);
 286         return CVMX_ADD_IO_SEG(0x0001070000100060ull) + ((offset) & 1) * 2048;
 287 }
 288 #else
 289 #define CVMX_MIXX_TSTAMP(offset) (CVMX_ADD_IO_SEG(0x0001070000100060ull) + ((offset) & 1) * 2048)
 290 #endif
 291
 292 /**
 293  * cvmx_mix#_bist
 294  *
 295  * MIX_BIST = MIX BIST Register
 296  *
 297  * Description:
 298  *  NOTE: To read the MIX_BIST register, a device would issue an IOBLD64 directed at the MIO.
 299  */
 300 union cvmx_mixx_bist {
 301         uint64_t u64;
 302         struct cvmx_mixx_bist_s {
 303 #ifdef __BIG_ENDIAN_BITFIELD
 304         uint64_t reserved_6_63                : 58;
 305         uint64_t opfdat                       : 1;  /**< Bist Results for AGO OPF Buffer RAM
 306                                                          - 0: GOOD (or bist in progress/never run)
 307                                                          - 1: BAD */
 308         uint64_t mrgdat                       : 1;  /**< Bist Results for AGI MRG Buffer RAM
 309                                                          - 0: GOOD (or bist in progress/never run)
 310                                                          - 1: BAD */
 311         uint64_t mrqdat                       : 1;  /**< Bist Results for NBR CSR RdReq RAM
 312                                                          - 0: GOOD (or bist in progress/never run)
 313                                                          - 1: BAD */
 314         uint64_t ipfdat                       : 1;  /**< Bist Results for MIX Inbound Packet RAM
 315                                                          - 0: GOOD (or bist in progress/never run)
 316                                                          - 1: BAD */
 317         uint64_t irfdat                       : 1;  /**< Bist Results for MIX I-Ring Entry RAM
 318                                                          - 0: GOOD (or bist in progress/never run)
 319                                                          - 1: BAD */
 320         uint64_t orfdat                       : 1;  /**< Bist Results for MIX O-Ring Entry RAM
 321                                                          - 0: GOOD (or bist in progress/never run)
 322                                                          - 1: BAD */
 323 #else
 324         uint64_t orfdat                       : 1;
 325         uint64_t irfdat                       : 1;
 326         uint64_t ipfdat                       : 1;
 327         uint64_t mrqdat                       : 1;
 328         uint64_t mrgdat                       : 1;
 329         uint64_t opfdat                       : 1;
 330         uint64_t reserved_6_63                : 58;
 331 #endif
 332         } s;
 333         struct cvmx_mixx_bist_cn52xx {
 334 #ifdef __BIG_ENDIAN_BITFIELD
 335         uint64_t reserved_4_63                : 60;
 336         uint64_t mrqdat                       : 1;  /**< Bist Results for NBR CSR RdReq RAM
 337                                                          - 0: GOOD (or bist in progress/never run)
 338                                                          - 1: BAD */
 339         uint64_t ipfdat                       : 1;  /**< Bist Results for MIX Inbound Packet RAM
 340                                                          - 0: GOOD (or bist in progress/never run)
 341                                                          - 1: BAD */
 342         uint64_t irfdat                       : 1;  /**< Bist Results for MIX I-Ring Entry RAM
 343                                                          - 0: GOOD (or bist in progress/never run)
 344                                                          - 1: BAD */
 345         uint64_t orfdat                       : 1;  /**< Bist Results for MIX O-Ring Entry RAM
 346                                                          - 0: GOOD (or bist in progress/never run)
 347                                                          - 1: BAD */
 348 #else
 349         uint64_t orfdat                       : 1;
 350         uint64_t irfdat                       : 1;
 351         uint64_t ipfdat                       : 1;
 352         uint64_t mrqdat                       : 1;
 353         uint64_t reserved_4_63                : 60;
 354 #endif
 355         } cn52xx;
 356         struct cvmx_mixx_bist_cn52xx          cn52xxp1;
 357         struct cvmx_mixx_bist_cn52xx          cn56xx;
 358         struct cvmx_mixx_bist_cn52xx          cn56xxp1;
 359         struct cvmx_mixx_bist_s               cn61xx;
 360         struct cvmx_mixx_bist_s               cn63xx;
 361         struct cvmx_mixx_bist_s               cn63xxp1;
 362         struct cvmx_mixx_bist_s               cn66xx;
 363         struct cvmx_mixx_bist_s               cn68xx;
 364         struct cvmx_mixx_bist_s               cn68xxp1;
 365 };
 366 typedef union cvmx_mixx_bist cvmx_mixx_bist_t;
 367
 368 /**
 369  * cvmx_mix#_ctl
 370  *
 371  * MIX_CTL = MIX Control Register
 372  *
 373  * Description:
 374  *  NOTE: To write to the MIX_CTL register, a device would issue an IOBST directed at the MIO.
 375  *        To read the MIX_CTL register, a device would issue an IOBLD64 directed at the MIO.
 376  */
 377 union cvmx_mixx_ctl {
 378         uint64_t u64;
 379         struct cvmx_mixx_ctl_s {
 380 #ifdef __BIG_ENDIAN_BITFIELD
 381         uint64_t reserved_12_63               : 52;
 382         uint64_t ts_thresh                    : 4;  /**< TimeStamp Interrupt Threshold
 383                                                          When the \#of pending Timestamp interrupts (MIX_TSCTL[TSCNT]
 384                                                          is greater than MIX_CTL[TS_THRESH], then a programmable
 385                                                          TimeStamp Interrupt is issued (see MIX_INTR[TS]
 386                                                          MIX_INTENA[TSENA]).
 387                                                          SWNOTE: For o63, since the implementation only supports
 388                                                          4 oustanding timestamp interrupts, this field should
 389                                                          only be programmed from [0..3]. */
 390         uint64_t crc_strip                    : 1;  /**< HW CRC Strip Enable
 391                                                          When enabled, the last 4 bytes(CRC) of the ingress packet
 392                                                          are not included in cumulative packet byte length.
 393                                                          In other words, the cumulative LEN field for all
 394                                                          I-Ring Buffer Entries associated with a given ingress
 395                                                          packet will be 4 bytes less (so that the final 4B HW CRC
 396                                                          packet data is not processed by software). */
 397         uint64_t busy                         : 1;  /**< MIX Busy Status bit
 398                                                          MIX will assert busy status any time there are:
 399                                                            1) L2/DRAM reads in-flight (NCB-arb to read
 400                                                               response)
 401                                                            2) L2/DRAM writes in-flight (NCB-arb to write
 402                                                               data is sent.
 403                                                            3) L2/DRAM write commits in-flight (NCB-arb to write
 404                                                               commit response).
 405                                                          NOTE: After MIX_CTL[EN]=0, the MIX will eventually
 406                                                          complete any "inflight" transactions, at which point the
 407                                                          BUSY will de-assert. */
 408         uint64_t en                           : 1;  /**< MIX Enable bit
 409                                                          When EN=0, MIX will no longer arbitrate for
 410                                                          any new L2/DRAM read/write requests on the NCB Bus.
 411                                                          MIX will complete any requests that are currently
 412                                                          pended for the NCB Bus. */
 413         uint64_t reset                        : 1;  /**< MIX Soft Reset
 414                                                           When SW writes a '1' to MIX_CTL[RESET], the
 415                                                           MII-MIX/AGL logic will execute a soft reset.
 416                                                           NOTE: During a soft reset, CSR accesses are not effected.
 417                                                           However, the values of the CSR fields will be effected by
 418                                                           soft reset (except MIX_CTL[RESET] itself).
 419                                                           NOTE: After power-on, the MII-AGL/MIX are held in reset
 420                                                           until the MIX_CTL[RESET] is written to zero. SW MUST also
 421                                                           perform a MIX_CTL CSR read after this write to ensure the
 422                                                           soft reset de-assertion has had sufficient time to propagate
 423                                                           to all MIO-MIX internal logic before any subsequent MIX CSR
 424                                                           accesses are issued.
 425                                                           The intended "soft reset" sequence is: (please also
 426                                                           refer to HRM Section 12.6.2 on MIX/AGL Block Reset).
 427                                                              1) Write MIX_CTL[EN]=0
 428                                                                 [To prevent any NEW transactions from being started]
 429                                                              2) Wait for MIX_CTL[BUSY]=0
 430                                                                 [To indicate that all inflight transactions have
 431                                                                  completed]
 432                                                              3) Write MIX_CTL[RESET]=1, followed by a MIX_CTL CSR read
 433                                                                 and wait for the result.
 434                                                              4) Re-Initialize the MIX/AGL just as would be done
 435                                                                 for a hard reset.
 436                                                          NOTE: Once the MII has been soft-reset, please refer to HRM Section
 437                                                          12.6.1 MIX/AGL BringUp Sequence to complete the MIX/AGL
 438                                                          re-initialization sequence. */
 439         uint64_t lendian                      : 1;  /**< Packet Little Endian Mode
 440                                                          (0: Big Endian Mode/1: Little Endian Mode)
 441                                                          When the mode is set, MIX will byte-swap packet data
 442                                                          loads/stores at the MIX/NCB boundary. */
 443         uint64_t nbtarb                       : 1;  /**< MIX CB-Request Arbitration Mode.
 444                                                          When set to zero, the arbiter is fixed priority with
 445                                                          the following priority scheme:
 446                                                              Highest Priority: I-Ring Packet Write Request
 447                                                                                O-Ring Packet Read Request
 448                                                                                I-Ring Entry Write Request
 449                                                                                I-Ring Entry Read Request
 450                                                                                O-Ring Entry Read Request
 451                                                          When set to one, the arbiter is round robin. */
 452         uint64_t mrq_hwm                      : 2;  /**< MIX CB-Request FIFO Programmable High Water Mark.
 453                                                          The MRQ contains 16 CB-Requests which are CSR Rd/Wr
 454                                                          Requests. If the MRQ backs up with "HWM" entries,
 455                                                          then new CB-Requests are 'stalled'.
 456                                                             [0]: HWM = 11
 457                                                             [1]: HWM = 10
 458                                                             [2]: HWM = 9
 459                                                             [3]: HWM = 8
 460                                                          NOTE: This must only be written at power-on/boot time. */
 461 #else
 462         uint64_t mrq_hwm                      : 2;
 463         uint64_t nbtarb                       : 1;
 464         uint64_t lendian                      : 1;
 465         uint64_t reset                        : 1;
 466         uint64_t en                           : 1;
 467         uint64_t busy                         : 1;
 468         uint64_t crc_strip                    : 1;
 469         uint64_t ts_thresh                    : 4;
 470         uint64_t reserved_12_63               : 52;
 471 #endif
 472         } s;
 473         struct cvmx_mixx_ctl_cn52xx {
 474 #ifdef __BIG_ENDIAN_BITFIELD
 475         uint64_t reserved_8_63                : 56;
 476         uint64_t crc_strip                    : 1;  /**< HW CRC Strip Enable
 477                                                          When enabled, the last 4 bytes(CRC) of the ingress packet
 478                                                          are not included in cumulative packet byte length.
 479                                                          In other words, the cumulative LEN field for all
 480                                                          I-Ring Buffer Entries associated with a given ingress
 481                                                          packet will be 4 bytes less (so that the final 4B HW CRC
 482                                                          packet data is not processed by software). */
 483         uint64_t busy                         : 1;  /**< MIX Busy Status bit
 484                                                          MIX will assert busy status any time there are:
 485                                                            1) L2/DRAM reads in-flight (NCB-arb to read
 486                                                               response)
 487                                                            2) L2/DRAM writes in-flight (NCB-arb to write
 488                                                               data is sent.
 489                                                            3) L2/DRAM write commits in-flight (NCB-arb to write
 490                                                               commit response).
 491                                                          NOTE: After MIX_CTL[EN]=0, the MIX will eventually
 492                                                          complete any "inflight" transactions, at which point the
 493                                                          BUSY will de-assert. */
 494         uint64_t en                           : 1;  /**< MIX Enable bit
 495                                                          When EN=0, MIX will no longer arbitrate for
 496                                                          any new L2/DRAM read/write requests on the NCB Bus.
 497                                                          MIX will complete any requests that are currently
 498                                                          pended for the NCB Bus. */
 499         uint64_t reset                        : 1;  /**< MIX Soft Reset
 500                                                           When SW writes a '1' to MIX_CTL[RESET], the
 501                                                           MII-MIX/AGL logic will execute a soft reset.
 502                                                           NOTE: During a soft reset, CSR accesses are not effected.
 503                                                           However, the values of the CSR fields will be effected by
 504                                                           soft reset (except MIX_CTL[RESET] itself).
 505                                                           NOTE: After power-on, the MII-AGL/MIX are held in reset
 506                                                           until the MIX_CTL[RESET] is written to zero. SW MUST also
 507                                                           perform a MIX_CTL CSR read after this write to ensure the
 508                                                           soft reset de-assertion has had sufficient time to propagate
 509                                                           to all MIO-MIX internal logic before any subsequent MIX CSR
 510                                                           accesses are issued.
 511                                                           The intended "soft reset" sequence is: (please also
 512                                                           refer to HRM Section 12.6.2 on MIX/AGL Block Reset).
 513                                                              1) Write MIX_CTL[EN]=0
 514                                                                 [To prevent any NEW transactions from being started]
 515                                                              2) Wait for MIX_CTL[BUSY]=0
 516                                                                 [To indicate that all inflight transactions have
 517                                                                  completed]
 518                                                              3) Write MIX_CTL[RESET]=1, followed by a MIX_CTL CSR read
 519                                                                 and wait for the result.
 520                                                              4) Re-Initialize the MIX/AGL just as would be done
 521                                                                 for a hard reset.
 522                                                          NOTE: Once the MII has been soft-reset, please refer to HRM Section
 523                                                          12.6.1 MIX/AGL BringUp Sequence to complete the MIX/AGL
 524                                                          re-initialization sequence. */
 525         uint64_t lendian                      : 1;  /**< Packet Little Endian Mode
 526                                                          (0: Big Endian Mode/1: Little Endian Mode)
 527                                                          When the mode is set, MIX will byte-swap packet data
 528                                                          loads/stores at the MIX/NCB boundary. */
 529         uint64_t nbtarb                       : 1;  /**< MIX CB-Request Arbitration Mode.
 530                                                          When set to zero, the arbiter is fixed priority with
 531                                                          the following priority scheme:
 532                                                              Highest Priority: I-Ring Packet Write Request
 533                                                                                O-Ring Packet Read Request
 534                                                                                I-Ring Entry Write Request
 535                                                                                I-Ring Entry Read Request
 536                                                                                O-Ring Entry Read Request
 537                                                          When set to one, the arbiter is round robin. */
 538         uint64_t mrq_hwm                      : 2;  /**< MIX CB-Request FIFO Programmable High Water Mark.
 539                                                          The MRQ contains 16 CB-Requests which are CSR Rd/Wr
 540                                                          Requests. If the MRQ backs up with "HWM" entries,
 541                                                          then new CB-Requests are 'stalled'.
 542                                                             [0]: HWM = 11
 543                                                             [1]: HWM = 10
 544                                                             [2]: HWM = 9
 545                                                             [3]: HWM = 8
 546                                                          NOTE: This must only be written at power-on/boot time. */
 547 #else
 548         uint64_t mrq_hwm                      : 2;
 549         uint64_t nbtarb                       : 1;
 550         uint64_t lendian                      : 1;
 551         uint64_t reset                        : 1;
 552         uint64_t en                           : 1;
 553         uint64_t busy                         : 1;
 554         uint64_t crc_strip                    : 1;
 555         uint64_t reserved_8_63                : 56;
 556 #endif
 557         } cn52xx;
 558         struct cvmx_mixx_ctl_cn52xx           cn52xxp1;
 559         struct cvmx_mixx_ctl_cn52xx           cn56xx;
 560         struct cvmx_mixx_ctl_cn52xx           cn56xxp1;
 561         struct cvmx_mixx_ctl_s                cn61xx;
 562         struct cvmx_mixx_ctl_s                cn63xx;
 563         struct cvmx_mixx_ctl_s                cn63xxp1;
 564         struct cvmx_mixx_ctl_s                cn66xx;
 565         struct cvmx_mixx_ctl_s                cn68xx;
 566         struct cvmx_mixx_ctl_s                cn68xxp1;
 567 };
 568 typedef union cvmx_mixx_ctl cvmx_mixx_ctl_t;
 569
 570 /**
 571  * cvmx_mix#_intena
 572  *
 573  * MIX_INTENA = MIX Local Interrupt Enable Mask Register
 574  *
 575  * Description:
 576  *  NOTE: To write to the MIX_INTENA register, a device would issue an IOBST directed at the MIO.
 577  *        To read the MIX_INTENA register, a device would issue an IOBLD64 directed at the MIO.
 578  */
 579 union cvmx_mixx_intena {
 580         uint64_t u64;
 581         struct cvmx_mixx_intena_s {
 582 #ifdef __BIG_ENDIAN_BITFIELD
 583         uint64_t reserved_8_63                : 56;
 584         uint64_t tsena                        : 1;  /**< TimeStamp Interrupt Enable
 585                                                          If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII])
 586                                                          and this local interrupt mask bit is set, than an
 587                                                          interrupt is reported for an Outbound Ring with Timestamp
 588                                                          event (see: MIX_ISR[TS]). */
 589         uint64_t orunena                      : 1;  /**< ORCNT UnderFlow Detected Enable
 590                                                          If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII])
 591                                                          and this local interrupt mask bit is set, than an
 592                                                          interrupt is reported for an ORCNT underflow condition
 593                                                          MIX_ISR[ORUN]. */
 594         uint64_t irunena                      : 1;  /**< IRCNT UnderFlow Interrupt Enable
 595                                                          If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII])
 596                                                          and this local interrupt mask bit is set, than an
 597                                                          interrupt is reported for an IRCNT underflow condition
 598                                                          MIX_ISR[IRUN]. */
 599         uint64_t data_drpena                  : 1;  /**< Data was dropped due to RX FIFO full Interrupt
 600                                                          enable. If both the global interrupt mask bits
 601                                                          (CIU2_EN_xx_yy_PKT[MII]) and the local interrupt mask
 602                                                          bit(DATA_DRPENA) is set, than an interrupt is
 603                                                          reported for this event. */
 604         uint64_t ithena                       : 1;  /**< Inbound Ring Threshold Exceeded Interrupt Enable
 605                                                          If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII])
 606                                                          and this local interrupt mask bit is set, than an
 607                                                          interrupt is reported for an Inbound Ring Threshold
 608                                                          Exceeded event(IRTHRESH). */
 609         uint64_t othena                       : 1;  /**< Outbound Ring Threshold Exceeded Interrupt Enable
 610                                                          If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII])
 611                                                          and this local interrupt mask bit is set, than an
 612                                                          interrupt is reported for an Outbound Ring Threshold
 613                                                          Exceeded event(ORTHRESH). */
 614         uint64_t ivfena                       : 1;  /**< Inbound DoorBell(IDBELL) Overflow Detected
 615                                                          If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII])
 616                                                          and this local interrupt mask bit is set, than an
 617                                                          interrupt is reported for an Inbound Doorbell Overflow
 618                                                          event(IDBOVF). */
 619         uint64_t ovfena                       : 1;  /**< Outbound DoorBell(ODBELL) Overflow Interrupt Enable
 620                                                          If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII])
 621                                                          and this local interrupt mask bit is set, than an
 622                                                          interrupt is reported for an Outbound Doorbell Overflow
 623                                                          event(ODBOVF). */
 624 #else
 625         uint64_t ovfena                       : 1;
 626         uint64_t ivfena                       : 1;
 627         uint64_t othena                       : 1;
 628         uint64_t ithena                       : 1;
 629         uint64_t data_drpena                  : 1;
 630         uint64_t irunena                      : 1;
 631         uint64_t orunena                      : 1;
 632         uint64_t tsena                        : 1;
 633         uint64_t reserved_8_63                : 56;
 634 #endif
 635         } s;
 636         struct cvmx_mixx_intena_cn52xx {
 637 #ifdef __BIG_ENDIAN_BITFIELD
 638         uint64_t reserved_7_63                : 57;
 639         uint64_t orunena                      : 1;  /**< ORCNT UnderFlow Detected
 640                                                          If both the global interrupt mask bits (CIU_INTx_EN*[MII])
 641                                                          and this local interrupt mask bit is set, than an
 642                                                          interrupt is reported for an ORCNT underflow condition
 643                                                          MIX_ISR[ORUN]. */
 644         uint64_t irunena                      : 1;  /**< IRCNT UnderFlow Interrupt Enable
 645                                                          If both the global interrupt mask bits (CIU_INTx_EN*[MII])
 646                                                          and this local interrupt mask bit is set, than an
 647                                                          interrupt is reported for an IRCNT underflow condition
 648                                                          MIX_ISR[IRUN]. */
 649         uint64_t data_drpena                  : 1;  /**< Data was dropped due to RX FIFO full Interrupt
 650                                                          enable. If both the global interrupt mask bits
 651                                                          (CIU_INTx_EN*[MII]) and the local interrupt mask
 652                                                          bit(DATA_DRPENA) is set, than an interrupt is
 653                                                          reported for this event. */
 654         uint64_t ithena                       : 1;  /**< Inbound Ring Threshold Exceeded Interrupt Enable
 655                                                          If both the global interrupt mask bits (CIU_INTx_EN*[MII])
 656                                                          and this local interrupt mask bit is set, than an
 657                                                          interrupt is reported for an Inbound Ring Threshold
 658                                                          Exceeded event(IRTHRESH). */
 659         uint64_t othena                       : 1;  /**< Outbound Ring Threshold Exceeded Interrupt Enable
 660                                                          If both the global interrupt mask bits (CIU_INTx_EN*[MII])
 661                                                          and this local interrupt mask bit is set, than an
 662                                                          interrupt is reported for an Outbound Ring Threshold
 663                                                          Exceeded event(ORTHRESH). */
 664         uint64_t ivfena                       : 1;  /**< Inbound DoorBell(IDBELL) Overflow Detected
 665                                                          If both the global interrupt mask bits (CIU_INTx_EN*[MII])
 666                                                          and this local interrupt mask bit is set, than an
 667                                                          interrupt is reported for an Inbound Doorbell Overflow
 668                                                          event(IDBOVF). */
 669         uint64_t ovfena                       : 1;  /**< Outbound DoorBell(ODBELL) Overflow Interrupt Enable
 670                                                          If both the global interrupt mask bits (CIU_INTx_EN*[MII])
 671                                                          and this local interrupt mask bit is set, than an
 672                                                          interrupt is reported for an Outbound Doorbell Overflow
 673                                                          event(ODBOVF). */
 674 #else
 675         uint64_t ovfena                       : 1;
 676         uint64_t ivfena                       : 1;
 677         uint64_t othena                       : 1;
 678         uint64_t ithena                       : 1;
 679         uint64_t data_drpena                  : 1;
 680         uint64_t irunena                      : 1;
 681         uint64_t orunena                      : 1;
 682         uint64_t reserved_7_63                : 57;
 683 #endif
 684         } cn52xx;
 685         struct cvmx_mixx_intena_cn52xx        cn52xxp1;
 686         struct cvmx_mixx_intena_cn52xx        cn56xx;
 687         struct cvmx_mixx_intena_cn52xx        cn56xxp1;
 688         struct cvmx_mixx_intena_s             cn61xx;
 689         struct cvmx_mixx_intena_s             cn63xx;
 690         struct cvmx_mixx_intena_s             cn63xxp1;
 691         struct cvmx_mixx_intena_s             cn66xx;
 692         struct cvmx_mixx_intena_s             cn68xx;
 693         struct cvmx_mixx_intena_s             cn68xxp1;
 694 };
 695 typedef union cvmx_mixx_intena cvmx_mixx_intena_t;
 696
 697 /**
 698  * cvmx_mix#_ircnt
 699  *
 700  * MIX_IRCNT = MIX I-Ring Pending Packet Counter
 701  *
 702  * Description:
 703  *  NOTE: To write to the MIX_IRCNT register, a device would issue an IOBST directed at the MIO.
 704  *        To read the MIX_IRCNT register, a device would issue an IOBLD64 directed at the MIO.
 705  */
 706 union cvmx_mixx_ircnt {
 707         uint64_t u64;
 708         struct cvmx_mixx_ircnt_s {
 709 #ifdef __BIG_ENDIAN_BITFIELD
 710         uint64_t reserved_20_63               : 44;
 711         uint64_t ircnt                        : 20; /**< Pending \# of I-Ring Packets.
 712                                                          Whenever HW writes a completion code of Done, Trunc,
 713                                                          CRCErr or Err, it increments the IRCNT (to indicate
 714                                                          to SW the \# of pending Input packets in system memory).
 715                                                          NOTE: The HW guarantees that the completion code write
 716                                                          is always visible in system memory BEFORE it increments
 717                                                          the IRCNT.
 718                                                          Reads of IRCNT return the current inbound packet count.
 719                                                          Writes of IRCNT decrement the count by the value
 720                                                          written.
 721                                                          This register is used to generate interrupts to alert
 722                                                          SW of pending inbound MIX packets in system memory.
 723                                                          NOTE: In the case of inbound packets that span multiple
 724                                                          I-Ring entries, SW must keep track of the \# of I-Ring Entries
 725                                                          associated with a given inbound packet to reclaim the
 726                                                          proper \# of I-Ring Entries for re-use. */
 727 #else
 728         uint64_t ircnt                        : 20;
 729         uint64_t reserved_20_63               : 44;
 730 #endif
 731         } s;
 732         struct cvmx_mixx_ircnt_s              cn52xx;
 733         struct cvmx_mixx_ircnt_s              cn52xxp1;
 734         struct cvmx_mixx_ircnt_s              cn56xx;
 735         struct cvmx_mixx_ircnt_s              cn56xxp1;
 736         struct cvmx_mixx_ircnt_s              cn61xx;
 737         struct cvmx_mixx_ircnt_s              cn63xx;
 738         struct cvmx_mixx_ircnt_s              cn63xxp1;
 739         struct cvmx_mixx_ircnt_s              cn66xx;
 740         struct cvmx_mixx_ircnt_s              cn68xx;
 741         struct cvmx_mixx_ircnt_s              cn68xxp1;
 742 };
 743 typedef union cvmx_mixx_ircnt cvmx_mixx_ircnt_t;
 744
 745 /**
 746  * cvmx_mix#_irhwm
 747  *
 748  * MIX_IRHWM = MIX I-Ring High-Water Mark Threshold Register
 749  *
 750  * Description:
 751  *  NOTE: To write to the MIX_IHWM register, a device would issue an IOBST directed at the MIO.
 752  *        To read the MIX_IHWM register, a device would issue an IOBLD64 directed at the MIO.
 753  */
 754 union cvmx_mixx_irhwm {
 755         uint64_t u64;
 756         struct cvmx_mixx_irhwm_s {
 757 #ifdef __BIG_ENDIAN_BITFIELD
 758         uint64_t reserved_40_63               : 24;
 759         uint64_t ibplwm                       : 20; /**< I-Ring BackPressure Low Water Mark Threshold.
 760                                                          When the \#of available I-Ring Entries (IDBELL)
 761                                                          is less than IBPLWM, the AGL-MAC will:
 762                                                            a) In full-duplex mode: send periodic PAUSE packets.
 763                                                            b) In half-duplex mode: Force collisions.
 764                                                          This programmable mechanism is provided as a means
 765                                                          to backpressure input traffic 'early' enough (so
 766                                                          that packets are not 'dropped' by OCTEON). */
 767         uint64_t irhwm                        : 20; /**< I-Ring Entry High Water Mark Threshold.
 768                                                          Used to determine when the \# of Inbound packets
 769                                                          in system memory(MIX_IRCNT[IRCNT]) exceeds this IRHWM
 770                                                          threshold.
 771                                                          NOTE: The power-on value of the CIU2_EN_xx_yy_PKT[MII]
 772                                                          interrupt enable bits is zero and must be enabled
 773                                                          to allow interrupts to be reported. */
 774 #else
 775         uint64_t irhwm                        : 20;
 776         uint64_t ibplwm                       : 20;
 777         uint64_t reserved_40_63               : 24;
 778 #endif
 779         } s;
 780         struct cvmx_mixx_irhwm_s              cn52xx;
 781         struct cvmx_mixx_irhwm_s              cn52xxp1;
 782         struct cvmx_mixx_irhwm_s              cn56xx;
 783         struct cvmx_mixx_irhwm_s              cn56xxp1;
 784         struct cvmx_mixx_irhwm_s              cn61xx;
 785         struct cvmx_mixx_irhwm_s              cn63xx;
 786         struct cvmx_mixx_irhwm_s              cn63xxp1;
 787         struct cvmx_mixx_irhwm_s              cn66xx;
 788         struct cvmx_mixx_irhwm_s              cn68xx;
 789         struct cvmx_mixx_irhwm_s              cn68xxp1;
 790 };
 791 typedef union cvmx_mixx_irhwm cvmx_mixx_irhwm_t;
 792
 793 /**
 794  * cvmx_mix#_iring1
 795  *
 796  * MIX_IRING1 = MIX Inbound Ring Register \#1
 797  *
 798  * Description:
 799  *  NOTE: To write to the MIX_IRING1 register, a device would issue an IOBST directed at the MIO.
 800  *        To read the MIX_IRING1 register, a device would issue an IOBLD64 directed at the MIO.
 801  */
 802 union cvmx_mixx_iring1 {
 803         uint64_t u64;
 804         struct cvmx_mixx_iring1_s {
 805 #ifdef __BIG_ENDIAN_BITFIELD
 806         uint64_t reserved_60_63               : 4;
 807         uint64_t isize                        : 20; /**< Represents the Inbound Ring Buffer's Size(in 8B
 808                                                          words). The ring can be as large as 1M entries.
 809                                                          NOTE: This CSR MUST BE setup written by SW poweron
 810                                                          (when IDBELL/IRCNT=0). */
 811         uint64_t ibase                        : 37; /**< Represents the 8B-aligned base address of the first
 812                                                          Inbound Ring entry in system memory.
 813                                                          NOTE: SW MUST ONLY write to this register during
 814                                                          power-on/boot code. */
 815         uint64_t reserved_0_2                 : 3;
 816 #else
 817         uint64_t reserved_0_2                 : 3;
 818         uint64_t ibase                        : 37;
 819         uint64_t isize                        : 20;
 820         uint64_t reserved_60_63               : 4;
 821 #endif
 822         } s;
 823         struct cvmx_mixx_iring1_cn52xx {
 824 #ifdef __BIG_ENDIAN_BITFIELD
 825         uint64_t reserved_60_63               : 4;
 826         uint64_t isize                        : 20; /**< Represents the Inbound Ring Buffer's Size(in 8B
 827                                                          words). The ring can be as large as 1M entries.
 828                                                          NOTE: This CSR MUST BE setup written by SW poweron
 829                                                          (when IDBELL/IRCNT=0). */
 830         uint64_t reserved_36_39               : 4;
 831         uint64_t ibase                        : 33; /**< Represents the 8B-aligned base address of the first
 832                                                          Inbound Ring entry in system memory.
 833                                                          NOTE: SW MUST ONLY write to this register during
 834                                                          power-on/boot code. */
 835         uint64_t reserved_0_2                 : 3;
 836 #else
 837         uint64_t reserved_0_2                 : 3;
 838         uint64_t ibase                        : 33;
 839         uint64_t reserved_36_39               : 4;
 840         uint64_t isize                        : 20;
 841         uint64_t reserved_60_63               : 4;
 842 #endif
 843         } cn52xx;
 844         struct cvmx_mixx_iring1_cn52xx        cn52xxp1;
 845         struct cvmx_mixx_iring1_cn52xx        cn56xx;
 846         struct cvmx_mixx_iring1_cn52xx        cn56xxp1;
 847         struct cvmx_mixx_iring1_s             cn61xx;
 848         struct cvmx_mixx_iring1_s             cn63xx;
 849         struct cvmx_mixx_iring1_s             cn63xxp1;
 850         struct cvmx_mixx_iring1_s             cn66xx;
 851         struct cvmx_mixx_iring1_s             cn68xx;
 852         struct cvmx_mixx_iring1_s             cn68xxp1;
 853 };
 854 typedef union cvmx_mixx_iring1 cvmx_mixx_iring1_t;
 855
 856 /**
 857  * cvmx_mix#_iring2
 858  *
 859  * MIX_IRING2 = MIX Inbound Ring Register \#2
 860  *
 861  * Description:
 862  *  NOTE: To write to the MIX_IRING2 register, a device would issue an IOBST directed at the MIO.
 863  *        To read the MIX_IRING2 register, a device would issue an IOBLD64 directed at the MIO.
 864  */
 865 union cvmx_mixx_iring2 {
 866         uint64_t u64;
 867         struct cvmx_mixx_iring2_s {
 868 #ifdef __BIG_ENDIAN_BITFIELD
 869         uint64_t reserved_52_63               : 12;
 870         uint64_t itlptr                       : 20; /**< The Inbound Ring Tail Pointer selects the I-Ring
 871                                                          Entry that the HW will process next. After the HW
 872                                                          completes receiving an inbound packet, it increments
 873                                                          the I-Ring Tail Pointer. [NOTE: The I-Ring Tail
 874                                                          Pointer HW increment is always modulo ISIZE.
 875                                                          NOTE: This field is 'read-only' to SW. */
 876         uint64_t reserved_20_31               : 12;
 877         uint64_t idbell                       : 20; /**< Represents the cumulative total of pending
 878                                                          Inbound Ring Buffer Entries. Each I-Ring
 879                                                          Buffer Entry contains 1) an L2/DRAM byte pointer
 880                                                          along with a 2) a Byte Length.
 881                                                          After SW inserts a new entry into the I-Ring Buffer,
 882                                                          it "rings the doorbell for the inbound ring". When
 883                                                          the MIX HW receives the doorbell ring, it advances
 884                                                          the doorbell count for the I-Ring.
 885                                                          SW must never cause the doorbell count for the
 886                                                          I-Ring to exceed the size of the I-ring(ISIZE).
 887                                                          A read of the CSR indicates the current doorbell
 888                                                          count. */
 889 #else
 890         uint64_t idbell                       : 20;
 891         uint64_t reserved_20_31               : 12;
 892         uint64_t itlptr                       : 20;
 893         uint64_t reserved_52_63               : 12;
 894 #endif
 895         } s;
 896         struct cvmx_mixx_iring2_s             cn52xx;
 897         struct cvmx_mixx_iring2_s             cn52xxp1;
 898         struct cvmx_mixx_iring2_s             cn56xx;
 899         struct cvmx_mixx_iring2_s             cn56xxp1;
 900         struct cvmx_mixx_iring2_s             cn61xx;
 901         struct cvmx_mixx_iring2_s             cn63xx;
 902         struct cvmx_mixx_iring2_s             cn63xxp1;
 903         struct cvmx_mixx_iring2_s             cn66xx;
 904         struct cvmx_mixx_iring2_s             cn68xx;
 905         struct cvmx_mixx_iring2_s             cn68xxp1;
 906 };
 907 typedef union cvmx_mixx_iring2 cvmx_mixx_iring2_t;
 908
 909 /**
 910  * cvmx_mix#_isr
 911  *
 912  * MIX_ISR = MIX Interrupt/Status Register
 913  *
 914  * Description:
 915  *  NOTE: To write to the MIX_ISR register, a device would issue an IOBST directed at the MIO.
 916  *        To read the MIX_ISR register, a device would issue an IOBLD64 directed at the MIO.
 917  */
 918 union cvmx_mixx_isr {
 919         uint64_t u64;
 920         struct cvmx_mixx_isr_s {
 921 #ifdef __BIG_ENDIAN_BITFIELD
 922         uint64_t reserved_8_63                : 56;
 923         uint64_t ts                           : 1;  /**< TimeStamp Interrupt
 924                                                          When the \#of pending Timestamp Interrupts (MIX_TSCTL[TSCNT])
 925                                                          is greater than the TimeStamp Interrupt Threshold
 926                                                          (MIX_CTL[TS_THRESH]) value this interrupt bit is set.
 927                                                          If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII])
 928                                                          and this local interrupt mask bit is set, than an
 929                                                          interrupt is reported for an Outbound Ring with Timestamp
 930                                                          event (see: MIX_INTENA[TSENA]). */
 931         uint64_t orun                         : 1;  /**< ORCNT UnderFlow Detected
 932                                                          If SW writes a larger value than what is currently
 933                                                          in the MIX_ORCNT[ORCNT], then HW will report the
 934                                                          underflow condition.
 935                                                          NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.
 936                                                          NOTE: If an ORUN underflow condition is detected,
 937                                                          the integrity of the MIX/AGL HW state has
 938                                                          been compromised. To recover, SW must issue a
 939                                                          software reset sequence (see: MIX_CTL[RESET] */
 940         uint64_t irun                         : 1;  /**< IRCNT UnderFlow Detected
 941                                                          If SW writes a larger value than what is currently
 942                                                          in the MIX_IRCNT[IRCNT], then HW will report the
 943                                                          underflow condition.
 944                                                          NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.
 945                                                          NOTE: If an IRUN underflow condition is detected,
 946                                                          the integrity of the MIX/AGL HW state has
 947                                                          been compromised. To recover, SW must issue a
 948                                                          software reset sequence (see: MIX_CTL[RESET] */
 949         uint64_t data_drp                     : 1;  /**< Data was dropped due to RX FIFO full
 950                                                          If this does occur, the DATA_DRP is set and the
 951                                                          CIU2_RAW_PKT[MII] bit is set.
 952                                                          If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII])
 953                                                          and the local interrupt mask bit(DATA_DRPENA) is set, than an
 954                                                          interrupt is reported for this event. */
 955         uint64_t irthresh                     : 1;  /**< Inbound Ring Packet Threshold Exceeded
 956                                                          When the pending \#inbound packets in system
 957                                                          memory(IRCNT) has exceeded a programmable threshold
 958                                                          (IRHWM), then this bit is set. If this does occur,
 959                                                          the IRTHRESH is set and the CIU2_RAW_PKT[MII] bit
 960                                                          is set if ((MIX_ISR & MIX_INTENA) != 0)).
 961                                                          If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII])
 962                                                          and the local interrupt mask bit(ITHENA) is set, than an
 963                                                          interrupt is reported for this event. */
 964         uint64_t orthresh                     : 1;  /**< Outbound Ring Packet Threshold Exceeded
 965                                                          When the pending \#outbound packets in system
 966                                                          memory(ORCNT) has exceeded a programmable threshold
 967                                                          (ORHWM), then this bit is set. If this does occur,
 968                                                          the ORTHRESH is set and the CIU2_RAW_PKT[MII] bit
 969                                                          is set if ((MIX_ISR & MIX_INTENA) != 0)).
 970                                                          If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII])
 971                                                          and the local interrupt mask bit(OTHENA) is set, than an
 972                                                          interrupt is reported for this event. */
 973         uint64_t idblovf                      : 1;  /**< Inbound DoorBell(IDBELL) Overflow Detected
 974                                                          If SW attempts to write to the MIX_IRING2[IDBELL]
 975                                                          with a value greater than the remaining \#of
 976                                                          I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then
 977                                                          the following occurs:
 978                                                          1) The  MIX_IRING2[IDBELL] write is IGNORED
 979                                                          2) The ODBLOVF is set and the CIU2_RAW_PKT[MII]
 980                                                             bit is set if ((MIX_ISR & MIX_INTENA) != 0)).
 981                                                          If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII])
 982                                                          and the local interrupt mask bit(IVFENA) is set, than an
 983                                                          interrupt is reported for this event.
 984                                                          SW should keep track of the \#I-Ring Entries in use
 985                                                          (ie: cumulative \# of IDBELL writes),  and ensure that
 986                                                          future IDBELL writes don't exceed the size of the
 987                                                          I-Ring Buffer (MIX_IRING2[ISIZE]).
 988                                                          SW must reclaim I-Ring Entries by keeping track of the
 989                                                          \#IRing-Entries, and writing to the MIX_IRCNT[IRCNT].
 990                                                          NOTE: The MIX_IRCNT[IRCNT] register represents the
 991                                                          total \#packets(not IRing Entries) and SW must further
 992                                                          keep track of the \# of I-Ring Entries associated with
 993                                                          each packet as they are processed.
 994                                                          NOTE: There is no recovery from an IDBLOVF Interrupt.
 995                                                          If it occurs, it's an indication that SW has
 996                                                          overwritten the I-Ring buffer, and the only recourse
 997                                                          is a HW reset. */
 998         uint64_t odblovf                      : 1;  /**< Outbound DoorBell(ODBELL) Overflow Detected
 999                                                          If SW attempts to write to the MIX_ORING2[ODBELL]
1000                                                          with a value greater than the remaining \#of
1001                                                          O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then
1002                                                          the following occurs:
1003                                                          1) The  MIX_ORING2[ODBELL] write is IGNORED
1004                                                          2) The ODBLOVF is set and the CIU2_RAW_PKT[MII]
1005                                                             bit is set if ((MIX_ISR & MIX_INTENA) != 0)).
1006                                                          If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII])
1007                                                          and the local interrupt mask bit(OVFENA) is set, than an
1008                                                          interrupt is reported for this event.
1009                                                          SW should keep track of the \#I-Ring Entries in use
1010                                                          (ie: cumulative \# of ODBELL writes),  and ensure that
1011                                                          future ODBELL writes don't exceed the size of the
1012                                                          O-Ring Buffer (MIX_ORING2[OSIZE]).
1013                                                          SW must reclaim O-Ring Entries by writing to the
1014                                                          MIX_ORCNT[ORCNT]. .
1015                                                          NOTE: There is no recovery from an ODBLOVF Interrupt.
1016                                                          If it occurs, it's an indication that SW has
1017                                                          overwritten the O-Ring buffer, and the only recourse
1018                                                          is a HW reset. */
1019 #else
1020         uint64_t odblovf                      : 1;
1021         uint64_t idblovf                      : 1;
1022         uint64_t orthresh                     : 1;
1023         uint64_t irthresh                     : 1;
1024         uint64_t data_drp                     : 1;
1025         uint64_t irun                         : 1;
1026         uint64_t orun                         : 1;
1027         uint64_t ts                           : 1;
1028         uint64_t reserved_8_63                : 56;
1029 #endif
1030         } s;
1031         struct cvmx_mixx_isr_cn52xx {
1032 #ifdef __BIG_ENDIAN_BITFIELD
1033         uint64_t reserved_7_63                : 57;
1034         uint64_t orun                         : 1;  /**< ORCNT UnderFlow Detected
1035                                                          If SW writes a larger value than what is currently
1036                                                          in the MIX_ORCNT[ORCNT], then HW will report the
1037                                                          underflow condition.
1038                                                          NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.
1039                                                          NOTE: If an ORUN underflow condition is detected,
1040                                                          the integrity of the MIX/AGL HW state has
1041                                                          been compromised. To recover, SW must issue a
1042                                                          software reset sequence (see: MIX_CTL[RESET] */
1043         uint64_t irun                         : 1;  /**< IRCNT UnderFlow Detected
1044                                                          If SW writes a larger value than what is currently
1045                                                          in the MIX_IRCNT[IRCNT], then HW will report the
1046                                                          underflow condition.
1047                                                          NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.
1048                                                          NOTE: If an IRUN underflow condition is detected,
1049                                                          the integrity of the MIX/AGL HW state has
1050                                                          been compromised. To recover, SW must issue a
1051                                                          software reset sequence (see: MIX_CTL[RESET] */
1052         uint64_t data_drp                     : 1;  /**< Data was dropped due to RX FIFO full
1053                                                          If this does occur, the DATA_DRP is set and the
1054                                                          CIU_INTx_SUM0,4[MII] bits are set.
1055                                                          If both the global interrupt mask bits (CIU_INTx_EN*[MII])
1056                                                          and the local interrupt mask bit(DATA_DRPENA) is set, than an
1057                                                          interrupt is reported for this event. */
1058         uint64_t irthresh                     : 1;  /**< Inbound Ring Packet Threshold Exceeded
1059                                                          When the pending \#inbound packets in system
1060                                                          memory(IRCNT) has exceeded a programmable threshold
1061                                                          (IRHWM), then this bit is set. If this does occur,
1062                                                          the IRTHRESH is set and the CIU_INTx_SUM0,4[MII] bits
1063                                                          are set if ((MIX_ISR & MIX_INTENA) != 0)).
1064                                                          If both the global interrupt mask bits (CIU_INTx_EN*[MII])
1065                                                          and the local interrupt mask bit(ITHENA) is set, than an
1066                                                          interrupt is reported for this event. */
1067         uint64_t orthresh                     : 1;  /**< Outbound Ring Packet Threshold Exceeded
1068                                                          When the pending \#outbound packets in system
1069                                                          memory(ORCNT) has exceeded a programmable threshold
1070                                                          (ORHWM), then this bit is set. If this does occur,
1071                                                          the ORTHRESH is set and the CIU_INTx_SUM0,4[MII] bits
1072                                                          are set if ((MIX_ISR & MIX_INTENA) != 0)).
1073                                                          If both the global interrupt mask bits (CIU_INTx_EN*[MII])
1074                                                          and the local interrupt mask bit(OTHENA) is set, than an
1075                                                          interrupt is reported for this event. */
1076         uint64_t idblovf                      : 1;  /**< Inbound DoorBell(IDBELL) Overflow Detected
1077                                                          If SW attempts to write to the MIX_IRING2[IDBELL]
1078                                                          with a value greater than the remaining \#of
1079                                                          I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then
1080                                                          the following occurs:
1081                                                          1) The  MIX_IRING2[IDBELL] write is IGNORED
1082                                                          2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]
1083                                                             bits are set if ((MIX_ISR & MIX_INTENA) != 0)).
1084                                                          If both the global interrupt mask bits (CIU_INTx_EN*[MII])
1085                                                          and the local interrupt mask bit(IVFENA) is set, than an
1086                                                          interrupt is reported for this event.
1087                                                          SW should keep track of the \#I-Ring Entries in use
1088                                                          (ie: cumulative \# of IDBELL writes),  and ensure that
1089                                                          future IDBELL writes don't exceed the size of the
1090                                                          I-Ring Buffer (MIX_IRING2[ISIZE]).
1091                                                          SW must reclaim I-Ring Entries by keeping track of the
1092                                                          \#IRing-Entries, and writing to the MIX_IRCNT[IRCNT].
1093                                                          NOTE: The MIX_IRCNT[IRCNT] register represents the
1094                                                          total \#packets(not IRing Entries) and SW must further
1095                                                          keep track of the \# of I-Ring Entries associated with
1096                                                          each packet as they are processed.
1097                                                          NOTE: There is no recovery from an IDBLOVF Interrupt.
1098                                                          If it occurs, it's an indication that SW has
1099                                                          overwritten the I-Ring buffer, and the only recourse
1100                                                          is a HW reset. */
1101         uint64_t odblovf                      : 1;  /**< Outbound DoorBell(ODBELL) Overflow Detected
1102                                                          If SW attempts to write to the MIX_ORING2[ODBELL]
1103                                                          with a value greater than the remaining \#of
1104                                                          O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then
1105                                                          the following occurs:
1106                                                          1) The  MIX_ORING2[ODBELL] write is IGNORED
1107                                                          2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]
1108                                                             bits are set if ((MIX_ISR & MIX_INTENA) != 0)).
1109                                                          If both the global interrupt mask bits (CIU_INTx_EN*[MII])
1110                                                          and the local interrupt mask bit(OVFENA) is set, than an
1111                                                          interrupt is reported for this event.
1112                                                          SW should keep track of the \#I-Ring Entries in use
1113                                                          (ie: cumulative \# of ODBELL writes),  and ensure that
1114                                                          future ODBELL writes don't exceed the size of the
1115                                                          O-Ring Buffer (MIX_ORING2[OSIZE]).
1116                                                          SW must reclaim O-Ring Entries by writing to the
1117                                                          MIX_ORCNT[ORCNT]. .
1118                                                          NOTE: There is no recovery from an ODBLOVF Interrupt.
1119                                                          If it occurs, it's an indication that SW has
1120                                                          overwritten the O-Ring buffer, and the only recourse
1121                                                          is a HW reset. */
1122 #else
1123         uint64_t odblovf                      : 1;
1124         uint64_t idblovf                      : 1;
1125         uint64_t orthresh                     : 1;
1126         uint64_t irthresh                     : 1;
1127         uint64_t data_drp                     : 1;
1128         uint64_t irun                         : 1;
1129         uint64_t orun                         : 1;
1130         uint64_t reserved_7_63                : 57;
1131 #endif
1132         } cn52xx;
1133         struct cvmx_mixx_isr_cn52xx           cn52xxp1;
1134         struct cvmx_mixx_isr_cn52xx           cn56xx;
1135         struct cvmx_mixx_isr_cn52xx           cn56xxp1;
1136         struct cvmx_mixx_isr_s                cn61xx;
1137         struct cvmx_mixx_isr_s                cn63xx;
1138         struct cvmx_mixx_isr_s                cn63xxp1;
1139         struct cvmx_mixx_isr_s                cn66xx;
1140         struct cvmx_mixx_isr_s                cn68xx;
1141         struct cvmx_mixx_isr_s                cn68xxp1;
1142 };
1143 typedef union cvmx_mixx_isr cvmx_mixx_isr_t;
1144
1145 /**
1146  * cvmx_mix#_orcnt
1147  *
1148  * MIX_ORCNT = MIX O-Ring Packets Sent Counter
1149  *
1150  * Description:
1151  *  NOTE: To write to the MIX_ORCNT register, a device would issue an IOBST directed at the MIO.
1152  *        To read the MIX_ORCNT register, a device would issue an IOBLD64 directed at the MIO.
1153  */
1154 union cvmx_mixx_orcnt {
1155         uint64_t u64;
1156         struct cvmx_mixx_orcnt_s {
1157 #ifdef __BIG_ENDIAN_BITFIELD
1158         uint64_t reserved_20_63               : 44;
1159         uint64_t orcnt                        : 20; /**< Pending \# of O-Ring Packets.
1160                                                          Whenever HW removes a packet from the O-Ring, it
1161                                                          increments the ORCNT (to indicate to SW the \# of
1162                                                          Output packets in system memory that can be reclaimed).
1163                                                          Reads of ORCNT return the current count.
1164                                                          Writes of ORCNT decrement the count by the value
1165                                                          written.
1166                                                          This register is used to generate interrupts to alert
1167                                                          SW of pending outbound MIX packets that have been
1168                                                          removed from system memory. (see MIX_ISR[ORTHRESH]
1169                                                          description for more details).
1170                                                          NOTE: For outbound packets, the \# of O-Ring Packets
1171                                                          is equal to the \# of O-Ring Entries. */
1172 #else
1173         uint64_t orcnt                        : 20;
1174         uint64_t reserved_20_63               : 44;
1175 #endif
1176         } s;
1177         struct cvmx_mixx_orcnt_s              cn52xx;
1178         struct cvmx_mixx_orcnt_s              cn52xxp1;
1179         struct cvmx_mixx_orcnt_s              cn56xx;
1180         struct cvmx_mixx_orcnt_s              cn56xxp1;
1181         struct cvmx_mixx_orcnt_s              cn61xx;
1182         struct cvmx_mixx_orcnt_s              cn63xx;
1183         struct cvmx_mixx_orcnt_s              cn63xxp1;
1184         struct cvmx_mixx_orcnt_s              cn66xx;
1185         struct cvmx_mixx_orcnt_s              cn68xx;
1186         struct cvmx_mixx_orcnt_s              cn68xxp1;
1187 };
1188 typedef union cvmx_mixx_orcnt cvmx_mixx_orcnt_t;
1189
1190 /**
1191  * cvmx_mix#_orhwm
1192  *
1193  * MIX_ORHWM = MIX O-Ring High-Water Mark Threshold Register
1194  *
1195  * Description:
1196  *  NOTE: To write to the MIX_ORHWM register, a device would issue an IOBST directed at the MIO.
1197  *        To read the MIX_ORHWM register, a device would issue an IOBLD64 directed at the MIO.
1198  */
1199 union cvmx_mixx_orhwm {
1200         uint64_t u64;
1201         struct cvmx_mixx_orhwm_s {
1202 #ifdef __BIG_ENDIAN_BITFIELD
1203         uint64_t reserved_20_63               : 44;
1204         uint64_t orhwm                        : 20; /**< O-Ring Entry High Water Mark Threshold.
1205                                                          Used to determine when the \# of Outbound packets
1206                                                          in system memory that can be reclaimed
1207                                                          (MIX_ORCNT[ORCNT]) exceeds this ORHWM threshold.
1208                                                          NOTE: The power-on value of the CIU2_EN_xx_yy_PKT[MII]
1209                                                          interrupt enable bits is zero and must be enabled
1210                                                          to allow interrupts to be reported. */
1211 #else
1212         uint64_t orhwm                        : 20;
1213         uint64_t reserved_20_63               : 44;
1214 #endif
1215         } s;
1216         struct cvmx_mixx_orhwm_s              cn52xx;
1217         struct cvmx_mixx_orhwm_s              cn52xxp1;
1218         struct cvmx_mixx_orhwm_s              cn56xx;
1219         struct cvmx_mixx_orhwm_s              cn56xxp1;
1220         struct cvmx_mixx_orhwm_s              cn61xx;
1221         struct cvmx_mixx_orhwm_s              cn63xx;
1222         struct cvmx_mixx_orhwm_s              cn63xxp1;
1223         struct cvmx_mixx_orhwm_s              cn66xx;
1224         struct cvmx_mixx_orhwm_s              cn68xx;
1225         struct cvmx_mixx_orhwm_s              cn68xxp1;
1226 };
1227 typedef union cvmx_mixx_orhwm cvmx_mixx_orhwm_t;
1228
1229 /**
1230  * cvmx_mix#_oring1
1231  *
1232  * MIX_ORING1 = MIX Outbound Ring Register \#1
1233  *
1234  * Description:
1235  *  NOTE: To write to the MIX_ORING1 register, a device would issue an IOBST directed at the MIO.
1236  *        To read the MIX_ORING1 register, a device would issue an IOBLD64 directed at the MIO.
1237  */
1238 union cvmx_mixx_oring1 {
1239         uint64_t u64;
1240         struct cvmx_mixx_oring1_s {
1241 #ifdef __BIG_ENDIAN_BITFIELD
1242         uint64_t reserved_60_63               : 4;
1243         uint64_t osize                        : 20; /**< Represents the Outbound Ring Buffer's Size(in 8B
1244                                                          words). The ring can be as large as 1M entries.
1245                                                          NOTE: This CSR MUST BE setup written by SW poweron
1246                                                          (when ODBELL/ORCNT=0). */
1247         uint64_t obase                        : 37; /**< Represents the 8B-aligned base address of the first
1248                                                          Outbound Ring(O-Ring) Entry in system memory.
1249                                                          NOTE: SW MUST ONLY write to this register during
1250                                                          power-on/boot code. */
1251         uint64_t reserved_0_2                 : 3;
1252 #else
1253         uint64_t reserved_0_2                 : 3;
1254         uint64_t obase                        : 37;
1255         uint64_t osize                        : 20;
1256         uint64_t reserved_60_63               : 4;
1257 #endif
1258         } s;
1259         struct cvmx_mixx_oring1_cn52xx {
1260 #ifdef __BIG_ENDIAN_BITFIELD
1261         uint64_t reserved_60_63               : 4;
1262         uint64_t osize                        : 20; /**< Represents the Outbound Ring Buffer's Size(in 8B
1263                                                          words). The ring can be as large as 1M entries.
1264                                                          NOTE: This CSR MUST BE setup written by SW poweron
1265                                                          (when ODBELL/ORCNT=0). */
1266         uint64_t reserved_36_39               : 4;
1267         uint64_t obase                        : 33; /**< Represents the 8B-aligned base address of the first
1268                                                          Outbound Ring(O-Ring) Entry in system memory.
1269                                                          NOTE: SW MUST ONLY write to this register during
1270                                                          power-on/boot code. */
1271         uint64_t reserved_0_2                 : 3;
1272 #else
1273         uint64_t reserved_0_2                 : 3;
1274         uint64_t obase                        : 33;
1275         uint64_t reserved_36_39               : 4;
1276         uint64_t osize                        : 20;
1277         uint64_t reserved_60_63               : 4;
1278 #endif
1279         } cn52xx;
1280         struct cvmx_mixx_oring1_cn52xx        cn52xxp1;
1281         struct cvmx_mixx_oring1_cn52xx        cn56xx;
1282         struct cvmx_mixx_oring1_cn52xx        cn56xxp1;
1283         struct cvmx_mixx_oring1_s             cn61xx;
1284         struct cvmx_mixx_oring1_s             cn63xx;
1285         struct cvmx_mixx_oring1_s             cn63xxp1;
1286         struct cvmx_mixx_oring1_s             cn66xx;
1287         struct cvmx_mixx_oring1_s             cn68xx;
1288         struct cvmx_mixx_oring1_s             cn68xxp1;
1289 };
1290 typedef union cvmx_mixx_oring1 cvmx_mixx_oring1_t;
1291
1292 /**
1293  * cvmx_mix#_oring2
1294  *
1295  * MIX_ORING2 = MIX Outbound Ring Register \#2
1296  *
1297  * Description:
1298  *  NOTE: To write to the MIX_ORING2 register, a device would issue an IOBST directed at the MIO.
1299  *        To read the MIX_ORING2 register, a device would issue an IOBLD64 directed at the MIO.
1300  */
1301 union cvmx_mixx_oring2 {
1302         uint64_t u64;
1303         struct cvmx_mixx_oring2_s {
1304 #ifdef __BIG_ENDIAN_BITFIELD
1305         uint64_t reserved_52_63               : 12;
1306         uint64_t otlptr                       : 20; /**< The Outbound Ring Tail Pointer selects the O-Ring
1307                                                          Entry that the HW will process next. After the HW
1308                                                          completes sending an outbound packet, it increments
1309                                                          the O-Ring Tail Pointer. [NOTE: The O-Ring Tail
1310                                                          Pointer HW increment is always modulo
1311                                                          MIX_ORING2[OSIZE].
1312                                                          NOTE: This field is 'read-only' to SW. */
1313         uint64_t reserved_20_31               : 12;
1314         uint64_t odbell                       : 20; /**< Represents the cumulative total of pending
1315                                                          Outbound Ring(O-Ring) Buffer Entries. Each O-Ring
1316                                                          Buffer Entry contains 1) an L2/DRAM byte pointer
1317                                                          along with a 2) a Byte Length.
1318                                                          After SW inserts new entries into the O-Ring Buffer,
1319                                                          it "rings the doorbell with the count of the newly
1320                                                          inserted entries". When the MIX HW receives the
1321                                                          doorbell ring, it increments the current doorbell
1322                                                          count by the CSR write value.
1323                                                          SW must never cause the doorbell count for the
1324                                                          O-Ring to exceed the size of the ring(OSIZE).
1325                                                          A read of the CSR indicates the current doorbell
1326                                                          count. */
1327 #else
1328         uint64_t odbell                       : 20;
1329         uint64_t reserved_20_31               : 12;
1330         uint64_t otlptr                       : 20;
1331         uint64_t reserved_52_63               : 12;
1332 #endif
1333         } s;
1334         struct cvmx_mixx_oring2_s             cn52xx;
1335         struct cvmx_mixx_oring2_s             cn52xxp1;
1336         struct cvmx_mixx_oring2_s             cn56xx;
1337         struct cvmx_mixx_oring2_s             cn56xxp1;
1338         struct cvmx_mixx_oring2_s             cn61xx;
1339         struct cvmx_mixx_oring2_s             cn63xx;
1340         struct cvmx_mixx_oring2_s             cn63xxp1;
1341         struct cvmx_mixx_oring2_s             cn66xx;
1342         struct cvmx_mixx_oring2_s             cn68xx;
1343         struct cvmx_mixx_oring2_s             cn68xxp1;
1344 };
1345 typedef union cvmx_mixx_oring2 cvmx_mixx_oring2_t;
1346
1347 /**
1348  * cvmx_mix#_remcnt
1349  *
1350  * MIX_REMCNT = MIX Ring Buffer Remainder Counts (useful for HW debug only)
1351  *
1352  * Description:
1353  *  NOTE: To read the MIX_REMCNT register, a device would issue an IOBLD64 directed at the MIO.
1354  */
1355 union cvmx_mixx_remcnt {
1356         uint64_t u64;
1357         struct cvmx_mixx_remcnt_s {
1358 #ifdef __BIG_ENDIAN_BITFIELD
1359         uint64_t reserved_52_63               : 12;
1360         uint64_t iremcnt                      : 20; /**< Remaining I-Ring Buffer Count
1361                                                          Reflects the \# of unused/remaining I-Ring Entries
1362                                                          that HW  currently detects in the I-Ring Buffer.
1363                                                          HW uses this value to detect I-Ring Doorbell overflows.
1364                                                          (see: MIX_ISR[IDBLOVF])
1365                                                          When SW writes the MIX_IRING1[ISIZE], the IREMCNT
1366                                                          is loaded with MIX_IRING2[ISIZE] value. (NOTE: ISIZE should only
1367                                                          be written at power-on, when it's known that there are
1368                                                          no I-Ring Entries currently in use by HW).
1369                                                          When SW writes to the IDBELL register, the IREMCNT
1370                                                          is decremented by the CSR write value.
1371                                                          When HW issues an IRing Write Request(onto NCB Bus),
1372                                                          the IREMCNT is incremented by 1. */
1373         uint64_t reserved_20_31               : 12;
1374         uint64_t oremcnt                      : 20; /**< Remaining O-Ring Buffer Count
1375                                                          Reflects the \# of unused/remaining O-Ring Entries
1376                                                          that HW  currently detects in the O-Ring Buffer.
1377                                                          HW uses this value to detect O-Ring Doorbell overflows.
1378                                                          (see: MIX_ISR[ODBLOVF])
1379                                                          When SW writes the MIX_IRING1[OSIZE], the OREMCNT
1380                                                          is loaded with MIX_ORING2[OSIZE] value. (NOTE: OSIZE should only
1381                                                          be written at power-on, when it's known that there are
1382                                                          no O-Ring Entries currently in use by HW).
1383                                                          When SW writes to the ODBELL register, the OREMCNT
1384                                                          is decremented by the CSR write value.
1385                                                          When SW writes to MIX_[OREMCNT], the OREMCNT is decremented
1386                                                          by the CSR write value. */
1387 #else
1388         uint64_t oremcnt                      : 20;
1389         uint64_t reserved_20_31               : 12;
1390         uint64_t iremcnt                      : 20;
1391         uint64_t reserved_52_63               : 12;
1392 #endif
1393         } s;
1394         struct cvmx_mixx_remcnt_s             cn52xx;
1395         struct cvmx_mixx_remcnt_s             cn52xxp1;
1396         struct cvmx_mixx_remcnt_s             cn56xx;
1397         struct cvmx_mixx_remcnt_s             cn56xxp1;
1398         struct cvmx_mixx_remcnt_s             cn61xx;
1399         struct cvmx_mixx_remcnt_s             cn63xx;
1400         struct cvmx_mixx_remcnt_s             cn63xxp1;
1401         struct cvmx_mixx_remcnt_s             cn66xx;
1402         struct cvmx_mixx_remcnt_s             cn68xx;
1403         struct cvmx_mixx_remcnt_s             cn68xxp1;
1404 };
1405 typedef union cvmx_mixx_remcnt cvmx_mixx_remcnt_t;
1406
1407 /**
1408  * cvmx_mix#_tsctl
1409  *
1410  * MIX_TSCTL = MIX TimeStamp Control Register
1411  *
1412  * Description:
1413  *  NOTE: To read the MIX_TSCTL register, a device would issue an IOBLD64 directed at the MIO.
1414  *
1415  * Notes:
1416  * SW can read the MIX_TSCTL register to determine the \#pending timestamp interrupts(TSCNT)
1417  * as well as the \#outstanding timestamp requests in flight(TSTOT), as well as the \#of available
1418  * timestamp entries (TSAVL) in the timestamp fifo.
1419  * A write to the MIX_TSCTL register will advance the MIX*_TSTAMP fifo head ptr by 1, and
1420  * also decrements the MIX*_TSCTL[TSCNT] and MIX*_TSCTL[TSTOT] pending count(s) by 1.
1421  * For example, if SW reads MIX*_TSCTL[TSCNT]=2 (2 pending timestamp interrupts), it would immediately
1422  * issue this sequence:
1423  *      1) MIX*_TSTAMP[TSTAMP] read followed by MIX*_TSCTL write
1424  *            [gets timestamp value/pops timestamp fifo and decrements pending count(s) by 1]
1425  *      2) MIX*_TSTAMP[TSTAMP] read followed by MIX*_TSCTL write
1426  *            [gets timestamp value/pops timestamp fifo and decrements pending count(s) by 1]
1427  *
1428  * SWNOTE: A MIX_TSCTL write when MIX_TSCTL[TSCNT]=0 (ie: TimeStamp Fifo empty), then the write is ignored.
1429  */
1430 union cvmx_mixx_tsctl {
1431         uint64_t u64;
1432         struct cvmx_mixx_tsctl_s {
1433 #ifdef __BIG_ENDIAN_BITFIELD
1434         uint64_t reserved_21_63               : 43;
1435         uint64_t tsavl                        : 5;  /**< # of MIX TimeStamp Entries Available for use
1436                                                          For o63: TSAVL MAX=4 (implementation
1437                                                          depth of timestamp fifo)
1438                                                          TSAVL = [IMPLEMENTATION_DEPTH=4(MAX) - TSCNT] */
1439         uint64_t reserved_13_15               : 3;
1440         uint64_t tstot                        : 5;  /**< # of pending MIX TimeStamp Requests in-flight
1441                                                          For o63: TSTOT must never exceed MAX=4 (implementation
1442                                                          depth of timestamp fifo) */
1443         uint64_t reserved_5_7                 : 3;
1444         uint64_t tscnt                        : 5;  /**< # of pending MIX TimeStamp Interrupts
1445                                                          For o63: TSCNT must never exceed MAX=4 (implementation
1446                                                          depth of timestamp fifo) */
1447 #else
1448         uint64_t tscnt                        : 5;
1449         uint64_t reserved_5_7                 : 3;
1450         uint64_t tstot                        : 5;
1451         uint64_t reserved_13_15               : 3;
1452         uint64_t tsavl                        : 5;
1453         uint64_t reserved_21_63               : 43;
1454 #endif
1455         } s;
1456         struct cvmx_mixx_tsctl_s              cn61xx;
1457         struct cvmx_mixx_tsctl_s              cn63xx;
1458         struct cvmx_mixx_tsctl_s              cn63xxp1;
1459         struct cvmx_mixx_tsctl_s              cn66xx;
1460         struct cvmx_mixx_tsctl_s              cn68xx;
1461         struct cvmx_mixx_tsctl_s              cn68xxp1;
1462 };
1463 typedef union cvmx_mixx_tsctl cvmx_mixx_tsctl_t;
1464
1465 /**
1466  * cvmx_mix#_tstamp
1467  *
1468  * MIX_TSTAMP = MIX TimeStamp Register
1469  *
1470  * Description:
1471  *  NOTE: To read the MIX_TSTAMP register, a device would issue an IOBLD64 directed at the MIO.
1472  */
1473 union cvmx_mixx_tstamp {
1474         uint64_t u64;
1475         struct cvmx_mixx_tstamp_s {
1476 #ifdef __BIG_ENDIAN_BITFIELD
1477         uint64_t tstamp                       : 64; /**< MIX TimeStamp Value
1478                                                           When SW sets up an ORING Entry with [47]=1(TSTAMP),
1479                                                           The packet is tagged with a specal SOP w/TSTAMP flag
1480                                                           as it is sent to the AGL.
1481                                                           Later the AGL will send "sample" strobe(s) to capture
1482                                                           a global 64bit timestamp value followed by a "commit"
1483                                                           strobe which writes the last sampled value into the
1484                                                           outbound Timestamp fifo (max depth=4) and increments
1485                                                           the MIX_TSCTL[TSCNT] register to indicate the total
1486                                                           \#of pending Timestamp interrupts.
1487                                                           If the \#pending Timestamp interrupts (MIX_TSCTL[TSCNT])
1488                                                           is greater than the MIX_CTL[TS_THRESH] value, then
1489                                                           a programmable interrupt is also triggered (see:
1490                                                           MIX_ISR[TS] MIX_INTENA[TSENA]).
1491                                                           SW will then read the MIX*_TSTAMP[TSTAMP]
1492                                                           register value, and MUST THEN write the MIX_TSCTL
1493                                                           register, which will decrement MIX_TSCTL[TSCNT] register,
1494                                                           to indicate that a single timestamp interrupt has
1495                                                           been serviced.
1496                                                           NOTE: The MIO-MIX HW tracks upto MAX=4 outstanding
1497                                                           timestamped outbound packets at a time. All subsequent
1498                                                           ORING Entries w/SOP-TSTAMP will be stalled until
1499                                                           SW can service the 4 outstanding interrupts.
1500                                                           SW can read the MIX_TSCTL register to determine the
1501                                                           \#pending timestamp interrupts(TSCNT) as well as the
1502                                                           \#outstanding timestamp requests in flight(TSTOT), as
1503                                                           well as the \#of available timestamp entries (TSAVL).
1504                                                          SW NOTE: A MIX_TSTAMP read when MIX_TSCTL[TSCNT]=0, will
1505                                                          result in a return value of all zeroes. SW should only
1506                                                          read this register when MIX_ISR[TS]=1 (or when
1507                                                          MIX_TSCTL[TSCNT] != 0) to retrieve the timestamp value
1508                                                          recorded by HW. If SW reads the TSTAMP when HW has not
1509                                                          recorded a valid timestamp, then an  all zeroes value is
1510                                                          returned. */
1511 #else
1512         uint64_t tstamp                       : 64;
1513 #endif
1514         } s;
1515         struct cvmx_mixx_tstamp_s             cn61xx;
1516         struct cvmx_mixx_tstamp_s             cn63xx;
1517         struct cvmx_mixx_tstamp_s             cn63xxp1;
1518         struct cvmx_mixx_tstamp_s             cn66xx;
1519         struct cvmx_mixx_tstamp_s             cn68xx;
1520         struct cvmx_mixx_tstamp_s             cn68xxp1;
1521 };
1522 typedef union cvmx_mixx_tstamp cvmx_mixx_tstamp_t;
1523
1524 #endif