1 /***********************license start***************
2 * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * * Neither the name of Cavium Inc. nor the names of
19 * its contributors may be used to endorse or promote products
20 * derived from this software without specific prior written
23 * This Software, including technical data, may be subject to U.S. export control
24 * laws, including the U.S. Export Administration Act and its associated
25 * regulations, and may be subject to export or import regulations in other
28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
38 ***********************license end**************************************/
44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_UAHCX_DEFS_H__
53 #define __CVMX_UAHCX_DEFS_H__
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
56 static inline uint64_t CVMX_UAHCX_EHCI_ASYNCLISTADDR(unsigned long block_id)
59 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
60 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
61 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
62 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
63 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
64 cvmx_warn("CVMX_UAHCX_EHCI_ASYNCLISTADDR(%lu) is invalid on this chip\n", block_id);
65 return CVMX_ADD_IO_SEG(0x00016F0000000028ull);
68 #define CVMX_UAHCX_EHCI_ASYNCLISTADDR(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000028ull))
70 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
71 static inline uint64_t CVMX_UAHCX_EHCI_CONFIGFLAG(unsigned long block_id)
74 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
75 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
76 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
77 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
78 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
79 cvmx_warn("CVMX_UAHCX_EHCI_CONFIGFLAG(%lu) is invalid on this chip\n", block_id);
80 return CVMX_ADD_IO_SEG(0x00016F0000000050ull);
83 #define CVMX_UAHCX_EHCI_CONFIGFLAG(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000050ull))
85 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
86 static inline uint64_t CVMX_UAHCX_EHCI_CTRLDSSEGMENT(unsigned long block_id)
89 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
90 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
91 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
92 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
93 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
94 cvmx_warn("CVMX_UAHCX_EHCI_CTRLDSSEGMENT(%lu) is invalid on this chip\n", block_id);
95 return CVMX_ADD_IO_SEG(0x00016F0000000020ull);
98 #define CVMX_UAHCX_EHCI_CTRLDSSEGMENT(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000020ull))
100 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
101 static inline uint64_t CVMX_UAHCX_EHCI_FRINDEX(unsigned long block_id)
104 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
105 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
106 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
107 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
108 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
109 cvmx_warn("CVMX_UAHCX_EHCI_FRINDEX(%lu) is invalid on this chip\n", block_id);
110 return CVMX_ADD_IO_SEG(0x00016F000000001Cull);
113 #define CVMX_UAHCX_EHCI_FRINDEX(block_id) (CVMX_ADD_IO_SEG(0x00016F000000001Cull))
115 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
116 static inline uint64_t CVMX_UAHCX_EHCI_HCCAPBASE(unsigned long block_id)
119 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
120 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
121 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
122 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
123 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
124 cvmx_warn("CVMX_UAHCX_EHCI_HCCAPBASE(%lu) is invalid on this chip\n", block_id);
125 return CVMX_ADD_IO_SEG(0x00016F0000000000ull);
128 #define CVMX_UAHCX_EHCI_HCCAPBASE(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000000ull))
130 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
131 static inline uint64_t CVMX_UAHCX_EHCI_HCCPARAMS(unsigned long block_id)
134 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
135 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
136 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
137 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
138 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
139 cvmx_warn("CVMX_UAHCX_EHCI_HCCPARAMS(%lu) is invalid on this chip\n", block_id);
140 return CVMX_ADD_IO_SEG(0x00016F0000000008ull);
143 #define CVMX_UAHCX_EHCI_HCCPARAMS(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000008ull))
145 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
146 static inline uint64_t CVMX_UAHCX_EHCI_HCSPARAMS(unsigned long block_id)
149 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
150 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
151 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
152 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
153 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
154 cvmx_warn("CVMX_UAHCX_EHCI_HCSPARAMS(%lu) is invalid on this chip\n", block_id);
155 return CVMX_ADD_IO_SEG(0x00016F0000000004ull);
158 #define CVMX_UAHCX_EHCI_HCSPARAMS(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000004ull))
160 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
161 static inline uint64_t CVMX_UAHCX_EHCI_INSNREG00(unsigned long block_id)
164 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
165 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
166 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
167 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
168 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
169 cvmx_warn("CVMX_UAHCX_EHCI_INSNREG00(%lu) is invalid on this chip\n", block_id);
170 return CVMX_ADD_IO_SEG(0x00016F0000000090ull);
173 #define CVMX_UAHCX_EHCI_INSNREG00(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000090ull))
175 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
176 static inline uint64_t CVMX_UAHCX_EHCI_INSNREG03(unsigned long block_id)
179 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
180 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
181 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
182 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
183 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
184 cvmx_warn("CVMX_UAHCX_EHCI_INSNREG03(%lu) is invalid on this chip\n", block_id);
185 return CVMX_ADD_IO_SEG(0x00016F000000009Cull);
188 #define CVMX_UAHCX_EHCI_INSNREG03(block_id) (CVMX_ADD_IO_SEG(0x00016F000000009Cull))
190 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
191 static inline uint64_t CVMX_UAHCX_EHCI_INSNREG04(unsigned long block_id)
194 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
195 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
196 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
197 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
198 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
199 cvmx_warn("CVMX_UAHCX_EHCI_INSNREG04(%lu) is invalid on this chip\n", block_id);
200 return CVMX_ADD_IO_SEG(0x00016F00000000A0ull);
203 #define CVMX_UAHCX_EHCI_INSNREG04(block_id) (CVMX_ADD_IO_SEG(0x00016F00000000A0ull))
205 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
206 static inline uint64_t CVMX_UAHCX_EHCI_INSNREG06(unsigned long block_id)
209 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
210 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
211 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
212 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
213 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
214 cvmx_warn("CVMX_UAHCX_EHCI_INSNREG06(%lu) is invalid on this chip\n", block_id);
215 return CVMX_ADD_IO_SEG(0x00016F00000000E8ull);
218 #define CVMX_UAHCX_EHCI_INSNREG06(block_id) (CVMX_ADD_IO_SEG(0x00016F00000000E8ull))
220 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
221 static inline uint64_t CVMX_UAHCX_EHCI_INSNREG07(unsigned long block_id)
224 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
225 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
226 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
227 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
228 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
229 cvmx_warn("CVMX_UAHCX_EHCI_INSNREG07(%lu) is invalid on this chip\n", block_id);
230 return CVMX_ADD_IO_SEG(0x00016F00000000ECull);
233 #define CVMX_UAHCX_EHCI_INSNREG07(block_id) (CVMX_ADD_IO_SEG(0x00016F00000000ECull))
235 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
236 static inline uint64_t CVMX_UAHCX_EHCI_PERIODICLISTBASE(unsigned long block_id)
239 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
240 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
241 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
242 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
243 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
244 cvmx_warn("CVMX_UAHCX_EHCI_PERIODICLISTBASE(%lu) is invalid on this chip\n", block_id);
245 return CVMX_ADD_IO_SEG(0x00016F0000000024ull);
248 #define CVMX_UAHCX_EHCI_PERIODICLISTBASE(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000024ull))
250 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
251 static inline uint64_t CVMX_UAHCX_EHCI_PORTSCX(unsigned long offset, unsigned long block_id)
254 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((((offset >= 1) && (offset <= 2))) && ((block_id == 0)))) ||
255 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((((offset >= 1) && (offset <= 2))) && ((block_id == 0)))) ||
256 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((((offset >= 1) && (offset <= 2))) && ((block_id == 0)))) ||
257 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((((offset >= 1) && (offset <= 2))) && ((block_id == 0)))) ||
258 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((((offset >= 1) && (offset <= 2))) && ((block_id == 0))))))
259 cvmx_warn("CVMX_UAHCX_EHCI_PORTSCX(%lu,%lu) is invalid on this chip\n", offset, block_id);
260 return CVMX_ADD_IO_SEG(0x00016F0000000050ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 4;
263 #define CVMX_UAHCX_EHCI_PORTSCX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0000000050ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 4)
265 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
266 static inline uint64_t CVMX_UAHCX_EHCI_USBCMD(unsigned long block_id)
269 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
270 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
271 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
272 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
273 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
274 cvmx_warn("CVMX_UAHCX_EHCI_USBCMD(%lu) is invalid on this chip\n", block_id);
275 return CVMX_ADD_IO_SEG(0x00016F0000000010ull);
278 #define CVMX_UAHCX_EHCI_USBCMD(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000010ull))
280 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
281 static inline uint64_t CVMX_UAHCX_EHCI_USBINTR(unsigned long block_id)
284 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
285 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
286 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
287 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
288 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
289 cvmx_warn("CVMX_UAHCX_EHCI_USBINTR(%lu) is invalid on this chip\n", block_id);
290 return CVMX_ADD_IO_SEG(0x00016F0000000018ull);
293 #define CVMX_UAHCX_EHCI_USBINTR(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000018ull))
295 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
296 static inline uint64_t CVMX_UAHCX_EHCI_USBSTS(unsigned long block_id)
299 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
300 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
301 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
302 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
303 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
304 cvmx_warn("CVMX_UAHCX_EHCI_USBSTS(%lu) is invalid on this chip\n", block_id);
305 return CVMX_ADD_IO_SEG(0x00016F0000000014ull);
308 #define CVMX_UAHCX_EHCI_USBSTS(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000014ull))
310 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
311 static inline uint64_t CVMX_UAHCX_OHCI0_HCBULKCURRENTED(unsigned long block_id)
314 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
315 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
316 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
317 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
318 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
319 cvmx_warn("CVMX_UAHCX_OHCI0_HCBULKCURRENTED(%lu) is invalid on this chip\n", block_id);
320 return CVMX_ADD_IO_SEG(0x00016F000000042Cull);
323 #define CVMX_UAHCX_OHCI0_HCBULKCURRENTED(block_id) (CVMX_ADD_IO_SEG(0x00016F000000042Cull))
325 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
326 static inline uint64_t CVMX_UAHCX_OHCI0_HCBULKHEADED(unsigned long block_id)
329 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
330 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
331 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
332 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
333 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
334 cvmx_warn("CVMX_UAHCX_OHCI0_HCBULKHEADED(%lu) is invalid on this chip\n", block_id);
335 return CVMX_ADD_IO_SEG(0x00016F0000000428ull);
338 #define CVMX_UAHCX_OHCI0_HCBULKHEADED(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000428ull))
340 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
341 static inline uint64_t CVMX_UAHCX_OHCI0_HCCOMMANDSTATUS(unsigned long block_id)
344 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
345 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
346 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
347 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
348 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
349 cvmx_warn("CVMX_UAHCX_OHCI0_HCCOMMANDSTATUS(%lu) is invalid on this chip\n", block_id);
350 return CVMX_ADD_IO_SEG(0x00016F0000000408ull);
353 #define CVMX_UAHCX_OHCI0_HCCOMMANDSTATUS(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000408ull))
355 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
356 static inline uint64_t CVMX_UAHCX_OHCI0_HCCONTROL(unsigned long block_id)
359 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
360 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
361 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
362 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
363 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
364 cvmx_warn("CVMX_UAHCX_OHCI0_HCCONTROL(%lu) is invalid on this chip\n", block_id);
365 return CVMX_ADD_IO_SEG(0x00016F0000000404ull);
368 #define CVMX_UAHCX_OHCI0_HCCONTROL(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000404ull))
370 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
371 static inline uint64_t CVMX_UAHCX_OHCI0_HCCONTROLCURRENTED(unsigned long block_id)
374 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
375 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
376 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
377 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
378 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
379 cvmx_warn("CVMX_UAHCX_OHCI0_HCCONTROLCURRENTED(%lu) is invalid on this chip\n", block_id);
380 return CVMX_ADD_IO_SEG(0x00016F0000000424ull);
383 #define CVMX_UAHCX_OHCI0_HCCONTROLCURRENTED(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000424ull))
385 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
386 static inline uint64_t CVMX_UAHCX_OHCI0_HCCONTROLHEADED(unsigned long block_id)
389 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
390 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
391 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
392 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
393 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
394 cvmx_warn("CVMX_UAHCX_OHCI0_HCCONTROLHEADED(%lu) is invalid on this chip\n", block_id);
395 return CVMX_ADD_IO_SEG(0x00016F0000000420ull);
398 #define CVMX_UAHCX_OHCI0_HCCONTROLHEADED(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000420ull))
400 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
401 static inline uint64_t CVMX_UAHCX_OHCI0_HCDONEHEAD(unsigned long block_id)
404 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
405 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
406 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
407 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
408 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
409 cvmx_warn("CVMX_UAHCX_OHCI0_HCDONEHEAD(%lu) is invalid on this chip\n", block_id);
410 return CVMX_ADD_IO_SEG(0x00016F0000000430ull);
413 #define CVMX_UAHCX_OHCI0_HCDONEHEAD(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000430ull))
415 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
416 static inline uint64_t CVMX_UAHCX_OHCI0_HCFMINTERVAL(unsigned long block_id)
419 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
420 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
421 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
422 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
423 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
424 cvmx_warn("CVMX_UAHCX_OHCI0_HCFMINTERVAL(%lu) is invalid on this chip\n", block_id);
425 return CVMX_ADD_IO_SEG(0x00016F0000000434ull);
428 #define CVMX_UAHCX_OHCI0_HCFMINTERVAL(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000434ull))
430 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
431 static inline uint64_t CVMX_UAHCX_OHCI0_HCFMNUMBER(unsigned long block_id)
434 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
435 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
436 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
437 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
438 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
439 cvmx_warn("CVMX_UAHCX_OHCI0_HCFMNUMBER(%lu) is invalid on this chip\n", block_id);
440 return CVMX_ADD_IO_SEG(0x00016F000000043Cull);
443 #define CVMX_UAHCX_OHCI0_HCFMNUMBER(block_id) (CVMX_ADD_IO_SEG(0x00016F000000043Cull))
445 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
446 static inline uint64_t CVMX_UAHCX_OHCI0_HCFMREMAINING(unsigned long block_id)
449 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
450 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
451 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
452 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
453 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
454 cvmx_warn("CVMX_UAHCX_OHCI0_HCFMREMAINING(%lu) is invalid on this chip\n", block_id);
455 return CVMX_ADD_IO_SEG(0x00016F0000000438ull);
458 #define CVMX_UAHCX_OHCI0_HCFMREMAINING(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000438ull))
460 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
461 static inline uint64_t CVMX_UAHCX_OHCI0_HCHCCA(unsigned long block_id)
464 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
465 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
466 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
467 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
468 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
469 cvmx_warn("CVMX_UAHCX_OHCI0_HCHCCA(%lu) is invalid on this chip\n", block_id);
470 return CVMX_ADD_IO_SEG(0x00016F0000000418ull);
473 #define CVMX_UAHCX_OHCI0_HCHCCA(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000418ull))
475 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
476 static inline uint64_t CVMX_UAHCX_OHCI0_HCINTERRUPTDISABLE(unsigned long block_id)
479 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
480 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
481 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
482 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
483 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
484 cvmx_warn("CVMX_UAHCX_OHCI0_HCINTERRUPTDISABLE(%lu) is invalid on this chip\n", block_id);
485 return CVMX_ADD_IO_SEG(0x00016F0000000414ull);
488 #define CVMX_UAHCX_OHCI0_HCINTERRUPTDISABLE(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000414ull))
490 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
491 static inline uint64_t CVMX_UAHCX_OHCI0_HCINTERRUPTENABLE(unsigned long block_id)
494 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
495 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
496 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
497 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
498 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
499 cvmx_warn("CVMX_UAHCX_OHCI0_HCINTERRUPTENABLE(%lu) is invalid on this chip\n", block_id);
500 return CVMX_ADD_IO_SEG(0x00016F0000000410ull);
503 #define CVMX_UAHCX_OHCI0_HCINTERRUPTENABLE(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000410ull))
505 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
506 static inline uint64_t CVMX_UAHCX_OHCI0_HCINTERRUPTSTATUS(unsigned long block_id)
509 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
510 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
511 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
512 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
513 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
514 cvmx_warn("CVMX_UAHCX_OHCI0_HCINTERRUPTSTATUS(%lu) is invalid on this chip\n", block_id);
515 return CVMX_ADD_IO_SEG(0x00016F000000040Cull);
518 #define CVMX_UAHCX_OHCI0_HCINTERRUPTSTATUS(block_id) (CVMX_ADD_IO_SEG(0x00016F000000040Cull))
520 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
521 static inline uint64_t CVMX_UAHCX_OHCI0_HCLSTHRESHOLD(unsigned long block_id)
524 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
525 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
526 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
527 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
528 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
529 cvmx_warn("CVMX_UAHCX_OHCI0_HCLSTHRESHOLD(%lu) is invalid on this chip\n", block_id);
530 return CVMX_ADD_IO_SEG(0x00016F0000000444ull);
533 #define CVMX_UAHCX_OHCI0_HCLSTHRESHOLD(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000444ull))
535 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
536 static inline uint64_t CVMX_UAHCX_OHCI0_HCPERIODCURRENTED(unsigned long block_id)
539 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
540 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
541 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
542 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
543 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
544 cvmx_warn("CVMX_UAHCX_OHCI0_HCPERIODCURRENTED(%lu) is invalid on this chip\n", block_id);
545 return CVMX_ADD_IO_SEG(0x00016F000000041Cull);
548 #define CVMX_UAHCX_OHCI0_HCPERIODCURRENTED(block_id) (CVMX_ADD_IO_SEG(0x00016F000000041Cull))
550 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
551 static inline uint64_t CVMX_UAHCX_OHCI0_HCPERIODICSTART(unsigned long block_id)
554 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
555 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
556 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
557 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
558 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
559 cvmx_warn("CVMX_UAHCX_OHCI0_HCPERIODICSTART(%lu) is invalid on this chip\n", block_id);
560 return CVMX_ADD_IO_SEG(0x00016F0000000440ull);
563 #define CVMX_UAHCX_OHCI0_HCPERIODICSTART(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000440ull))
565 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
566 static inline uint64_t CVMX_UAHCX_OHCI0_HCREVISION(unsigned long block_id)
569 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
570 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
571 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
572 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
573 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
574 cvmx_warn("CVMX_UAHCX_OHCI0_HCREVISION(%lu) is invalid on this chip\n", block_id);
575 return CVMX_ADD_IO_SEG(0x00016F0000000400ull);
578 #define CVMX_UAHCX_OHCI0_HCREVISION(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000400ull))
580 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
581 static inline uint64_t CVMX_UAHCX_OHCI0_HCRHDESCRIPTORA(unsigned long block_id)
584 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
585 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
586 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
587 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
588 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
589 cvmx_warn("CVMX_UAHCX_OHCI0_HCRHDESCRIPTORA(%lu) is invalid on this chip\n", block_id);
590 return CVMX_ADD_IO_SEG(0x00016F0000000448ull);
593 #define CVMX_UAHCX_OHCI0_HCRHDESCRIPTORA(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000448ull))
595 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
596 static inline uint64_t CVMX_UAHCX_OHCI0_HCRHDESCRIPTORB(unsigned long block_id)
599 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
600 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
601 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
602 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
603 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
604 cvmx_warn("CVMX_UAHCX_OHCI0_HCRHDESCRIPTORB(%lu) is invalid on this chip\n", block_id);
605 return CVMX_ADD_IO_SEG(0x00016F000000044Cull);
608 #define CVMX_UAHCX_OHCI0_HCRHDESCRIPTORB(block_id) (CVMX_ADD_IO_SEG(0x00016F000000044Cull))
610 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
611 static inline uint64_t CVMX_UAHCX_OHCI0_HCRHPORTSTATUSX(unsigned long offset, unsigned long block_id)
614 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((((offset >= 1) && (offset <= 2))) && ((block_id == 0)))) ||
615 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((((offset >= 1) && (offset <= 2))) && ((block_id == 0)))) ||
616 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((((offset >= 1) && (offset <= 2))) && ((block_id == 0)))) ||
617 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((((offset >= 1) && (offset <= 2))) && ((block_id == 0)))) ||
618 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((((offset >= 1) && (offset <= 2))) && ((block_id == 0))))))
619 cvmx_warn("CVMX_UAHCX_OHCI0_HCRHPORTSTATUSX(%lu,%lu) is invalid on this chip\n", offset, block_id);
620 return CVMX_ADD_IO_SEG(0x00016F0000000450ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 4;
623 #define CVMX_UAHCX_OHCI0_HCRHPORTSTATUSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0000000450ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 4)
625 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
626 static inline uint64_t CVMX_UAHCX_OHCI0_HCRHSTATUS(unsigned long block_id)
629 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
630 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
631 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
632 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
633 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
634 cvmx_warn("CVMX_UAHCX_OHCI0_HCRHSTATUS(%lu) is invalid on this chip\n", block_id);
635 return CVMX_ADD_IO_SEG(0x00016F0000000450ull);
638 #define CVMX_UAHCX_OHCI0_HCRHSTATUS(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000450ull))
640 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
641 static inline uint64_t CVMX_UAHCX_OHCI0_INSNREG06(unsigned long block_id)
644 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
645 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
646 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
647 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
648 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
649 cvmx_warn("CVMX_UAHCX_OHCI0_INSNREG06(%lu) is invalid on this chip\n", block_id);
650 return CVMX_ADD_IO_SEG(0x00016F0000000498ull);
653 #define CVMX_UAHCX_OHCI0_INSNREG06(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000498ull))
655 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
656 static inline uint64_t CVMX_UAHCX_OHCI0_INSNREG07(unsigned long block_id)
659 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
660 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
661 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
662 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
663 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
664 cvmx_warn("CVMX_UAHCX_OHCI0_INSNREG07(%lu) is invalid on this chip\n", block_id);
665 return CVMX_ADD_IO_SEG(0x00016F000000049Cull);
668 #define CVMX_UAHCX_OHCI0_INSNREG07(block_id) (CVMX_ADD_IO_SEG(0x00016F000000049Cull))
672 * cvmx_uahc#_ehci_asynclistaddr
674 * ASYNCLISTADDR = Current Asynchronous List Address Register
676 * This 32-bit register contains the address of the next asynchronous queue head to be executed. If the host
677 * controller is in 64-bit mode (as indicated by a one in 64-bit Addressing Capability field in the
678 * HCCPARAMS register), then the most significant 32 bits of every control data structure address comes from
679 * the CTRLDSSEGMENT register (See Section 2.3.5). Bits [4:0] of this register cannot be modified by system
680 * software and will always return a zero when read. The memory structure referenced by this physical memory
681 * pointer is assumed to be 32-byte (cache line) aligned.
683 union cvmx_uahcx_ehci_asynclistaddr {
685 struct cvmx_uahcx_ehci_asynclistaddr_s {
686 #ifdef __BIG_ENDIAN_BITFIELD
687 uint32_t lpl : 27; /**< Link Pointer Low (LPL). These bits correspond to memory address signals [31:5],
688 respectively. This field may only reference a Queue Head (QH). */
689 uint32_t reserved_0_4 : 5;
691 uint32_t reserved_0_4 : 5;
695 struct cvmx_uahcx_ehci_asynclistaddr_s cn61xx;
696 struct cvmx_uahcx_ehci_asynclistaddr_s cn63xx;
697 struct cvmx_uahcx_ehci_asynclistaddr_s cn63xxp1;
698 struct cvmx_uahcx_ehci_asynclistaddr_s cn66xx;
699 struct cvmx_uahcx_ehci_asynclistaddr_s cn68xx;
700 struct cvmx_uahcx_ehci_asynclistaddr_s cn68xxp1;
701 struct cvmx_uahcx_ehci_asynclistaddr_s cnf71xx;
703 typedef union cvmx_uahcx_ehci_asynclistaddr cvmx_uahcx_ehci_asynclistaddr_t;
706 * cvmx_uahc#_ehci_configflag
708 * CONFIGFLAG = Configure Flag Register
709 * This register is in the auxiliary power well. It is only reset by hardware when the auxiliary power is initially
710 * applied or in response to a host controller reset.
712 union cvmx_uahcx_ehci_configflag {
714 struct cvmx_uahcx_ehci_configflag_s {
715 #ifdef __BIG_ENDIAN_BITFIELD
716 uint32_t reserved_1_31 : 31;
717 uint32_t cf : 1; /**< Configure Flag (CF) .Host software sets this bit as the last action in
718 its process of configuring the Host Controller (see Section 4.1). This bit controls the
719 default port-routing control logic. Bit values and side-effects are listed below.
720 0b: Port routing control logic default-routes each port to an implementation
721 dependent classic host controller.
722 1b: Port routing control logic default-routes all ports to this host controller. */
725 uint32_t reserved_1_31 : 31;
728 struct cvmx_uahcx_ehci_configflag_s cn61xx;
729 struct cvmx_uahcx_ehci_configflag_s cn63xx;
730 struct cvmx_uahcx_ehci_configflag_s cn63xxp1;
731 struct cvmx_uahcx_ehci_configflag_s cn66xx;
732 struct cvmx_uahcx_ehci_configflag_s cn68xx;
733 struct cvmx_uahcx_ehci_configflag_s cn68xxp1;
734 struct cvmx_uahcx_ehci_configflag_s cnf71xx;
736 typedef union cvmx_uahcx_ehci_configflag cvmx_uahcx_ehci_configflag_t;
739 * cvmx_uahc#_ehci_ctrldssegment
741 * CTRLDSSEGMENT = Control Data Structure Segment Register
743 * This 32-bit register corresponds to the most significant address bits [63:32] for all EHCI data structures. If
744 * the 64-bit Addressing Capability field in HCCPARAMS is a zero, then this register is not used. Software
745 * cannot write to it and a read from this register will return zeros.
747 * If the 64-bit Addressing Capability field in HCCPARAMS is a one, then this register is used with the link
748 * pointers to construct 64-bit addresses to EHCI control data structures. This register is concatenated with the
749 * link pointer from either the PERIODICLISTBASE, ASYNCLISTADDR, or any control data structure link
750 * field to construct a 64-bit address.
752 * This register allows the host software to locate all control data structures within the same 4 Gigabyte
755 union cvmx_uahcx_ehci_ctrldssegment {
757 struct cvmx_uahcx_ehci_ctrldssegment_s {
758 #ifdef __BIG_ENDIAN_BITFIELD
759 uint32_t ctrldsseg : 32; /**< Control Data Strucute Semgent Address Bit [63:32] */
761 uint32_t ctrldsseg : 32;
764 struct cvmx_uahcx_ehci_ctrldssegment_s cn61xx;
765 struct cvmx_uahcx_ehci_ctrldssegment_s cn63xx;
766 struct cvmx_uahcx_ehci_ctrldssegment_s cn63xxp1;
767 struct cvmx_uahcx_ehci_ctrldssegment_s cn66xx;
768 struct cvmx_uahcx_ehci_ctrldssegment_s cn68xx;
769 struct cvmx_uahcx_ehci_ctrldssegment_s cn68xxp1;
770 struct cvmx_uahcx_ehci_ctrldssegment_s cnf71xx;
772 typedef union cvmx_uahcx_ehci_ctrldssegment cvmx_uahcx_ehci_ctrldssegment_t;
775 * cvmx_uahc#_ehci_frindex
777 * FRINDEX = Frame Index Register
778 * This register is used by the host controller to index into the periodic frame list. The register updates every
779 * 125 microseconds (once each micro-frame). Bits [N:3] are used to select a particular entry in the Periodic
780 * Frame List during periodic schedule execution. The number of bits used for the index depends on the size of
781 * the frame list as set by system software in the Frame List Size field in the USBCMD register.
782 * This register cannot be written unless the Host Controller is in the Halted state as indicated by the
783 * HCHalted bit. A write to this register while the Run/Stop bit is set to a one (USBCMD register) produces
784 * undefined results. Writes to this register also affect the SOF value.
786 union cvmx_uahcx_ehci_frindex {
788 struct cvmx_uahcx_ehci_frindex_s {
789 #ifdef __BIG_ENDIAN_BITFIELD
790 uint32_t reserved_14_31 : 18;
791 uint32_t fi : 14; /**< Frame Index. The value in this register increments at the end of each time frame (e.g.
792 micro-frame). Bits [N:3] are used for the Frame List current index. This means that each
793 location of the frame list is accessed 8 times (frames or micro-frames) before moving to
794 the next index. The following illustrates values of N based on the value of the Frame List
795 Size field in the USBCMD register.
796 USBCMD[Frame List Size] Number Elements N
803 uint32_t reserved_14_31 : 18;
806 struct cvmx_uahcx_ehci_frindex_s cn61xx;
807 struct cvmx_uahcx_ehci_frindex_s cn63xx;
808 struct cvmx_uahcx_ehci_frindex_s cn63xxp1;
809 struct cvmx_uahcx_ehci_frindex_s cn66xx;
810 struct cvmx_uahcx_ehci_frindex_s cn68xx;
811 struct cvmx_uahcx_ehci_frindex_s cn68xxp1;
812 struct cvmx_uahcx_ehci_frindex_s cnf71xx;
814 typedef union cvmx_uahcx_ehci_frindex cvmx_uahcx_ehci_frindex_t;
817 * cvmx_uahc#_ehci_hccapbase
819 * HCCAPBASE = Host Controller BASE Capability Register
822 union cvmx_uahcx_ehci_hccapbase {
824 struct cvmx_uahcx_ehci_hccapbase_s {
825 #ifdef __BIG_ENDIAN_BITFIELD
826 uint32_t hciversion : 16; /**< Host Controller Interface Version Number */
827 uint32_t reserved_8_15 : 8;
828 uint32_t caplength : 8; /**< Capabitlity Registers Length */
830 uint32_t caplength : 8;
831 uint32_t reserved_8_15 : 8;
832 uint32_t hciversion : 16;
835 struct cvmx_uahcx_ehci_hccapbase_s cn61xx;
836 struct cvmx_uahcx_ehci_hccapbase_s cn63xx;
837 struct cvmx_uahcx_ehci_hccapbase_s cn63xxp1;
838 struct cvmx_uahcx_ehci_hccapbase_s cn66xx;
839 struct cvmx_uahcx_ehci_hccapbase_s cn68xx;
840 struct cvmx_uahcx_ehci_hccapbase_s cn68xxp1;
841 struct cvmx_uahcx_ehci_hccapbase_s cnf71xx;
843 typedef union cvmx_uahcx_ehci_hccapbase cvmx_uahcx_ehci_hccapbase_t;
846 * cvmx_uahc#_ehci_hccparams
848 * HCCPARAMS = Host Controller Capability Parameters
849 * Multiple Mode control (time-base bit functionality), addressing capability
851 union cvmx_uahcx_ehci_hccparams {
853 struct cvmx_uahcx_ehci_hccparams_s {
854 #ifdef __BIG_ENDIAN_BITFIELD
855 uint32_t reserved_16_31 : 16;
856 uint32_t eecp : 8; /**< EHCI Extended Capabilities Pointer. Default = Implementation Dependent.
857 This optional field indicates the existence of a capabilities list. A value of 00h indicates
858 no extended capabilities are implemented. A non-zero value in this register indicates the
859 offset in PCI configuration space of the first EHCI extended capability. The pointer value
860 must be 40h or greater if implemented to maintain the consistency of the PCI header
861 defined for this class of device. */
862 uint32_t ist : 4; /**< Isochronous Scheduling Threshold. Default = implementation dependent. This field
863 indicates, relative to the current position of the executing host controller, where software
864 can reliably update the isochronous schedule. When bit [7] is zero, the value of the least
865 significant 3 bits indicates the number of micro-frames a host controller can hold a set of
866 isochronous data structures (one or more) before flushing the state. When bit [7] is a
867 one, then host software assumes the host controller may cache an isochronous data
868 structure for an entire frame. Refer to Section 4.7.2.1 for details on how software uses
869 this information for scheduling isochronous transfers. */
870 uint32_t reserved_3_3 : 1;
871 uint32_t aspc : 1; /**< Asynchronous Schedule Park Capability. Default = Implementation dependent. If this
872 bit is set to a one, then the host controller supports the park feature for high-speed
873 queue heads in the Asynchronous Schedule. The feature can be disabled or enabled
874 and set to a specific level by using the Asynchronous Schedule Park Mode Enable and
875 Asynchronous Schedule Park Mode Count fields in the USBCMD register. */
876 uint32_t pflf : 1; /**< Programmable Frame List Flag. Default = Implementation dependent. If this bit is set
877 to a zero, then system software must use a frame list length of 1024 elements with this
878 host controller. The USBCMD register Frame List Size field is a read-only register and
879 should be set to zero.
880 If set to a one, then system software can specify and use a smaller frame list and
881 configure the host controller via the USBCMD register Frame List Size field. The frame
882 list must always be aligned on a 4K page boundary. This requirement ensures that the
883 frame list is always physically contiguous. */
884 uint32_t ac64 : 1; /**< 64-bit Addressing Capability1 . This field documents the addressing range capability of
885 this implementation. The value of this field determines whether software should use the
886 data structures defined in Section 3 (32-bit) or those defined in Appendix B (64-bit).
887 Values for this field have the following interpretation:
888 - 0: data structures using 32-bit address memory pointers
889 - 1: data structures using 64-bit address memory pointers */
894 uint32_t reserved_3_3 : 1;
897 uint32_t reserved_16_31 : 16;
900 struct cvmx_uahcx_ehci_hccparams_s cn61xx;
901 struct cvmx_uahcx_ehci_hccparams_s cn63xx;
902 struct cvmx_uahcx_ehci_hccparams_s cn63xxp1;
903 struct cvmx_uahcx_ehci_hccparams_s cn66xx;
904 struct cvmx_uahcx_ehci_hccparams_s cn68xx;
905 struct cvmx_uahcx_ehci_hccparams_s cn68xxp1;
906 struct cvmx_uahcx_ehci_hccparams_s cnf71xx;
908 typedef union cvmx_uahcx_ehci_hccparams cvmx_uahcx_ehci_hccparams_t;
911 * cvmx_uahc#_ehci_hcsparams
913 * HCSPARAMS = Host Controller Structural Parameters
914 * This is a set of fields that are structural parameters: Number of downstream ports, etc.
916 union cvmx_uahcx_ehci_hcsparams {
918 struct cvmx_uahcx_ehci_hcsparams_s {
919 #ifdef __BIG_ENDIAN_BITFIELD
920 uint32_t reserved_24_31 : 8;
921 uint32_t dpn : 4; /**< Debug Port Number. Optional. This register identifies which of the host controller ports
922 is the debug port. The value is the port number (one-based) of the debug port. A nonzero
923 value in this field indicates the presence of a debug port. The value in this register
924 must not be greater than N_PORTS (see below). */
925 uint32_t reserved_17_19 : 3;
926 uint32_t p_indicator : 1; /**< Port Indicator. This bit indicates whether the ports support port
927 indicator control. When this bit is a one, the port status and control
928 registers include a read/writeable field for controlling the state of
929 the port indicator. */
930 uint32_t n_cc : 4; /**< Number of Companion Controller. This field indicates the number of
931 companion controllers associated with this USB 2.0 host controller.
932 A zero in this field indicates there are no companion host controllers.
933 Port-ownership hand-off is not supported. Only high-speed devices are
934 supported on the host controller root ports.
935 A value larger than zero in this field indicates there are companion USB 1.1 host
936 controller(s). Port-ownership hand-offs are supported. High, Full-and Low-speed
937 devices are supported on the host controller root ports. */
938 uint32_t n_pcc : 4; /**< Number of Ports per Companion Controller (N_PCC). This field indicates
939 the number of ports supported per companion host controller. It is used to
940 indicate the port routing configuration to system software. */
941 uint32_t prr : 1; /**< Port Routing Rules. This field indicates the method used by this implementation for
942 how all ports are mapped to companion controllers. The value of this field has
943 the following interpretation:
944 0 The first N_PCC ports are routed to the lowest numbered function
945 companion host controller, the next N_PCC port are routed to the next
946 lowest function companion controller, and so on.
947 1 The port routing is explicitly enumerated by the first N_PORTS elements
948 of the HCSP-PORTROUTE array. */
949 uint32_t reserved_5_6 : 2;
950 uint32_t ppc : 1; /**< Port Power Control. This field indicates whether the host controller
951 implementation includes port power control. A one in this bit indicates the ports have
952 port power switches. A zero in this bit indicates the port do not have port power
953 switches. The value of this field affects the functionality of the Port Power field
954 in each port status and control register (see Section 2.3.8). */
955 uint32_t n_ports : 4; /**< This field specifies the number of physical downstream ports implemented
956 on this host controller. The value of this field determines how many port registers are
957 addressable in the Operational Register Space (see Table 2-8). Valid values are in the
958 range of 1H to FH. A zero in this field is undefined. */
960 uint32_t n_ports : 4;
962 uint32_t reserved_5_6 : 2;
966 uint32_t p_indicator : 1;
967 uint32_t reserved_17_19 : 3;
969 uint32_t reserved_24_31 : 8;
972 struct cvmx_uahcx_ehci_hcsparams_s cn61xx;
973 struct cvmx_uahcx_ehci_hcsparams_s cn63xx;
974 struct cvmx_uahcx_ehci_hcsparams_s cn63xxp1;
975 struct cvmx_uahcx_ehci_hcsparams_s cn66xx;
976 struct cvmx_uahcx_ehci_hcsparams_s cn68xx;
977 struct cvmx_uahcx_ehci_hcsparams_s cn68xxp1;
978 struct cvmx_uahcx_ehci_hcsparams_s cnf71xx;
980 typedef union cvmx_uahcx_ehci_hcsparams cvmx_uahcx_ehci_hcsparams_t;
983 * cvmx_uahc#_ehci_insnreg00
985 * EHCI_INSNREG00 = EHCI Programmable Microframe Base Value Register (Synopsys Speicific)
986 * This register allows you to change the microframe length value (default is microframe SOF = 125 s) to reduce the simulation time.
988 union cvmx_uahcx_ehci_insnreg00 {
990 struct cvmx_uahcx_ehci_insnreg00_s {
991 #ifdef __BIG_ENDIAN_BITFIELD
992 uint32_t reserved_14_31 : 18;
993 uint32_t mfmc : 13; /**< For byte interface (8-bits), <13:1> is used as the 1-microframe counter.
994 For word interface (16_bits> <12:1> is used as the 1-microframe counter with word
995 interface (16-bits). */
996 uint32_t en : 1; /**< Writing 1b1 enables this register.
997 Note: Do not enable this register for the gate-level netlist */
1001 uint32_t reserved_14_31 : 18;
1004 struct cvmx_uahcx_ehci_insnreg00_s cn61xx;
1005 struct cvmx_uahcx_ehci_insnreg00_s cn63xx;
1006 struct cvmx_uahcx_ehci_insnreg00_s cn63xxp1;
1007 struct cvmx_uahcx_ehci_insnreg00_s cn66xx;
1008 struct cvmx_uahcx_ehci_insnreg00_s cn68xx;
1009 struct cvmx_uahcx_ehci_insnreg00_s cn68xxp1;
1010 struct cvmx_uahcx_ehci_insnreg00_s cnf71xx;
1012 typedef union cvmx_uahcx_ehci_insnreg00 cvmx_uahcx_ehci_insnreg00_t;
1015 * cvmx_uahc#_ehci_insnreg03
1017 * EHCI_INSNREG03 = EHCI Timing Adjust Register (Synopsys Speicific)
1018 * This register allows you to change the timing of Phy Tx turnaround delay etc.
1020 union cvmx_uahcx_ehci_insnreg03 {
1022 struct cvmx_uahcx_ehci_insnreg03_s {
1023 #ifdef __BIG_ENDIAN_BITFIELD
1024 uint32_t reserved_13_31 : 19;
1025 uint32_t txtx_tadao : 3; /**< Tx-Tx turnaround Delay Add on. This field specifies the extra delays in phy_clks to
1026 be added to the "Transmit to Transmit turnaround delay" value maintained in the core.
1027 The default value of this register field is 0. This default value of 0 is sufficient
1028 for most PHYs. But for some PHYs which puts wait states during the token packet, it
1029 may be required to program a value greater than 0 to meet the transmit to transmit
1030 minimum turnaround time. The recommendation to use the default value of 0 and change
1031 it only if there is an issue with minimum transmit-to- transmit turnaround time. This
1032 value should be programmed during core initialization and should not be changed afterwards. */
1033 uint32_t reserved_9_9 : 1;
1034 uint32_t ta_off : 8; /**< Time-Available Offset. This value indicates the additional number of bytes to be
1035 accommodated for the time-available calculation. The USB traffic on the bus can be started
1036 only when sufficient time is available to complete the packet within the EOF1 point. Refer
1037 to the USB 2.0 specification for details of the EOF1 point. This time-available
1038 calculation is done in the hardware, and can be further offset by programming a value in
1040 Note: Time-available calculation is added for future flexibility. The application is not
1041 required to program this field by default. */
1042 uint32_t reserved_0_0 : 1;
1044 uint32_t reserved_0_0 : 1;
1045 uint32_t ta_off : 8;
1046 uint32_t reserved_9_9 : 1;
1047 uint32_t txtx_tadao : 3;
1048 uint32_t reserved_13_31 : 19;
1051 struct cvmx_uahcx_ehci_insnreg03_s cn61xx;
1052 struct cvmx_uahcx_ehci_insnreg03_s cn63xx;
1053 struct cvmx_uahcx_ehci_insnreg03_s cn63xxp1;
1054 struct cvmx_uahcx_ehci_insnreg03_s cn66xx;
1055 struct cvmx_uahcx_ehci_insnreg03_s cn68xx;
1056 struct cvmx_uahcx_ehci_insnreg03_s cn68xxp1;
1057 struct cvmx_uahcx_ehci_insnreg03_s cnf71xx;
1059 typedef union cvmx_uahcx_ehci_insnreg03 cvmx_uahcx_ehci_insnreg03_t;
1062 * cvmx_uahc#_ehci_insnreg04
1064 * EHCI_INSNREG04 = EHCI Debug Register (Synopsys Speicific)
1065 * This register is used only for debug purposes.
1067 union cvmx_uahcx_ehci_insnreg04 {
1069 struct cvmx_uahcx_ehci_insnreg04_s {
1070 #ifdef __BIG_ENDIAN_BITFIELD
1071 uint32_t reserved_6_31 : 26;
1072 uint32_t auto_dis : 1; /**< Automatic feature disable.
1073 1'b0: 0 by default, the automatic feature is enabled. The Suspend signal is deasserted
1074 (logic level 1'b1) when run/stop is reset by software, but the hchalted bit is not
1076 1'b1: Disables the automatic feature, which takes all ports out of suspend when software
1077 clears the run/stop bit. This is for backward compatibility.
1078 This bit has an added functionality in release 2.80a and later. For systems where the host
1079 is halted without waking up all ports out of suspend, the port can become stuck because
1080 the PHYCLK is not running when the halt is programmed. To avoid this, the DWC H20AHB host
1081 core automatically pulls ports out of suspend when the host is halted by software. This bit
1082 is used to disable this automatic function. */
1083 uint32_t nakrf_dis : 1; /**< NAK Reload Fix Disable.
1084 1b0: NAK reload fix enabled.
1085 1b1: NAK reload fix disabled. (Incorrect NAK reload transition at the end of a microframe
1086 for backward compatibility with Release 2.40c. For more information see the USB 2.0
1087 Host-AHB Release Notes. */
1088 uint32_t reserved_3_3 : 1;
1089 uint32_t pesd : 1; /**< Scales down port enumeration time.
1090 1'b1: scale down enabled
1091 1'b0: scale downd disabled
1092 This is for simulation only. */
1093 uint32_t hcp_fw : 1; /**< HCCPARAMS Field Writeable.
1094 1'b1: The HCCPARAMS register's bits 17, 15:4, and 2:0 become writable.
1095 1'b0: The HCCPARAMS register's bits 17, 15:4, and 2:0 are not writable. */
1096 uint32_t hcp_rw : 1; /**< HCCPARAMS Reigster Writeable.
1097 1'b1: The HCCPARAMS register becomes writable.
1098 1'b0: The HCCPARAMS register is not writable. */
1100 uint32_t hcp_rw : 1;
1101 uint32_t hcp_fw : 1;
1103 uint32_t reserved_3_3 : 1;
1104 uint32_t nakrf_dis : 1;
1105 uint32_t auto_dis : 1;
1106 uint32_t reserved_6_31 : 26;
1109 struct cvmx_uahcx_ehci_insnreg04_s cn61xx;
1110 struct cvmx_uahcx_ehci_insnreg04_s cn63xx;
1111 struct cvmx_uahcx_ehci_insnreg04_s cn63xxp1;
1112 struct cvmx_uahcx_ehci_insnreg04_s cn66xx;
1113 struct cvmx_uahcx_ehci_insnreg04_s cn68xx;
1114 struct cvmx_uahcx_ehci_insnreg04_s cn68xxp1;
1115 struct cvmx_uahcx_ehci_insnreg04_s cnf71xx;
1117 typedef union cvmx_uahcx_ehci_insnreg04 cvmx_uahcx_ehci_insnreg04_t;
1120 * cvmx_uahc#_ehci_insnreg06
1122 * EHCI_INSNREG06 = EHCI AHB Error Status Register (Synopsys Speicific)
1123 * This register contains AHB Error Status.
1125 union cvmx_uahcx_ehci_insnreg06 {
1127 struct cvmx_uahcx_ehci_insnreg06_s {
1128 #ifdef __BIG_ENDIAN_BITFIELD
1129 uint32_t vld : 1; /**< AHB Error Captured. Indicator that an AHB error was encountered and values were captured.
1130 To clear this field the application must write a 0 to it. */
1131 uint32_t reserved_0_30 : 31;
1133 uint32_t reserved_0_30 : 31;
1137 struct cvmx_uahcx_ehci_insnreg06_s cn61xx;
1138 struct cvmx_uahcx_ehci_insnreg06_s cn63xx;
1139 struct cvmx_uahcx_ehci_insnreg06_s cn63xxp1;
1140 struct cvmx_uahcx_ehci_insnreg06_s cn66xx;
1141 struct cvmx_uahcx_ehci_insnreg06_s cn68xx;
1142 struct cvmx_uahcx_ehci_insnreg06_s cn68xxp1;
1143 struct cvmx_uahcx_ehci_insnreg06_s cnf71xx;
1145 typedef union cvmx_uahcx_ehci_insnreg06 cvmx_uahcx_ehci_insnreg06_t;
1148 * cvmx_uahc#_ehci_insnreg07
1150 * EHCI_INSNREG07 = EHCI AHB Error Address Register (Synopsys Speicific)
1151 * This register contains AHB Error Status.
1153 union cvmx_uahcx_ehci_insnreg07 {
1155 struct cvmx_uahcx_ehci_insnreg07_s {
1156 #ifdef __BIG_ENDIAN_BITFIELD
1157 uint32_t err_addr : 32; /**< AHB Master Error Address. AHB address of the control phase at which the AHB error occurred */
1159 uint32_t err_addr : 32;
1162 struct cvmx_uahcx_ehci_insnreg07_s cn61xx;
1163 struct cvmx_uahcx_ehci_insnreg07_s cn63xx;
1164 struct cvmx_uahcx_ehci_insnreg07_s cn63xxp1;
1165 struct cvmx_uahcx_ehci_insnreg07_s cn66xx;
1166 struct cvmx_uahcx_ehci_insnreg07_s cn68xx;
1167 struct cvmx_uahcx_ehci_insnreg07_s cn68xxp1;
1168 struct cvmx_uahcx_ehci_insnreg07_s cnf71xx;
1170 typedef union cvmx_uahcx_ehci_insnreg07 cvmx_uahcx_ehci_insnreg07_t;
1173 * cvmx_uahc#_ehci_periodiclistbase
1175 * PERIODICLISTBASE = Periodic Frame List Base Address Register
1177 * This 32-bit register contains the beginning address of the Periodic Frame List in the system memory. If the
1178 * host controller is in 64-bit mode (as indicated by a one in the 64-bit Addressing Capability field in the
1179 * HCCSPARAMS register), then the most significant 32 bits of every control data structure address comes
1180 * from the CTRLDSSEGMENT register (see Section 2.3.5). System software loads this register prior to
1181 * starting the schedule execution by the Host Controller (see 4.1). The memory structure referenced by this
1182 * physical memory pointer is assumed to be 4-Kbyte aligned. The contents of this register are combined with
1183 * the Frame Index Register (FRINDEX) to enable the Host Controller to step through the Periodic Frame List
1186 union cvmx_uahcx_ehci_periodiclistbase {
1188 struct cvmx_uahcx_ehci_periodiclistbase_s {
1189 #ifdef __BIG_ENDIAN_BITFIELD
1190 uint32_t baddr : 20; /**< Base Address (Low). These bits correspond to memory address signals [31:12],respectively. */
1191 uint32_t reserved_0_11 : 12;
1193 uint32_t reserved_0_11 : 12;
1194 uint32_t baddr : 20;
1197 struct cvmx_uahcx_ehci_periodiclistbase_s cn61xx;
1198 struct cvmx_uahcx_ehci_periodiclistbase_s cn63xx;
1199 struct cvmx_uahcx_ehci_periodiclistbase_s cn63xxp1;
1200 struct cvmx_uahcx_ehci_periodiclistbase_s cn66xx;
1201 struct cvmx_uahcx_ehci_periodiclistbase_s cn68xx;
1202 struct cvmx_uahcx_ehci_periodiclistbase_s cn68xxp1;
1203 struct cvmx_uahcx_ehci_periodiclistbase_s cnf71xx;
1205 typedef union cvmx_uahcx_ehci_periodiclistbase cvmx_uahcx_ehci_periodiclistbase_t;
1208 * cvmx_uahc#_ehci_portsc#
1210 * PORTSCX = Port X Status and Control Register
1211 * Default: 00002000h (w/PPC set to one); 00003000h (w/PPC set to a zero)
1213 union cvmx_uahcx_ehci_portscx {
1215 struct cvmx_uahcx_ehci_portscx_s {
1216 #ifdef __BIG_ENDIAN_BITFIELD
1217 uint32_t reserved_23_31 : 9;
1218 uint32_t wkoc_e : 1; /**< Wake on Over-current Enable.Writing this bit to a
1219 one enables the port to be sensitive to over-current conditions as wake-up events.
1220 This field is zero if Port Power is zero. */
1221 uint32_t wkdscnnt_e : 1; /**< Wake on Disconnect Enable. Writing this bit to a one enables the port to be
1222 sensitive to device disconnects as wake-up events.
1223 This field is zero if Port Power is zero. */
1224 uint32_t wkcnnt_e : 1; /**< Wake on Connect Enable. Writing this bit to a one enables the port to be
1225 sensitive to device connects as wake-up events.
1226 This field is zero if Port Power is zero. */
1227 uint32_t ptc : 4; /**< Port Test Control. When this field is zero, the port is NOT
1228 operating in a test mode. A non-zero value indicates that it is operating
1229 in test mode and the specific test mode is indicated by the specific value.
1230 The encoding of the test mode bits are (0110b - 1111b are reserved):
1232 0000b Test mode not enabled
1237 0101b Test FORCE_ENABLE */
1238 uint32_t pic : 2; /**< Port Indicator Control. Writing to these bits has no effect if the
1239 P_INDICATOR bit in the HCSPARAMS register is a zero. If P_INDICATOR bit is a one,
1240 then the bit encodings are:
1242 00b Port indicators are off
1246 This field is zero if Port Power is zero. */
1247 uint32_t po : 1; /**< Port Owner.This bit unconditionally goes to a 0b when the
1248 Configured bit in the CONFIGFLAG register makes a 0b to 1b transition. This bit
1249 unconditionally goes to 1b whenever the Configured bit is zero.
1250 System software uses this field to release ownership of the port to a selected host
1251 controller (in the event that the attached device is not a high-speed device). Software
1252 writes a one to this bit when the attached device is not a high-speed device. A one in
1253 this bit means that a companion host controller owns and controls the port. */
1254 uint32_t pp : 1; /**< Port Power. The function of this bit depends on the value of the Port
1255 Power Control (PPC) field in the HCSPARAMS register. The behavior is as follows:
1257 0b 1b RO - Host controller does not have port power control switches.
1258 Each port is hard-wired to power.
1259 1b 1b/0b R/W - Host controller has port power control switches. This bit
1260 represents the current setting of the switch (0 = off, 1 = on). When
1261 power is not available on a port (i.e. PP equals a 0), the port is
1262 nonfunctional and will not report attaches, detaches, etc.
1263 When an over-current condition is detected on a powered port and PPC is a one, the PP
1264 bit in each affected port may be transitioned by the host controller from a 1 to 0
1265 (removing power from the port). */
1266 uint32_t lsts : 2; /**< Line Status.These bits reflect the current logical levels of the D+ (bit 11) and D(bit 10)
1267 signal lines. These bits are used for detection of low-speed USB devices prior to
1268 the port reset and enable sequence. This field is valid only when the port enable bit is
1269 zero and the current connect status bit is set to a one.
1270 The encoding of the bits are:
1271 Bits[11:10] USB State Interpretation
1272 00b SE0 Not Low-speed device, perform EHCI reset
1273 10b J-state Not Low-speed device, perform EHCI reset
1274 01b K-state Low-speed device, release ownership of port
1275 11b Undefined Not Low-speed device, perform EHCI reset.
1276 This value of this field is undefined if Port Power is zero. */
1277 uint32_t reserved_9_9 : 1;
1278 uint32_t prst : 1; /**< Port Reset.1=Port is in Reset. 0=Port is not in Reset. Default = 0. When
1279 software writes a one to this bit (from a zero), the bus reset sequence as defined in the
1280 USB Specification Revision 2.0 is started. Software writes a zero to this bit to terminate
1281 the bus reset sequence. Software must keep this bit at a one long enough to ensure the
1282 reset sequence, as specified in the USB Specification Revision 2.0, completes. Note:
1283 when software writes this bit to a one, it must also write a zero to the Port Enable bit.
1284 Note that when software writes a zero to this bit there may be a delay before the bit
1285 status changes to a zero. The bit status will not read as a zero until after the reset has
1286 completed. If the port is in high-speed mode after reset is complete, the host controller
1287 will automatically enable this port (e.g. set the Port Enable bit to a one). A host controller
1288 must terminate the reset and stabilize the state of the port within 2 milliseconds of
1289 software transitioning this bit from a one to a zero. For example: if the port detects that
1290 the attached device is high-speed during reset, then the host controller must have the
1291 port in the enabled state within 2ms of software writing this bit to a zero.
1292 The HCHalted bit in the USBSTS register should be a zero before software attempts to
1293 use this bit. The host controller may hold Port Reset asserted to a one when the
1294 HCHalted bit is a one.
1295 This field is zero if Port Power is zero. */
1296 uint32_t spd : 1; /**< Suspend. 1=Port in suspend state. 0=Port not in suspend state. Default = 0. Port
1297 Enabled Bit and Suspend bit of this register define the port states as follows:
1298 Bits [Port Enabled, Suspend] Port State
1302 When in suspend state, downstream propagation of data is blocked on this port, except
1303 for port reset. The blocking occurs at the end of the current transaction, if a transaction
1304 was in progress when this bit was written to 1. In the suspend state, the port is sensitive
1305 to resume detection. Note that the bit status does not change until the port is
1306 suspended and that there may be a delay in suspending a port if there is a transaction
1307 currently in progress on the USB.
1308 A write of zero to this bit is ignored by the host controller. The host controller will
1309 unconditionally set this bit to a zero when:
1310 . Software sets the Force Port Resume bit to a zero (from a one).
1311 . Software sets the Port Reset bit to a one (from a zero).
1312 If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is
1313 a zero) the results are undefined.
1314 This field is zero if Port Power is zero. */
1315 uint32_t fpr : 1; /**< Force Port Resume.
1316 1= Resume detected/driven on port. 0=No resume (Kstate)
1317 detected/driven on port. Default = 0. This functionality defined for manipulating
1318 this bit depends on the value of the Suspend bit. For example, if the port is not
1319 suspended (Suspend and Enabled bits are a one) and software transitions this bit to a
1320 one, then the effects on the bus are undefined.
1321 Software sets this bit to a 1 to drive resume signaling. The Host Controller sets this bit to
1322 a 1 if a J-to-K transition is detected while the port is in the Suspend state. When this bit
1323 transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in
1324 the USBSTS register is also set to a one. If software sets this bit to a one, the host
1325 controller must not set the Port Change Detect bit.
1326 Note that when the EHCI controller owns the port, the resume sequence follows the
1327 defined sequence documented in the USB Specification Revision 2.0. The resume
1328 signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. Software
1329 must appropriately time the Resume and set this bit to a zero when the appropriate
1330 amount of time has elapsed. Writing a zero (from one) causes the port to return to high-
1331 speed mode (forcing the bus below the port into a high-speed idle). This bit will remain a
1332 one until the port has switched to the high-speed idle. The host controller must complete
1333 this transition within 2 milliseconds of software setting this bit to a zero.
1334 This field is zero if Port Power is zero. */
1335 uint32_t occ : 1; /**< Over-current Change. 1=This bit gets set to a one when there is a change to Over-current Active.
1336 Software clears this bit by writing a one to this bit position. */
1337 uint32_t oca : 1; /**< Over-current Active. 1=This port currently has an over-current condition. 0=This port does not
1338 have an over-current condition. This bit will automatically transition from a one to a zero when
1339 the over current condition is removed. */
1340 uint32_t pedc : 1; /**< Port Enable/Disable Change. 1=Port enabled/disabled status has changed.
1341 0=No change. Default = 0. For the root hub, this bit gets set to a one only when a port is
1342 disabled due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of
1343 the USB Specification for the definition of a Port Error). Software clears this bit by writing
1345 This field is zero if Port Power is zero. */
1346 uint32_t ped : 1; /**< Port Enabled/Disabled. 1=Enable. 0=Disable. Ports can only be
1347 enabled by the host controller as a part of the reset and enable. Software cannot enable
1348 a port by writing a one to this field. The host controller will only set this bit to a one when
1349 the reset sequence determines that the attached device is a high-speed device.
1350 Ports can be disabled by either a fault condition (disconnect event or other fault
1351 condition) or by host software. Note that the bit status does not change until the port
1352 state actually changes. There may be a delay in disabling or enabling a port due to other
1353 host controller and bus events. See Section 4.2 for full details on port reset and enable.
1354 When the port is disabled (0b) downstream propagation of data is blocked on this port,
1356 This field is zero if Port Power is zero. */
1357 uint32_t csc : 1; /**< Connect Status Change. 1=Change in Current Connect Status. 0=No change. Indicates a change
1358 has occurred in the port's Current Connect Status. The host controller sets this bit for all
1359 changes to the port device connect status, even if system software has not cleared an existing
1360 connect status change. For example, the insertion status changes twice before system software
1361 has cleared the changed condition, hub hardware will be setting an already-set bit
1362 (i.e., the bit will remain set). Software sets this bit to 0 by writing a 1 to it.
1363 This field is zero if Port Power is zero. */
1364 uint32_t ccs : 1; /**< Current Connect Status. 1=Device is present on port. 0=No device is present.
1365 This value reflects the current state of the port, and may not correspond
1366 directly to the event that caused the Connect Status Change bit (Bit 1) to be set.
1367 This field is zero if Port Power is zero. */
1378 uint32_t reserved_9_9 : 1;
1384 uint32_t wkcnnt_e : 1;
1385 uint32_t wkdscnnt_e : 1;
1386 uint32_t wkoc_e : 1;
1387 uint32_t reserved_23_31 : 9;
1390 struct cvmx_uahcx_ehci_portscx_s cn61xx;
1391 struct cvmx_uahcx_ehci_portscx_s cn63xx;
1392 struct cvmx_uahcx_ehci_portscx_s cn63xxp1;
1393 struct cvmx_uahcx_ehci_portscx_s cn66xx;
1394 struct cvmx_uahcx_ehci_portscx_s cn68xx;
1395 struct cvmx_uahcx_ehci_portscx_s cn68xxp1;
1396 struct cvmx_uahcx_ehci_portscx_s cnf71xx;
1398 typedef union cvmx_uahcx_ehci_portscx cvmx_uahcx_ehci_portscx_t;
1401 * cvmx_uahc#_ehci_usbcmd
1403 * USBCMD = USB Command Register
1404 * The Command Register indicates the command to be executed by the serial bus host controller. Writing to the register causes a command to be executed.
1406 union cvmx_uahcx_ehci_usbcmd {
1408 struct cvmx_uahcx_ehci_usbcmd_s {
1409 #ifdef __BIG_ENDIAN_BITFIELD
1410 uint32_t reserved_24_31 : 8;
1411 uint32_t itc : 8; /**< Interrupt Threshold Control. This field is used by system software
1412 to select the maximum rate at which the host controller will issue interrupts. The only
1413 valid values are defined below. If software writes an invalid value to this register, the
1414 results are undefined. Value Maximum Interrupt Interval
1419 08h 8 micro-frames (default, equates to 1 ms)
1420 10h 16 micro-frames (2 ms)
1421 20h 32 micro-frames (4 ms)
1422 40h 64 micro-frames (8 ms) */
1423 uint32_t reserved_12_15 : 4;
1424 uint32_t aspm_en : 1; /**< Asynchronous Schedule Park Mode Enable. */
1425 uint32_t reserved_10_10 : 1;
1426 uint32_t aspmc : 2; /**< Asynchronous Schedule Park Mode Count. */
1427 uint32_t lhcr : 1; /**< Light Host Controller Reset */
1428 uint32_t iaa_db : 1; /**< Interrupt on Async Advance Doorbell.This bit is used as a doorbell by
1429 software to tell the host controller to issue an interrupt the next time it advances
1430 asynchronous schedule. Software must write a 1 to this bit to ring the doorbell.
1431 When the host controller has evicted all appropriate cached schedule state, it sets the
1432 Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Async
1433 Advance Enable bit in the USBINTR register is a one then the host controller will assert
1434 an interrupt at the next interrupt threshold. */
1435 uint32_t as_en : 1; /**< Asynchronous Schedule Enable .This bit controls whether the host
1436 controller skips processing the Asynchronous Schedule. Values mean:
1437 - 0: Do not process the Asynchronous Schedule
1438 - 1: Use the ASYNCLISTADDR register to access the Asynchronous Schedule. */
1439 uint32_t ps_en : 1; /**< Periodic Schedule Enable. This bit controls whether the host
1440 controller skips processing the Periodic Schedule. Values mean:
1441 - 0: Do not process the Periodic Schedule
1442 - 1: Use the PERIODICLISTBASE register to access the Periodic Schedule. */
1443 uint32_t fls : 2; /**< Frame List Size. This field is R/W only if Programmable
1444 Frame List Flag in the HCCPARAMS registers is set to a one. This field specifies the
1445 size of the frame list. The size the frame list controls which bits in the Frame Index
1446 Register should be used for the Frame List Current index. Values mean:
1447 00b: 1024 elements (4096 bytes) Default value
1448 01b: 512 elements (2048 bytes)
1449 10b: 256 elements (1024 bytes) - for resource-constrained environments
1451 uint32_t hcreset : 1; /**< Host Controller Reset (HCRESET). This control bit is used by software to reset
1452 the host controller. The effects of this on Root Hub registers are similar to a Chip
1453 Hardware Reset. When software writes a one to this bit, the Host Controller resets
1454 its internal pipelines, timers, counters, state machines, etc. to their initial
1455 value. Any transaction currently in progress on USB is immediately terminated.
1456 A USB reset is not driven on downstream ports.
1457 This bit is set to zero by the Host Controller when the reset process is complete. Software can not
1458 terminate the reset process early by writing zero to this register.
1459 Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero.
1460 Attempting to reset an activtely running host controller will result in undefined behavior. */
1461 uint32_t rs : 1; /**< Run/Stop (RS).
1463 When set to a 1, the Host Controller proceeds with execution of the schedule.
1464 The Host Controller continues execution as long as this bit is set to a 1.
1465 When this bit is set to 0, the Host Controller completes the current and any
1466 actively pipelined transactions on the USB and then halts. The Host
1467 Controller must halt within 16 micro-frames after software clears the Run bit. The HC
1468 Halted bit in the status register indicates when the Host Controller has finished its
1469 pending pipelined transactions and has entered the stopped state. Software must not
1470 write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in
1471 the USBSTS register is a one). Doing so will yield undefined results. */
1474 uint32_t hcreset : 1;
1478 uint32_t iaa_db : 1;
1481 uint32_t reserved_10_10 : 1;
1482 uint32_t aspm_en : 1;
1483 uint32_t reserved_12_15 : 4;
1485 uint32_t reserved_24_31 : 8;
1488 struct cvmx_uahcx_ehci_usbcmd_s cn61xx;
1489 struct cvmx_uahcx_ehci_usbcmd_s cn63xx;
1490 struct cvmx_uahcx_ehci_usbcmd_s cn63xxp1;
1491 struct cvmx_uahcx_ehci_usbcmd_s cn66xx;
1492 struct cvmx_uahcx_ehci_usbcmd_s cn68xx;
1493 struct cvmx_uahcx_ehci_usbcmd_s cn68xxp1;
1494 struct cvmx_uahcx_ehci_usbcmd_s cnf71xx;
1496 typedef union cvmx_uahcx_ehci_usbcmd cvmx_uahcx_ehci_usbcmd_t;
1499 * cvmx_uahc#_ehci_usbintr
1501 * USBINTR = USB Interrupt Enable Register
1502 * This register enables and disables reporting of the corresponding interrupt to the software. When a bit is set
1503 * and the corresponding interrupt is active, an interrupt is generated to the host. Interrupt sources that are
1504 * disabled in this register still appear in the USBSTS to allow the software to poll for events.
1505 * Each interrupt enable bit description indicates whether it is dependent on the interrupt threshold mechanism.
1506 * Note: for all enable register bits, 1= Enabled, 0= Disabled
1508 union cvmx_uahcx_ehci_usbintr {
1510 struct cvmx_uahcx_ehci_usbintr_s {
1511 #ifdef __BIG_ENDIAN_BITFIELD
1512 uint32_t reserved_6_31 : 26;
1513 uint32_t ioaa_en : 1; /**< Interrupt on Async Advance Enable When this bit is a one, and the Interrupt on
1514 Async Advance bit in the USBSTS register is a one, the host controller will issue an
1515 interrupt at the next interrupt threshold. The interrupt is acknowledged by software
1516 clearing the Interrupt on Async Advance bit. */
1517 uint32_t hserr_en : 1; /**< Host System Error Enable When this bit is a one, and the Host System
1518 Error Status bit in the USBSTS register is a one, the host controller will issue an
1519 interrupt. The interrupt is acknowledged by software clearing the Host System Error bit. */
1520 uint32_t flro_en : 1; /**< Frame List Rollover Enable. When this bit is a one, and the Frame List
1521 Rollover bit in the USBSTS register is a one, the host controller will issue an
1522 interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit. */
1523 uint32_t pci_en : 1; /**< Port Change Interrupt Enable. When this bit is a one, and the Port Change Detect bit in
1524 the USBSTS register is a one, the host controller will issue an interrupt.
1525 The interrupt is acknowledged by software clearing the Port Change Detect bit. */
1526 uint32_t usberrint_en : 1; /**< USB Error Interrupt Enable. When this bit is a one, and the USBERRINT
1527 bit in the USBSTS register is a one, the host controller will issue an interrupt at the next
1528 interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit. */
1529 uint32_t usbint_en : 1; /**< USB Interrupt Enable. When this bit is a one, and the USBINT bit in the USBSTS register
1530 is a one, the host controller will issue an interrupt at the next interrupt threshold.
1531 The interrupt is acknowledged by software clearing the USBINT bit. */
1533 uint32_t usbint_en : 1;
1534 uint32_t usberrint_en : 1;
1535 uint32_t pci_en : 1;
1536 uint32_t flro_en : 1;
1537 uint32_t hserr_en : 1;
1538 uint32_t ioaa_en : 1;
1539 uint32_t reserved_6_31 : 26;
1542 struct cvmx_uahcx_ehci_usbintr_s cn61xx;
1543 struct cvmx_uahcx_ehci_usbintr_s cn63xx;
1544 struct cvmx_uahcx_ehci_usbintr_s cn63xxp1;
1545 struct cvmx_uahcx_ehci_usbintr_s cn66xx;
1546 struct cvmx_uahcx_ehci_usbintr_s cn68xx;
1547 struct cvmx_uahcx_ehci_usbintr_s cn68xxp1;
1548 struct cvmx_uahcx_ehci_usbintr_s cnf71xx;
1550 typedef union cvmx_uahcx_ehci_usbintr cvmx_uahcx_ehci_usbintr_t;
1553 * cvmx_uahc#_ehci_usbsts
1555 * USBSTS = USB Status Register
1556 * This register indicates pending interrupts and various states of the Host Controller. The status resulting from
1557 * a transaction on the serial bus is not indicated in this register. Software sets a bit to 0 in this register by
1558 * writing a 1 to it.
1560 union cvmx_uahcx_ehci_usbsts {
1562 struct cvmx_uahcx_ehci_usbsts_s {
1563 #ifdef __BIG_ENDIAN_BITFIELD
1564 uint32_t reserved_16_31 : 16;
1565 uint32_t ass : 1; /**< Asynchronous Schedule Status. The bit reports the current real
1566 status of the Asynchronous Schedule. If this bit is a zero then the status of the
1567 Asynchronous Schedule is disabled. If this bit is a one then the status of the
1568 Asynchronous Schedule is enabled. The Host Controller is not required to immediately
1569 disable or enable the Asynchronous Schedule when software transitions the
1570 Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the
1571 Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is
1572 either enabled (1) or disabled (0). */
1573 uint32_t pss : 1; /**< Periodic Schedule Status. The bit reports the current real status of
1574 the Periodic Schedule. If this bit is a zero then the status of the Periodic
1575 Schedule is disabled. If this bit is a one then the status of the Periodic Schedule
1576 is enabled. The Host Controller is not required to immediately disable or enable the
1577 Periodic Schedule when software transitions the Periodic Schedule Enable bit in
1578 the USBCMD register. When this bit and the Periodic Schedule Enable bit are the
1579 same value, the Periodic Schedule is either enabled (1) or disabled (0). */
1580 uint32_t reclm : 1; /**< Reclamation.This is a read-only status bit, which is used to detect an
1581 empty asynchronous schedule. */
1582 uint32_t hchtd : 1; /**< HCHalted. This bit is a zero whenever the Run/Stop bit is a one. The
1583 Host Controller sets this bit to one after it has stopped executing as a result of the
1584 Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g.
1586 uint32_t reserved_6_11 : 6;
1587 uint32_t ioaa : 1; /**< Interrupt on Async Advance. System software can force the host
1588 controller to issue an interrupt the next time the host controller advances the
1589 asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit
1590 in the USBCMD register. This status bit indicates the assertion of that interrupt source. */
1591 uint32_t hsyserr : 1; /**< Host System Error. The Host Controller sets this bit to 1 when a serious error
1592 occurs during a host system access involving the Host Controller module. */
1593 uint32_t flro : 1; /**< Frame List Rollover. The Host Controller sets this bit to a one when the
1594 Frame List Index rolls over from its maximum value to zero. The exact value at
1595 which the rollover occurs depends on the frame list size. For example, if
1596 the frame list size (as programmed in the Frame List Size field of the USBCMD register)
1597 is 1024, the Frame Index Register rolls over every time FRINDEX[13] toggles. Similarly,
1598 if the size is 512, the Host Controller sets this bit to a one every time FRINDEX[12]
1600 uint32_t pcd : 1; /**< Port Change Detect. The Host Controller sets this bit to a one when any port
1601 for which the Port Owner bit is set to zero (see Section 2.3.9) has a change bit transition
1602 from a zero to a one or a Force Port Resume bit transition from a zero to a one as a
1603 result of a J-K transition detected on a suspended port. This bit will also be set as a
1604 result of the Connect Status Change being set to a one after system software has
1605 relinquished ownership of a connected port by writing a one to a port's Port Owner bit. */
1606 uint32_t usberrint : 1; /**< USB Error Interrupt. The Host Controller sets this bit to 1 when completion of a USB
1607 transaction results in an error condition (e.g., error counter underflow). If the TD on
1608 which the error interrupt occurred also had its IOC bit set, both this bit and USBINT
1610 uint32_t usbint : 1; /**< USB Interrupt. The Host Controller sets this bit to 1 on the completion of a USB
1611 transaction, which results in the retirement of a Transfer Descriptor that had its
1612 IOC bit set. The Host Controller also sets this bit to 1 when a short packet is
1613 detected (actual number of bytes received was less than the expected number of bytes). */
1615 uint32_t usbint : 1;
1616 uint32_t usberrint : 1;
1619 uint32_t hsyserr : 1;
1621 uint32_t reserved_6_11 : 6;
1626 uint32_t reserved_16_31 : 16;
1629 struct cvmx_uahcx_ehci_usbsts_s cn61xx;
1630 struct cvmx_uahcx_ehci_usbsts_s cn63xx;
1631 struct cvmx_uahcx_ehci_usbsts_s cn63xxp1;
1632 struct cvmx_uahcx_ehci_usbsts_s cn66xx;
1633 struct cvmx_uahcx_ehci_usbsts_s cn68xx;
1634 struct cvmx_uahcx_ehci_usbsts_s cn68xxp1;
1635 struct cvmx_uahcx_ehci_usbsts_s cnf71xx;
1637 typedef union cvmx_uahcx_ehci_usbsts cvmx_uahcx_ehci_usbsts_t;
1640 * cvmx_uahc#_ohci0_hcbulkcurrented
1642 * HCBULKCURRENTED = Host Controller Bulk Current ED Register
1644 * The HcBulkCurrentED register contains the physical address of the current endpoint of the Bulk list. As the Bulk list will be served in a round-robin
1645 * fashion, the endpoints will be ordered according to their insertion to the list.
1647 union cvmx_uahcx_ohci0_hcbulkcurrented {
1649 struct cvmx_uahcx_ohci0_hcbulkcurrented_s {
1650 #ifdef __BIG_ENDIAN_BITFIELD
1651 uint32_t bced : 28; /**< BulkCurrentED. This is advanced to the next ED after the HC has served the
1652 present one. HC continues processing the list from where it left off in the
1653 last Frame. When it reaches the end of the Bulk list, HC checks the
1654 ControlListFilled of HcControl. If set, it copies the content of HcBulkHeadED
1655 to HcBulkCurrentED and clears the bit. If it is not set, it does nothing.
1656 HCD is only allowed to modify this register when the BulkListEnable of
1657 HcControl is cleared. When set, the HCD only reads the instantaneous value of
1658 this register. This is initially set to zero to indicate the end of the Bulk
1660 uint32_t reserved_0_3 : 4;
1662 uint32_t reserved_0_3 : 4;
1666 struct cvmx_uahcx_ohci0_hcbulkcurrented_s cn61xx;
1667 struct cvmx_uahcx_ohci0_hcbulkcurrented_s cn63xx;
1668 struct cvmx_uahcx_ohci0_hcbulkcurrented_s cn63xxp1;
1669 struct cvmx_uahcx_ohci0_hcbulkcurrented_s cn66xx;
1670 struct cvmx_uahcx_ohci0_hcbulkcurrented_s cn68xx;
1671 struct cvmx_uahcx_ohci0_hcbulkcurrented_s cn68xxp1;
1672 struct cvmx_uahcx_ohci0_hcbulkcurrented_s cnf71xx;
1674 typedef union cvmx_uahcx_ohci0_hcbulkcurrented cvmx_uahcx_ohci0_hcbulkcurrented_t;
1677 * cvmx_uahc#_ohci0_hcbulkheaded
1679 * HCBULKHEADED = Host Controller Bulk Head ED Register
1681 * The HcBulkHeadED register contains the physical address of the first Endpoint Descriptor of the Bulk list.
1683 union cvmx_uahcx_ohci0_hcbulkheaded {
1685 struct cvmx_uahcx_ohci0_hcbulkheaded_s {
1686 #ifdef __BIG_ENDIAN_BITFIELD
1687 uint32_t bhed : 28; /**< BulkHeadED. HC traverses the Bulk list starting with the HcBulkHeadED
1688 pointer. The content is loaded from HCCA during the initialization of HC. */
1689 uint32_t reserved_0_3 : 4;
1691 uint32_t reserved_0_3 : 4;
1695 struct cvmx_uahcx_ohci0_hcbulkheaded_s cn61xx;
1696 struct cvmx_uahcx_ohci0_hcbulkheaded_s cn63xx;
1697 struct cvmx_uahcx_ohci0_hcbulkheaded_s cn63xxp1;
1698 struct cvmx_uahcx_ohci0_hcbulkheaded_s cn66xx;
1699 struct cvmx_uahcx_ohci0_hcbulkheaded_s cn68xx;
1700 struct cvmx_uahcx_ohci0_hcbulkheaded_s cn68xxp1;
1701 struct cvmx_uahcx_ohci0_hcbulkheaded_s cnf71xx;
1703 typedef union cvmx_uahcx_ohci0_hcbulkheaded cvmx_uahcx_ohci0_hcbulkheaded_t;
1706 * cvmx_uahc#_ohci0_hccommandstatus
1708 * HCCOMMANDSTATUS = Host Controller Command Status Register
1710 * The HcCommandStatus register is used by the Host Controller to receive commands issued by the Host Controller Driver, as well as reflecting the
1711 * current status of the Host Controller. To the Host Controller Driver, it appears to be a "write to set" register. The Host Controller must ensure
1712 * that bits written as '1' become set in the register while bits written as '0' remain unchanged in the register. The Host Controller Driver
1713 * may issue multiple distinct commands to the Host Controller without concern for corrupting previously issued commands. The Host Controller Driver
1714 * has normal read access to all bits.
1715 * The SchedulingOverrunCount field indicates the number of frames with which the Host Controller has detected the scheduling overrun error. This
1716 * occurs when the Periodic list does not complete before EOF. When a scheduling overrun error is detected, the Host Controller increments the counter
1717 * and sets the SchedulingOverrun field in the HcInterruptStatus register.
1719 union cvmx_uahcx_ohci0_hccommandstatus {
1721 struct cvmx_uahcx_ohci0_hccommandstatus_s {
1722 #ifdef __BIG_ENDIAN_BITFIELD
1723 uint32_t reserved_18_31 : 14;
1724 uint32_t soc : 2; /**< SchedulingOverrunCount. These bits are incremented on each scheduling overrun
1725 error. It is initialized to 00b and wraps around at 11b. This will be
1726 incremented when a scheduling overrun is detected even if SchedulingOverrun
1727 in HcInterruptStatus has already been set. This is used by HCD to monitor
1728 any persistent scheduling problems. */
1729 uint32_t reserved_4_15 : 12;
1730 uint32_t ocr : 1; /**< OwnershipChangeRequest. This bit is set by an OS HCD to request a change of
1731 control of the HC. When set HC will set the OwnershipChange field in
1732 HcInterruptStatus. After the changeover, this bit is cleared and remains so
1733 until the next request from OS HCD. */
1734 uint32_t blf : 1; /**< BulkListFilled This bit is used to indicate whether there are any TDs on the
1735 Bulk list. It is set by HCD whenever it adds a TD to an ED in the Bulk list.
1736 When HC begins to process the head of the Bulk list, it checks BF. As long
1737 as BulkListFilled is 0, HC will not start processing the Bulk list. If
1738 BulkListFilled is 1, HC will start processing the Bulk list and will set BF
1739 to 0. If HC finds a TD on the list, then HC will set BulkListFilled to 1
1740 causing the Bulk list processing to continue. If no TD is found on the Bulk
1741 list,and if HCD does not set BulkListFilled, then BulkListFilled will still
1742 be 0 when HC completes processing the Bulk list and Bulk list processing will
1744 uint32_t clf : 1; /**< ControlListFilled. This bit is used to indicate whether there are any TDs
1745 on the Control list. It is set by HCD whenever it adds a TD to an ED in the
1746 Control list. When HC begins to process the head of the Control list, it
1747 checks CLF. As long as ControlListFilled is 0, HC will not start processing
1748 the Control list. If CF is 1, HC will start processing the Control list and
1749 will set ControlListFilled to 0. If HC finds a TD on the list, then HC will
1750 set ControlListFilled to 1 causing the Control list processing to continue.
1751 If no TD is found on the Control list, and if the HCD does not set
1752 ControlListFilled, then ControlListFilled will still be 0 when HC completes
1753 processing the Control list and Control list processing will stop. */
1754 uint32_t hcr : 1; /**< HostControllerReset. This bit is set by HCD to initiate a software reset of
1755 HC. Regardless of the functional state of HC, it moves to the USBSUSPEND
1756 state in which most of the operational registers are reset except those
1757 stated otherwise; e.g., the InterruptRouting field of HcControl, and no
1758 Host bus accesses are allowed. This bit is cleared by HC upon the
1759 completion of the reset operation. The reset operation must be completed
1760 within 10 ms. This bit, when set, should not cause a reset to the Root Hub
1761 and no subsequent reset signaling should be asserted to its downstream ports. */
1767 uint32_t reserved_4_15 : 12;
1769 uint32_t reserved_18_31 : 14;
1772 struct cvmx_uahcx_ohci0_hccommandstatus_s cn61xx;
1773 struct cvmx_uahcx_ohci0_hccommandstatus_s cn63xx;
1774 struct cvmx_uahcx_ohci0_hccommandstatus_s cn63xxp1;
1775 struct cvmx_uahcx_ohci0_hccommandstatus_s cn66xx;
1776 struct cvmx_uahcx_ohci0_hccommandstatus_s cn68xx;
1777 struct cvmx_uahcx_ohci0_hccommandstatus_s cn68xxp1;
1778 struct cvmx_uahcx_ohci0_hccommandstatus_s cnf71xx;
1780 typedef union cvmx_uahcx_ohci0_hccommandstatus cvmx_uahcx_ohci0_hccommandstatus_t;
1783 * cvmx_uahc#_ohci0_hccontrol
1785 * HCCONTROL = Host Controller Control Register
1787 * The HcControl register defines the operating modes for the Host Controller. Most of the fields in this register are modified only by the Host Controller
1788 * Driver, except HostControllerFunctionalState and RemoteWakeupConnected.
1790 union cvmx_uahcx_ohci0_hccontrol {
1792 struct cvmx_uahcx_ohci0_hccontrol_s {
1793 #ifdef __BIG_ENDIAN_BITFIELD
1794 uint32_t reserved_11_31 : 21;
1795 uint32_t rwe : 1; /**< RemoteWakeupEnable. This bit is used by HCD to enable or disable the remote wakeup
1796 feature upon the detection of upstream resume signaling. When this bit is set and
1797 the ResumeDetected bit in HcInterruptStatus is set, a remote wakeup is signaled
1798 to the host system. Setting this bit has no impact on the generation of hardware
1800 uint32_t rwc : 1; /**< RemoteWakeupConnected.This bit indicates whether HC supports remote wakeup signaling.
1801 If remote wakeup is supported and used by the system it is the responsibility of
1802 system firmware to set this bit during POST. HC clears the bit upon a hardware reset
1803 but does not alter it upon a software reset. Remote wakeup signaling of the host
1804 system is host-bus-specific and is not described in this specification. */
1805 uint32_t ir : 1; /**< InterruptRouting
1806 This bit determines the routing of interrupts generated by events registered in
1807 HcInterruptStatus. If clear, all interrupts are routed to the normal host bus
1808 interrupt mechanism. If set, interrupts are routed to the System Management
1809 Interrupt. HCD clears this bit upon a hardware reset, but it does not alter
1810 this bit upon a software reset. HCD uses this bit as a tag to indicate the
1812 uint32_t hcfs : 2; /**< HostControllerFunctionalState for USB
1817 A transition to USBOPERATIONAL from another state causes SOF generation to begin
1818 1 ms later. HCD may determine whether HC has begun sending SOFs by reading the
1819 StartofFrame field of HcInterruptStatus.
1820 This field may be changed by HC only when in the USBSUSPEND state. HC may move from
1821 the USBSUSPEND state to the USBRESUME state after detecting the resume signaling
1822 from a downstream port.
1823 HC enters USBSUSPEND after a software reset, whereas it enters USBRESET after a
1824 hardware reset. The latter also resets the Root Hub and asserts subsequent reset
1825 signaling to downstream ports. */
1826 uint32_t ble : 1; /**< BulkListEnable. This bit is set to enable the processing of the Bulk list in the
1827 next Frame. If cleared by HCD, processing of the Bulk list does not occur after
1828 the next SOF. HC checks this bit whenever it determines to process the list. When
1829 disabled, HCD may modify the list. If HcBulkCurrentED is pointing to an ED to be
1830 removed, HCD must advance the pointer by updating HcBulkCurrentED before re-enabling
1831 processing of the list. */
1832 uint32_t cle : 1; /**< ControlListEnable. This bit is set to enable the processing of the Control list in
1833 the next Frame. If cleared by HCD, processing of the Control list does not occur
1834 after the next SOF. HC must check this bit whenever it determines to process the
1835 list. When disabled, HCD may modify the list. If HcControlCurrentED is pointing to
1836 an ED to be removed, HCD must advance the pointer by updating HcControlCurrentED
1837 before re-enabling processing of the list. */
1838 uint32_t ie : 1; /**< IsochronousEnable This bit is used by HCD to enable/disable processing of
1839 isochronous EDs. While processing the periodic list in a Frame, HC checks the
1840 status of this bit when it finds an Isochronous ED (F=1). If set (enabled), HC
1841 continues processing the EDs. If cleared (disabled), HC halts processing of the
1842 periodic list (which now contains only isochronous EDs) and begins processing the
1843 Bulk/Control lists. Setting this bit is guaranteed to take effect in the next
1844 Frame (not the current Frame). */
1845 uint32_t ple : 1; /**< PeriodicListEnable. This bit is set to enable the processing of the periodic list
1846 in the next Frame. If cleared by HCD, processing of the periodic list does not
1847 occur after the next SOF. HC must check this bit before it starts processing
1849 uint32_t cbsr : 2; /**< ControlBulkServiceRatio. This specifies the service ratio between Control and
1850 Bulk EDs. Before processing any of the nonperiodic lists, HC must compare the
1851 ratio specified with its internal count on how many nonempty Control EDs have
1852 been processed, in determining whether to continue serving another Control ED
1853 or switching to Bulk EDs. The internal count will be retained when crossing
1854 the frame boundary. In case of reset, HCD is responsible for restoring this
1857 CBSR No. of Control EDs Over Bulk EDs Served
1872 uint32_t reserved_11_31 : 21;
1875 struct cvmx_uahcx_ohci0_hccontrol_s cn61xx;
1876 struct cvmx_uahcx_ohci0_hccontrol_s cn63xx;
1877 struct cvmx_uahcx_ohci0_hccontrol_s cn63xxp1;
1878 struct cvmx_uahcx_ohci0_hccontrol_s cn66xx;
1879 struct cvmx_uahcx_ohci0_hccontrol_s cn68xx;
1880 struct cvmx_uahcx_ohci0_hccontrol_s cn68xxp1;
1881 struct cvmx_uahcx_ohci0_hccontrol_s cnf71xx;
1883 typedef union cvmx_uahcx_ohci0_hccontrol cvmx_uahcx_ohci0_hccontrol_t;
1886 * cvmx_uahc#_ohci0_hccontrolcurrented
1888 * HCCONTROLCURRENTED = Host Controller Control Current ED Register
1890 * The HcControlCurrentED register contains the physical address of the current Endpoint Descriptor of the Control list.
1892 union cvmx_uahcx_ohci0_hccontrolcurrented {
1894 struct cvmx_uahcx_ohci0_hccontrolcurrented_s {
1895 #ifdef __BIG_ENDIAN_BITFIELD
1896 uint32_t cced : 28; /**< ControlCurrentED. This pointer is advanced to the next ED after serving the
1897 present one. HC will continue processing the list from where it left off in
1898 the last Frame. When it reaches the end of the Control list, HC checks the
1899 ControlListFilled of in HcCommandStatus. If set, it copies the content of
1900 HcControlHeadED to HcControlCurrentED and clears the bit. If not set, it
1901 does nothing. HCD is allowed to modify this register only when the
1902 ControlListEnable of HcControl is cleared. When set, HCD only reads the
1903 instantaneous value of this register. Initially, this is set to zero to
1904 indicate the end of the Control list. */
1905 uint32_t reserved_0_3 : 4;
1907 uint32_t reserved_0_3 : 4;
1911 struct cvmx_uahcx_ohci0_hccontrolcurrented_s cn61xx;
1912 struct cvmx_uahcx_ohci0_hccontrolcurrented_s cn63xx;
1913 struct cvmx_uahcx_ohci0_hccontrolcurrented_s cn63xxp1;
1914 struct cvmx_uahcx_ohci0_hccontrolcurrented_s cn66xx;
1915 struct cvmx_uahcx_ohci0_hccontrolcurrented_s cn68xx;
1916 struct cvmx_uahcx_ohci0_hccontrolcurrented_s cn68xxp1;
1917 struct cvmx_uahcx_ohci0_hccontrolcurrented_s cnf71xx;
1919 typedef union cvmx_uahcx_ohci0_hccontrolcurrented cvmx_uahcx_ohci0_hccontrolcurrented_t;
1922 * cvmx_uahc#_ohci0_hccontrolheaded
1924 * HCCONTROLHEADED = Host Controller Control Head ED Register
1926 * The HcControlHeadED register contains the physical address of the first Endpoint Descriptor of the Control list.
1928 union cvmx_uahcx_ohci0_hccontrolheaded {
1930 struct cvmx_uahcx_ohci0_hccontrolheaded_s {
1931 #ifdef __BIG_ENDIAN_BITFIELD
1932 uint32_t ched : 28; /**< ControlHeadED. HC traverses the Control list starting with the HcControlHeadED
1933 pointer. The content is loaded from HCCA during the initialization of HC. */
1934 uint32_t reserved_0_3 : 4;
1936 uint32_t reserved_0_3 : 4;
1940 struct cvmx_uahcx_ohci0_hccontrolheaded_s cn61xx;
1941 struct cvmx_uahcx_ohci0_hccontrolheaded_s cn63xx;
1942 struct cvmx_uahcx_ohci0_hccontrolheaded_s cn63xxp1;
1943 struct cvmx_uahcx_ohci0_hccontrolheaded_s cn66xx;
1944 struct cvmx_uahcx_ohci0_hccontrolheaded_s cn68xx;
1945 struct cvmx_uahcx_ohci0_hccontrolheaded_s cn68xxp1;
1946 struct cvmx_uahcx_ohci0_hccontrolheaded_s cnf71xx;
1948 typedef union cvmx_uahcx_ohci0_hccontrolheaded cvmx_uahcx_ohci0_hccontrolheaded_t;
1951 * cvmx_uahc#_ohci0_hcdonehead
1953 * HCDONEHEAD = Host Controller Done Head Register
1955 * The HcDoneHead register contains the physical address of the last completed Transfer Descriptor that was added to the Done queue. In normal operation,
1956 * the Host Controller Driver should not need to read this register as its content is periodically written to the HCCA.
1958 union cvmx_uahcx_ohci0_hcdonehead {
1960 struct cvmx_uahcx_ohci0_hcdonehead_s {
1961 #ifdef __BIG_ENDIAN_BITFIELD
1962 uint32_t dh : 28; /**< DoneHead. When a TD is completed, HC writes the content of HcDoneHead to the
1963 NextTD field of the TD. HC then overwrites the content of HcDoneHead with the
1964 address of this TD. This is set to zero whenever HC writes the content of
1965 this register to HCCA. It also sets the WritebackDoneHead of HcInterruptStatus. */
1966 uint32_t reserved_0_3 : 4;
1968 uint32_t reserved_0_3 : 4;
1972 struct cvmx_uahcx_ohci0_hcdonehead_s cn61xx;
1973 struct cvmx_uahcx_ohci0_hcdonehead_s cn63xx;
1974 struct cvmx_uahcx_ohci0_hcdonehead_s cn63xxp1;
1975 struct cvmx_uahcx_ohci0_hcdonehead_s cn66xx;
1976 struct cvmx_uahcx_ohci0_hcdonehead_s cn68xx;
1977 struct cvmx_uahcx_ohci0_hcdonehead_s cn68xxp1;
1978 struct cvmx_uahcx_ohci0_hcdonehead_s cnf71xx;
1980 typedef union cvmx_uahcx_ohci0_hcdonehead cvmx_uahcx_ohci0_hcdonehead_t;
1983 * cvmx_uahc#_ohci0_hcfminterval
1985 * HCFMINTERVAL = Host Controller Frame Interval Register
1987 * The HcFmInterval register contains a 14-bit value which indicates the bit time interval in a Frame, (i.e., between two consecutive SOFs), and a 15-bit value
1988 * indicating the Full Speed maximum packet size that the Host Controller may transmit or receive without causing scheduling overrun. The Host Controller Driver
1989 * may carry out minor adjustment on the FrameInterval by writing a new value over the present one at each SOF. This provides the programmability necessary for
1990 * the Host Controller to synchronize with an external clocking resource and to adjust any unknown local clock offset.
1992 union cvmx_uahcx_ohci0_hcfminterval {
1994 struct cvmx_uahcx_ohci0_hcfminterval_s {
1995 #ifdef __BIG_ENDIAN_BITFIELD
1996 uint32_t fit : 1; /**< FrameIntervalToggle. HCD toggles this bit whenever it loads a new value to
1998 uint32_t fsmps : 15; /**< FSLargestDataPacket. This field specifies a value which is loaded into the
1999 Largest Data Packet Counter at the beginning of each frame. The counter value
2000 represents the largest amount of data in bits which can be sent or received by
2001 the HC in a single transaction at any given time without causing scheduling
2002 overrun. The field value is calculated by the HCD. */
2003 uint32_t reserved_14_15 : 2;
2004 uint32_t fi : 14; /**< FrameInterval. This specifies the interval between two consecutive SOFs in bit
2005 times. The nominal value is set to be 11,999. HCD should store the current
2006 value of this field before resetting HC. By setting the HostControllerReset
2007 field of HcCommandStatus as this will cause the HC to reset this field to its
2008 nominal value. HCD may choose to restore the stored value upon the completion
2009 of the Reset sequence. */
2012 uint32_t reserved_14_15 : 2;
2013 uint32_t fsmps : 15;
2017 struct cvmx_uahcx_ohci0_hcfminterval_s cn61xx;
2018 struct cvmx_uahcx_ohci0_hcfminterval_s cn63xx;
2019 struct cvmx_uahcx_ohci0_hcfminterval_s cn63xxp1;
2020 struct cvmx_uahcx_ohci0_hcfminterval_s cn66xx;
2021 struct cvmx_uahcx_ohci0_hcfminterval_s cn68xx;
2022 struct cvmx_uahcx_ohci0_hcfminterval_s cn68xxp1;
2023 struct cvmx_uahcx_ohci0_hcfminterval_s cnf71xx;
2025 typedef union cvmx_uahcx_ohci0_hcfminterval cvmx_uahcx_ohci0_hcfminterval_t;
2028 * cvmx_uahc#_ohci0_hcfmnumber
2030 * HCFMNUMBER = Host Cotroller Frame Number Register
2032 * The HcFmNumber register is a 16-bit counter. It provides a timing reference among events happening in the Host Controller and the Host Controller Driver.
2033 * The Host Controller Driver may use the 16-bit value specified in this register and generate a 32-bit frame number without requiring frequent access to
2036 union cvmx_uahcx_ohci0_hcfmnumber {
2038 struct cvmx_uahcx_ohci0_hcfmnumber_s {
2039 #ifdef __BIG_ENDIAN_BITFIELD
2040 uint32_t reserved_16_31 : 16;
2041 uint32_t fn : 16; /**< FrameNumber. This is incremented when HcFmRemaining is re-loaded. It will be
2042 rolled over to 0h after ffffh. When entering the USBOPERATIONAL state,
2043 this will be incremented automatically. The content will be written to HCCA
2044 after HC has incremented the FrameNumber at each frame boundary and sent a
2045 SOF but before HC reads the first ED in that Frame. After writing to HCCA,
2046 HC will set the StartofFrame in HcInterruptStatus. */
2049 uint32_t reserved_16_31 : 16;
2052 struct cvmx_uahcx_ohci0_hcfmnumber_s cn61xx;
2053 struct cvmx_uahcx_ohci0_hcfmnumber_s cn63xx;
2054 struct cvmx_uahcx_ohci0_hcfmnumber_s cn63xxp1;
2055 struct cvmx_uahcx_ohci0_hcfmnumber_s cn66xx;
2056 struct cvmx_uahcx_ohci0_hcfmnumber_s cn68xx;
2057 struct cvmx_uahcx_ohci0_hcfmnumber_s cn68xxp1;
2058 struct cvmx_uahcx_ohci0_hcfmnumber_s cnf71xx;
2060 typedef union cvmx_uahcx_ohci0_hcfmnumber cvmx_uahcx_ohci0_hcfmnumber_t;
2063 * cvmx_uahc#_ohci0_hcfmremaining
2065 * HCFMREMAINING = Host Controller Frame Remaining Register
2066 * The HcFmRemaining register is a 14-bit down counter showing the bit time remaining in the current Frame.
2068 union cvmx_uahcx_ohci0_hcfmremaining {
2070 struct cvmx_uahcx_ohci0_hcfmremaining_s {
2071 #ifdef __BIG_ENDIAN_BITFIELD
2072 uint32_t frt : 1; /**< FrameRemainingToggle. This bit is loaded from the FrameIntervalToggle field
2073 of HcFmInterval whenever FrameRemaining reaches 0. This bit is used by HCD
2074 for the synchronization between FrameInterval and FrameRemaining. */
2075 uint32_t reserved_14_30 : 17;
2076 uint32_t fr : 14; /**< FrameRemaining. This counter is decremented at each bit time. When it
2077 reaches zero, it is reset by loading the FrameInterval value specified in
2078 HcFmInterval at the next bit time boundary. When entering the USBOPERATIONAL
2079 state, HC re-loads the content with the FrameInterval of HcFmInterval and uses
2080 the updated value from the next SOF. */
2083 uint32_t reserved_14_30 : 17;
2087 struct cvmx_uahcx_ohci0_hcfmremaining_s cn61xx;
2088 struct cvmx_uahcx_ohci0_hcfmremaining_s cn63xx;
2089 struct cvmx_uahcx_ohci0_hcfmremaining_s cn63xxp1;
2090 struct cvmx_uahcx_ohci0_hcfmremaining_s cn66xx;
2091 struct cvmx_uahcx_ohci0_hcfmremaining_s cn68xx;
2092 struct cvmx_uahcx_ohci0_hcfmremaining_s cn68xxp1;
2093 struct cvmx_uahcx_ohci0_hcfmremaining_s cnf71xx;
2095 typedef union cvmx_uahcx_ohci0_hcfmremaining cvmx_uahcx_ohci0_hcfmremaining_t;
2098 * cvmx_uahc#_ohci0_hchcca
2100 * HCHCCA = Host Controller Host Controller Communication Area Register
2102 * The HcHCCA register contains the physical address of the Host Controller Communication Area. The Host Controller Driver determines the alignment restrictions
2103 * by writing all 1s to HcHCCA and reading the content of HcHCCA. The alignment is evaluated by examining the number of zeroes in the lower order bits. The
2104 * minimum alignment is 256 bytes; therefore, bits 0 through 7 must always return '0' when read. Detailed description can be found in Chapter 4. This area
2105 * is used to hold the control structures and the Interrupt table that are accessed by both the Host Controller and the Host Controller Driver.
2107 union cvmx_uahcx_ohci0_hchcca {
2109 struct cvmx_uahcx_ohci0_hchcca_s {
2110 #ifdef __BIG_ENDIAN_BITFIELD
2111 uint32_t hcca : 24; /**< This is the base address (bits [31:8]) of the Host Controller Communication Area. */
2112 uint32_t reserved_0_7 : 8;
2114 uint32_t reserved_0_7 : 8;
2118 struct cvmx_uahcx_ohci0_hchcca_s cn61xx;
2119 struct cvmx_uahcx_ohci0_hchcca_s cn63xx;
2120 struct cvmx_uahcx_ohci0_hchcca_s cn63xxp1;
2121 struct cvmx_uahcx_ohci0_hchcca_s cn66xx;
2122 struct cvmx_uahcx_ohci0_hchcca_s cn68xx;
2123 struct cvmx_uahcx_ohci0_hchcca_s cn68xxp1;
2124 struct cvmx_uahcx_ohci0_hchcca_s cnf71xx;
2126 typedef union cvmx_uahcx_ohci0_hchcca cvmx_uahcx_ohci0_hchcca_t;
2129 * cvmx_uahc#_ohci0_hcinterruptdisable
2131 * HCINTERRUPTDISABLE = Host Controller InterruptDisable Register
2133 * Each disable bit in the HcInterruptDisable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptDisable
2134 * register is coupled with the HcInterruptEnable register. Thus, writing a '1' to a bit in this register clears the corresponding bit in the HcInterruptEnable
2135 * register, whereas writing a '0' to a bit in this register leaves the corresponding bit in the HcInterruptEnable register unchanged. On read, the current
2136 * value of the HcInterruptEnable register is returned.
2138 union cvmx_uahcx_ohci0_hcinterruptdisable {
2140 struct cvmx_uahcx_ohci0_hcinterruptdisable_s {
2141 #ifdef __BIG_ENDIAN_BITFIELD
2142 uint32_t mie : 1; /**< A '0' written to this field is ignored by HC.
2143 A '1' written to this field disables interrupt generation due to events
2144 specified in the other bits of this register. This field is set after a
2145 hardware or software reset. */
2146 uint32_t oc : 1; /**< 0 - Ignore; 1 - Disable interrupt generation due to Ownership Change. */
2147 uint32_t reserved_7_29 : 23;
2148 uint32_t rhsc : 1; /**< 0 - Ignore; 1 - Disable interrupt generation due to Root Hub Status Change. */
2149 uint32_t fno : 1; /**< 0 - Ignore; 1 - Disable interrupt generation due to Frame Number Overflow. */
2150 uint32_t ue : 1; /**< 0 - Ignore; 1 - Disable interrupt generation due to Unrecoverable Error. */
2151 uint32_t rd : 1; /**< 0 - Ignore; 1 - Disable interrupt generation due to Resume Detect. */
2152 uint32_t sf : 1; /**< 0 - Ignore; 1 - Disable interrupt generation due to Start of Frame. */
2153 uint32_t wdh : 1; /**< 0 - Ignore; 1 - Disable interrupt generation due to HcDoneHead Writeback. */
2154 uint32_t so : 1; /**< 0 - Ignore; 1 - Disable interrupt generation due to Scheduling Overrun. */
2163 uint32_t reserved_7_29 : 23;
2168 struct cvmx_uahcx_ohci0_hcinterruptdisable_s cn61xx;
2169 struct cvmx_uahcx_ohci0_hcinterruptdisable_s cn63xx;
2170 struct cvmx_uahcx_ohci0_hcinterruptdisable_s cn63xxp1;
2171 struct cvmx_uahcx_ohci0_hcinterruptdisable_s cn66xx;
2172 struct cvmx_uahcx_ohci0_hcinterruptdisable_s cn68xx;
2173 struct cvmx_uahcx_ohci0_hcinterruptdisable_s cn68xxp1;
2174 struct cvmx_uahcx_ohci0_hcinterruptdisable_s cnf71xx;
2176 typedef union cvmx_uahcx_ohci0_hcinterruptdisable cvmx_uahcx_ohci0_hcinterruptdisable_t;
2179 * cvmx_uahc#_ohci0_hcinterruptenable
2181 * HCINTERRUPTENABLE = Host Controller InterruptEnable Register
2183 * Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptEnable
2184 * register is used to control which events generate a hardware interrupt. When a bit is set in the HcInterruptStatus register AND the corresponding bit
2185 * in the HcInterruptEnable register is set AND the MasterInterruptEnable bit is set, then a hardware interrupt is requested on the host bus.
2186 * Writing a '1' to a bit in this register sets the corresponding bit, whereas writing a '0' to a bit in this register leaves the corresponding bit
2187 * unchanged. On read, the current value of this register is returned.
2189 union cvmx_uahcx_ohci0_hcinterruptenable {
2191 struct cvmx_uahcx_ohci0_hcinterruptenable_s {
2192 #ifdef __BIG_ENDIAN_BITFIELD
2193 uint32_t mie : 1; /**< A '0' written to this field is ignored by HC.
2194 A '1' written to this field enables interrupt generation due to events
2195 specified in the other bits of this register. This is used by HCD as a Master
2196 Interrupt Enable. */
2197 uint32_t oc : 1; /**< 0 - Ignore; 1 - Enable interrupt generation due to Ownership Change. */
2198 uint32_t reserved_7_29 : 23;
2199 uint32_t rhsc : 1; /**< 0 - Ignore; 1 - Enable interrupt generation due to Root Hub Status Change. */
2200 uint32_t fno : 1; /**< 0 - Ignore; 1 - Enable interrupt generation due to Frame Number Overflow. */
2201 uint32_t ue : 1; /**< 0 - Ignore; 1 - Enable interrupt generation due to Unrecoverable Error. */
2202 uint32_t rd : 1; /**< 0 - Ignore; 1 - Enable interrupt generation due to Resume Detect. */
2203 uint32_t sf : 1; /**< 0 - Ignore; 1 - Enable interrupt generation due to Start of Frame. */
2204 uint32_t wdh : 1; /**< 0 - Ignore; 1 - Enable interrupt generation due to HcDoneHead Writeback. */
2205 uint32_t so : 1; /**< 0 - Ignore; 1 - Enable interrupt generation due to Scheduling Overrun. */
2214 uint32_t reserved_7_29 : 23;
2219 struct cvmx_uahcx_ohci0_hcinterruptenable_s cn61xx;
2220 struct cvmx_uahcx_ohci0_hcinterruptenable_s cn63xx;
2221 struct cvmx_uahcx_ohci0_hcinterruptenable_s cn63xxp1;
2222 struct cvmx_uahcx_ohci0_hcinterruptenable_s cn66xx;
2223 struct cvmx_uahcx_ohci0_hcinterruptenable_s cn68xx;
2224 struct cvmx_uahcx_ohci0_hcinterruptenable_s cn68xxp1;
2225 struct cvmx_uahcx_ohci0_hcinterruptenable_s cnf71xx;
2227 typedef union cvmx_uahcx_ohci0_hcinterruptenable cvmx_uahcx_ohci0_hcinterruptenable_t;
2230 * cvmx_uahc#_ohci0_hcinterruptstatus
2232 * HCINTERRUPTSTATUS = Host Controller InterruptStatus Register
2234 * This register provides status on various events that cause hardware interrupts. When an event occurs, Host Controller sets the corresponding bit
2235 * in this register. When a bit becomes set, a hardware interrupt is generated if the interrupt is enabled in the HcInterruptEnable register
2236 * and the MasterInterruptEnable bit is set. The Host Controller Driver may clear specific bits in this register by writing '1' to bit positions
2237 * to be cleared. The Host Controller Driver may not set any of these bits. The Host Controller will never clear the bit.
2239 union cvmx_uahcx_ohci0_hcinterruptstatus {
2241 struct cvmx_uahcx_ohci0_hcinterruptstatus_s {
2242 #ifdef __BIG_ENDIAN_BITFIELD
2243 uint32_t reserved_31_31 : 1;
2244 uint32_t oc : 1; /**< OwnershipChange. This bit is set by HC when HCD sets the OwnershipChangeRequest
2245 field in HcCommandStatus. This event, when unmasked, will always generate an
2246 System Management Interrupt (SMI) immediately. This bit is tied to 0b when the
2247 SMI pin is not implemented. */
2248 uint32_t reserved_7_29 : 23;
2249 uint32_t rhsc : 1; /**< RootHubStatusChange. This bit is set when the content of HcRhStatus or the
2250 content of any of HcRhPortStatus[NumberofDownstreamPort] has changed. */
2251 uint32_t fno : 1; /**< FrameNumberOverflow. This bit is set when the MSb of HcFmNumber (bit 15)
2252 changes value, from 0 to 1 or from 1 to 0, and after HccaFrameNumber has been
2254 uint32_t ue : 1; /**< UnrecoverableError. This bit is set when HC detects a system error not related
2255 to USB. HC should not proceed with any processing nor signaling before the
2256 system error has been corrected. HCD clears this bit after HC has been reset. */
2257 uint32_t rd : 1; /**< ResumeDetected. This bit is set when HC detects that a device on the USB is
2258 asserting resume signaling. It is the transition from no resume signaling to
2259 resume signaling causing this bit to be set. This bit is not set when HCD
2260 sets the USBRESUME state. */
2261 uint32_t sf : 1; /**< StartofFrame. This bit is set by HC at each start of a frame and after the
2262 update of HccaFrameNumber. HC also generates a SOF token at the same time. */
2263 uint32_t wdh : 1; /**< WritebackDoneHead. This bit is set immediately after HC has written
2264 HcDoneHead to HccaDoneHead. Further updates of the HccaDoneHead will not
2265 occur until this bit has been cleared. HCD should only clear this bit after
2266 it has saved the content of HccaDoneHead. */
2267 uint32_t so : 1; /**< SchedulingOverrun. This bit is set when the USB schedule for the current
2268 Frame overruns and after the update of HccaFrameNumber. A scheduling overrun
2269 will also cause the SchedulingOverrunCount of HcCommandStatus to be
2279 uint32_t reserved_7_29 : 23;
2281 uint32_t reserved_31_31 : 1;
2284 struct cvmx_uahcx_ohci0_hcinterruptstatus_s cn61xx;
2285 struct cvmx_uahcx_ohci0_hcinterruptstatus_s cn63xx;
2286 struct cvmx_uahcx_ohci0_hcinterruptstatus_s cn63xxp1;
2287 struct cvmx_uahcx_ohci0_hcinterruptstatus_s cn66xx;
2288 struct cvmx_uahcx_ohci0_hcinterruptstatus_s cn68xx;
2289 struct cvmx_uahcx_ohci0_hcinterruptstatus_s cn68xxp1;
2290 struct cvmx_uahcx_ohci0_hcinterruptstatus_s cnf71xx;
2292 typedef union cvmx_uahcx_ohci0_hcinterruptstatus cvmx_uahcx_ohci0_hcinterruptstatus_t;
2295 * cvmx_uahc#_ohci0_hclsthreshold
2297 * HCLSTHRESHOLD = Host Controller LS Threshold Register
2299 * The HcLSThreshold register contains an 11-bit value used by the Host Controller to determine whether to commit to the transfer of a maximum of 8-byte
2300 * LS packet before EOF. Neither the Host Controller nor the Host Controller Driver are allowed to change this value.
2302 union cvmx_uahcx_ohci0_hclsthreshold {
2304 struct cvmx_uahcx_ohci0_hclsthreshold_s {
2305 #ifdef __BIG_ENDIAN_BITFIELD
2306 uint32_t reserved_12_31 : 20;
2307 uint32_t lst : 12; /**< LSThreshold
2308 This field contains a value which is compared to the FrameRemaining field
2309 prior to initiating a Low Speed transaction. The transaction is started only
2310 if FrameRemaining >= this field. The value is calculated by HCD
2311 with the consideration of transmission and setup overhead. */
2314 uint32_t reserved_12_31 : 20;
2317 struct cvmx_uahcx_ohci0_hclsthreshold_s cn61xx;
2318 struct cvmx_uahcx_ohci0_hclsthreshold_s cn63xx;
2319 struct cvmx_uahcx_ohci0_hclsthreshold_s cn63xxp1;
2320 struct cvmx_uahcx_ohci0_hclsthreshold_s cn66xx;
2321 struct cvmx_uahcx_ohci0_hclsthreshold_s cn68xx;
2322 struct cvmx_uahcx_ohci0_hclsthreshold_s cn68xxp1;
2323 struct cvmx_uahcx_ohci0_hclsthreshold_s cnf71xx;
2325 typedef union cvmx_uahcx_ohci0_hclsthreshold cvmx_uahcx_ohci0_hclsthreshold_t;
2328 * cvmx_uahc#_ohci0_hcperiodcurrented
2330 * HCPERIODCURRENTED = Host Controller Period Current ED Register
2332 * The HcPeriodCurrentED register contains the physical address of the current Isochronous or Interrupt Endpoint Descriptor.
2334 union cvmx_uahcx_ohci0_hcperiodcurrented {
2336 struct cvmx_uahcx_ohci0_hcperiodcurrented_s {
2337 #ifdef __BIG_ENDIAN_BITFIELD
2338 uint32_t pced : 28; /**< PeriodCurrentED. This is used by HC to point to the head of one of the
2339 Periodic lists which will be processed in the current Frame. The content of
2340 this register is updated by HC after a periodic ED has been processed. HCD
2341 may read the content in determining which ED is currently being processed
2342 at the time of reading. */
2343 uint32_t reserved_0_3 : 4;
2345 uint32_t reserved_0_3 : 4;
2349 struct cvmx_uahcx_ohci0_hcperiodcurrented_s cn61xx;
2350 struct cvmx_uahcx_ohci0_hcperiodcurrented_s cn63xx;
2351 struct cvmx_uahcx_ohci0_hcperiodcurrented_s cn63xxp1;
2352 struct cvmx_uahcx_ohci0_hcperiodcurrented_s cn66xx;
2353 struct cvmx_uahcx_ohci0_hcperiodcurrented_s cn68xx;
2354 struct cvmx_uahcx_ohci0_hcperiodcurrented_s cn68xxp1;
2355 struct cvmx_uahcx_ohci0_hcperiodcurrented_s cnf71xx;
2357 typedef union cvmx_uahcx_ohci0_hcperiodcurrented cvmx_uahcx_ohci0_hcperiodcurrented_t;
2360 * cvmx_uahc#_ohci0_hcperiodicstart
2362 * HCPERIODICSTART = Host Controller Periodic Start Register
2364 * The HcPeriodicStart register has a 14-bit programmable value which determines when is the earliest time HC should start processing the periodic list.
2366 union cvmx_uahcx_ohci0_hcperiodicstart {
2368 struct cvmx_uahcx_ohci0_hcperiodicstart_s {
2369 #ifdef __BIG_ENDIAN_BITFIELD
2370 uint32_t reserved_14_31 : 18;
2371 uint32_t ps : 14; /**< PeriodicStart After a hardware reset, this field is cleared. This is then set
2372 by HCD during the HC initialization. The value is calculated roughly as 10%
2373 off from HcFmInterval.. A typical value will be 3E67h. When HcFmRemaining
2374 reaches the value specified, processing of the periodic lists will have
2375 priority over Control/Bulk processing. HC will therefore start processing
2376 the Interrupt list after completing the current Control or Bulk transaction
2377 that is in progress. */
2380 uint32_t reserved_14_31 : 18;
2383 struct cvmx_uahcx_ohci0_hcperiodicstart_s cn61xx;
2384 struct cvmx_uahcx_ohci0_hcperiodicstart_s cn63xx;
2385 struct cvmx_uahcx_ohci0_hcperiodicstart_s cn63xxp1;
2386 struct cvmx_uahcx_ohci0_hcperiodicstart_s cn66xx;
2387 struct cvmx_uahcx_ohci0_hcperiodicstart_s cn68xx;
2388 struct cvmx_uahcx_ohci0_hcperiodicstart_s cn68xxp1;
2389 struct cvmx_uahcx_ohci0_hcperiodicstart_s cnf71xx;
2391 typedef union cvmx_uahcx_ohci0_hcperiodicstart cvmx_uahcx_ohci0_hcperiodicstart_t;
2394 * cvmx_uahc#_ohci0_hcrevision
2396 * HCREVISION = Host Controller Revision Register
2399 union cvmx_uahcx_ohci0_hcrevision {
2401 struct cvmx_uahcx_ohci0_hcrevision_s {
2402 #ifdef __BIG_ENDIAN_BITFIELD
2403 uint32_t reserved_8_31 : 24;
2404 uint32_t rev : 8; /**< Revision This read-only field contains the BCD representation of the version
2405 of the HCI specification that is implemented by this HC. For example, a value
2406 of 11h corresponds to version 1.1. All of the HC implementations that are
2407 compliant with this specification will have a value of 10h. */
2410 uint32_t reserved_8_31 : 24;
2413 struct cvmx_uahcx_ohci0_hcrevision_s cn61xx;
2414 struct cvmx_uahcx_ohci0_hcrevision_s cn63xx;
2415 struct cvmx_uahcx_ohci0_hcrevision_s cn63xxp1;
2416 struct cvmx_uahcx_ohci0_hcrevision_s cn66xx;
2417 struct cvmx_uahcx_ohci0_hcrevision_s cn68xx;
2418 struct cvmx_uahcx_ohci0_hcrevision_s cn68xxp1;
2419 struct cvmx_uahcx_ohci0_hcrevision_s cnf71xx;
2421 typedef union cvmx_uahcx_ohci0_hcrevision cvmx_uahcx_ohci0_hcrevision_t;
2424 * cvmx_uahc#_ohci0_hcrhdescriptora
2426 * HCRHDESCRIPTORA = Host Controller Root Hub DescriptorA Register
2428 * The HcRhDescriptorA register is the first register of two describing the characteristics of the Root Hub. Reset values are implementation-specific.
2429 * The descriptor length (11), descriptor type (0x29), and hub controller current (0) fields of the hub Class Descriptor are emulated by the HCD. All
2430 * other fields are located in the HcRhDescriptorA and HcRhDescriptorB registers.
2432 union cvmx_uahcx_ohci0_hcrhdescriptora {
2434 struct cvmx_uahcx_ohci0_hcrhdescriptora_s {
2435 #ifdef __BIG_ENDIAN_BITFIELD
2436 uint32_t potpgt : 8; /**< PowerOnToPowerGoodTime. This byte specifies the duration HCD has to wait before
2437 accessing a powered-on port of the Root Hub. It is implementation-specific. The
2438 unit of time is 2 ms. The duration is calculated as POTPGT * 2 ms. */
2439 uint32_t reserved_13_23 : 11;
2440 uint32_t nocp : 1; /**< NoOverCurrentProtection. This bit describes how the overcurrent status for the
2441 Root Hub ports are reported. When this bit is cleared, the
2442 OverCurrentProtectionMode field specifies global or per-port reporting.
2443 - 0: Over-current status is reported collectively for all downstream ports
2444 - 1: No overcurrent protection supported */
2445 uint32_t ocpm : 1; /**< OverCurrentProtectionMode. This bit describes how the overcurrent status for
2446 the Root Hub ports are reported. At reset, this fields should reflect the same
2447 mode as PowerSwitchingMode. This field is valid only if the
2448 NoOverCurrentProtection field is cleared. 0: over-current status is reported
2449 collectively for all downstream ports 1: over-current status is reported on a
2451 uint32_t dt : 1; /**< DeviceType. This bit specifies that the Root Hub is not a compound device. The
2452 Root Hub is not permitted to be a compound device. This field should always
2454 uint32_t psm : 1; /**< PowerSwitchingMode. This bit is used to specify how the power switching of
2455 the Root Hub ports is controlled. It is implementation-specific. This field
2456 is only valid if the NoPowerSwitching field is cleared. 0: all ports are
2457 powered at the same time. 1: each port is powered individually. This mode
2458 allows port power to be controlled by either the global switch or per-port
2459 switching. If the PortPowerControlMask bit is set, the port responds only
2460 to port power commands (Set/ClearPortPower). If the port mask is cleared,
2461 then the port is controlled only by the global power switch
2462 (Set/ClearGlobalPower). */
2463 uint32_t nps : 1; /**< NoPowerSwitching These bits are used to specify whether power switching is
2464 supported or port are always powered. It is implementation-specific. When
2465 this bit is cleared, the PowerSwitchingMode specifies global or per-port
2467 - 0: Ports are power switched
2468 - 1: Ports are always powered on when the HC is powered on */
2469 uint32_t ndp : 8; /**< NumberDownstreamPorts. These bits specify the number of downstream ports
2470 supported by the Root Hub. It is implementation-specific. The minimum number
2471 of ports is 1. The maximum number of ports supported by OpenHCI is 15. */
2479 uint32_t reserved_13_23 : 11;
2480 uint32_t potpgt : 8;
2483 struct cvmx_uahcx_ohci0_hcrhdescriptora_s cn61xx;
2484 struct cvmx_uahcx_ohci0_hcrhdescriptora_s cn63xx;
2485 struct cvmx_uahcx_ohci0_hcrhdescriptora_s cn63xxp1;
2486 struct cvmx_uahcx_ohci0_hcrhdescriptora_s cn66xx;
2487 struct cvmx_uahcx_ohci0_hcrhdescriptora_s cn68xx;
2488 struct cvmx_uahcx_ohci0_hcrhdescriptora_s cn68xxp1;
2489 struct cvmx_uahcx_ohci0_hcrhdescriptora_s cnf71xx;
2491 typedef union cvmx_uahcx_ohci0_hcrhdescriptora cvmx_uahcx_ohci0_hcrhdescriptora_t;
2494 * cvmx_uahc#_ohci0_hcrhdescriptorb
2496 * HCRHDESCRIPTORB = Host Controller Root Hub DescriptorB Register
2498 * The HcRhDescriptorB register is the second register of two describing the characteristics of the Root Hub. These fields are written during
2499 * initialization to correspond with the system implementation. Reset values are implementation-specific.
2501 union cvmx_uahcx_ohci0_hcrhdescriptorb {
2503 struct cvmx_uahcx_ohci0_hcrhdescriptorb_s {
2504 #ifdef __BIG_ENDIAN_BITFIELD
2505 uint32_t ppcm : 16; /**< PortPowerControlMask.
2506 Each bit indicates if a port is affected by a global power control command
2507 when PowerSwitchingMode is set. When set, the port's power state is only
2508 affected by per-port power control (Set/ClearPortPower). When cleared, the
2509 port is controlled by the global power switch (Set/ClearGlobalPower). If
2510 the device is configured to global switching mode (PowerSwitchingMode=0),
2511 this field is not valid.
2513 bit 1: Ganged-power mask on Port \#1
2514 bit 2: Ganged-power mask on Port \#2
2516 bit15: Ganged-power mask on Port \#15 */
2517 uint32_t dr : 16; /**< DeviceRemovable.
2518 Each bit is dedicated to a port of the Root Hub. When cleared,the attached
2519 device is removable. When set, the attached device is not removable.
2521 bit 1: Device attached to Port \#1
2522 bit 2: Device attached to Port \#2
2524 bit15: Device attached to Port \#15 */
2530 struct cvmx_uahcx_ohci0_hcrhdescriptorb_s cn61xx;
2531 struct cvmx_uahcx_ohci0_hcrhdescriptorb_s cn63xx;
2532 struct cvmx_uahcx_ohci0_hcrhdescriptorb_s cn63xxp1;
2533 struct cvmx_uahcx_ohci0_hcrhdescriptorb_s cn66xx;
2534 struct cvmx_uahcx_ohci0_hcrhdescriptorb_s cn68xx;
2535 struct cvmx_uahcx_ohci0_hcrhdescriptorb_s cn68xxp1;
2536 struct cvmx_uahcx_ohci0_hcrhdescriptorb_s cnf71xx;
2538 typedef union cvmx_uahcx_ohci0_hcrhdescriptorb cvmx_uahcx_ohci0_hcrhdescriptorb_t;
2541 * cvmx_uahc#_ohci0_hcrhportstatus#
2543 * HCRHPORTSTATUSX = Host Controller Root Hub Port X Status Registers
2545 * The HcRhPortStatus[1:NDP] register is used to control and report port events on a per-port basis. NumberDownstreamPorts represents the number
2546 * of HcRhPortStatus registers that are implemented in hardware. The lower word is used to reflect the port status, whereas the upper word reflects
2547 * the status change bits. Some status bits are implemented with special write behavior (see below). If a transaction (token through handshake) is
2548 * in progress when a write to change port status occurs, the resulting port status change must be postponed until the transaction completes.
2549 * Reserved bits should always be written '0'.
2551 union cvmx_uahcx_ohci0_hcrhportstatusx {
2553 struct cvmx_uahcx_ohci0_hcrhportstatusx_s {
2554 #ifdef __BIG_ENDIAN_BITFIELD
2555 uint32_t reserved_21_31 : 11;
2556 uint32_t prsc : 1; /**< PortResetStatusChange. This bit is set at the end of the 10-ms port reset
2557 signal. The HCD writes a '1' to clear this bit. Writing a '0' has no effect.
2558 0 = port reset is not complete
2559 1 = port reset is complete */
2560 uint32_t ocic : 1; /**< PortOverCurrentIndicatorChange. This bit is valid only if overcurrent
2561 conditions are reported on a per-port basis. This bit is set when Root Hub
2562 changes the PortOverCurrentIndicator bit. The HCD writes a '1' to clear this
2563 bit. Writing a '0' has no effect.
2564 0 = no change in PortOverCurrentIndicator
2565 1 = PortOverCurrentIndicator has changed */
2566 uint32_t pssc : 1; /**< PortSuspendStatusChange. This bit is set when the full resume sequence has
2567 been completed. This sequence includes the 20-s resume pulse, LS EOP, and
2568 3-ms resychronization delay.
2569 The HCD writes a '1' to clear this bit. Writing a '0' has no effect. This
2570 bit is also cleared when ResetStatusChange is set.
2571 0 = resume is not completed
2572 1 = resume completed */
2573 uint32_t pesc : 1; /**< PortEnableStatusChange. This bit is set when hardware events cause the
2574 PortEnableStatus bit to be cleared. Changes from HCD writes do not set this
2575 bit. The HCD writes a '1' to clear this bit. Writing a '0' has no effect.
2576 0 = no change in PortEnableStatus
2577 1 = change in PortEnableStatus */
2578 uint32_t csc : 1; /**< ConnectStatusChange. This bit is set whenever a connect or disconnect event
2579 occurs. The HCD writes a '1' to clear this bit. Writing a '0' has no
2580 effect. If CurrentConnectStatus is cleared when a SetPortReset,SetPortEnable,
2581 or SetPortSuspend write occurs, this bit is set to force the driver to
2582 re-evaluate the connection status since these writes should not occur if the
2583 port is disconnected.
2584 0 = no change in CurrentConnectStatus
2585 1 = change in CurrentConnectStatus
2586 Note: If the DeviceRemovable[NDP] bit is set, this bit is set only after a
2587 Root Hub reset to inform the system that the device is attached. Description */
2588 uint32_t reserved_10_15 : 6;
2589 uint32_t lsda : 1; /**< (read) LowSpeedDeviceAttached. This bit indicates the speed of the device
2590 attached to this port. When set, a Low Speed device is attached to this
2591 port. When clear, a Full Speed device is attached to this port. This
2592 field is valid only when the CurrentConnectStatus is set.
2593 0 = full speed device attached
2594 1 = low speed device attached
2595 (write) ClearPortPower. The HCD clears the PortPowerStatus bit by writing a
2596 '1' to this bit. Writing a '0' has no effect. */
2597 uint32_t pps : 1; /**< (read) PortPowerStatus. This bit reflects the port's power status, regardless
2598 of the type of power switching implemented. This bit is cleared if an
2599 overcurrent condition is detected. HCD sets this bit by writing
2600 SetPortPower or SetGlobalPower. HCD clears this bit by writing
2601 ClearPortPower or ClearGlobalPower. Which power control switches are
2602 enabled is determined by PowerSwitchingMode and PortPortControlMask[NDP].
2603 In global switching mode (PowerSwitchingMode=0), only Set/ClearGlobalPower
2604 controls this bit. In per-port power switching (PowerSwitchingMode=1),
2605 if the PortPowerControlMask[NDP] bit for the port is set, only
2606 Set/ClearPortPower commands are enabled. If the mask is not set, only
2607 Set/ClearGlobalPower commands are enabled. When port power is disabled,
2608 CurrentConnectStatus, PortEnableStatus, PortSuspendStatus, and
2609 PortResetStatus should be reset.
2610 0 = port power is off
2611 1 = port power is on
2612 (write) SetPortPower. The HCD writes a '1' to set the PortPowerStatus bit.
2613 Writing a '0' has no effect. Note: This bit is always reads '1'
2614 if power switching is not supported. */
2615 uint32_t reserved_5_7 : 3;
2616 uint32_t prs : 1; /**< (read) PortResetStatus. When this bit is set by a write to SetPortReset, port
2617 reset signaling is asserted. When reset is completed, this bit is
2618 cleared when PortResetStatusChange is set. This bit cannot be set if
2619 CurrentConnectStatus is cleared.
2620 0 = port reset signal is not active
2621 1 = port reset signal is active
2622 (write) SetPortReset. The HCD sets the port reset signaling by writing a '1'
2623 to this bit. Writing a '0'has no effect. If CurrentConnectStatus is
2624 cleared, this write does not set PortResetStatus, but instead sets
2625 ConnectStatusChange. This informs the driver that it attempted to reset
2626 a disconnected port. Description */
2627 uint32_t poci : 1; /**< (read) PortOverCurrentIndicator. This bit is only valid when the Root Hub is
2628 configured in such a way that overcurrent conditions are reported on a
2629 per-port basis. If per-port overcurrent reporting is not supported, this
2630 bit is set to 0. If cleared, all power operations are normal for this
2631 port. If set, an overcurrent condition exists on this port. This bit
2632 always reflects the overcurrent input signal
2633 0 = no overcurrent condition.
2634 1 = overcurrent condition detected.
2635 (write) ClearSuspendStatus. The HCD writes a '1' to initiate a resume.
2636 Writing a '0' has no effect. A resume is initiated only if
2637 PortSuspendStatus is set. */
2638 uint32_t pss : 1; /**< (read) PortSuspendStatus. This bit indicates the port is suspended or in the
2639 resume sequence. It is set by a SetSuspendState write and cleared when
2640 PortSuspendStatusChange is set at the end of the resume interval. This
2641 bit cannot be set if CurrentConnectStatus is cleared. This bit is also
2642 cleared when PortResetStatusChange is set at the end of the port reset
2643 or when the HC is placed in the USBRESUME state. If an upstream resume is
2644 in progress, it should propagate to the HC.
2645 0 = port is not suspended
2646 1 = port is suspended
2647 (write) SetPortSuspend. The HCD sets the PortSuspendStatus bit by writing a
2648 '1' to this bit. Writing a '0' has no effect. If CurrentConnectStatus
2649 is cleared, this write does not set PortSuspendStatus; instead it sets
2650 ConnectStatusChange.This informs the driver that it attempted to suspend
2651 a disconnected port. */
2652 uint32_t pes : 1; /**< (read) PortEnableStatus. This bit indicates whether the port is enabled or
2653 disabled. The Root Hub may clear this bit when an overcurrent condition,
2654 disconnect event, switched-off power, or operational bus error such
2655 as babble is detected. This change also causes PortEnabledStatusChange
2656 to be set. HCD sets this bit by writing SetPortEnable and clears it by
2657 writing ClearPortEnable. This bit cannot be set when CurrentConnectStatus
2658 is cleared. This bit is also set, if not already, at the completion of a
2659 port reset when ResetStatusChange is set or port suspend when
2660 SuspendStatusChange is set.
2661 0 = port is disabled
2663 (write) SetPortEnable. The HCD sets PortEnableStatus by writing a '1'.
2664 Writing a '0' has no effect. If CurrentConnectStatus is cleared, this
2665 write does not set PortEnableStatus, but instead sets ConnectStatusChange.
2666 This informs the driver that it attempted to enable a disconnected port. */
2667 uint32_t ccs : 1; /**< (read) CurrentConnectStatus. This bit reflects the current state of the
2669 0 = no device connected
2670 1 = device connected
2671 (write) ClearPortEnable.
2672 The HCD writes a '1' to this bit to clear the PortEnableStatus bit.
2673 Writing a '0' has no effect. The CurrentConnectStatus is not
2674 affected by any write.
2675 Note: This bit is always read '1b' when the attached device is
2676 nonremovable (DeviceRemoveable[NDP]). */
2683 uint32_t reserved_5_7 : 3;
2686 uint32_t reserved_10_15 : 6;
2692 uint32_t reserved_21_31 : 11;
2695 struct cvmx_uahcx_ohci0_hcrhportstatusx_s cn61xx;
2696 struct cvmx_uahcx_ohci0_hcrhportstatusx_s cn63xx;
2697 struct cvmx_uahcx_ohci0_hcrhportstatusx_s cn63xxp1;
2698 struct cvmx_uahcx_ohci0_hcrhportstatusx_s cn66xx;
2699 struct cvmx_uahcx_ohci0_hcrhportstatusx_s cn68xx;
2700 struct cvmx_uahcx_ohci0_hcrhportstatusx_s cn68xxp1;
2701 struct cvmx_uahcx_ohci0_hcrhportstatusx_s cnf71xx;
2703 typedef union cvmx_uahcx_ohci0_hcrhportstatusx cvmx_uahcx_ohci0_hcrhportstatusx_t;
2706 * cvmx_uahc#_ohci0_hcrhstatus
2708 * HCRHSTATUS = Host Controller Root Hub Status Register
2710 * The HcRhStatus register is divided into two parts. The lower word of a Dword represents the Hub Status field and the upper word represents the Hub
2711 * Status Change field. Reserved bits should always be written '0'.
2713 union cvmx_uahcx_ohci0_hcrhstatus {
2715 struct cvmx_uahcx_ohci0_hcrhstatus_s {
2716 #ifdef __BIG_ENDIAN_BITFIELD
2717 uint32_t crwe : 1; /**< (write) ClearRemoteWakeupEnable Writing a '1' clears DeviceRemoveWakeupEnable.
2718 Writing a '0' has no effect. */
2719 uint32_t reserved_18_30 : 13;
2720 uint32_t ccic : 1; /**< OverCurrentIndicatorChange. This bit is set by hardware when a change has
2721 occurred to the OCI field of this register. The HCD clears this bit by
2722 writing a '1'. Writing a '0' has no effect. */
2723 uint32_t lpsc : 1; /**< (read) LocalPowerStatusChange. The Root Hub does not support the local power
2724 status feature; thus, this bit is always read as '0'.
2725 (write) SetGlobalPower In global power mode (PowerSwitchingMode=0), This bit
2726 is written to '1' to turn on power to all ports (clear PortPowerStatus).
2727 In per-port power mode, it sets PortPowerStatus only on ports whose
2728 PortPowerControlMask bit is not set. Writing a '0' has no effect. */
2729 uint32_t drwe : 1; /**< (read) DeviceRemoteWakeupEnable. This bit enables a ConnectStatusChange bit as
2730 a resume event, causing a USBSUSPEND to USBRESUME state transition and
2731 setting the ResumeDetected interrupt. 0 = ConnectStatusChange is not a
2732 remote wakeup event. 1 = ConnectStatusChange is a remote wakeup event.
2733 (write) SetRemoteWakeupEnable Writing a '1' sets DeviceRemoveWakeupEnable.
2734 Writing a '0' has no effect. */
2735 uint32_t reserved_2_14 : 13;
2736 uint32_t oci : 1; /**< OverCurrentIndicator. This bit reports overcurrent conditions when the global
2737 reporting is implemented. When set, an overcurrent condition exists. When
2738 cleared, all power operations are normal. If per-port overcurrent protection
2739 is implemented this bit is always '0' */
2740 uint32_t lps : 1; /**< (read) LocalPowerStatus. The Root Hub does not support the local power status
2741 feature; thus, this bit is always read as '0.
2742 (write) ClearGlobalPower. In global power mode (PowerSwitchingMode=0), This
2743 bit is written to '1' to turn off power to all ports
2744 (clear PortPowerStatus). In per-port power mode, it clears
2745 PortPowerStatus only on ports whose PortPowerControlMask bit is not
2746 set. Writing a '0' has no effect. Description */
2750 uint32_t reserved_2_14 : 13;
2754 uint32_t reserved_18_30 : 13;
2758 struct cvmx_uahcx_ohci0_hcrhstatus_s cn61xx;
2759 struct cvmx_uahcx_ohci0_hcrhstatus_s cn63xx;
2760 struct cvmx_uahcx_ohci0_hcrhstatus_s cn63xxp1;
2761 struct cvmx_uahcx_ohci0_hcrhstatus_s cn66xx;
2762 struct cvmx_uahcx_ohci0_hcrhstatus_s cn68xx;
2763 struct cvmx_uahcx_ohci0_hcrhstatus_s cn68xxp1;
2764 struct cvmx_uahcx_ohci0_hcrhstatus_s cnf71xx;
2766 typedef union cvmx_uahcx_ohci0_hcrhstatus cvmx_uahcx_ohci0_hcrhstatus_t;
2769 * cvmx_uahc#_ohci0_insnreg06
2771 * OHCI0_INSNREG06 = OHCI AHB Error Status Register (Synopsys Speicific)
2773 * This register contains AHB Error Status.
2775 union cvmx_uahcx_ohci0_insnreg06 {
2777 struct cvmx_uahcx_ohci0_insnreg06_s {
2778 #ifdef __BIG_ENDIAN_BITFIELD
2779 uint32_t vld : 1; /**< AHB Error Captured. Indicator that an AHB error was encountered and values were captured.
2780 To clear this field the application must write a 0 to it. */
2781 uint32_t reserved_0_30 : 31;
2783 uint32_t reserved_0_30 : 31;
2787 struct cvmx_uahcx_ohci0_insnreg06_s cn61xx;
2788 struct cvmx_uahcx_ohci0_insnreg06_s cn63xx;
2789 struct cvmx_uahcx_ohci0_insnreg06_s cn63xxp1;
2790 struct cvmx_uahcx_ohci0_insnreg06_s cn66xx;
2791 struct cvmx_uahcx_ohci0_insnreg06_s cn68xx;
2792 struct cvmx_uahcx_ohci0_insnreg06_s cn68xxp1;
2793 struct cvmx_uahcx_ohci0_insnreg06_s cnf71xx;
2795 typedef union cvmx_uahcx_ohci0_insnreg06 cvmx_uahcx_ohci0_insnreg06_t;
2798 * cvmx_uahc#_ohci0_insnreg07
2800 * OHCI0_INSNREG07 = OHCI AHB Error Address Register (Synopsys Speicific)
2802 * This register contains AHB Error Status.
2804 union cvmx_uahcx_ohci0_insnreg07 {
2806 struct cvmx_uahcx_ohci0_insnreg07_s {
2807 #ifdef __BIG_ENDIAN_BITFIELD
2808 uint32_t err_addr : 32; /**< AHB Master Error Address. AHB address of the control phase at which the AHB error occurred */
2810 uint32_t err_addr : 32;
2813 struct cvmx_uahcx_ohci0_insnreg07_s cn61xx;
2814 struct cvmx_uahcx_ohci0_insnreg07_s cn63xx;
2815 struct cvmx_uahcx_ohci0_insnreg07_s cn63xxp1;
2816 struct cvmx_uahcx_ohci0_insnreg07_s cn66xx;
2817 struct cvmx_uahcx_ohci0_insnreg07_s cn68xx;
2818 struct cvmx_uahcx_ohci0_insnreg07_s cn68xxp1;
2819 struct cvmx_uahcx_ohci0_insnreg07_s cnf71xx;
2821 typedef union cvmx_uahcx_ohci0_insnreg07 cvmx_uahcx_ohci0_insnreg07_t;
projects / FreeBSD / releng / 10.0.git / blob