2 * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/module.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
36 #include <sys/endian.h>
37 #include <sys/malloc.h>
39 #include <sys/mutex.h>
40 #include <machine/stdarg.h>
41 #include <machine/resource.h>
42 #include <machine/bus.h>
44 #include <dev/pci/pcivar.h>
45 #include <dev/pci/pcireg.h>
49 #include <cam/cam_ccb.h>
50 #include <cam/cam_sim.h>
51 #include <cam/cam_xpt_sim.h>
52 #include <cam/cam_debug.h>
54 /* local prototypes */
55 static int ahci_setup_interrupt(device_t dev);
56 static void ahci_intr(void *data);
57 static void ahci_intr_one(void *data);
58 static int ahci_suspend(device_t dev);
59 static int ahci_resume(device_t dev);
60 static int ahci_ch_init(device_t dev);
61 static int ahci_ch_deinit(device_t dev);
62 static int ahci_ch_suspend(device_t dev);
63 static int ahci_ch_resume(device_t dev);
64 static void ahci_ch_pm(void *arg);
65 static void ahci_ch_intr_locked(void *data);
66 static void ahci_ch_intr(void *data);
67 static int ahci_ctlr_reset(device_t dev);
68 static int ahci_ctlr_setup(device_t dev);
69 static void ahci_begin_transaction(device_t dev, union ccb *ccb);
70 static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error);
71 static void ahci_execute_transaction(struct ahci_slot *slot);
72 static void ahci_timeout(struct ahci_slot *slot);
73 static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et);
74 static int ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag);
75 static void ahci_dmainit(device_t dev);
76 static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
77 static void ahci_dmafini(device_t dev);
78 static void ahci_slotsalloc(device_t dev);
79 static void ahci_slotsfree(device_t dev);
80 static void ahci_reset(device_t dev);
81 static void ahci_start(device_t dev, int fbs);
82 static void ahci_stop(device_t dev);
83 static void ahci_clo(device_t dev);
84 static void ahci_start_fr(device_t dev);
85 static void ahci_stop_fr(device_t dev);
87 static int ahci_sata_connect(struct ahci_channel *ch);
88 static int ahci_sata_phy_reset(device_t dev);
89 static int ahci_wait_ready(device_t dev, int t, int t0);
91 static void ahci_issue_recovery(device_t dev);
92 static void ahci_process_read_log(device_t dev, union ccb *ccb);
93 static void ahci_process_request_sense(device_t dev, union ccb *ccb);
95 static void ahciaction(struct cam_sim *sim, union ccb *ccb);
96 static void ahcipoll(struct cam_sim *sim);
98 static MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers");
105 #define AHCI_Q_NOFORCE 1
106 #define AHCI_Q_NOPMP 2
107 #define AHCI_Q_NONCQ 4
109 #define AHCI_Q_2CH 16
110 #define AHCI_Q_4CH 32
111 #define AHCI_Q_EDGEIS 64
112 #define AHCI_Q_SATA2 128
113 #define AHCI_Q_NOBSYRES 256
114 #define AHCI_Q_NOAA 512
115 #define AHCI_Q_NOCOUNT 1024
116 #define AHCI_Q_ALTSIG 2048
117 #define AHCI_Q_NOMSI 4096
119 #define AHCI_Q_BIT_STRING \
135 {0x43801002, 0x00, "ATI IXP600", AHCI_Q_NOMSI},
136 {0x43901002, 0x00, "ATI IXP700", 0},
137 {0x43911002, 0x00, "ATI IXP700", 0},
138 {0x43921002, 0x00, "ATI IXP700", 0},
139 {0x43931002, 0x00, "ATI IXP700", 0},
140 {0x43941002, 0x00, "ATI IXP800", 0},
141 {0x43951002, 0x00, "ATI IXP800", 0},
142 {0x78001022, 0x00, "AMD Hudson-2", 0},
143 {0x78011022, 0x00, "AMD Hudson-2", 0},
144 {0x78021022, 0x00, "AMD Hudson-2", 0},
145 {0x78031022, 0x00, "AMD Hudson-2", 0},
146 {0x78041022, 0x00, "AMD Hudson-2", 0},
147 {0x06121b21, 0x00, "ASMedia ASM1061", 0},
148 {0x26528086, 0x00, "Intel ICH6", AHCI_Q_NOFORCE},
149 {0x26538086, 0x00, "Intel ICH6M", AHCI_Q_NOFORCE},
150 {0x26818086, 0x00, "Intel ESB2", 0},
151 {0x26828086, 0x00, "Intel ESB2", 0},
152 {0x26838086, 0x00, "Intel ESB2", 0},
153 {0x27c18086, 0x00, "Intel ICH7", 0},
154 {0x27c38086, 0x00, "Intel ICH7", 0},
155 {0x27c58086, 0x00, "Intel ICH7M", 0},
156 {0x27c68086, 0x00, "Intel ICH7M", 0},
157 {0x28218086, 0x00, "Intel ICH8", 0},
158 {0x28228086, 0x00, "Intel ICH8", 0},
159 {0x28248086, 0x00, "Intel ICH8", 0},
160 {0x28298086, 0x00, "Intel ICH8M", 0},
161 {0x282a8086, 0x00, "Intel ICH8M", 0},
162 {0x29228086, 0x00, "Intel ICH9", 0},
163 {0x29238086, 0x00, "Intel ICH9", 0},
164 {0x29248086, 0x00, "Intel ICH9", 0},
165 {0x29258086, 0x00, "Intel ICH9", 0},
166 {0x29278086, 0x00, "Intel ICH9", 0},
167 {0x29298086, 0x00, "Intel ICH9M", 0},
168 {0x292a8086, 0x00, "Intel ICH9M", 0},
169 {0x292b8086, 0x00, "Intel ICH9M", 0},
170 {0x292c8086, 0x00, "Intel ICH9M", 0},
171 {0x292f8086, 0x00, "Intel ICH9M", 0},
172 {0x294d8086, 0x00, "Intel ICH9", 0},
173 {0x294e8086, 0x00, "Intel ICH9M", 0},
174 {0x3a058086, 0x00, "Intel ICH10", 0},
175 {0x3a228086, 0x00, "Intel ICH10", 0},
176 {0x3a258086, 0x00, "Intel ICH10", 0},
177 {0x3b228086, 0x00, "Intel 5 Series/3400 Series", 0},
178 {0x3b238086, 0x00, "Intel 5 Series/3400 Series", 0},
179 {0x3b258086, 0x00, "Intel 5 Series/3400 Series", 0},
180 {0x3b298086, 0x00, "Intel 5 Series/3400 Series", 0},
181 {0x3b2c8086, 0x00, "Intel 5 Series/3400 Series", 0},
182 {0x3b2f8086, 0x00, "Intel 5 Series/3400 Series", 0},
183 {0x1c028086, 0x00, "Intel Cougar Point", 0},
184 {0x1c038086, 0x00, "Intel Cougar Point", 0},
185 {0x1c048086, 0x00, "Intel Cougar Point", 0},
186 {0x1c058086, 0x00, "Intel Cougar Point", 0},
187 {0x1d028086, 0x00, "Intel Patsburg", 0},
188 {0x1d048086, 0x00, "Intel Patsburg", 0},
189 {0x1d068086, 0x00, "Intel Patsburg", 0},
190 {0x28268086, 0x00, "Intel Patsburg (RAID)", 0},
191 {0x1e028086, 0x00, "Intel Panther Point", 0},
192 {0x1e038086, 0x00, "Intel Panther Point", 0},
193 {0x1e048086, 0x00, "Intel Panther Point", 0},
194 {0x1e058086, 0x00, "Intel Panther Point", 0},
195 {0x1e068086, 0x00, "Intel Panther Point", 0},
196 {0x1e078086, 0x00, "Intel Panther Point", 0},
197 {0x1e0e8086, 0x00, "Intel Panther Point", 0},
198 {0x1e0f8086, 0x00, "Intel Panther Point", 0},
199 {0x23a38086, 0x00, "Intel Coleto Creek", 0},
200 {0x8c028086, 0x00, "Intel Lynx Point", 0},
201 {0x8c038086, 0x00, "Intel Lynx Point", 0},
202 {0x8c048086, 0x00, "Intel Lynx Point", 0},
203 {0x8c058086, 0x00, "Intel Lynx Point", 0},
204 {0x8c068086, 0x00, "Intel Lynx Point", 0},
205 {0x8c078086, 0x00, "Intel Lynx Point", 0},
206 {0x8c0e8086, 0x00, "Intel Lynx Point", 0},
207 {0x8c0f8086, 0x00, "Intel Lynx Point", 0},
208 {0x23238086, 0x00, "Intel DH89xxCC", 0},
209 {0x2360197b, 0x00, "JMicron JMB360", 0},
210 {0x2361197b, 0x00, "JMicron JMB361", AHCI_Q_NOFORCE},
211 {0x2362197b, 0x00, "JMicron JMB362", 0},
212 {0x2363197b, 0x00, "JMicron JMB363", AHCI_Q_NOFORCE},
213 {0x2365197b, 0x00, "JMicron JMB365", AHCI_Q_NOFORCE},
214 {0x2366197b, 0x00, "JMicron JMB366", AHCI_Q_NOFORCE},
215 {0x2368197b, 0x00, "JMicron JMB368", AHCI_Q_NOFORCE},
216 {0x611111ab, 0x00, "Marvell 88SE6111", AHCI_Q_NOFORCE | AHCI_Q_1CH |
218 {0x612111ab, 0x00, "Marvell 88SE6121", AHCI_Q_NOFORCE | AHCI_Q_2CH |
219 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT},
220 {0x614111ab, 0x00, "Marvell 88SE6141", AHCI_Q_NOFORCE | AHCI_Q_4CH |
221 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT},
222 {0x614511ab, 0x00, "Marvell 88SE6145", AHCI_Q_NOFORCE | AHCI_Q_4CH |
223 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT},
224 {0x91201b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_NOBSYRES},
225 {0x91231b4b, 0x11, "Marvell 88SE912x", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG},
226 {0x91231b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_SATA2|AHCI_Q_NOBSYRES},
227 {0x91251b4b, 0x00, "Marvell 88SE9125", AHCI_Q_NOBSYRES},
228 {0x91281b4b, 0x00, "Marvell 88SE9128", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG},
229 {0x91301b4b, 0x00, "Marvell 88SE9130", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG},
230 {0x91721b4b, 0x00, "Marvell 88SE9172", AHCI_Q_NOBSYRES},
231 {0x91821b4b, 0x00, "Marvell 88SE9182", AHCI_Q_NOBSYRES},
232 {0x91831b4b, 0x00, "Marvell 88SS9183", AHCI_Q_NOBSYRES},
233 {0x91a01b4b, 0x00, "Marvell 88SE91Ax", AHCI_Q_NOBSYRES},
234 {0x92151b4b, 0x00, "Marvell 88SE9215", AHCI_Q_NOBSYRES},
235 {0x92201b4b, 0x00, "Marvell 88SE9220", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG},
236 {0x92301b4b, 0x00, "Marvell 88SE9230", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG},
237 {0x92351b4b, 0x00, "Marvell 88SE9235", AHCI_Q_NOBSYRES},
238 {0x06201103, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES},
239 {0x06201b4b, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES},
240 {0x06221103, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES},
241 {0x06221b4b, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES},
242 {0x06401103, 0x00, "HighPoint RocketRAID 640", AHCI_Q_NOBSYRES},
243 {0x06401b4b, 0x00, "HighPoint RocketRAID 640", AHCI_Q_NOBSYRES},
244 {0x06441103, 0x00, "HighPoint RocketRAID 644", AHCI_Q_NOBSYRES},
245 {0x06441b4b, 0x00, "HighPoint RocketRAID 644", AHCI_Q_NOBSYRES},
246 {0x06411103, 0x00, "HighPoint RocketRAID 640L", AHCI_Q_NOBSYRES},
247 {0x06421103, 0x00, "HighPoint RocketRAID 642L", AHCI_Q_NOBSYRES},
248 {0x06451103, 0x00, "HighPoint RocketRAID 644L", AHCI_Q_NOBSYRES},
249 {0x044c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
250 {0x044d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
251 {0x044e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
252 {0x044f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
253 {0x045c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
254 {0x045d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
255 {0x045e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
256 {0x045f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
257 {0x055010de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
258 {0x055110de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
259 {0x055210de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
260 {0x055310de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
261 {0x055410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
262 {0x055510de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
263 {0x055610de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
264 {0x055710de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
265 {0x055810de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
266 {0x055910de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
267 {0x055A10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
268 {0x055B10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
269 {0x058410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
270 {0x07f010de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
271 {0x07f110de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
272 {0x07f210de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
273 {0x07f310de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
274 {0x07f410de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
275 {0x07f510de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
276 {0x07f610de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
277 {0x07f710de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
278 {0x07f810de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
279 {0x07f910de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
280 {0x07fa10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
281 {0x07fb10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
282 {0x0ad010de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
283 {0x0ad110de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
284 {0x0ad210de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
285 {0x0ad310de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
286 {0x0ad410de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
287 {0x0ad510de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
288 {0x0ad610de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
289 {0x0ad710de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
290 {0x0ad810de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
291 {0x0ad910de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
292 {0x0ada10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
293 {0x0adb10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
294 {0x0ab410de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
295 {0x0ab510de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
296 {0x0ab610de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
297 {0x0ab710de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
298 {0x0ab810de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
299 {0x0ab910de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
300 {0x0aba10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
301 {0x0abb10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
302 {0x0abc10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
303 {0x0abd10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
304 {0x0abe10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
305 {0x0abf10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
306 {0x0d8410de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
307 {0x0d8510de, 0x00, "NVIDIA MCP89", AHCI_Q_NOFORCE|AHCI_Q_NOAA},
308 {0x0d8610de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
309 {0x0d8710de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
310 {0x0d8810de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
311 {0x0d8910de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
312 {0x0d8a10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
313 {0x0d8b10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
314 {0x0d8c10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
315 {0x0d8d10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
316 {0x0d8e10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
317 {0x0d8f10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
318 {0x33491106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ},
319 {0x62871106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ},
320 {0x11841039, 0x00, "SiS 966", 0},
321 {0x11851039, 0x00, "SiS 968", 0},
322 {0x01861039, 0x00, "SiS 968", 0},
323 {0x00000000, 0x00, NULL, 0}
326 #define recovery_type spriv_field0
327 #define RECOVERY_NONE 0
328 #define RECOVERY_READ_LOG 1
329 #define RECOVERY_REQUEST_SENSE 2
330 #define recovery_slot spriv_field1
332 static int force_ahci = 1;
333 TUNABLE_INT("hw.ahci.force", &force_ahci);
336 ahci_probe(device_t dev)
340 uint32_t devid = pci_get_devid(dev);
341 uint8_t revid = pci_get_revid(dev);
343 /* Is this a possible AHCI candidate? */
344 if (pci_get_class(dev) == PCIC_STORAGE &&
345 pci_get_subclass(dev) == PCIS_STORAGE_SATA &&
346 pci_get_progif(dev) == PCIP_STORAGE_SATA_AHCI_1_0)
348 /* Is this a known AHCI chip? */
349 for (i = 0; ahci_ids[i].id != 0; i++) {
350 if (ahci_ids[i].id == devid &&
351 ahci_ids[i].rev <= revid &&
352 (valid || (force_ahci == 1 &&
353 !(ahci_ids[i].quirks & AHCI_Q_NOFORCE)))) {
354 /* Do not attach JMicrons with single PCI function. */
355 if (pci_get_vendor(dev) == 0x197b &&
356 (pci_read_config(dev, 0xdf, 1) & 0x40) == 0)
358 snprintf(buf, sizeof(buf), "%s AHCI SATA controller",
360 device_set_desc_copy(dev, buf);
361 return (BUS_PROBE_VENDOR);
366 device_set_desc_copy(dev, "AHCI SATA controller");
367 return (BUS_PROBE_VENDOR);
371 ahci_ata_probe(device_t dev)
375 uint32_t devid = pci_get_devid(dev);
376 uint8_t revid = pci_get_revid(dev);
378 if ((intptr_t)device_get_ivars(dev) >= 0)
380 /* Is this a known AHCI chip? */
381 for (i = 0; ahci_ids[i].id != 0; i++) {
382 if (ahci_ids[i].id == devid &&
383 ahci_ids[i].rev <= revid) {
384 snprintf(buf, sizeof(buf), "%s AHCI SATA controller",
386 device_set_desc_copy(dev, buf);
387 return (BUS_PROBE_VENDOR);
390 device_set_desc_copy(dev, "AHCI SATA controller");
391 return (BUS_PROBE_VENDOR);
395 ahci_attach(device_t dev)
397 struct ahci_controller *ctlr = device_get_softc(dev);
399 int error, unit, speed, i;
400 uint32_t devid = pci_get_devid(dev);
401 uint8_t revid = pci_get_revid(dev);
406 while (ahci_ids[i].id != 0 &&
407 (ahci_ids[i].id != devid ||
408 ahci_ids[i].rev > revid))
410 ctlr->quirks = ahci_ids[i].quirks;
411 resource_int_value(device_get_name(dev),
412 device_get_unit(dev), "ccc", &ctlr->ccc);
413 /* if we have a memory BAR(5) we are likely on an AHCI part */
414 ctlr->r_rid = PCIR_BAR(5);
415 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
416 &ctlr->r_rid, RF_ACTIVE)))
418 /* Setup our own memory management for channels. */
419 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem);
420 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem);
421 ctlr->sc_iomem.rm_type = RMAN_ARRAY;
422 ctlr->sc_iomem.rm_descr = "I/O memory addresses";
423 if ((error = rman_init(&ctlr->sc_iomem)) != 0) {
424 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
427 if ((error = rman_manage_region(&ctlr->sc_iomem,
428 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) {
429 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
430 rman_fini(&ctlr->sc_iomem);
433 pci_enable_busmaster(dev);
434 /* Reset controller */
435 if ((error = ahci_ctlr_reset(dev)) != 0) {
436 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
437 rman_fini(&ctlr->sc_iomem);
440 /* Get the HW capabilities */
441 version = ATA_INL(ctlr->r_mem, AHCI_VS);
442 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP);
443 if (version >= 0x00010200)
444 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2);
445 if (ctlr->caps & AHCI_CAP_EMS)
446 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL);
447 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI);
449 /* Identify and set separate quirks for HBA and RAID f/w Marvells. */
450 if ((ctlr->quirks & AHCI_Q_NOBSYRES) &&
451 (ctlr->quirks & AHCI_Q_ALTSIG) &&
452 (ctlr->caps & AHCI_CAP_SPM) == 0)
453 ctlr->quirks &= ~AHCI_Q_NOBSYRES;
455 if (ctlr->quirks & AHCI_Q_1CH) {
456 ctlr->caps &= ~AHCI_CAP_NPMASK;
457 ctlr->ichannels &= 0x01;
459 if (ctlr->quirks & AHCI_Q_2CH) {
460 ctlr->caps &= ~AHCI_CAP_NPMASK;
462 ctlr->ichannels &= 0x03;
464 if (ctlr->quirks & AHCI_Q_4CH) {
465 ctlr->caps &= ~AHCI_CAP_NPMASK;
467 ctlr->ichannels &= 0x0f;
469 ctlr->channels = MAX(flsl(ctlr->ichannels),
470 (ctlr->caps & AHCI_CAP_NPMASK) + 1);
471 if (ctlr->quirks & AHCI_Q_NOPMP)
472 ctlr->caps &= ~AHCI_CAP_SPM;
473 if (ctlr->quirks & AHCI_Q_NONCQ)
474 ctlr->caps &= ~AHCI_CAP_SNCQ;
475 if ((ctlr->caps & AHCI_CAP_CCCS) == 0)
477 ctlr->emloc = ATA_INL(ctlr->r_mem, AHCI_EM_LOC);
479 /* Create controller-wide DMA tag. */
480 if (bus_dma_tag_create(bus_get_dma_tag(dev), 0, 0,
481 (ctlr->caps & AHCI_CAP_64BIT) ? BUS_SPACE_MAXADDR :
482 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
483 BUS_SPACE_MAXSIZE, BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE,
484 0, NULL, NULL, &ctlr->dma_tag)) {
485 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid,
487 rman_fini(&ctlr->sc_iomem);
491 ahci_ctlr_setup(dev);
492 /* Setup interrupts. */
493 if (ahci_setup_interrupt(dev)) {
494 bus_dma_tag_destroy(ctlr->dma_tag);
495 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
496 rman_fini(&ctlr->sc_iomem);
499 /* Announce HW capabilities. */
500 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT;
502 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s%s\n",
503 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f),
504 ((version >> 4) & 0xf0) + (version & 0x0f),
505 (ctlr->caps & AHCI_CAP_NPMASK) + 1,
506 ((speed == 1) ? "1.5":((speed == 2) ? "3":
507 ((speed == 3) ? "6":"?"))),
508 (ctlr->caps & AHCI_CAP_SPM) ?
509 "supported" : "not supported",
510 (ctlr->caps & AHCI_CAP_FBSS) ?
512 if (ctlr->quirks != 0) {
513 device_printf(dev, "quirks=0x%b\n", ctlr->quirks,
517 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps",
518 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"",
519 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"",
520 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"",
521 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"",
522 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"",
523 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"",
524 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"",
525 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"",
526 ((speed == 1) ? "1.5":((speed == 2) ? "3":
527 ((speed == 3) ? "6":"?"))));
528 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n",
529 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"",
530 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"",
531 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"",
532 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"",
533 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"",
534 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"",
535 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1,
536 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"",
537 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"",
538 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"",
539 (ctlr->caps & AHCI_CAP_NPMASK) + 1);
541 if (bootverbose && version >= 0x00010200) {
542 device_printf(dev, "Caps2:%s%s%s%s%s%s\n",
543 (ctlr->caps2 & AHCI_CAP2_DESO) ? " DESO":"",
544 (ctlr->caps2 & AHCI_CAP2_SADM) ? " SADM":"",
545 (ctlr->caps2 & AHCI_CAP2_SDS) ? " SDS":"",
546 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"",
547 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"",
548 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":"");
550 /* Attach all channels on this controller */
551 for (unit = 0; unit < ctlr->channels; unit++) {
552 child = device_add_child(dev, "ahcich", -1);
554 device_printf(dev, "failed to add channel device\n");
557 device_set_ivars(child, (void *)(intptr_t)unit);
558 if ((ctlr->ichannels & (1 << unit)) == 0)
559 device_disable(child);
561 if (ctlr->caps & AHCI_CAP_EMS) {
562 child = device_add_child(dev, "ahciem", -1);
564 device_printf(dev, "failed to add enclosure device\n");
566 device_set_ivars(child, (void *)(intptr_t)-1);
568 bus_generic_attach(dev);
573 ahci_detach(device_t dev)
575 struct ahci_controller *ctlr = device_get_softc(dev);
578 /* Detach & delete all children */
579 device_delete_children(dev);
581 /* Free interrupts. */
582 for (i = 0; i < ctlr->numirqs; i++) {
583 if (ctlr->irqs[i].r_irq) {
584 bus_teardown_intr(dev, ctlr->irqs[i].r_irq,
585 ctlr->irqs[i].handle);
586 bus_release_resource(dev, SYS_RES_IRQ,
587 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq);
590 pci_release_msi(dev);
591 bus_dma_tag_destroy(ctlr->dma_tag);
593 rman_fini(&ctlr->sc_iomem);
595 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
600 ahci_ctlr_reset(device_t dev)
602 struct ahci_controller *ctlr = device_get_softc(dev);
605 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == 0x28298086 &&
606 (pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04)
607 pci_write_config(dev, 0x92, 0x01, 1);
608 /* Enable AHCI mode */
609 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
610 /* Reset AHCI controller */
611 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR);
612 for (timeout = 1000; timeout > 0; timeout--) {
614 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0)
618 device_printf(dev, "AHCI controller reset failure\n");
621 /* Reenable AHCI mode */
622 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
627 ahci_ctlr_setup(device_t dev)
629 struct ahci_controller *ctlr = device_get_softc(dev);
630 /* Clear interrupts */
631 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS));
634 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI));
635 ATA_OUTL(ctlr->r_mem, AHCI_CCCC,
636 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) |
637 (4 << AHCI_CCCC_CC_SHIFT) |
639 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) &
640 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT;
643 "CCC with %dms/4cmd enabled on vector %d\n",
644 ctlr->ccc, ctlr->cccv);
647 /* Enable AHCI interrupts */
648 ATA_OUTL(ctlr->r_mem, AHCI_GHC,
649 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE);
654 ahci_suspend(device_t dev)
656 struct ahci_controller *ctlr = device_get_softc(dev);
658 bus_generic_suspend(dev);
659 /* Disable interupts, so the state change(s) doesn't trigger */
660 ATA_OUTL(ctlr->r_mem, AHCI_GHC,
661 ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE));
666 ahci_resume(device_t dev)
670 if ((res = ahci_ctlr_reset(dev)) != 0)
672 ahci_ctlr_setup(dev);
673 return (bus_generic_resume(dev));
677 ahci_setup_interrupt(device_t dev)
679 struct ahci_controller *ctlr = device_get_softc(dev);
683 if (ctlr->quirks & AHCI_Q_NOMSI)
685 resource_int_value(device_get_name(dev),
686 device_get_unit(dev), "msi", &msi);
690 msi = min(1, pci_msi_count(dev));
692 msi = pci_msi_count(dev);
693 /* Allocate MSI if needed/present. */
694 if (msi && pci_alloc_msi(dev, &msi) == 0) {
700 /* Check for single MSI vector fallback. */
701 if (ctlr->numirqs > 1 &&
702 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) {
703 device_printf(dev, "Falling back to one MSI\n");
706 /* Allocate all IRQs. */
707 for (i = 0; i < ctlr->numirqs; i++) {
708 ctlr->irqs[i].ctlr = ctlr;
709 ctlr->irqs[i].r_irq_rid = i + (msi ? 1 : 0);
710 if (ctlr->numirqs == 1 || i >= ctlr->channels ||
711 (ctlr->ccc && i == ctlr->cccv))
712 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL;
713 else if (i == ctlr->numirqs - 1)
714 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER;
716 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE;
717 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
718 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) {
719 device_printf(dev, "unable to map interrupt\n");
722 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL,
723 (ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE) ? ahci_intr_one : ahci_intr,
724 &ctlr->irqs[i], &ctlr->irqs[i].handle))) {
725 /* SOS XXX release r_irq */
726 device_printf(dev, "unable to setup interrupt\n");
729 if (ctlr->numirqs > 1) {
730 bus_describe_intr(dev, ctlr->irqs[i].r_irq,
731 ctlr->irqs[i].handle,
732 ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ?
740 * Common case interrupt handler.
743 ahci_intr(void *data)
745 struct ahci_controller_irq *irq = data;
746 struct ahci_controller *ctlr = irq->ctlr;
747 u_int32_t is, ise = 0;
751 if (irq->mode == AHCI_IRQ_MODE_ALL) {
754 is = ctlr->ichannels;
756 is = ATA_INL(ctlr->r_mem, AHCI_IS);
757 } else { /* AHCI_IRQ_MODE_AFTER */
758 unit = irq->r_irq_rid - 1;
759 is = ATA_INL(ctlr->r_mem, AHCI_IS);
761 /* CCC interrupt is edge triggered. */
763 ise = 1 << ctlr->cccv;
764 /* Some controllers have edge triggered IS. */
765 if (ctlr->quirks & AHCI_Q_EDGEIS)
768 ATA_OUTL(ctlr->r_mem, AHCI_IS, ise);
769 for (; unit < ctlr->channels; unit++) {
770 if ((is & (1 << unit)) != 0 &&
771 (arg = ctlr->interrupt[unit].argument)) {
772 ctlr->interrupt[unit].function(arg);
775 /* AHCI declares level triggered IS. */
776 if (!(ctlr->quirks & AHCI_Q_EDGEIS))
777 ATA_OUTL(ctlr->r_mem, AHCI_IS, is);
781 * Simplified interrupt handler for multivector MSI mode.
784 ahci_intr_one(void *data)
786 struct ahci_controller_irq *irq = data;
787 struct ahci_controller *ctlr = irq->ctlr;
791 unit = irq->r_irq_rid - 1;
792 /* Some controllers have edge triggered IS. */
793 if (ctlr->quirks & AHCI_Q_EDGEIS)
794 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
795 if ((arg = ctlr->interrupt[unit].argument))
796 ctlr->interrupt[unit].function(arg);
797 /* AHCI declares level triggered IS. */
798 if (!(ctlr->quirks & AHCI_Q_EDGEIS))
799 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
802 static struct resource *
803 ahci_alloc_resource(device_t dev, device_t child, int type, int *rid,
804 u_long start, u_long end, u_long count, u_int flags)
806 struct ahci_controller *ctlr = device_get_softc(dev);
807 struct resource *res;
809 int offset, size, unit;
811 unit = (intptr_t)device_get_ivars(child);
816 offset = AHCI_OFFSET + (unit << 7);
818 } else if (*rid == 0) {
819 offset = AHCI_EM_CTL;
822 offset = (ctlr->emloc & 0xffff0000) >> 14;
823 size = (ctlr->emloc & 0x0000ffff) << 2;
825 if (*rid == 2 && (ctlr->capsem &
826 (AHCI_EM_XMT | AHCI_EM_SMB)) == 0)
832 st = rman_get_start(ctlr->r_mem);
833 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset,
834 st + offset + size - 1, size, RF_ACTIVE, child);
836 bus_space_handle_t bsh;
838 bsh = rman_get_bushandle(ctlr->r_mem);
839 bst = rman_get_bustag(ctlr->r_mem);
840 bus_space_subregion(bst, bsh, offset, 128, &bsh);
841 rman_set_bushandle(res, bsh);
842 rman_set_bustag(res, bst);
846 if (*rid == ATA_IRQ_RID)
847 res = ctlr->irqs[0].r_irq;
854 ahci_release_resource(device_t dev, device_t child, int type, int rid,
860 rman_release_resource(r);
863 if (rid != ATA_IRQ_RID)
871 ahci_setup_intr(device_t dev, device_t child, struct resource *irq,
872 int flags, driver_filter_t *filter, driver_intr_t *function,
873 void *argument, void **cookiep)
875 struct ahci_controller *ctlr = device_get_softc(dev);
876 int unit = (intptr_t)device_get_ivars(child);
878 if (filter != NULL) {
879 printf("ahci.c: we cannot use a filter here\n");
882 ctlr->interrupt[unit].function = function;
883 ctlr->interrupt[unit].argument = argument;
888 ahci_teardown_intr(device_t dev, device_t child, struct resource *irq,
891 struct ahci_controller *ctlr = device_get_softc(dev);
892 int unit = (intptr_t)device_get_ivars(child);
894 ctlr->interrupt[unit].function = NULL;
895 ctlr->interrupt[unit].argument = NULL;
900 ahci_print_child(device_t dev, device_t child)
904 retval = bus_print_child_header(dev, child);
905 channel = (int)(intptr_t)device_get_ivars(child);
907 retval += printf(" at channel %d", channel);
908 retval += bus_print_child_footer(dev, child);
913 ahci_child_location_str(device_t dev, device_t child, char *buf,
918 channel = (int)(intptr_t)device_get_ivars(child);
920 snprintf(buf, buflen, "channel=%d", channel);
925 ahci_get_dma_tag(device_t dev, device_t child)
927 struct ahci_controller *ctlr = device_get_softc(dev);
929 return (ctlr->dma_tag);
932 devclass_t ahci_devclass;
933 static device_method_t ahci_methods[] = {
934 DEVMETHOD(device_probe, ahci_probe),
935 DEVMETHOD(device_attach, ahci_attach),
936 DEVMETHOD(device_detach, ahci_detach),
937 DEVMETHOD(device_suspend, ahci_suspend),
938 DEVMETHOD(device_resume, ahci_resume),
939 DEVMETHOD(bus_print_child, ahci_print_child),
940 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource),
941 DEVMETHOD(bus_release_resource, ahci_release_resource),
942 DEVMETHOD(bus_setup_intr, ahci_setup_intr),
943 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr),
944 DEVMETHOD(bus_child_location_str, ahci_child_location_str),
945 DEVMETHOD(bus_get_dma_tag, ahci_get_dma_tag),
948 static driver_t ahci_driver = {
951 sizeof(struct ahci_controller)
953 DRIVER_MODULE(ahci, pci, ahci_driver, ahci_devclass, 0, 0);
954 static device_method_t ahci_ata_methods[] = {
955 DEVMETHOD(device_probe, ahci_ata_probe),
956 DEVMETHOD(device_attach, ahci_attach),
957 DEVMETHOD(device_detach, ahci_detach),
958 DEVMETHOD(device_suspend, ahci_suspend),
959 DEVMETHOD(device_resume, ahci_resume),
960 DEVMETHOD(bus_print_child, ahci_print_child),
961 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource),
962 DEVMETHOD(bus_release_resource, ahci_release_resource),
963 DEVMETHOD(bus_setup_intr, ahci_setup_intr),
964 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr),
965 DEVMETHOD(bus_child_location_str, ahci_child_location_str),
968 static driver_t ahci_ata_driver = {
971 sizeof(struct ahci_controller)
973 DRIVER_MODULE(ahci, atapci, ahci_ata_driver, ahci_devclass, 0, 0);
974 MODULE_VERSION(ahci, 1);
975 MODULE_DEPEND(ahci, cam, 1, 1, 1);
978 ahci_ch_probe(device_t dev)
981 device_set_desc_copy(dev, "AHCI channel");
986 ahci_ch_attach(device_t dev)
988 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev));
989 struct ahci_channel *ch = device_get_softc(dev);
990 struct cam_devq *devq;
991 int rid, error, i, sata_rev = 0;
995 ch->unit = (intptr_t)device_get_ivars(dev);
996 ch->caps = ctlr->caps;
997 ch->caps2 = ctlr->caps2;
998 ch->quirks = ctlr->quirks;
999 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1;
1000 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF);
1001 resource_int_value(device_get_name(dev),
1002 device_get_unit(dev), "pm_level", &ch->pm_level);
1003 if (ch->pm_level > 3)
1004 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0);
1005 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0);
1006 /* Limit speed for my onboard JMicron external port.
1007 * It is not eSATA really. */
1008 if (pci_get_devid(ctlr->dev) == 0x2363197b &&
1009 pci_get_subvendor(ctlr->dev) == 0x1043 &&
1010 pci_get_subdevice(ctlr->dev) == 0x81e4 &&
1013 if (ch->quirks & AHCI_Q_SATA2)
1015 resource_int_value(device_get_name(dev),
1016 device_get_unit(dev), "sata_rev", &sata_rev);
1017 for (i = 0; i < 16; i++) {
1018 ch->user[i].revision = sata_rev;
1019 ch->user[i].mode = 0;
1020 ch->user[i].bytecount = 8192;
1021 ch->user[i].tags = ch->numslots;
1022 ch->user[i].caps = 0;
1023 ch->curr[i] = ch->user[i];
1025 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ |
1026 CTS_SATA_CAPS_H_APST |
1027 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST;
1029 ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA |
1033 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1037 ahci_slotsalloc(dev);
1041 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1042 &rid, RF_SHAREABLE | RF_ACTIVE))) {
1043 device_printf(dev, "Unable to map interrupt\n");
1047 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL,
1048 ahci_ch_intr_locked, dev, &ch->ih))) {
1049 device_printf(dev, "Unable to setup interrupt\n");
1053 ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD);
1054 version = ATA_INL(ctlr->r_mem, AHCI_VS);
1055 if (version < 0x00010200 && (ctlr->caps & AHCI_CAP_FBSS))
1056 ch->chcaps |= AHCI_P_CMD_FBSCP;
1058 device_printf(dev, "Caps:%s%s%s%s%s\n",
1059 (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"",
1060 (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"",
1061 (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"",
1062 (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"",
1063 (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":"");
1065 /* Create the device queue for our SIM. */
1066 devq = cam_simq_alloc(ch->numslots);
1068 device_printf(dev, "Unable to allocate simq\n");
1072 /* Construct SIM entry */
1073 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch,
1074 device_get_unit(dev), &ch->mtx,
1075 min(2, ch->numslots),
1076 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0,
1078 if (ch->sim == NULL) {
1079 cam_simq_free(devq);
1080 device_printf(dev, "unable to allocate sim\n");
1084 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) {
1085 device_printf(dev, "unable to register xpt bus\n");
1089 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim),
1090 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
1091 device_printf(dev, "unable to create path\n");
1095 if (ch->pm_level > 3) {
1096 callout_reset(&ch->pm_timer,
1097 (ch->pm_level == 4) ? hz / 1000 : hz / 8,
1100 mtx_unlock(&ch->mtx);
1104 xpt_bus_deregister(cam_sim_path(ch->sim));
1106 cam_sim_free(ch->sim, /*free_devq*/TRUE);
1108 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
1110 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
1111 mtx_unlock(&ch->mtx);
1112 mtx_destroy(&ch->mtx);
1117 ahci_ch_detach(device_t dev)
1119 struct ahci_channel *ch = device_get_softc(dev);
1122 xpt_async(AC_LOST_DEVICE, ch->path, NULL);
1123 /* Forget about reset. */
1124 if (ch->resetting) {
1126 xpt_release_simq(ch->sim, TRUE);
1128 xpt_free_path(ch->path);
1129 xpt_bus_deregister(cam_sim_path(ch->sim));
1130 cam_sim_free(ch->sim, /*free_devq*/TRUE);
1131 mtx_unlock(&ch->mtx);
1133 if (ch->pm_level > 3)
1134 callout_drain(&ch->pm_timer);
1135 callout_drain(&ch->reset_timer);
1136 bus_teardown_intr(dev, ch->r_irq, ch->ih);
1137 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
1139 ahci_ch_deinit(dev);
1140 ahci_slotsfree(dev);
1143 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
1144 mtx_destroy(&ch->mtx);
1149 ahci_ch_init(device_t dev)
1151 struct ahci_channel *ch = device_get_softc(dev);
1154 /* Disable port interrupts */
1155 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
1156 /* Setup work areas */
1157 work = ch->dma.work_bus + AHCI_CL_OFFSET;
1158 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff);
1159 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32);
1160 work = ch->dma.rfis_bus;
1161 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff);
1162 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32);
1163 /* Activate the channel and power/spin up device */
1164 ATA_OUTL(ch->r_mem, AHCI_P_CMD,
1165 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD |
1166 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) |
1167 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 )));
1174 ahci_ch_deinit(device_t dev)
1176 struct ahci_channel *ch = device_get_softc(dev);
1178 /* Disable port interrupts. */
1179 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
1180 /* Reset command register. */
1183 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0);
1184 /* Allow everything, including partial and slumber modes. */
1185 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0);
1186 /* Request slumber mode transition and give some time to get there. */
1187 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER);
1190 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE);
1195 ahci_ch_suspend(device_t dev)
1197 struct ahci_channel *ch = device_get_softc(dev);
1200 xpt_freeze_simq(ch->sim, 1);
1201 /* Forget about reset. */
1202 if (ch->resetting) {
1204 callout_stop(&ch->reset_timer);
1205 xpt_release_simq(ch->sim, TRUE);
1208 msleep(ch, &ch->mtx, PRIBIO, "ahcisusp", hz/100);
1209 ahci_ch_deinit(dev);
1210 mtx_unlock(&ch->mtx);
1215 ahci_ch_resume(device_t dev)
1217 struct ahci_channel *ch = device_get_softc(dev);
1222 xpt_release_simq(ch->sim, TRUE);
1223 mtx_unlock(&ch->mtx);
1227 devclass_t ahcich_devclass;
1228 static device_method_t ahcich_methods[] = {
1229 DEVMETHOD(device_probe, ahci_ch_probe),
1230 DEVMETHOD(device_attach, ahci_ch_attach),
1231 DEVMETHOD(device_detach, ahci_ch_detach),
1232 DEVMETHOD(device_suspend, ahci_ch_suspend),
1233 DEVMETHOD(device_resume, ahci_ch_resume),
1236 static driver_t ahcich_driver = {
1239 sizeof(struct ahci_channel)
1241 DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, 0, 0);
1243 struct ahci_dc_cb_args {
1249 ahci_dmainit(device_t dev)
1251 struct ahci_channel *ch = device_get_softc(dev);
1252 struct ahci_dc_cb_args dcba;
1256 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0,
1257 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1258 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE,
1259 0, NULL, NULL, &ch->dma.work_tag))
1261 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work,
1262 BUS_DMA_ZERO, &ch->dma.work_map))
1264 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work,
1265 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) {
1266 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map);
1269 ch->dma.work_bus = dcba.maddr;
1270 /* FIS receive area. */
1271 if (ch->chcaps & AHCI_P_CMD_FBSCP)
1275 if (bus_dma_tag_create(bus_get_dma_tag(dev), rfsize, 0,
1276 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1277 NULL, NULL, rfsize, 1, rfsize,
1278 0, NULL, NULL, &ch->dma.rfis_tag))
1280 if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0,
1283 if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis,
1284 rfsize, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) {
1285 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map);
1288 ch->dma.rfis_bus = dcba.maddr;
1290 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
1291 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1293 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots,
1294 AHCI_SG_ENTRIES, AHCI_PRD_MAX,
1295 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) {
1301 device_printf(dev, "WARNING - DMA initialization failed\n");
1306 ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
1308 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc;
1310 if (!(dcba->error = error))
1311 dcba->maddr = segs[0].ds_addr;
1315 ahci_dmafini(device_t dev)
1317 struct ahci_channel *ch = device_get_softc(dev);
1319 if (ch->dma.data_tag) {
1320 bus_dma_tag_destroy(ch->dma.data_tag);
1321 ch->dma.data_tag = NULL;
1323 if (ch->dma.rfis_bus) {
1324 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map);
1325 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map);
1326 ch->dma.rfis_bus = 0;
1327 ch->dma.rfis_map = NULL;
1328 ch->dma.rfis = NULL;
1330 if (ch->dma.work_bus) {
1331 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map);
1332 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map);
1333 ch->dma.work_bus = 0;
1334 ch->dma.work_map = NULL;
1335 ch->dma.work = NULL;
1337 if (ch->dma.work_tag) {
1338 bus_dma_tag_destroy(ch->dma.work_tag);
1339 ch->dma.work_tag = NULL;
1344 ahci_slotsalloc(device_t dev)
1346 struct ahci_channel *ch = device_get_softc(dev);
1349 /* Alloc and setup command/dma slots */
1350 bzero(ch->slot, sizeof(ch->slot));
1351 for (i = 0; i < ch->numslots; i++) {
1352 struct ahci_slot *slot = &ch->slot[i];
1356 slot->state = AHCI_SLOT_EMPTY;
1358 callout_init_mtx(&slot->timeout, &ch->mtx, 0);
1360 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map))
1361 device_printf(ch->dev, "FAILURE - create data_map\n");
1366 ahci_slotsfree(device_t dev)
1368 struct ahci_channel *ch = device_get_softc(dev);
1371 /* Free all dma slots */
1372 for (i = 0; i < ch->numslots; i++) {
1373 struct ahci_slot *slot = &ch->slot[i];
1375 callout_drain(&slot->timeout);
1376 if (slot->dma.data_map) {
1377 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map);
1378 slot->dma.data_map = NULL;
1384 ahci_phy_check_events(device_t dev, u_int32_t serr)
1386 struct ahci_channel *ch = device_get_softc(dev);
1388 if (((ch->pm_level == 0) && (serr & ATA_SE_PHY_CHANGED)) ||
1389 ((ch->pm_level != 0 || ch->listening) && (serr & ATA_SE_EXCHANGED))) {
1390 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS);
1394 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE)
1395 device_printf(dev, "CONNECT requested\n");
1397 device_printf(dev, "DISCONNECT requested\n");
1400 if ((ccb = xpt_alloc_ccb_nowait()) == NULL)
1402 if (xpt_create_path(&ccb->ccb_h.path, NULL,
1403 cam_sim_path(ch->sim),
1404 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
1415 ahci_cpd_check_events(device_t dev)
1417 struct ahci_channel *ch = device_get_softc(dev);
1421 if (ch->pm_level == 0)
1424 status = ATA_INL(ch->r_mem, AHCI_P_CMD);
1425 if ((status & AHCI_P_CMD_CPD) == 0)
1429 if (status & AHCI_P_CMD_CPS) {
1430 device_printf(dev, "COLD CONNECT requested\n");
1432 device_printf(dev, "COLD DISCONNECT requested\n");
1435 if ((ccb = xpt_alloc_ccb_nowait()) == NULL)
1437 if (xpt_create_path(&ccb->ccb_h.path, NULL, cam_sim_path(ch->sim),
1438 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
1446 ahci_notify_events(device_t dev, u_int32_t status)
1448 struct ahci_channel *ch = device_get_softc(dev);
1449 struct cam_path *dpath;
1452 if (ch->caps & AHCI_CAP_SSNTF)
1453 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status);
1455 device_printf(dev, "SNTF 0x%04x\n", status);
1456 for (i = 0; i < 16; i++) {
1457 if ((status & (1 << i)) == 0)
1459 if (xpt_create_path(&dpath, NULL,
1460 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) {
1461 xpt_async(AC_SCSI_AEN, dpath, NULL);
1462 xpt_free_path(dpath);
1468 ahci_ch_intr_locked(void *data)
1470 device_t dev = (device_t)data;
1471 struct ahci_channel *ch = device_get_softc(dev);
1474 xpt_batch_start(ch->sim);
1476 xpt_batch_done(ch->sim);
1477 mtx_unlock(&ch->mtx);
1481 ahci_ch_pm(void *arg)
1483 device_t dev = (device_t)arg;
1484 struct ahci_channel *ch = device_get_softc(dev);
1487 if (ch->numrslots != 0)
1489 work = ATA_INL(ch->r_mem, AHCI_P_CMD);
1490 if (ch->pm_level == 4)
1491 work |= AHCI_P_CMD_PARTIAL;
1493 work |= AHCI_P_CMD_SLUMBER;
1494 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work);
1498 ahci_ch_intr(void *data)
1500 device_t dev = (device_t)data;
1501 struct ahci_channel *ch = device_get_softc(dev);
1502 uint32_t istatus, cstatus, serr = 0, sntf = 0, ok, err;
1503 enum ahci_err_type et;
1504 int i, ccs, port, reset = 0;
1506 /* Read and clear interrupt statuses. */
1507 istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
1510 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus);
1511 /* Read command statuses. */
1512 if (ch->numtslots != 0)
1513 cstatus = ATA_INL(ch->r_mem, AHCI_P_SACT);
1516 if (ch->numrslots != ch->numtslots)
1517 cstatus |= ATA_INL(ch->r_mem, AHCI_P_CI);
1518 /* Read SNTF in one of possible ways. */
1519 if ((istatus & AHCI_P_IX_SDB) &&
1520 (ch->pm_present || ch->curr[0].atapi != 0)) {
1521 if (ch->caps & AHCI_CAP_SSNTF)
1522 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF);
1523 else if (ch->fbs_enabled) {
1524 u_int8_t *fis = ch->dma.rfis + 0x58;
1526 for (i = 0; i < 16; i++) {
1527 if (fis[1] & 0x80) {
1534 u_int8_t *fis = ch->dma.rfis + 0x58;
1537 sntf = (1 << (fis[1] & 0x0f));
1540 /* Process PHY events */
1541 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF |
1542 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) {
1543 serr = ATA_INL(ch->r_mem, AHCI_P_SERR);
1545 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr);
1546 reset = ahci_phy_check_events(dev, serr);
1549 /* Process cold presence detection events */
1550 if ((istatus & AHCI_P_IX_CPD) && !reset)
1551 ahci_cpd_check_events(dev);
1552 /* Process command errors */
1553 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF |
1554 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) {
1555 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK)
1556 >> AHCI_P_CMD_CCS_SHIFT;
1557 //device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n",
1558 // __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD),
1559 // serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs);
1561 if (ch->fbs_enabled) {
1562 uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS);
1563 if (fbs & AHCI_P_FBS_SDE) {
1564 port = (fbs & AHCI_P_FBS_DWE)
1565 >> AHCI_P_FBS_DWE_SHIFT;
1567 for (i = 0; i < 16; i++) {
1568 if (ch->numrslotspd[i] == 0)
1572 else if (port != i) {
1579 err = ch->rslots & cstatus;
1585 /* Complete all successfull commands. */
1586 ok = ch->rslots & ~cstatus;
1587 for (i = 0; i < ch->numslots; i++) {
1589 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE);
1591 /* On error, complete the rest of commands with error statuses. */
1594 union ccb *fccb = ch->frozen;
1596 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
1597 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
1598 xpt_freeze_devq(fccb->ccb_h.path, 1);
1599 fccb->ccb_h.status |= CAM_DEV_QFRZN;
1603 for (i = 0; i < ch->numslots; i++) {
1604 /* XXX: reqests in loading state. */
1605 if (((err >> i) & 1) == 0)
1608 ch->slot[i].ccb->ccb_h.target_id != port)
1610 if (istatus & AHCI_P_IX_TFE) {
1612 /* Task File Error */
1613 if (ch->numtslotspd[
1614 ch->slot[i].ccb->ccb_h.target_id] == 0) {
1615 /* Untagged operation. */
1619 et = AHCI_ERR_INNOCENT;
1621 /* Tagged operation. */
1628 } else if (istatus & AHCI_P_IX_IF) {
1629 if (ch->numtslots == 0 && i != ccs && port != -2)
1630 et = AHCI_ERR_INNOCENT;
1634 et = AHCI_ERR_INVALID;
1635 ahci_end_transaction(&ch->slot[i], et);
1638 * We can't reinit port if there are some other
1639 * commands active, use resume to complete them.
1641 if (ch->rslots != 0 && !ch->recoverycmd)
1642 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC);
1644 /* Process NOTIFY events */
1646 ahci_notify_events(dev, sntf);
1649 /* Must be called with channel locked. */
1651 ahci_check_collision(device_t dev, union ccb *ccb)
1653 struct ahci_channel *ch = device_get_softc(dev);
1654 int t = ccb->ccb_h.target_id;
1656 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1657 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1658 /* Tagged command while we have no supported tag free. */
1659 if (((~ch->oslots) & (0xffffffff >> (32 -
1660 ch->curr[t].tags))) == 0)
1662 /* If we have FBS */
1663 if (ch->fbs_enabled) {
1664 /* Tagged command while untagged are active. */
1665 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0)
1668 /* Tagged command while untagged are active. */
1669 if (ch->numrslots != 0 && ch->numtslots == 0)
1671 /* Tagged command while tagged to other target is active. */
1672 if (ch->numtslots != 0 &&
1673 ch->taggedtarget != ccb->ccb_h.target_id)
1677 /* If we have FBS */
1678 if (ch->fbs_enabled) {
1679 /* Untagged command while tagged are active. */
1680 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0)
1683 /* Untagged command while tagged are active. */
1684 if (ch->numrslots != 0 && ch->numtslots != 0)
1688 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1689 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) {
1690 /* Atomic command while anything active. */
1691 if (ch->numrslots != 0)
1694 /* We have some atomic command running. */
1695 if (ch->aslots != 0)
1700 /* Must be called with channel locked. */
1702 ahci_begin_transaction(device_t dev, union ccb *ccb)
1704 struct ahci_channel *ch = device_get_softc(dev);
1705 struct ahci_slot *slot;
1708 /* Choose empty slot. */
1709 tags = ch->numslots;
1710 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1711 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA))
1712 tags = ch->curr[ccb->ccb_h.target_id].tags;
1717 if (ch->slot[tag].state == AHCI_SLOT_EMPTY)
1722 /* Occupy chosen slot. */
1723 slot = &ch->slot[tag];
1725 /* Stop PM timer. */
1726 if (ch->numrslots == 0 && ch->pm_level > 3)
1727 callout_stop(&ch->pm_timer);
1728 /* Update channel stats. */
1729 ch->oslots |= (1 << slot->slot);
1731 ch->numrslotspd[ccb->ccb_h.target_id]++;
1732 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1733 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1735 ch->numtslotspd[ccb->ccb_h.target_id]++;
1736 ch->taggedtarget = ccb->ccb_h.target_id;
1738 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1739 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)))
1740 ch->aslots |= (1 << slot->slot);
1741 slot->dma.nsegs = 0;
1742 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1743 slot->state = AHCI_SLOT_LOADING;
1744 bus_dmamap_load_ccb(ch->dma.data_tag, slot->dma.data_map, ccb,
1745 ahci_dmasetprd, slot, 0);
1747 ahci_execute_transaction(slot);
1750 /* Locked by busdma engine. */
1752 ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1754 struct ahci_slot *slot = arg;
1755 struct ahci_channel *ch = device_get_softc(slot->dev);
1756 struct ahci_cmd_tab *ctp;
1757 struct ahci_dma_prd *prd;
1761 device_printf(slot->dev, "DMA load error\n");
1762 ahci_end_transaction(slot, AHCI_ERR_INVALID);
1765 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n"));
1766 /* Get a piece of the workspace for this request */
1767 ctp = (struct ahci_cmd_tab *)
1768 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot));
1769 /* Fill S/G table */
1770 prd = &ctp->prd_tab[0];
1771 for (i = 0; i < nsegs; i++) {
1772 prd[i].dba = htole64(segs[i].ds_addr);
1773 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK);
1775 slot->dma.nsegs = nsegs;
1776 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
1777 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ?
1778 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE));
1779 ahci_execute_transaction(slot);
1782 /* Must be called with channel locked. */
1784 ahci_execute_transaction(struct ahci_slot *slot)
1786 device_t dev = slot->dev;
1787 struct ahci_channel *ch = device_get_softc(dev);
1788 struct ahci_cmd_tab *ctp;
1789 struct ahci_cmd_list *clp;
1790 union ccb *ccb = slot->ccb;
1791 int port = ccb->ccb_h.target_id & 0x0f;
1792 int fis_size, i, softreset;
1793 uint8_t *fis = ch->dma.rfis + 0x40;
1796 /* Get a piece of the workspace for this request */
1797 ctp = (struct ahci_cmd_tab *)
1798 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot));
1799 /* Setup the FIS for this request */
1800 if (!(fis_size = ahci_setup_fis(dev, ctp, ccb, slot->slot))) {
1801 device_printf(ch->dev, "Setting up SATA FIS failed\n");
1802 ahci_end_transaction(slot, AHCI_ERR_INVALID);
1805 /* Setup the command list entry */
1806 clp = (struct ahci_cmd_list *)
1807 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot));
1808 clp->cmd_flags = htole16(
1809 (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) |
1810 (ccb->ccb_h.func_code == XPT_SCSI_IO ?
1811 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) |
1812 (fis_size / sizeof(u_int32_t)) |
1814 clp->prd_length = htole16(slot->dma.nsegs);
1815 /* Special handling for Soft Reset command. */
1816 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1817 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) {
1818 if (ccb->ataio.cmd.control & ATA_A_RESET) {
1820 /* Kick controller into sane state */
1824 clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY;
1827 /* Prepare FIS receive area for check. */
1828 for (i = 0; i < 20; i++)
1834 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET +
1835 (AHCI_CT_SIZE * slot->slot));
1836 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
1837 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1838 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map,
1839 BUS_DMASYNC_PREREAD);
1840 /* Set ACTIVE bit for NCQ commands. */
1841 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1842 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1843 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot);
1845 /* If FBS is enabled, set PMP port. */
1846 if (ch->fbs_enabled) {
1847 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN |
1848 (port << AHCI_P_FBS_DEV_SHIFT));
1850 /* Issue command to the controller. */
1851 slot->state = AHCI_SLOT_RUNNING;
1852 ch->rslots |= (1 << slot->slot);
1853 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot));
1854 /* Device reset commands doesn't interrupt. Poll them. */
1855 if (ccb->ccb_h.func_code == XPT_ATA_IO &&
1856 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || softreset)) {
1857 int count, timeout = ccb->ccb_h.timeout * 100;
1858 enum ahci_err_type et = AHCI_ERR_NONE;
1860 for (count = 0; count < timeout; count++) {
1862 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot)))
1864 if ((ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) &&
1867 device_printf(ch->dev,
1868 "Poll error on slot %d, TFD: %04x\n",
1869 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD));
1874 /* Workaround for ATI SB600/SB700 chipsets. */
1875 if (ccb->ccb_h.target_id == 15 &&
1876 pci_get_vendor(device_get_parent(dev)) == 0x1002 &&
1877 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) {
1878 et = AHCI_ERR_TIMEOUT;
1883 /* Marvell controllers do not wait for readyness. */
1884 if ((ch->quirks & AHCI_Q_NOBSYRES) && softreset == 2 &&
1885 et == AHCI_ERR_NONE) {
1886 while ((val = fis[2]) & ATA_S_BUSY) {
1888 if (count++ >= timeout)
1893 if (timeout && (count >= timeout)) {
1894 device_printf(dev, "Poll timeout on slot %d port %d\n",
1896 device_printf(dev, "is %08x cs %08x ss %08x "
1897 "rs %08x tfd %02x serr %08x cmd %08x\n",
1898 ATA_INL(ch->r_mem, AHCI_P_IS),
1899 ATA_INL(ch->r_mem, AHCI_P_CI),
1900 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots,
1901 ATA_INL(ch->r_mem, AHCI_P_TFD),
1902 ATA_INL(ch->r_mem, AHCI_P_SERR),
1903 ATA_INL(ch->r_mem, AHCI_P_CMD));
1904 et = AHCI_ERR_TIMEOUT;
1907 /* Kick controller into sane state and enable FBS. */
1909 ch->eslots |= (1 << slot->slot);
1910 ahci_end_transaction(slot, et);
1913 /* Start command execution timeout */
1914 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 2000,
1915 (timeout_t*)ahci_timeout, slot);
1919 /* Must be called with channel locked. */
1921 ahci_process_timeout(device_t dev)
1923 struct ahci_channel *ch = device_get_softc(dev);
1926 mtx_assert(&ch->mtx, MA_OWNED);
1927 /* Handle the rest of commands. */
1928 for (i = 0; i < ch->numslots; i++) {
1929 /* Do we have a running request on slot? */
1930 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
1932 ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT);
1936 /* Must be called with channel locked. */
1938 ahci_rearm_timeout(device_t dev)
1940 struct ahci_channel *ch = device_get_softc(dev);
1943 mtx_assert(&ch->mtx, MA_OWNED);
1944 for (i = 0; i < ch->numslots; i++) {
1945 struct ahci_slot *slot = &ch->slot[i];
1947 /* Do we have a running request on slot? */
1948 if (slot->state < AHCI_SLOT_RUNNING)
1950 if ((ch->toslots & (1 << i)) == 0)
1952 callout_reset(&slot->timeout,
1953 (int)slot->ccb->ccb_h.timeout * hz / 2000,
1954 (timeout_t*)ahci_timeout, slot);
1958 /* Locked by callout mechanism. */
1960 ahci_timeout(struct ahci_slot *slot)
1962 device_t dev = slot->dev;
1963 struct ahci_channel *ch = device_get_softc(dev);
1968 /* Check for stale timeout. */
1969 if (slot->state < AHCI_SLOT_RUNNING)
1972 /* Check if slot was not being executed last time we checked. */
1973 if (slot->state < AHCI_SLOT_EXECUTING) {
1974 /* Check if slot started executing. */
1975 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT);
1976 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK)
1977 >> AHCI_P_CMD_CCS_SHIFT;
1978 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot ||
1979 ch->fbs_enabled || ch->wrongccs)
1980 slot->state = AHCI_SLOT_EXECUTING;
1981 else if ((ch->rslots & (1 << ccs)) == 0) {
1983 slot->state = AHCI_SLOT_EXECUTING;
1986 callout_reset(&slot->timeout,
1987 (int)slot->ccb->ccb_h.timeout * hz / 2000,
1988 (timeout_t*)ahci_timeout, slot);
1992 device_printf(dev, "Timeout on slot %d port %d\n",
1993 slot->slot, slot->ccb->ccb_h.target_id & 0x0f);
1994 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x "
1995 "serr %08x cmd %08x\n",
1996 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI),
1997 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots,
1998 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR),
1999 ATA_INL(ch->r_mem, AHCI_P_CMD));
2001 /* Handle frozen command. */
2003 union ccb *fccb = ch->frozen;
2005 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
2006 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
2007 xpt_freeze_devq(fccb->ccb_h.path, 1);
2008 fccb->ccb_h.status |= CAM_DEV_QFRZN;
2012 if (!ch->fbs_enabled && !ch->wrongccs) {
2013 /* Without FBS we know real timeout source. */
2015 /* Handle command with timeout. */
2016 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT);
2017 /* Handle the rest of commands. */
2018 for (i = 0; i < ch->numslots; i++) {
2019 /* Do we have a running request on slot? */
2020 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
2022 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT);
2025 /* With FBS we wait for other commands timeout and pray. */
2026 if (ch->toslots == 0)
2027 xpt_freeze_simq(ch->sim, 1);
2028 ch->toslots |= (1 << slot->slot);
2029 if ((ch->rslots & ~ch->toslots) == 0)
2030 ahci_process_timeout(dev);
2032 device_printf(dev, " ... waiting for slots %08x\n",
2033 ch->rslots & ~ch->toslots);
2037 /* Must be called with channel locked. */
2039 ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et)
2041 device_t dev = slot->dev;
2042 struct ahci_channel *ch = device_get_softc(dev);
2043 union ccb *ccb = slot->ccb;
2044 struct ahci_cmd_list *clp;
2048 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
2049 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2050 clp = (struct ahci_cmd_list *)
2051 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot));
2052 /* Read result registers to the result struct
2053 * May be incorrect if several commands finished same time,
2054 * so read only when sure or have to.
2056 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
2057 struct ata_res *res = &ccb->ataio.res;
2059 if ((et == AHCI_ERR_TFE) ||
2060 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) {
2061 u_int8_t *fis = ch->dma.rfis + 0x40;
2063 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map,
2064 BUS_DMASYNC_POSTREAD);
2065 if (ch->fbs_enabled) {
2066 fis += ccb->ccb_h.target_id * 256;
2067 res->status = fis[2];
2068 res->error = fis[3];
2070 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD);
2073 res->error = tfd >> 8;
2075 res->lba_low = fis[4];
2076 res->lba_mid = fis[5];
2077 res->lba_high = fis[6];
2078 res->device = fis[7];
2079 res->lba_low_exp = fis[8];
2080 res->lba_mid_exp = fis[9];
2081 res->lba_high_exp = fis[10];
2082 res->sector_count = fis[12];
2083 res->sector_count_exp = fis[13];
2086 * Some weird controllers do not return signature in
2087 * FIS receive area. Read it from PxSIG register.
2089 if ((ch->quirks & AHCI_Q_ALTSIG) &&
2090 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) &&
2091 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) {
2092 sig = ATA_INL(ch->r_mem, AHCI_P_SIG);
2093 res->lba_high = sig >> 24;
2094 res->lba_mid = sig >> 16;
2095 res->lba_low = sig >> 8;
2096 res->sector_count = sig;
2099 bzero(res, sizeof(*res));
2100 if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 &&
2101 (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
2102 (ch->quirks & AHCI_Q_NOCOUNT) == 0) {
2104 ccb->ataio.dxfer_len - le32toh(clp->bytecount);
2107 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
2108 (ch->quirks & AHCI_Q_NOCOUNT) == 0) {
2110 ccb->csio.dxfer_len - le32toh(clp->bytecount);
2113 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
2114 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
2115 (ccb->ccb_h.flags & CAM_DIR_IN) ?
2116 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
2117 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map);
2119 if (et != AHCI_ERR_NONE)
2120 ch->eslots |= (1 << slot->slot);
2121 /* In case of error, freeze device for proper recovery. */
2122 if ((et != AHCI_ERR_NONE) && (!ch->recoverycmd) &&
2123 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) {
2124 xpt_freeze_devq(ccb->ccb_h.path, 1);
2125 ccb->ccb_h.status |= CAM_DEV_QFRZN;
2127 /* Set proper result status. */
2128 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2131 ccb->ccb_h.status |= CAM_REQ_CMP;
2132 if (ccb->ccb_h.func_code == XPT_SCSI_IO)
2133 ccb->csio.scsi_status = SCSI_STATUS_OK;
2135 case AHCI_ERR_INVALID:
2137 ccb->ccb_h.status |= CAM_REQ_INVALID;
2139 case AHCI_ERR_INNOCENT:
2140 ccb->ccb_h.status |= CAM_REQUEUE_REQ;
2144 if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
2145 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
2146 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
2148 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR;
2153 if (!ch->recoverycmd) {
2154 xpt_freeze_simq(ch->sim, 1);
2155 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2156 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
2158 ccb->ccb_h.status |= CAM_UNCOR_PARITY;
2160 case AHCI_ERR_TIMEOUT:
2161 if (!ch->recoverycmd) {
2162 xpt_freeze_simq(ch->sim, 1);
2163 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2164 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
2166 ccb->ccb_h.status |= CAM_CMD_TIMEOUT;
2170 ccb->ccb_h.status |= CAM_REQ_CMP_ERR;
2173 ch->oslots &= ~(1 << slot->slot);
2174 ch->rslots &= ~(1 << slot->slot);
2175 ch->aslots &= ~(1 << slot->slot);
2176 slot->state = AHCI_SLOT_EMPTY;
2178 /* Update channel stats. */
2180 ch->numrslotspd[ccb->ccb_h.target_id]--;
2181 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
2182 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
2184 ch->numtslotspd[ccb->ccb_h.target_id]--;
2186 /* Cancel timeout state if request completed normally. */
2187 if (et != AHCI_ERR_TIMEOUT) {
2188 lastto = (ch->toslots == (1 << slot->slot));
2189 ch->toslots &= ~(1 << slot->slot);
2191 xpt_release_simq(ch->sim, TRUE);
2193 /* If it was first request of reset sequence and there is no error,
2194 * proceed to second request. */
2195 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
2196 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) &&
2197 (ccb->ataio.cmd.control & ATA_A_RESET) &&
2198 et == AHCI_ERR_NONE) {
2199 ccb->ataio.cmd.control &= ~ATA_A_RESET;
2200 ahci_begin_transaction(dev, ccb);
2203 /* If it was our READ LOG command - process it. */
2204 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) {
2205 ahci_process_read_log(dev, ccb);
2206 /* If it was our REQUEST SENSE command - process it. */
2207 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) {
2208 ahci_process_request_sense(dev, ccb);
2209 /* If it was NCQ or ATAPI command error, put result on hold. */
2210 } else if (et == AHCI_ERR_NCQ ||
2211 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR &&
2212 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) {
2213 ch->hold[slot->slot] = ccb;
2217 /* If we have no other active commands, ... */
2218 if (ch->rslots == 0) {
2219 /* if there was fatal error - reset port. */
2220 if (ch->toslots != 0 || ch->fatalerr) {
2223 /* if we have slots in error, we can reinit port. */
2224 if (ch->eslots != 0) {
2229 /* if there commands on hold, we can do READ LOG. */
2230 if (!ch->recoverycmd && ch->numhslots)
2231 ahci_issue_recovery(dev);
2233 /* If all the rest of commands are in timeout - give them chance. */
2234 } else if ((ch->rslots & ~ch->toslots) == 0 &&
2235 et != AHCI_ERR_TIMEOUT)
2236 ahci_rearm_timeout(dev);
2237 /* Unfreeze frozen command. */
2238 if (ch->frozen && !ahci_check_collision(dev, ch->frozen)) {
2239 union ccb *fccb = ch->frozen;
2241 ahci_begin_transaction(dev, fccb);
2242 xpt_release_simq(ch->sim, TRUE);
2244 /* Start PM timer. */
2245 if (ch->numrslots == 0 && ch->pm_level > 3 &&
2246 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) {
2247 callout_schedule(&ch->pm_timer,
2248 (ch->pm_level == 4) ? hz / 1000 : hz / 8);
2253 ahci_issue_recovery(device_t dev)
2255 struct ahci_channel *ch = device_get_softc(dev);
2257 struct ccb_ataio *ataio;
2258 struct ccb_scsiio *csio;
2261 /* Find some held command. */
2262 for (i = 0; i < ch->numslots; i++) {
2266 ccb = xpt_alloc_ccb_nowait();
2268 device_printf(dev, "Unable to allocate recovery command\n");
2270 /* We can't do anything -- complete held commands. */
2271 for (i = 0; i < ch->numslots; i++) {
2272 if (ch->hold[i] == NULL)
2274 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2275 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL;
2276 xpt_done(ch->hold[i]);
2283 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */
2284 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
2286 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG;
2287 ccb->ccb_h.func_code = XPT_ATA_IO;
2288 ccb->ccb_h.flags = CAM_DIR_IN;
2289 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */
2290 ataio = &ccb->ataio;
2291 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT);
2292 if (ataio->data_ptr == NULL) {
2295 "Unable to allocate memory for READ LOG command\n");
2298 ataio->dxfer_len = 512;
2299 bzero(&ataio->cmd, sizeof(ataio->cmd));
2300 ataio->cmd.flags = CAM_ATAIO_48BIT;
2301 ataio->cmd.command = 0x2F; /* READ LOG EXT */
2302 ataio->cmd.sector_count = 1;
2303 ataio->cmd.sector_count_exp = 0;
2304 ataio->cmd.lba_low = 0x10;
2305 ataio->cmd.lba_mid = 0;
2306 ataio->cmd.lba_mid_exp = 0;
2309 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE;
2310 ccb->ccb_h.recovery_slot = i;
2311 ccb->ccb_h.func_code = XPT_SCSI_IO;
2312 ccb->ccb_h.flags = CAM_DIR_IN;
2313 ccb->ccb_h.status = 0;
2314 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */
2316 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data;
2317 csio->dxfer_len = ch->hold[i]->csio.sense_len;
2319 bzero(&csio->cdb_io, sizeof(csio->cdb_io));
2320 csio->cdb_io.cdb_bytes[0] = 0x03;
2321 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len;
2323 /* Freeze SIM while doing recovery. */
2324 ch->recoverycmd = 1;
2325 xpt_freeze_simq(ch->sim, 1);
2326 ahci_begin_transaction(dev, ccb);
2330 ahci_process_read_log(device_t dev, union ccb *ccb)
2332 struct ahci_channel *ch = device_get_softc(dev);
2334 struct ata_res *res;
2337 ch->recoverycmd = 0;
2339 data = ccb->ataio.data_ptr;
2340 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP &&
2341 (data[0] & 0x80) == 0) {
2342 for (i = 0; i < ch->numslots; i++) {
2345 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO)
2347 if ((data[0] & 0x1F) == i) {
2348 res = &ch->hold[i]->ataio.res;
2349 res->status = data[2];
2350 res->error = data[3];
2351 res->lba_low = data[4];
2352 res->lba_mid = data[5];
2353 res->lba_high = data[6];
2354 res->device = data[7];
2355 res->lba_low_exp = data[8];
2356 res->lba_mid_exp = data[9];
2357 res->lba_high_exp = data[10];
2358 res->sector_count = data[12];
2359 res->sector_count_exp = data[13];
2361 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2362 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ;
2364 xpt_done(ch->hold[i]);
2369 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP)
2370 device_printf(dev, "Error while READ LOG EXT\n");
2371 else if ((data[0] & 0x80) == 0) {
2372 device_printf(dev, "Non-queued command error in READ LOG EXT\n");
2374 for (i = 0; i < ch->numslots; i++) {
2377 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO)
2379 xpt_done(ch->hold[i]);
2384 free(ccb->ataio.data_ptr, M_AHCI);
2386 xpt_release_simq(ch->sim, TRUE);
2390 ahci_process_request_sense(device_t dev, union ccb *ccb)
2392 struct ahci_channel *ch = device_get_softc(dev);
2395 ch->recoverycmd = 0;
2397 i = ccb->ccb_h.recovery_slot;
2398 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) {
2399 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID;
2401 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2402 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL;
2404 xpt_done(ch->hold[i]);
2408 xpt_release_simq(ch->sim, TRUE);
2412 ahci_start(device_t dev, int fbs)
2414 struct ahci_channel *ch = device_get_softc(dev);
2417 /* Clear SATA error register */
2418 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF);
2419 /* Clear any interrupts pending on this channel */
2420 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF);
2421 /* Configure FIS-based switching if supported. */
2422 if (ch->chcaps & AHCI_P_CMD_FBSCP) {
2423 ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0;
2424 ATA_OUTL(ch->r_mem, AHCI_P_FBS,
2425 ch->fbs_enabled ? AHCI_P_FBS_EN : 0);
2427 /* Start operations on this channel */
2428 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2429 cmd &= ~AHCI_P_CMD_PMA;
2430 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST |
2431 (ch->pm_present ? AHCI_P_CMD_PMA : 0));
2435 ahci_stop(device_t dev)
2437 struct ahci_channel *ch = device_get_softc(dev);
2441 /* Kill all activity on this channel */
2442 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2443 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST);
2444 /* Wait for activity stop. */
2448 if (timeout++ > 50000) {
2449 device_printf(dev, "stopping AHCI engine failed\n");
2452 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR);
2457 ahci_clo(device_t dev)
2459 struct ahci_channel *ch = device_get_softc(dev);
2463 /* Issue Command List Override if supported */
2464 if (ch->caps & AHCI_CAP_SCLO) {
2465 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2466 cmd |= AHCI_P_CMD_CLO;
2467 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd);
2471 if (timeout++ > 50000) {
2472 device_printf(dev, "executing CLO failed\n");
2475 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO);
2480 ahci_stop_fr(device_t dev)
2482 struct ahci_channel *ch = device_get_softc(dev);
2486 /* Kill all FIS reception on this channel */
2487 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2488 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE);
2489 /* Wait for FIS reception stop. */
2493 if (timeout++ > 50000) {
2494 device_printf(dev, "stopping AHCI FR engine failed\n");
2497 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR);
2501 ahci_start_fr(device_t dev)
2503 struct ahci_channel *ch = device_get_softc(dev);
2506 /* Start FIS reception on this channel */
2507 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2508 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE);
2512 ahci_wait_ready(device_t dev, int t, int t0)
2514 struct ahci_channel *ch = device_get_softc(dev);
2518 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) &
2519 (ATA_S_BUSY | ATA_S_DRQ)) {
2523 "AHCI reset: device not ready after %dms "
2525 MAX(t, 0) + t0, val);
2533 device_printf(dev, "AHCI reset: device ready after %dms\n",
2539 ahci_reset_to(void *arg)
2542 struct ahci_channel *ch = device_get_softc(dev);
2544 if (ch->resetting == 0)
2547 if (ahci_wait_ready(dev, ch->resetting == 0 ? -1 : 0,
2548 (310 - ch->resetting) * 100) == 0) {
2551 xpt_release_simq(ch->sim, TRUE);
2554 if (ch->resetting == 0) {
2557 xpt_release_simq(ch->sim, TRUE);
2560 callout_schedule(&ch->reset_timer, hz / 10);
2564 ahci_reset(device_t dev)
2566 struct ahci_channel *ch = device_get_softc(dev);
2567 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev));
2570 xpt_freeze_simq(ch->sim, 1);
2572 device_printf(dev, "AHCI reset...\n");
2573 /* Forget about previous reset. */
2574 if (ch->resetting) {
2576 callout_stop(&ch->reset_timer);
2577 xpt_release_simq(ch->sim, TRUE);
2579 /* Requeue freezed command. */
2581 union ccb *fccb = ch->frozen;
2583 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
2584 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
2585 xpt_freeze_devq(fccb->ccb_h.path, 1);
2586 fccb->ccb_h.status |= CAM_DEV_QFRZN;
2590 /* Kill the engine and requeue all running commands. */
2592 for (i = 0; i < ch->numslots; i++) {
2593 /* Do we have a running request on slot? */
2594 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
2596 /* XXX; Commands in loading state. */
2597 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT);
2599 for (i = 0; i < ch->numslots; i++) {
2602 xpt_done(ch->hold[i]);
2606 if (ch->toslots != 0)
2607 xpt_release_simq(ch->sim, TRUE);
2612 /* Tell the XPT about the event */
2613 xpt_async(AC_BUS_RESET, ch->path, NULL);
2614 /* Disable port interrupts */
2615 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
2616 /* Reset and reconnect PHY, */
2617 if (!ahci_sata_phy_reset(dev)) {
2620 "AHCI reset: device not found\n");
2622 /* Enable wanted port interrupts */
2623 ATA_OUTL(ch->r_mem, AHCI_P_IE,
2624 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) |
2625 AHCI_P_IX_PRC | AHCI_P_IX_PC));
2626 xpt_release_simq(ch->sim, TRUE);
2630 device_printf(dev, "AHCI reset: device found\n");
2631 /* Wait for clearing busy status. */
2632 if (ahci_wait_ready(dev, dumping ? 31000 : 0, 0)) {
2636 ch->resetting = 310;
2639 /* Enable wanted port interrupts */
2640 ATA_OUTL(ch->r_mem, AHCI_P_IE,
2641 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) |
2642 AHCI_P_IX_TFE | AHCI_P_IX_HBF |
2643 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF |
2644 ((ch->pm_level == 0) ? AHCI_P_IX_PRC : 0) | AHCI_P_IX_PC |
2645 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) |
2646 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR)));
2648 callout_reset(&ch->reset_timer, hz / 10, ahci_reset_to, dev);
2651 xpt_release_simq(ch->sim, TRUE);
2656 ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag)
2658 struct ahci_channel *ch = device_get_softc(dev);
2659 u_int8_t *fis = &ctp->cfis[0];
2661 bzero(ctp->cfis, 16);
2662 fis[0] = 0x27; /* host to device */
2663 fis[1] = (ccb->ccb_h.target_id & 0x0f);
2664 if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
2666 fis[2] = ATA_PACKET_CMD;
2667 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
2668 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA)
2671 fis[5] = ccb->csio.dxfer_len;
2672 fis[6] = ccb->csio.dxfer_len >> 8;
2675 fis[15] = ATA_A_4BIT;
2676 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ?
2677 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes,
2678 ctp->acmd, ccb->csio.cdb_len);
2679 bzero(ctp->acmd + ccb->csio.cdb_len, 32 - ccb->csio.cdb_len);
2680 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) {
2682 fis[2] = ccb->ataio.cmd.command;
2683 fis[3] = ccb->ataio.cmd.features;
2684 fis[4] = ccb->ataio.cmd.lba_low;
2685 fis[5] = ccb->ataio.cmd.lba_mid;
2686 fis[6] = ccb->ataio.cmd.lba_high;
2687 fis[7] = ccb->ataio.cmd.device;
2688 fis[8] = ccb->ataio.cmd.lba_low_exp;
2689 fis[9] = ccb->ataio.cmd.lba_mid_exp;
2690 fis[10] = ccb->ataio.cmd.lba_high_exp;
2691 fis[11] = ccb->ataio.cmd.features_exp;
2692 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
2696 fis[12] = ccb->ataio.cmd.sector_count;
2697 fis[13] = ccb->ataio.cmd.sector_count_exp;
2699 fis[15] = ATA_A_4BIT;
2701 fis[15] = ccb->ataio.cmd.control;
2707 ahci_sata_connect(struct ahci_channel *ch)
2710 int timeout, found = 0;
2712 /* Wait up to 100ms for "connect well" */
2713 for (timeout = 0; timeout < 1000 ; timeout++) {
2714 status = ATA_INL(ch->r_mem, AHCI_P_SSTS);
2715 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE)
2717 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) &&
2718 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) &&
2719 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE))
2721 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) {
2723 device_printf(ch->dev, "SATA offline status=%08x\n",
2728 if (found == 0 && timeout >= 100)
2732 if (timeout >= 1000 || !found) {
2734 device_printf(ch->dev,
2735 "SATA connect timeout time=%dus status=%08x\n",
2736 timeout * 100, status);
2741 device_printf(ch->dev, "SATA connect time=%dus status=%08x\n",
2742 timeout * 100, status);
2744 /* Clear SATA error register */
2745 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff);
2750 ahci_sata_phy_reset(device_t dev)
2752 struct ahci_channel *ch = device_get_softc(dev);
2756 if (ch->listening) {
2757 val = ATA_INL(ch->r_mem, AHCI_P_CMD);
2758 val |= AHCI_P_CMD_SUD;
2759 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val);
2762 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision;
2764 val = ATA_SC_SPD_SPEED_GEN1;
2765 else if (sata_rev == 2)
2766 val = ATA_SC_SPD_SPEED_GEN2;
2767 else if (sata_rev == 3)
2768 val = ATA_SC_SPD_SPEED_GEN3;
2771 ATA_OUTL(ch->r_mem, AHCI_P_SCTL,
2772 ATA_SC_DET_RESET | val |
2773 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER);
2775 ATA_OUTL(ch->r_mem, AHCI_P_SCTL,
2776 ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 :
2777 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER)));
2778 if (!ahci_sata_connect(ch)) {
2779 if (ch->caps & AHCI_CAP_SSS) {
2780 val = ATA_INL(ch->r_mem, AHCI_P_CMD);
2781 val &= ~AHCI_P_CMD_SUD;
2782 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val);
2784 } else if (ch->pm_level > 0)
2785 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE);
2792 ahci_check_ids(device_t dev, union ccb *ccb)
2794 struct ahci_channel *ch = device_get_softc(dev);
2796 if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) {
2797 ccb->ccb_h.status = CAM_TID_INVALID;
2801 if (ccb->ccb_h.target_lun != 0) {
2802 ccb->ccb_h.status = CAM_LUN_INVALID;
2810 ahciaction(struct cam_sim *sim, union ccb *ccb)
2812 device_t dev, parent;
2813 struct ahci_channel *ch;
2815 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n",
2816 ccb->ccb_h.func_code));
2818 ch = (struct ahci_channel *)cam_sim_softc(sim);
2820 switch (ccb->ccb_h.func_code) {
2821 /* Common cases first */
2822 case XPT_ATA_IO: /* Execute the requested I/O operation */
2824 if (ahci_check_ids(dev, ccb))
2826 if (ch->devices == 0 ||
2827 (ch->pm_present == 0 &&
2828 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) {
2829 ccb->ccb_h.status = CAM_SEL_TIMEOUT;
2832 ccb->ccb_h.recovery_type = RECOVERY_NONE;
2833 /* Check for command collision. */
2834 if (ahci_check_collision(dev, ccb)) {
2835 /* Freeze command. */
2837 /* We have only one frozen slot, so freeze simq also. */
2838 xpt_freeze_simq(ch->sim, 1);
2841 ahci_begin_transaction(dev, ccb);
2843 case XPT_EN_LUN: /* Enable LUN as a target */
2844 case XPT_TARGET_IO: /* Execute target I/O request */
2845 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */
2846 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/
2847 case XPT_ABORT: /* Abort the specified CCB */
2849 ccb->ccb_h.status = CAM_REQ_INVALID;
2851 case XPT_SET_TRAN_SETTINGS:
2853 struct ccb_trans_settings *cts = &ccb->cts;
2854 struct ahci_device *d;
2856 if (ahci_check_ids(dev, ccb))
2858 if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2859 d = &ch->curr[ccb->ccb_h.target_id];
2861 d = &ch->user[ccb->ccb_h.target_id];
2862 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION)
2863 d->revision = cts->xport_specific.sata.revision;
2864 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE)
2865 d->mode = cts->xport_specific.sata.mode;
2866 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT)
2867 d->bytecount = min(8192, cts->xport_specific.sata.bytecount);
2868 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS)
2869 d->tags = min(ch->numslots, cts->xport_specific.sata.tags);
2870 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM)
2871 ch->pm_present = cts->xport_specific.sata.pm_present;
2872 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI)
2873 d->atapi = cts->xport_specific.sata.atapi;
2874 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS)
2875 d->caps = cts->xport_specific.sata.caps;
2876 ccb->ccb_h.status = CAM_REQ_CMP;
2879 case XPT_GET_TRAN_SETTINGS:
2880 /* Get default/user set transfer settings for the target */
2882 struct ccb_trans_settings *cts = &ccb->cts;
2883 struct ahci_device *d;
2886 if (ahci_check_ids(dev, ccb))
2888 if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2889 d = &ch->curr[ccb->ccb_h.target_id];
2891 d = &ch->user[ccb->ccb_h.target_id];
2892 cts->protocol = PROTO_UNSPECIFIED;
2893 cts->protocol_version = PROTO_VERSION_UNSPECIFIED;
2894 cts->transport = XPORT_SATA;
2895 cts->transport_version = XPORT_VERSION_UNSPECIFIED;
2896 cts->proto_specific.valid = 0;
2897 cts->xport_specific.sata.valid = 0;
2898 if (cts->type == CTS_TYPE_CURRENT_SETTINGS &&
2899 (ccb->ccb_h.target_id == 15 ||
2900 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) {
2901 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK;
2902 if (status & 0x0f0) {
2903 cts->xport_specific.sata.revision =
2904 (status & 0x0f0) >> 4;
2905 cts->xport_specific.sata.valid |=
2906 CTS_SATA_VALID_REVISION;
2908 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D;
2910 if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC))
2911 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ;
2912 if (ch->caps2 & AHCI_CAP2_APST)
2913 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST;
2915 if ((ch->caps & AHCI_CAP_SNCQ) &&
2916 (ch->quirks & AHCI_Q_NOAA) == 0)
2917 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA;
2918 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN;
2919 cts->xport_specific.sata.caps &=
2920 ch->user[ccb->ccb_h.target_id].caps;
2921 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
2923 cts->xport_specific.sata.revision = d->revision;
2924 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION;
2925 cts->xport_specific.sata.caps = d->caps;
2926 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
2928 cts->xport_specific.sata.mode = d->mode;
2929 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE;
2930 cts->xport_specific.sata.bytecount = d->bytecount;
2931 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT;
2932 cts->xport_specific.sata.pm_present = ch->pm_present;
2933 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM;
2934 cts->xport_specific.sata.tags = d->tags;
2935 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS;
2936 cts->xport_specific.sata.atapi = d->atapi;
2937 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI;
2938 ccb->ccb_h.status = CAM_REQ_CMP;
2941 case XPT_RESET_BUS: /* Reset the specified SCSI bus */
2942 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */
2944 ccb->ccb_h.status = CAM_REQ_CMP;
2946 case XPT_TERM_IO: /* Terminate the I/O process */
2948 ccb->ccb_h.status = CAM_REQ_INVALID;
2950 case XPT_PATH_INQ: /* Path routing inquiry */
2952 struct ccb_pathinq *cpi = &ccb->cpi;
2954 parent = device_get_parent(dev);
2955 cpi->version_num = 1; /* XXX??? */
2956 cpi->hba_inquiry = PI_SDTR_ABLE;
2957 if (ch->caps & AHCI_CAP_SNCQ)
2958 cpi->hba_inquiry |= PI_TAG_ABLE;
2959 if (ch->caps & AHCI_CAP_SPM)
2960 cpi->hba_inquiry |= PI_SATAPM;
2961 cpi->target_sprt = 0;
2962 cpi->hba_misc = PIM_SEQSCAN | PIM_UNMAPPED;
2963 cpi->hba_eng_cnt = 0;
2964 if (ch->caps & AHCI_CAP_SPM)
2965 cpi->max_target = 15;
2967 cpi->max_target = 0;
2969 cpi->initiator_id = 0;
2970 cpi->bus_id = cam_sim_bus(sim);
2971 cpi->base_transfer_speed = 150000;
2972 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
2973 strncpy(cpi->hba_vid, "AHCI", HBA_IDLEN);
2974 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
2975 cpi->unit_number = cam_sim_unit(sim);
2976 cpi->transport = XPORT_SATA;
2977 cpi->transport_version = XPORT_VERSION_UNSPECIFIED;
2978 cpi->protocol = PROTO_ATA;
2979 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED;
2980 cpi->maxio = MAXPHYS;
2981 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */
2982 if (pci_get_devid(parent) == 0x43801002)
2983 cpi->maxio = min(cpi->maxio, 128 * 512);
2984 cpi->hba_vendor = pci_get_vendor(parent);
2985 cpi->hba_device = pci_get_device(parent);
2986 cpi->hba_subvendor = pci_get_subvendor(parent);
2987 cpi->hba_subdevice = pci_get_subdevice(parent);
2988 cpi->ccb_h.status = CAM_REQ_CMP;
2992 ccb->ccb_h.status = CAM_REQ_INVALID;
2999 ahcipoll(struct cam_sim *sim)
3001 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim);
3003 ahci_ch_intr(ch->dev);
3004 if (ch->resetting != 0 &&
3005 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) {
3006 ch->resetpolldiv = 1000;
3007 ahci_reset_to(ch->dev);