2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
23 #include "ah_internal.h"
25 #include "ar5416/ar5416.h"
26 #include "ar5416/ar5416reg.h"
27 #include "ar5416/ar5416desc.h"
30 * Get the receive filter.
33 ar5416GetRxFilter(struct ath_hal *ah)
35 uint32_t bits = OS_REG_READ(ah, AR_RX_FILTER);
36 uint32_t phybits = OS_REG_READ(ah, AR_PHY_ERR);
38 if (phybits & AR_PHY_ERR_RADAR)
39 bits |= HAL_RX_FILTER_PHYRADAR;
40 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
41 bits |= HAL_RX_FILTER_PHYERR;
46 * Set the receive filter.
49 ar5416SetRxFilter(struct ath_hal *ah, u_int32_t bits)
53 OS_REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff));
55 if (bits & HAL_RX_FILTER_PHYRADAR)
56 phybits |= AR_PHY_ERR_RADAR;
57 if (bits & HAL_RX_FILTER_PHYERR)
58 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
59 OS_REG_WRITE(ah, AR_PHY_ERR, phybits);
61 OS_REG_WRITE(ah, AR_RXCFG,
62 OS_REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
64 OS_REG_WRITE(ah, AR_RXCFG,
65 OS_REG_READ(ah, AR_RXCFG) &~ AR_RXCFG_ZLFDMA);
70 * Stop Receive at the DMA engine
73 ar5416StopDmaReceive(struct ath_hal *ah)
77 OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_DMA_STOP);
78 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
79 if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) {
80 OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_DMA_STOP_ERR);
82 ath_hal_printf(ah, "%s: dma failed to stop in 10ms\n"
83 "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n",
85 OS_REG_READ(ah, AR_CR),
86 OS_REG_READ(ah, AR_DIAG_SW));
94 * XXX Is this to flush whatever is in a FIFO somewhere?
95 * XXX If so, what should the correct behaviour should be?
104 * Start receive at the PCU engine
107 ar5416StartPcuReceive(struct ath_hal *ah)
109 struct ath_hal_private *ahp = AH_PRIVATE(ah);
111 HALDEBUG(ah, HAL_DEBUG_RX, "%s: Start PCU Receive \n", __func__);
112 ar5212EnableMibCounters(ah);
113 /* NB: restore current settings */
114 ar5416AniReset(ah, ahp->ah_curchan, ahp->ah_opmode, AH_TRUE);
116 * NB: must do after enabling phy errors to avoid rx
117 * frames w/ corrupted descriptor status.
119 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
123 * Stop receive at the PCU engine
124 * and abort current frame in PCU
127 ar5416StopPcuReceive(struct ath_hal *ah)
129 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
131 HALDEBUG(ah, HAL_DEBUG_RX, "%s: Stop PCU Receive \n", __func__);
132 ar5212DisableMibCounters(ah);
136 * Initialize RX descriptor, by clearing the status and setting
137 * the size (and any other flags).
140 ar5416SetupRxDesc(struct ath_hal *ah, struct ath_desc *ds,
141 uint32_t size, u_int flags)
143 struct ar5416_desc *ads = AR5416DESC(ds);
145 HALASSERT((size &~ AR_BufLen) == 0);
147 ads->ds_ctl1 = size & AR_BufLen;
148 if (flags & HAL_RXDESC_INTREQ)
149 ads->ds_ctl1 |= AR_RxIntrReq;
151 /* this should be enough */
152 ads->ds_rxstatus8 &= ~AR_RxDone;
154 /* clear the rest of the status fields */
155 OS_MEMZERO(&(ads->u), sizeof(ads->u));
161 * Process an RX descriptor, and return the status to the caller.
162 * Copy some hardware specific items into the software portion
165 * NB: the caller is responsible for validating the memory contents
166 * of the descriptor (e.g. flushing any cached copy).
169 ar5416ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds,
170 uint32_t pa, struct ath_desc *nds, uint64_t tsf,
171 struct ath_rx_status *rs)
173 struct ar5416_desc *ads = AR5416DESC(ds);
175 if ((ads->ds_rxstatus8 & AR_RxDone) == 0)
176 return HAL_EINPROGRESS;
181 rs->rs_datalen = ads->ds_rxstatus1 & AR_DataLen;
182 rs->rs_tstamp = ads->AR_RcvTimestamp;
184 /* XXX what about KeyCacheMiss? */
186 rs->rs_rssi = MS(ads->ds_rxstatus4, AR_RxRSSICombined);
187 rs->rs_rssi_ctl[0] = MS(ads->ds_rxstatus0, AR_RxRSSIAnt00);
188 rs->rs_rssi_ctl[1] = MS(ads->ds_rxstatus0, AR_RxRSSIAnt01);
189 rs->rs_rssi_ctl[2] = MS(ads->ds_rxstatus0, AR_RxRSSIAnt02);
190 rs->rs_rssi_ext[0] = MS(ads->ds_rxstatus4, AR_RxRSSIAnt10);
191 rs->rs_rssi_ext[1] = MS(ads->ds_rxstatus4, AR_RxRSSIAnt11);
192 rs->rs_rssi_ext[2] = MS(ads->ds_rxstatus4, AR_RxRSSIAnt12);
194 if (ads->ds_rxstatus8 & AR_RxKeyIdxValid)
195 rs->rs_keyix = MS(ads->ds_rxstatus8, AR_KeyIdx);
197 rs->rs_keyix = HAL_RXKEYIX_INVALID;
199 /* NB: caller expected to do rate table mapping */
200 rs->rs_rate = RXSTATUS_RATE(ah, ads);
201 rs->rs_more = (ads->ds_rxstatus1 & AR_RxMore) ? 1 : 0;
203 rs->rs_isaggr = (ads->ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
204 rs->rs_moreaggr = (ads->ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
205 rs->rs_antenna = MS(ads->ds_rxstatus3, AR_RxAntenna);
207 if (ads->ds_rxstatus3 & AR_GI)
208 rs->rs_flags |= HAL_RX_GI;
209 if (ads->ds_rxstatus3 & AR_2040)
210 rs->rs_flags |= HAL_RX_2040;
213 * Only the AR9280 and later chips support STBC RX, so
214 * ensure we only set this bit for those chips.
216 if (AR_SREV_MERLIN_10_OR_LATER(ah)
217 && ads->ds_rxstatus3 & AR_STBCFrame)
218 rs->rs_flags |= HAL_RX_STBC;
220 if (ads->ds_rxstatus8 & AR_PreDelimCRCErr)
221 rs->rs_flags |= HAL_RX_DELIM_CRC_PRE;
222 if (ads->ds_rxstatus8 & AR_PostDelimCRCErr)
223 rs->rs_flags |= HAL_RX_DELIM_CRC_POST;
224 if (ads->ds_rxstatus8 & AR_DecryptBusyErr)
225 rs->rs_flags |= HAL_RX_DECRYPT_BUSY;
226 if (ads->ds_rxstatus8 & AR_HiRxChain)
227 rs->rs_flags |= HAL_RX_HI_RX_CHAIN;
229 if ((ads->ds_rxstatus8 & AR_RxFrameOK) == 0) {
231 * These four bits should not be set together. The
232 * 5416 spec states a Michael error can only occur if
233 * DecryptCRCErr not set (and TKIP is used). Experience
234 * indicates however that you can also get Michael errors
235 * when a CRC error is detected, but these are specious.
236 * Consequently we filter them out here so we don't
237 * confuse and/or complicate drivers.
241 * The AR5416 sometimes sets both AR_CRCErr and AR_PHYErr
242 * when reporting radar pulses. In this instance
243 * set HAL_RXERR_PHY as well as HAL_RXERR_CRC and
244 * let the driver layer figure out what to do.
246 * See PR kern/169362.
248 if (ads->ds_rxstatus8 & AR_PHYErr) {
252 * Packets with OFDM_RESTART on post delimiter are CRC OK and
253 * usable and MAC ACKs them.
254 * To avoid packet from being lost, we remove the PHY Err flag
255 * so that driver layer does not drop them.
257 phyerr = MS(ads->ds_rxstatus8, AR_PHYErrCode);
259 if ((phyerr == HAL_PHYERR_OFDM_RESTART) &&
260 (ads->ds_rxstatus8 & AR_PostDelimCRCErr)) {
262 "%s: OFDM_RESTART on post-delim CRC error\n",
266 rs->rs_status |= HAL_RXERR_PHY;
267 rs->rs_phyerr = phyerr;
270 if (ads->ds_rxstatus8 & AR_CRCErr)
271 rs->rs_status |= HAL_RXERR_CRC;
272 else if (ads->ds_rxstatus8 & AR_DecryptCRCErr)
273 rs->rs_status |= HAL_RXERR_DECRYPT;
274 else if (ads->ds_rxstatus8 & AR_MichaelErr)
275 rs->rs_status |= HAL_RXERR_MIC;