sys/dev/bge/if_bge.c

   1 /*-
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/cdefs.h>
  35 __FBSDID("$FreeBSD$");
  36
  37 /*
  38  * Broadcom BCM57xx(x)/BCM590x NetXtreme and NetLink family Ethernet driver
  39  *
  40  * The Broadcom BCM5700 is based on technology originally developed by
  41  * Alteon Networks as part of the Tigon I and Tigon II Gigabit Ethernet
  42  * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has
  43  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  44  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  45  * frames, highly configurable RX filtering, and 16 RX and TX queues
  46  * (which, along with RX filter rules, can be used for QOS applications).
  47  * Other features, such as TCP segmentation, may be available as part
  48  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  49  * firmware images can be stored in hardware and need not be compiled
  50  * into the driver.
  51  *
  52  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  53  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  54  *
  55  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  56  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
  57  * does not support external SSRAM.
  58  *
  59  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  60  * brand name, which is functionally similar but lacks PCI-X support.
  61  *
  62  * Without external SSRAM, you can only have at most 4 TX rings,
  63  * and the use of the mini RX ring is disabled. This seems to imply
  64  * that these features are simply not available on the BCM5701. As a
  65  * result, this driver does not implement any support for the mini RX
  66  * ring.
  67  */
  68
  69 #ifdef HAVE_KERNEL_OPTION_HEADERS
  70 #include "opt_device_polling.h"
  71 #endif
  72
  73 #include <sys/param.h>
  74 #include <sys/endian.h>
  75 #include <sys/systm.h>
  76 #include <sys/sockio.h>
  77 #include <sys/mbuf.h>
  78 #include <sys/malloc.h>
  79 #include <sys/kernel.h>
  80 #include <sys/module.h>
  81 #include <sys/socket.h>
  82 #include <sys/sysctl.h>
  83 #include <sys/taskqueue.h>
  84
  85 #include <net/if.h>
  86 #include <net/if_arp.h>
  87 #include <net/ethernet.h>
  88 #include <net/if_dl.h>
  89 #include <net/if_media.h>
  90
  91 #include <net/bpf.h>
  92
  93 #include <net/if_types.h>
  94 #include <net/if_vlan_var.h>
  95
  96 #include <netinet/in_systm.h>
  97 #include <netinet/in.h>
  98 #include <netinet/ip.h>
  99 #include <netinet/tcp.h>
 100
 101 #include <machine/bus.h>
 102 #include <machine/resource.h>
 103 #include <sys/bus.h>
 104 #include <sys/rman.h>
 105
 106 #include <dev/mii/mii.h>
 107 #include <dev/mii/miivar.h>
 108 #include "miidevs.h"
 109 #include <dev/mii/brgphyreg.h>
 110
 111 #ifdef __sparc64__
 112 #include <dev/ofw/ofw_bus.h>
 113 #include <dev/ofw/openfirm.h>
 114 #include <machine/ofw_machdep.h>
 115 #include <machine/ver.h>
 116 #endif
 117
 118 #include <dev/pci/pcireg.h>
 119 #include <dev/pci/pcivar.h>
 120
 121 #include <dev/bge/if_bgereg.h>
 122
 123 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP)
 124 #define ETHER_MIN_NOPAD         (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
 125
 126 MODULE_DEPEND(bge, pci, 1, 1, 1);
 127 MODULE_DEPEND(bge, ether, 1, 1, 1);
 128 MODULE_DEPEND(bge, miibus, 1, 1, 1);
 129
 130 /* "device miibus" required.  See GENERIC if you get errors here. */
 131 #include "miibus_if.h"
 132
 133 /*
 134  * Various supported device vendors/types and their names. Note: the
 135  * spec seems to indicate that the hardware still has Alteon's vendor
 136  * ID burned into it, though it will always be overriden by the vendor
 137  * ID in the EEPROM. Just to be safe, we cover all possibilities.
 138  */
 139 static const struct bge_type {
 140         uint16_t        bge_vid;
 141         uint16_t        bge_did;
 142 } bge_devs[] = {
 143         { ALTEON_VENDORID,      ALTEON_DEVICEID_BCM5700 },
 144         { ALTEON_VENDORID,      ALTEON_DEVICEID_BCM5701 },
 145
 146         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC1000 },
 147         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC1002 },
 148         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC9100 },
 149
 150         { APPLE_VENDORID,       APPLE_DEVICE_BCM5701 },
 151
 152         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5700 },
 153         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5701 },
 154         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702 },
 155         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702_ALT },
 156         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702X },
 157         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703 },
 158         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703_ALT },
 159         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703X },
 160         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704C },
 161         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704S },
 162         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704S_ALT },
 163         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705 },
 164         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705F },
 165         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705K },
 166         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705M },
 167         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705M_ALT },
 168         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5714C },
 169         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5714S },
 170         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5715 },
 171         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5715S },
 172         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5717 },
 173         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5718 },
 174         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5719 },
 175         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5720 },
 176         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5721 },
 177         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5722 },
 178         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5723 },
 179         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5725 },
 180         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5727 },
 181         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5750 },
 182         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5750M },
 183         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751 },
 184         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751F },
 185         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751M },
 186         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5752 },
 187         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5752M },
 188         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753 },
 189         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753F },
 190         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753M },
 191         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5754 },
 192         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5754M },
 193         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5755 },
 194         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5755M },
 195         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5756 },
 196         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761 },
 197         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761E },
 198         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761S },
 199         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761SE },
 200         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5762 },
 201         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5764 },
 202         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5780 },
 203         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5780S },
 204         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5781 },
 205         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5782 },
 206         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5784 },
 207         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5785F },
 208         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5785G },
 209         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5786 },
 210         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787 },
 211         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787F },
 212         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787M },
 213         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5788 },
 214         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5789 },
 215         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5901 },
 216         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5901A2 },
 217         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5903M },
 218         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5906 },
 219         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5906M },
 220         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57760 },
 221         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57761 },
 222         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57762 },
 223         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57764 },
 224         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57765 },
 225         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57766 },
 226         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57767 },
 227         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57780 },
 228         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57781 },
 229         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57782 },
 230         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57785 },
 231         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57786 },
 232         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57787 },
 233         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57788 },
 234         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57790 },
 235         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57791 },
 236         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57795 },
 237
 238         { SK_VENDORID,          SK_DEVICEID_ALTIMA },
 239
 240         { TC_VENDORID,          TC_DEVICEID_3C996 },
 241
 242         { FJTSU_VENDORID,       FJTSU_DEVICEID_PW008GE4 },
 243         { FJTSU_VENDORID,       FJTSU_DEVICEID_PW008GE5 },
 244         { FJTSU_VENDORID,       FJTSU_DEVICEID_PP250450 },
 245
 246         { 0, 0 }
 247 };
 248
 249 static const struct bge_vendor {
 250         uint16_t        v_id;
 251         const char      *v_name;
 252 } bge_vendors[] = {
 253         { ALTEON_VENDORID,      "Alteon" },
 254         { ALTIMA_VENDORID,      "Altima" },
 255         { APPLE_VENDORID,       "Apple" },
 256         { BCOM_VENDORID,        "Broadcom" },
 257         { SK_VENDORID,          "SysKonnect" },
 258         { TC_VENDORID,          "3Com" },
 259         { FJTSU_VENDORID,       "Fujitsu" },
 260
 261         { 0, NULL }
 262 };
 263
 264 static const struct bge_revision {
 265         uint32_t        br_chipid;
 266         const char      *br_name;
 267 } bge_revisions[] = {
 268         { BGE_CHIPID_BCM5700_A0,        "BCM5700 A0" },
 269         { BGE_CHIPID_BCM5700_A1,        "BCM5700 A1" },
 270         { BGE_CHIPID_BCM5700_B0,        "BCM5700 B0" },
 271         { BGE_CHIPID_BCM5700_B1,        "BCM5700 B1" },
 272         { BGE_CHIPID_BCM5700_B2,        "BCM5700 B2" },
 273         { BGE_CHIPID_BCM5700_B3,        "BCM5700 B3" },
 274         { BGE_CHIPID_BCM5700_ALTIMA,    "BCM5700 Altima" },
 275         { BGE_CHIPID_BCM5700_C0,        "BCM5700 C0" },
 276         { BGE_CHIPID_BCM5701_A0,        "BCM5701 A0" },
 277         { BGE_CHIPID_BCM5701_B0,        "BCM5701 B0" },
 278         { BGE_CHIPID_BCM5701_B2,        "BCM5701 B2" },
 279         { BGE_CHIPID_BCM5701_B5,        "BCM5701 B5" },
 280         { BGE_CHIPID_BCM5703_A0,        "BCM5703 A0" },
 281         { BGE_CHIPID_BCM5703_A1,        "BCM5703 A1" },
 282         { BGE_CHIPID_BCM5703_A2,        "BCM5703 A2" },
 283         { BGE_CHIPID_BCM5703_A3,        "BCM5703 A3" },
 284         { BGE_CHIPID_BCM5703_B0,        "BCM5703 B0" },
 285         { BGE_CHIPID_BCM5704_A0,        "BCM5704 A0" },
 286         { BGE_CHIPID_BCM5704_A1,        "BCM5704 A1" },
 287         { BGE_CHIPID_BCM5704_A2,        "BCM5704 A2" },
 288         { BGE_CHIPID_BCM5704_A3,        "BCM5704 A3" },
 289         { BGE_CHIPID_BCM5704_B0,        "BCM5704 B0" },
 290         { BGE_CHIPID_BCM5705_A0,        "BCM5705 A0" },
 291         { BGE_CHIPID_BCM5705_A1,        "BCM5705 A1" },
 292         { BGE_CHIPID_BCM5705_A2,        "BCM5705 A2" },
 293         { BGE_CHIPID_BCM5705_A3,        "BCM5705 A3" },
 294         { BGE_CHIPID_BCM5750_A0,        "BCM5750 A0" },
 295         { BGE_CHIPID_BCM5750_A1,        "BCM5750 A1" },
 296         { BGE_CHIPID_BCM5750_A3,        "BCM5750 A3" },
 297         { BGE_CHIPID_BCM5750_B0,        "BCM5750 B0" },
 298         { BGE_CHIPID_BCM5750_B1,        "BCM5750 B1" },
 299         { BGE_CHIPID_BCM5750_C0,        "BCM5750 C0" },
 300         { BGE_CHIPID_BCM5750_C1,        "BCM5750 C1" },
 301         { BGE_CHIPID_BCM5750_C2,        "BCM5750 C2" },
 302         { BGE_CHIPID_BCM5714_A0,        "BCM5714 A0" },
 303         { BGE_CHIPID_BCM5752_A0,        "BCM5752 A0" },
 304         { BGE_CHIPID_BCM5752_A1,        "BCM5752 A1" },
 305         { BGE_CHIPID_BCM5752_A2,        "BCM5752 A2" },
 306         { BGE_CHIPID_BCM5714_B0,        "BCM5714 B0" },
 307         { BGE_CHIPID_BCM5714_B3,        "BCM5714 B3" },
 308         { BGE_CHIPID_BCM5715_A0,        "BCM5715 A0" },
 309         { BGE_CHIPID_BCM5715_A1,        "BCM5715 A1" },
 310         { BGE_CHIPID_BCM5715_A3,        "BCM5715 A3" },
 311         { BGE_CHIPID_BCM5717_A0,        "BCM5717 A0" },
 312         { BGE_CHIPID_BCM5717_B0,        "BCM5717 B0" },
 313         { BGE_CHIPID_BCM5719_A0,        "BCM5719 A0" },
 314         { BGE_CHIPID_BCM5720_A0,        "BCM5720 A0" },
 315         { BGE_CHIPID_BCM5755_A0,        "BCM5755 A0" },
 316         { BGE_CHIPID_BCM5755_A1,        "BCM5755 A1" },
 317         { BGE_CHIPID_BCM5755_A2,        "BCM5755 A2" },
 318         { BGE_CHIPID_BCM5722_A0,        "BCM5722 A0" },
 319         { BGE_CHIPID_BCM5761_A0,        "BCM5761 A0" },
 320         { BGE_CHIPID_BCM5761_A1,        "BCM5761 A1" },
 321         { BGE_CHIPID_BCM5762_A0,        "BCM5762 A0" },
 322         { BGE_CHIPID_BCM5784_A0,        "BCM5784 A0" },
 323         { BGE_CHIPID_BCM5784_A1,        "BCM5784 A1" },
 324         /* 5754 and 5787 share the same ASIC ID */
 325         { BGE_CHIPID_BCM5787_A0,        "BCM5754/5787 A0" },
 326         { BGE_CHIPID_BCM5787_A1,        "BCM5754/5787 A1" },
 327         { BGE_CHIPID_BCM5787_A2,        "BCM5754/5787 A2" },
 328         { BGE_CHIPID_BCM5906_A1,        "BCM5906 A1" },
 329         { BGE_CHIPID_BCM5906_A2,        "BCM5906 A2" },
 330         { BGE_CHIPID_BCM57765_A0,       "BCM57765 A0" },
 331         { BGE_CHIPID_BCM57765_B0,       "BCM57765 B0" },
 332         { BGE_CHIPID_BCM57780_A0,       "BCM57780 A0" },
 333         { BGE_CHIPID_BCM57780_A1,       "BCM57780 A1" },
 334
 335         { 0, NULL }
 336 };
 337
 338 /*
 339  * Some defaults for major revisions, so that newer steppings
 340  * that we don't know about have a shot at working.
 341  */
 342 static const struct bge_revision bge_majorrevs[] = {
 343         { BGE_ASICREV_BCM5700,          "unknown BCM5700" },
 344         { BGE_ASICREV_BCM5701,          "unknown BCM5701" },
 345         { BGE_ASICREV_BCM5703,          "unknown BCM5703" },
 346         { BGE_ASICREV_BCM5704,          "unknown BCM5704" },
 347         { BGE_ASICREV_BCM5705,          "unknown BCM5705" },
 348         { BGE_ASICREV_BCM5750,          "unknown BCM5750" },
 349         { BGE_ASICREV_BCM5714_A0,       "unknown BCM5714" },
 350         { BGE_ASICREV_BCM5752,          "unknown BCM5752" },
 351         { BGE_ASICREV_BCM5780,          "unknown BCM5780" },
 352         { BGE_ASICREV_BCM5714,          "unknown BCM5714" },
 353         { BGE_ASICREV_BCM5755,          "unknown BCM5755" },
 354         { BGE_ASICREV_BCM5761,          "unknown BCM5761" },
 355         { BGE_ASICREV_BCM5784,          "unknown BCM5784" },
 356         { BGE_ASICREV_BCM5785,          "unknown BCM5785" },
 357         /* 5754 and 5787 share the same ASIC ID */
 358         { BGE_ASICREV_BCM5787,          "unknown BCM5754/5787" },
 359         { BGE_ASICREV_BCM5906,          "unknown BCM5906" },
 360         { BGE_ASICREV_BCM57765,         "unknown BCM57765" },
 361         { BGE_ASICREV_BCM57766,         "unknown BCM57766" },
 362         { BGE_ASICREV_BCM57780,         "unknown BCM57780" },
 363         { BGE_ASICREV_BCM5717,          "unknown BCM5717" },
 364         { BGE_ASICREV_BCM5719,          "unknown BCM5719" },
 365         { BGE_ASICREV_BCM5720,          "unknown BCM5720" },
 366         { BGE_ASICREV_BCM5762,          "unknown BCM5762" },
 367
 368         { 0, NULL }
 369 };
 370
 371 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
 372 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
 373 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
 374 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
 375 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
 376 #define BGE_IS_5755_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
 377 #define BGE_IS_5717_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5717_PLUS)
 378 #define BGE_IS_57765_PLUS(sc)           ((sc)->bge_flags & BGE_FLAG_57765_PLUS)
 379
 380 static uint32_t bge_chipid(device_t);
 381 static const struct bge_vendor * bge_lookup_vendor(uint16_t);
 382 static const struct bge_revision * bge_lookup_rev(uint32_t);
 383
 384 typedef int     (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
 385
 386 static int bge_probe(device_t);
 387 static int bge_attach(device_t);
 388 static int bge_detach(device_t);
 389 static int bge_suspend(device_t);
 390 static int bge_resume(device_t);
 391 static void bge_release_resources(struct bge_softc *);
 392 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
 393 static int bge_dma_alloc(struct bge_softc *);
 394 static void bge_dma_free(struct bge_softc *);
 395 static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t,
 396     bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *);
 397
 398 static void bge_devinfo(struct bge_softc *);
 399 static int bge_mbox_reorder(struct bge_softc *);
 400
 401 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]);
 402 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
 403 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
 404 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
 405 static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
 406
 407 static void bge_txeof(struct bge_softc *, uint16_t);
 408 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *);
 409 static int bge_rxeof(struct bge_softc *, uint16_t, int);
 410
 411 static void bge_asf_driver_up (struct bge_softc *);
 412 static void bge_tick(void *);
 413 static void bge_stats_clear_regs(struct bge_softc *);
 414 static void bge_stats_update(struct bge_softc *);
 415 static void bge_stats_update_regs(struct bge_softc *);
 416 static struct mbuf *bge_check_short_dma(struct mbuf *);
 417 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *,
 418     uint16_t *, uint16_t *);
 419 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
 420
 421 static void bge_intr(void *);
 422 static int bge_msi_intr(void *);
 423 static void bge_intr_task(void *, int);
 424 static void bge_start_locked(struct ifnet *);
 425 static void bge_start(struct ifnet *);
 426 static int bge_ioctl(struct ifnet *, u_long, caddr_t);
 427 static void bge_init_locked(struct bge_softc *);
 428 static void bge_init(void *);
 429 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t);
 430 static void bge_stop(struct bge_softc *);
 431 static void bge_watchdog(struct bge_softc *);
 432 static int bge_shutdown(device_t);
 433 static int bge_ifmedia_upd_locked(struct ifnet *);
 434 static int bge_ifmedia_upd(struct ifnet *);
 435 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 436
 437 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
 438 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
 439
 440 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
 441 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
 442
 443 static void bge_setpromisc(struct bge_softc *);
 444 static void bge_setmulti(struct bge_softc *);
 445 static void bge_setvlan(struct bge_softc *);
 446
 447 static __inline void bge_rxreuse_std(struct bge_softc *, int);
 448 static __inline void bge_rxreuse_jumbo(struct bge_softc *, int);
 449 static int bge_newbuf_std(struct bge_softc *, int);
 450 static int bge_newbuf_jumbo(struct bge_softc *, int);
 451 static int bge_init_rx_ring_std(struct bge_softc *);
 452 static void bge_free_rx_ring_std(struct bge_softc *);
 453 static int bge_init_rx_ring_jumbo(struct bge_softc *);
 454 static void bge_free_rx_ring_jumbo(struct bge_softc *);
 455 static void bge_free_tx_ring(struct bge_softc *);
 456 static int bge_init_tx_ring(struct bge_softc *);
 457
 458 static int bge_chipinit(struct bge_softc *);
 459 static int bge_blockinit(struct bge_softc *);
 460 static uint32_t bge_dma_swap_options(struct bge_softc *);
 461
 462 static int bge_has_eaddr(struct bge_softc *);
 463 static uint32_t bge_readmem_ind(struct bge_softc *, int);
 464 static void bge_writemem_ind(struct bge_softc *, int, int);
 465 static void bge_writembx(struct bge_softc *, int, int);
 466 #ifdef notdef
 467 static uint32_t bge_readreg_ind(struct bge_softc *, int);
 468 #endif
 469 static void bge_writemem_direct(struct bge_softc *, int, int);
 470 static void bge_writereg_ind(struct bge_softc *, int, int);
 471
 472 static int bge_miibus_readreg(device_t, int, int);
 473 static int bge_miibus_writereg(device_t, int, int, int);
 474 static void bge_miibus_statchg(device_t);
 475 #ifdef DEVICE_POLLING
 476 static int bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
 477 #endif
 478
 479 #define BGE_RESET_SHUTDOWN      0
 480 #define BGE_RESET_START         1
 481 #define BGE_RESET_SUSPEND       2
 482 static void bge_sig_post_reset(struct bge_softc *, int);
 483 static void bge_sig_legacy(struct bge_softc *, int);
 484 static void bge_sig_pre_reset(struct bge_softc *, int);
 485 static void bge_stop_fw(struct bge_softc *);
 486 static int bge_reset(struct bge_softc *);
 487 static void bge_link_upd(struct bge_softc *);
 488
 489 static void bge_ape_lock_init(struct bge_softc *);
 490 static void bge_ape_read_fw_ver(struct bge_softc *);
 491 static int bge_ape_lock(struct bge_softc *, int);
 492 static void bge_ape_unlock(struct bge_softc *, int);
 493 static void bge_ape_send_event(struct bge_softc *, uint32_t);
 494 static void bge_ape_driver_state_change(struct bge_softc *, int);
 495
 496 /*
 497  * The BGE_REGISTER_DEBUG option is only for low-level debugging.  It may
 498  * leak information to untrusted users.  It is also known to cause alignment
 499  * traps on certain architectures.
 500  */
 501 #ifdef BGE_REGISTER_DEBUG
 502 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
 503 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
 504 static int bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS);
 505 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS);
 506 #endif
 507 static void bge_add_sysctls(struct bge_softc *);
 508 static void bge_add_sysctl_stats_regs(struct bge_softc *,
 509     struct sysctl_ctx_list *, struct sysctl_oid_list *);
 510 static void bge_add_sysctl_stats(struct bge_softc *, struct sysctl_ctx_list *,
 511     struct sysctl_oid_list *);
 512 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS);
 513
 514 static device_method_t bge_methods[] = {
 515         /* Device interface */
 516         DEVMETHOD(device_probe,         bge_probe),
 517         DEVMETHOD(device_attach,        bge_attach),
 518         DEVMETHOD(device_detach,        bge_detach),
 519         DEVMETHOD(device_shutdown,      bge_shutdown),
 520         DEVMETHOD(device_suspend,       bge_suspend),
 521         DEVMETHOD(device_resume,        bge_resume),
 522
 523         /* MII interface */
 524         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
 525         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
 526         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
 527
 528         DEVMETHOD_END
 529 };
 530
 531 static driver_t bge_driver = {
 532         "bge",
 533         bge_methods,
 534         sizeof(struct bge_softc)
 535 };
 536
 537 static devclass_t bge_devclass;
 538
 539 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0);
 540 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
 541
 542 static int bge_allow_asf = 1;
 543
 544 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf);
 545
 546 static SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters");
 547 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0,
 548         "Allow ASF mode if available");
 549
 550 #define SPARC64_BLADE_1500_MODEL        "SUNW,Sun-Blade-1500"
 551 #define SPARC64_BLADE_1500_PATH_BGE     "/pci@1f,700000/network@2"
 552 #define SPARC64_BLADE_2500_MODEL        "SUNW,Sun-Blade-2500"
 553 #define SPARC64_BLADE_2500_PATH_BGE     "/pci@1c,600000/network@3"
 554 #define SPARC64_OFW_SUBVENDOR           "subsystem-vendor-id"
 555
 556 static int
 557 bge_has_eaddr(struct bge_softc *sc)
 558 {
 559 #ifdef __sparc64__
 560         char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)];
 561         device_t dev;
 562         uint32_t subvendor;
 563
 564         dev = sc->bge_dev;
 565
 566         /*
 567          * The on-board BGEs found in sun4u machines aren't fitted with
 568          * an EEPROM which means that we have to obtain the MAC address
 569          * via OFW and that some tests will always fail.  We distinguish
 570          * such BGEs by the subvendor ID, which also has to be obtained
 571          * from OFW instead of the PCI configuration space as the latter
 572          * indicates Broadcom as the subvendor of the netboot interface.
 573          * For early Blade 1500 and 2500 we even have to check the OFW
 574          * device path as the subvendor ID always defaults to Broadcom
 575          * there.
 576          */
 577         if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR,
 578             &subvendor, sizeof(subvendor)) == sizeof(subvendor) &&
 579             (subvendor == FJTSU_VENDORID || subvendor == SUN_VENDORID))
 580                 return (0);
 581         memset(buf, 0, sizeof(buf));
 582         if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) {
 583                 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 &&
 584                     strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0)
 585                         return (0);
 586                 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 &&
 587                     strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0)
 588                         return (0);
 589         }
 590 #endif
 591         return (1);
 592 }
 593
 594 static uint32_t
 595 bge_readmem_ind(struct bge_softc *sc, int off)
 596 {
 597         device_t dev;
 598         uint32_t val;
 599
 600         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 601             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
 602                 return (0);
 603
 604         dev = sc->bge_dev;
 605
 606         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 607         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 608         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 609         return (val);
 610 }
 611
 612 static void
 613 bge_writemem_ind(struct bge_softc *sc, int off, int val)
 614 {
 615         device_t dev;
 616
 617         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 618             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
 619                 return;
 620
 621         dev = sc->bge_dev;
 622
 623         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 624         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 625         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 626 }
 627
 628 #ifdef notdef
 629 static uint32_t
 630 bge_readreg_ind(struct bge_softc *sc, int off)
 631 {
 632         device_t dev;
 633
 634         dev = sc->bge_dev;
 635
 636         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 637         return (pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 638 }
 639 #endif
 640
 641 static void
 642 bge_writereg_ind(struct bge_softc *sc, int off, int val)
 643 {
 644         device_t dev;
 645
 646         dev = sc->bge_dev;
 647
 648         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 649         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 650 }
 651
 652 static void
 653 bge_writemem_direct(struct bge_softc *sc, int off, int val)
 654 {
 655         CSR_WRITE_4(sc, off, val);
 656 }
 657
 658 static void
 659 bge_writembx(struct bge_softc *sc, int off, int val)
 660 {
 661         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
 662                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
 663
 664         CSR_WRITE_4(sc, off, val);
 665         if ((sc->bge_flags & BGE_FLAG_MBOX_REORDER) != 0)
 666                 CSR_READ_4(sc, off);
 667 }
 668
 669 /*
 670  * Clear all stale locks and select the lock for this driver instance.
 671  */
 672 static void
 673 bge_ape_lock_init(struct bge_softc *sc)
 674 {
 675         uint32_t bit, regbase;
 676         int i;
 677
 678         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
 679                 regbase = BGE_APE_LOCK_GRANT;
 680         else
 681                 regbase = BGE_APE_PER_LOCK_GRANT;
 682
 683         /* Clear any stale locks. */
 684         for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) {
 685                 switch (i) {
 686                 case BGE_APE_LOCK_PHY0:
 687                 case BGE_APE_LOCK_PHY1:
 688                 case BGE_APE_LOCK_PHY2:
 689                 case BGE_APE_LOCK_PHY3:
 690                         bit = BGE_APE_LOCK_GRANT_DRIVER0;
 691                         break;
 692                 default:
 693                         if (sc->bge_func_addr == 0)
 694                                 bit = BGE_APE_LOCK_GRANT_DRIVER0;
 695                         else
 696                                 bit = (1 << sc->bge_func_addr);
 697                 }
 698                 APE_WRITE_4(sc, regbase + 4 * i, bit);
 699         }
 700
 701         /* Select the PHY lock based on the device's function number. */
 702         switch (sc->bge_func_addr) {
 703         case 0:
 704                 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0;
 705                 break;
 706         case 1:
 707                 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1;
 708                 break;
 709         case 2:
 710                 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2;
 711                 break;
 712         case 3:
 713                 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3;
 714                 break;
 715         default:
 716                 device_printf(sc->bge_dev,
 717                     "PHY lock not supported on this function\n");
 718         }
 719 }
 720
 721 /*
 722  * Check for APE firmware, set flags, and print version info.
 723  */
 724 static void
 725 bge_ape_read_fw_ver(struct bge_softc *sc)
 726 {
 727         const char *fwtype;
 728         uint32_t apedata, features;
 729
 730         /* Check for a valid APE signature in shared memory. */
 731         apedata = APE_READ_4(sc, BGE_APE_SEG_SIG);
 732         if (apedata != BGE_APE_SEG_SIG_MAGIC) {
 733                 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE;
 734                 return;
 735         }
 736
 737         /* Check if APE firmware is running. */
 738         apedata = APE_READ_4(sc, BGE_APE_FW_STATUS);
 739         if ((apedata & BGE_APE_FW_STATUS_READY) == 0) {
 740                 device_printf(sc->bge_dev, "APE signature found "
 741                     "but FW status not ready! 0x%08x\n", apedata);
 742                 return;
 743         }
 744
 745         sc->bge_mfw_flags |= BGE_MFW_ON_APE;
 746
 747         /* Fetch the APE firwmare type and version. */
 748         apedata = APE_READ_4(sc, BGE_APE_FW_VERSION);
 749         features = APE_READ_4(sc, BGE_APE_FW_FEATURES);
 750         if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) {
 751                 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI;
 752                 fwtype = "NCSI";
 753         } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) {
 754                 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH;
 755                 fwtype = "DASH";
 756         } else
 757                 fwtype = "UNKN";
 758
 759         /* Print the APE firmware version. */
 760         device_printf(sc->bge_dev, "APE FW version: %s v%d.%d.%d.%d\n",
 761             fwtype,
 762             (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT,
 763             (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT,
 764             (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT,
 765             (apedata & BGE_APE_FW_VERSION_BLDMSK));
 766 }
 767
 768 static int
 769 bge_ape_lock(struct bge_softc *sc, int locknum)
 770 {
 771         uint32_t bit, gnt, req, status;
 772         int i, off;
 773
 774         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
 775                 return (0);
 776
 777         /* Lock request/grant registers have different bases. */
 778         if (sc->bge_asicrev == BGE_ASICREV_BCM5761) {
 779                 req = BGE_APE_LOCK_REQ;
 780                 gnt = BGE_APE_LOCK_GRANT;
 781         } else {
 782                 req = BGE_APE_PER_LOCK_REQ;
 783                 gnt = BGE_APE_PER_LOCK_GRANT;
 784         }
 785
 786         off = 4 * locknum;
 787
 788         switch (locknum) {
 789         case BGE_APE_LOCK_GPIO:
 790                 /* Lock required when using GPIO. */
 791                 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
 792                         return (0);
 793                 if (sc->bge_func_addr == 0)
 794                         bit = BGE_APE_LOCK_REQ_DRIVER0;
 795                 else
 796                         bit = (1 << sc->bge_func_addr);
 797                 break;
 798         case BGE_APE_LOCK_GRC:
 799                 /* Lock required to reset the device. */
 800                 if (sc->bge_func_addr == 0)
 801                         bit = BGE_APE_LOCK_REQ_DRIVER0;
 802                 else
 803                         bit = (1 << sc->bge_func_addr);
 804                 break;
 805         case BGE_APE_LOCK_MEM:
 806                 /* Lock required when accessing certain APE memory. */
 807                 if (sc->bge_func_addr == 0)
 808                         bit = BGE_APE_LOCK_REQ_DRIVER0;
 809                 else
 810                         bit = (1 << sc->bge_func_addr);
 811                 break;
 812         case BGE_APE_LOCK_PHY0:
 813         case BGE_APE_LOCK_PHY1:
 814         case BGE_APE_LOCK_PHY2:
 815         case BGE_APE_LOCK_PHY3:
 816                 /* Lock required when accessing PHYs. */
 817                 bit = BGE_APE_LOCK_REQ_DRIVER0;
 818                 break;
 819         default:
 820                 return (EINVAL);
 821         }
 822
 823         /* Request a lock. */
 824         APE_WRITE_4(sc, req + off, bit);
 825
 826         /* Wait up to 1 second to acquire lock. */
 827         for (i = 0; i < 20000; i++) {
 828                 status = APE_READ_4(sc, gnt + off);
 829                 if (status == bit)
 830                         break;
 831                 DELAY(50);
 832         }
 833
 834         /* Handle any errors. */
 835         if (status != bit) {
 836                 device_printf(sc->bge_dev, "APE lock %d request failed! "
 837                     "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n",
 838                     locknum, req + off, bit & 0xFFFF, gnt + off,
 839                     status & 0xFFFF);
 840                 /* Revoke the lock request. */
 841                 APE_WRITE_4(sc, gnt + off, bit);
 842                 return (EBUSY);
 843         }
 844
 845         return (0);
 846 }
 847
 848 static void
 849 bge_ape_unlock(struct bge_softc *sc, int locknum)
 850 {
 851         uint32_t bit, gnt;
 852         int off;
 853
 854         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
 855                 return;
 856
 857         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
 858                 gnt = BGE_APE_LOCK_GRANT;
 859         else
 860                 gnt = BGE_APE_PER_LOCK_GRANT;
 861
 862         off = 4 * locknum;
 863
 864         switch (locknum) {
 865         case BGE_APE_LOCK_GPIO:
 866                 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
 867                         return;
 868                 if (sc->bge_func_addr == 0)
 869                         bit = BGE_APE_LOCK_GRANT_DRIVER0;
 870                 else
 871                         bit = (1 << sc->bge_func_addr);
 872                 break;
 873         case BGE_APE_LOCK_GRC:
 874                 if (sc->bge_func_addr == 0)
 875                         bit = BGE_APE_LOCK_GRANT_DRIVER0;
 876                 else
 877                         bit = (1 << sc->bge_func_addr);
 878                 break;
 879         case BGE_APE_LOCK_MEM:
 880                 if (sc->bge_func_addr == 0)
 881                         bit = BGE_APE_LOCK_GRANT_DRIVER0;
 882                 else
 883                         bit = (1 << sc->bge_func_addr);
 884                 break;
 885         case BGE_APE_LOCK_PHY0:
 886         case BGE_APE_LOCK_PHY1:
 887         case BGE_APE_LOCK_PHY2:
 888         case BGE_APE_LOCK_PHY3:
 889                 bit = BGE_APE_LOCK_GRANT_DRIVER0;
 890                 break;
 891         default:
 892                 return;
 893         }
 894
 895         APE_WRITE_4(sc, gnt + off, bit);
 896 }
 897
 898 /*
 899  * Send an event to the APE firmware.
 900  */
 901 static void
 902 bge_ape_send_event(struct bge_softc *sc, uint32_t event)
 903 {
 904         uint32_t apedata;
 905         int i;
 906
 907         /* NCSI does not support APE events. */
 908         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
 909                 return;
 910
 911         /* Wait up to 1ms for APE to service previous event. */
 912         for (i = 10; i > 0; i--) {
 913                 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0)
 914                         break;
 915                 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS);
 916                 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) {
 917                         APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event |
 918                             BGE_APE_EVENT_STATUS_EVENT_PENDING);
 919                         bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
 920                         APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1);
 921                         break;
 922                 }
 923                 bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
 924                 DELAY(100);
 925         }
 926         if (i == 0)
 927                 device_printf(sc->bge_dev, "APE event 0x%08x send timed out\n",
 928                     event);
 929 }
 930
 931 static void
 932 bge_ape_driver_state_change(struct bge_softc *sc, int kind)
 933 {
 934         uint32_t apedata, event;
 935
 936         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
 937                 return;
 938
 939         switch (kind) {
 940         case BGE_RESET_START:
 941                 /* If this is the first load, clear the load counter. */
 942                 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG);
 943                 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC)
 944                         APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0);
 945                 else {
 946                         apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT);
 947                         APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata);
 948                 }
 949                 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG,
 950                     BGE_APE_HOST_SEG_SIG_MAGIC);
 951                 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN,
 952                     BGE_APE_HOST_SEG_LEN_MAGIC);
 953
 954                 /* Add some version info if bge(4) supports it. */
 955                 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID,
 956                     BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0));
 957                 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR,
 958                     BGE_APE_HOST_BEHAV_NO_PHYLOCK);
 959                 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS,
 960                     BGE_APE_HOST_HEARTBEAT_INT_DISABLE);
 961                 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
 962                     BGE_APE_HOST_DRVR_STATE_START);
 963                 event = BGE_APE_EVENT_STATUS_STATE_START;
 964                 break;
 965         case BGE_RESET_SHUTDOWN:
 966                 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
 967                     BGE_APE_HOST_DRVR_STATE_UNLOAD);
 968                 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD;
 969                 break;
 970         case BGE_RESET_SUSPEND:
 971                 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND;
 972                 break;
 973         default:
 974                 return;
 975         }
 976
 977         bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT |
 978             BGE_APE_EVENT_STATUS_STATE_CHNGE);
 979 }
 980
 981 /*
 982  * Map a single buffer address.
 983  */
 984
 985 static void
 986 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 987 {
 988         struct bge_dmamap_arg *ctx;
 989
 990         if (error)
 991                 return;
 992
 993         KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg));
 994
 995         ctx = arg;
 996         ctx->bge_busaddr = segs->ds_addr;
 997 }
 998
 999 static uint8_t
1000 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
1001 {
1002         uint32_t access, byte = 0;
1003         int i;
1004
1005         /* Lock. */
1006         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
1007         for (i = 0; i < 8000; i++) {
1008                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
1009                         break;
1010                 DELAY(20);
1011         }
1012         if (i == 8000)
1013                 return (1);
1014
1015         /* Enable access. */
1016         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
1017         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
1018
1019         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
1020         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
1021         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
1022                 DELAY(10);
1023                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
1024                         DELAY(10);
1025                         break;
1026                 }
1027         }
1028
1029         if (i == BGE_TIMEOUT * 10) {
1030                 if_printf(sc->bge_ifp, "nvram read timed out\n");
1031                 return (1);
1032         }
1033
1034         /* Get result. */
1035         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
1036
1037         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
1038
1039         /* Disable access. */
1040         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
1041
1042         /* Unlock. */
1043         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
1044         CSR_READ_4(sc, BGE_NVRAM_SWARB);
1045
1046         return (0);
1047 }
1048
1049 /*
1050  * Read a sequence of bytes from NVRAM.
1051  */
1052 static int
1053 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
1054 {
1055         int err = 0, i;
1056         uint8_t byte = 0;
1057
1058         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
1059                 return (1);
1060
1061         for (i = 0; i < cnt; i++) {
1062                 err = bge_nvram_getbyte(sc, off + i, &byte);
1063                 if (err)
1064                         break;
1065                 *(dest + i) = byte;
1066         }
1067
1068         return (err ? 1 : 0);
1069 }
1070
1071 /*
1072  * Read a byte of data stored in the EEPROM at address 'addr.' The
1073  * BCM570x supports both the traditional bitbang interface and an
1074  * auto access interface for reading the EEPROM. We use the auto
1075  * access method.
1076  */
1077 static uint8_t
1078 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
1079 {
1080         int i;
1081         uint32_t byte = 0;
1082
1083         /*
1084          * Enable use of auto EEPROM access so we can avoid
1085          * having to use the bitbang method.
1086          */
1087         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
1088
1089         /* Reset the EEPROM, load the clock period. */
1090         CSR_WRITE_4(sc, BGE_EE_ADDR,
1091             BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
1092         DELAY(20);
1093
1094         /* Issue the read EEPROM command. */
1095         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
1096
1097         /* Wait for completion */
1098         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
1099                 DELAY(10);
1100                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
1101                         break;
1102         }
1103
1104         if (i == BGE_TIMEOUT * 10) {
1105                 device_printf(sc->bge_dev, "EEPROM read timed out\n");
1106                 return (1);
1107         }
1108
1109         /* Get result. */
1110         byte = CSR_READ_4(sc, BGE_EE_DATA);
1111
1112         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
1113
1114         return (0);
1115 }
1116
1117 /*
1118  * Read a sequence of bytes from the EEPROM.
1119  */
1120 static int
1121 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
1122 {
1123         int i, error = 0;
1124         uint8_t byte = 0;
1125
1126         for (i = 0; i < cnt; i++) {
1127                 error = bge_eeprom_getbyte(sc, off + i, &byte);
1128                 if (error)
1129                         break;
1130                 *(dest + i) = byte;
1131         }
1132
1133         return (error ? 1 : 0);
1134 }
1135
1136 static int
1137 bge_miibus_readreg(device_t dev, int phy, int reg)
1138 {
1139         struct bge_softc *sc;
1140         uint32_t val;
1141         int i;
1142
1143         sc = device_get_softc(dev);
1144
1145         if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
1146                 return (0);
1147
1148         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
1149         if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1150                 CSR_WRITE_4(sc, BGE_MI_MODE,
1151                     sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
1152                 DELAY(80);
1153         }
1154
1155         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
1156             BGE_MIPHY(phy) | BGE_MIREG(reg));
1157
1158         /* Poll for the PHY register access to complete. */
1159         for (i = 0; i < BGE_TIMEOUT; i++) {
1160                 DELAY(10);
1161                 val = CSR_READ_4(sc, BGE_MI_COMM);
1162                 if ((val & BGE_MICOMM_BUSY) == 0) {
1163                         DELAY(5);
1164                         val = CSR_READ_4(sc, BGE_MI_COMM);
1165                         break;
1166                 }
1167         }
1168
1169         if (i == BGE_TIMEOUT) {
1170                 device_printf(sc->bge_dev,
1171                     "PHY read timed out (phy %d, reg %d, val 0x%08x)\n",
1172                     phy, reg, val);
1173                 val = 0;
1174         }
1175
1176         /* Restore the autopoll bit if necessary. */
1177         if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1178                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1179                 DELAY(80);
1180         }
1181
1182         bge_ape_unlock(sc, sc->bge_phy_ape_lock);
1183
1184         if (val & BGE_MICOMM_READFAIL)
1185                 return (0);
1186
1187         return (val & 0xFFFF);
1188 }
1189
1190 static int
1191 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
1192 {
1193         struct bge_softc *sc;
1194         int i;
1195
1196         sc = device_get_softc(dev);
1197
1198         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
1199             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
1200                 return (0);
1201
1202         if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
1203                 return (0);
1204
1205         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
1206         if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1207                 CSR_WRITE_4(sc, BGE_MI_MODE,
1208                     sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
1209                 DELAY(80);
1210         }
1211
1212         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
1213             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
1214
1215         for (i = 0; i < BGE_TIMEOUT; i++) {
1216                 DELAY(10);
1217                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
1218                         DELAY(5);
1219                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
1220                         break;
1221                 }
1222         }
1223
1224         /* Restore the autopoll bit if necessary. */
1225         if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1226                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1227                 DELAY(80);
1228         }
1229
1230         bge_ape_unlock(sc, sc->bge_phy_ape_lock);
1231
1232         if (i == BGE_TIMEOUT)
1233                 device_printf(sc->bge_dev,
1234                     "PHY write timed out (phy %d, reg %d, val 0x%04x)\n",
1235                     phy, reg, val);
1236
1237         return (0);
1238 }
1239
1240 static void
1241 bge_miibus_statchg(device_t dev)
1242 {
1243         struct bge_softc *sc;
1244         struct mii_data *mii;
1245         uint32_t mac_mode, rx_mode, tx_mode;
1246
1247         sc = device_get_softc(dev);
1248         if ((sc->bge_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1249                 return;
1250         mii = device_get_softc(sc->bge_miibus);
1251
1252         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1253             (IFM_ACTIVE | IFM_AVALID)) {
1254                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1255                 case IFM_10_T:
1256                 case IFM_100_TX:
1257                         sc->bge_link = 1;
1258                         break;
1259                 case IFM_1000_T:
1260                 case IFM_1000_SX:
1261                 case IFM_2500_SX:
1262                         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
1263                                 sc->bge_link = 1;
1264                         else
1265                                 sc->bge_link = 0;
1266                         break;
1267                 default:
1268                         sc->bge_link = 0;
1269                         break;
1270                 }
1271         } else
1272                 sc->bge_link = 0;
1273         if (sc->bge_link == 0)
1274                 return;
1275
1276         /*
1277          * APE firmware touches these registers to keep the MAC
1278          * connected to the outside world.  Try to keep the
1279          * accesses atomic.
1280          */
1281
1282         /* Set the port mode (MII/GMII) to match the link speed. */
1283         mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) &
1284             ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX);
1285         tx_mode = CSR_READ_4(sc, BGE_TX_MODE);
1286         rx_mode = CSR_READ_4(sc, BGE_RX_MODE);
1287
1288         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1289             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
1290                 mac_mode |= BGE_PORTMODE_GMII;
1291         else
1292                 mac_mode |= BGE_PORTMODE_MII;
1293
1294         /* Set MAC flow control behavior to match link flow control settings. */
1295         tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE;
1296         rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE;
1297         if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1298                 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1299                         tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE;
1300                 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1301                         rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE;
1302         } else
1303                 mac_mode |= BGE_MACMODE_HALF_DUPLEX;
1304
1305         CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode);
1306         DELAY(40);
1307         CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode);
1308         CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode);
1309 }
1310
1311 /*
1312  * Intialize a standard receive ring descriptor.
1313  */
1314 static int
1315 bge_newbuf_std(struct bge_softc *sc, int i)
1316 {
1317         struct mbuf *m;
1318         struct bge_rx_bd *r;
1319         bus_dma_segment_t segs[1];
1320         bus_dmamap_t map;
1321         int error, nsegs;
1322
1323         if (sc->bge_flags & BGE_FLAG_JUMBO_STD &&
1324             (sc->bge_ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN +
1325             ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) {
1326                 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
1327                 if (m == NULL)
1328                         return (ENOBUFS);
1329                 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1330         } else {
1331                 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1332                 if (m == NULL)
1333                         return (ENOBUFS);
1334                 m->m_len = m->m_pkthdr.len = MCLBYTES;
1335         }
1336         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1337                 m_adj(m, ETHER_ALIGN);
1338
1339         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag,
1340             sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0);
1341         if (error != 0) {
1342                 m_freem(m);
1343                 return (error);
1344         }
1345         if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1346                 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1347                     sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD);
1348                 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1349                     sc->bge_cdata.bge_rx_std_dmamap[i]);
1350         }
1351         map = sc->bge_cdata.bge_rx_std_dmamap[i];
1352         sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap;
1353         sc->bge_cdata.bge_rx_std_sparemap = map;
1354         sc->bge_cdata.bge_rx_std_chain[i] = m;
1355         sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len;
1356         r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
1357         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1358         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1359         r->bge_flags = BGE_RXBDFLAG_END;
1360         r->bge_len = segs[0].ds_len;
1361         r->bge_idx = i;
1362
1363         bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1364             sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD);
1365
1366         return (0);
1367 }
1368
1369 /*
1370  * Initialize a jumbo receive ring descriptor. This allocates
1371  * a jumbo buffer from the pool managed internally by the driver.
1372  */
1373 static int
1374 bge_newbuf_jumbo(struct bge_softc *sc, int i)
1375 {
1376         bus_dma_segment_t segs[BGE_NSEG_JUMBO];
1377         bus_dmamap_t map;
1378         struct bge_extrx_bd *r;
1379         struct mbuf *m;
1380         int error, nsegs;
1381
1382         MGETHDR(m, M_NOWAIT, MT_DATA);
1383         if (m == NULL)
1384                 return (ENOBUFS);
1385
1386         m_cljget(m, M_NOWAIT, MJUM9BYTES);
1387         if (!(m->m_flags & M_EXT)) {
1388                 m_freem(m);
1389                 return (ENOBUFS);
1390         }
1391         m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1392         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1393                 m_adj(m, ETHER_ALIGN);
1394
1395         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
1396             sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0);
1397         if (error != 0) {
1398                 m_freem(m);
1399                 return (error);
1400         }
1401
1402         if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1403                 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1404                     sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD);
1405                 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1406                     sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1407         }
1408         map = sc->bge_cdata.bge_rx_jumbo_dmamap[i];
1409         sc->bge_cdata.bge_rx_jumbo_dmamap[i] =
1410             sc->bge_cdata.bge_rx_jumbo_sparemap;
1411         sc->bge_cdata.bge_rx_jumbo_sparemap = map;
1412         sc->bge_cdata.bge_rx_jumbo_chain[i] = m;
1413         sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0;
1414         sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0;
1415         sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0;
1416         sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0;
1417
1418         /*
1419          * Fill in the extended RX buffer descriptor.
1420          */
1421         r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
1422         r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
1423         r->bge_idx = i;
1424         r->bge_len3 = r->bge_len2 = r->bge_len1 = 0;
1425         switch (nsegs) {
1426         case 4:
1427                 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr);
1428                 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr);
1429                 r->bge_len3 = segs[3].ds_len;
1430                 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len;
1431         case 3:
1432                 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr);
1433                 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr);
1434                 r->bge_len2 = segs[2].ds_len;
1435                 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len;
1436         case 2:
1437                 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr);
1438                 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr);
1439                 r->bge_len1 = segs[1].ds_len;
1440                 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len;
1441         case 1:
1442                 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1443                 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1444                 r->bge_len0 = segs[0].ds_len;
1445                 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len;
1446                 break;
1447         default:
1448                 panic("%s: %d segments\n", __func__, nsegs);
1449         }
1450
1451         bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1452             sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD);
1453
1454         return (0);
1455 }
1456
1457 static int
1458 bge_init_rx_ring_std(struct bge_softc *sc)
1459 {
1460         int error, i;
1461
1462         bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
1463         sc->bge_std = 0;
1464         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1465                 if ((error = bge_newbuf_std(sc, i)) != 0)
1466                         return (error);
1467                 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1468         }
1469
1470         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1471             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
1472
1473         sc->bge_std = 0;
1474         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1);
1475
1476         return (0);
1477 }
1478
1479 static void
1480 bge_free_rx_ring_std(struct bge_softc *sc)
1481 {
1482         int i;
1483
1484         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1485                 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1486                         bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1487                             sc->bge_cdata.bge_rx_std_dmamap[i],
1488                             BUS_DMASYNC_POSTREAD);
1489                         bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1490                             sc->bge_cdata.bge_rx_std_dmamap[i]);
1491                         m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1492                         sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1493                 }
1494                 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
1495                     sizeof(struct bge_rx_bd));
1496         }
1497 }
1498
1499 static int
1500 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1501 {
1502         struct bge_rcb *rcb;
1503         int error, i;
1504
1505         bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ);
1506         sc->bge_jumbo = 0;
1507         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1508                 if ((error = bge_newbuf_jumbo(sc, i)) != 0)
1509                         return (error);
1510                 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1511         }
1512
1513         bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1514             sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
1515
1516         sc->bge_jumbo = 0;
1517
1518         /* Enable the jumbo receive producer ring. */
1519         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1520         rcb->bge_maxlen_flags =
1521             BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD);
1522         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1523
1524         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1);
1525
1526         return (0);
1527 }
1528
1529 static void
1530 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1531 {
1532         int i;
1533
1534         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1535                 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1536                         bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1537                             sc->bge_cdata.bge_rx_jumbo_dmamap[i],
1538                             BUS_DMASYNC_POSTREAD);
1539                         bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1540                             sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1541                         m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1542                         sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1543                 }
1544                 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
1545                     sizeof(struct bge_extrx_bd));
1546         }
1547 }
1548
1549 static void
1550 bge_free_tx_ring(struct bge_softc *sc)
1551 {
1552         int i;
1553
1554         if (sc->bge_ldata.bge_tx_ring == NULL)
1555                 return;
1556
1557         for (i = 0; i < BGE_TX_RING_CNT; i++) {
1558                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1559                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
1560                             sc->bge_cdata.bge_tx_dmamap[i],
1561                             BUS_DMASYNC_POSTWRITE);
1562                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1563                             sc->bge_cdata.bge_tx_dmamap[i]);
1564                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
1565                         sc->bge_cdata.bge_tx_chain[i] = NULL;
1566                 }
1567                 bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
1568                     sizeof(struct bge_tx_bd));
1569         }
1570 }
1571
1572 static int
1573 bge_init_tx_ring(struct bge_softc *sc)
1574 {
1575         sc->bge_txcnt = 0;
1576         sc->bge_tx_saved_considx = 0;
1577
1578         bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
1579         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
1580             sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
1581
1582         /* Initialize transmit producer index for host-memory send ring. */
1583         sc->bge_tx_prodidx = 0;
1584         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1585
1586         /* 5700 b2 errata */
1587         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1588                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1589
1590         /* NIC-memory send ring not used; initialize to zero. */
1591         bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1592         /* 5700 b2 errata */
1593         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1594                 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1595
1596         return (0);
1597 }
1598
1599 static void
1600 bge_setpromisc(struct bge_softc *sc)
1601 {
1602         struct ifnet *ifp;
1603
1604         BGE_LOCK_ASSERT(sc);
1605
1606         ifp = sc->bge_ifp;
1607
1608         /* Enable or disable promiscuous mode as needed. */
1609         if (ifp->if_flags & IFF_PROMISC)
1610                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1611         else
1612                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1613 }
1614
1615 static void
1616 bge_setmulti(struct bge_softc *sc)
1617 {
1618         struct ifnet *ifp;
1619         struct ifmultiaddr *ifma;
1620         uint32_t hashes[4] = { 0, 0, 0, 0 };
1621         int h, i;
1622
1623         BGE_LOCK_ASSERT(sc);
1624
1625         ifp = sc->bge_ifp;
1626
1627         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1628                 for (i = 0; i < 4; i++)
1629                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1630                 return;
1631         }
1632
1633         /* First, zot all the existing filters. */
1634         for (i = 0; i < 4; i++)
1635                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1636
1637         /* Now program new ones. */
1638         if_maddr_rlock(ifp);
1639         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1640                 if (ifma->ifma_addr->sa_family != AF_LINK)
1641                         continue;
1642                 h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1643                     ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F;
1644                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1645         }
1646         if_maddr_runlock(ifp);
1647
1648         for (i = 0; i < 4; i++)
1649                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1650 }
1651
1652 static void
1653 bge_setvlan(struct bge_softc *sc)
1654 {
1655         struct ifnet *ifp;
1656
1657         BGE_LOCK_ASSERT(sc);
1658
1659         ifp = sc->bge_ifp;
1660
1661         /* Enable or disable VLAN tag stripping as needed. */
1662         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
1663                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1664         else
1665                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1666 }
1667
1668 static void
1669 bge_sig_pre_reset(struct bge_softc *sc, int type)
1670 {
1671
1672         /*
1673          * Some chips don't like this so only do this if ASF is enabled
1674          */
1675         if (sc->bge_asf_mode)
1676                 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
1677
1678         if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1679                 switch (type) {
1680                 case BGE_RESET_START:
1681                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1682                             BGE_FW_DRV_STATE_START);
1683                         break;
1684                 case BGE_RESET_SHUTDOWN:
1685                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1686                             BGE_FW_DRV_STATE_UNLOAD);
1687                         break;
1688                 case BGE_RESET_SUSPEND:
1689                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1690                             BGE_FW_DRV_STATE_SUSPEND);
1691                         break;
1692                 }
1693         }
1694
1695         if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND)
1696                 bge_ape_driver_state_change(sc, type);
1697 }
1698
1699 static void
1700 bge_sig_post_reset(struct bge_softc *sc, int type)
1701 {
1702
1703         if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1704                 switch (type) {
1705                 case BGE_RESET_START:
1706                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1707                             BGE_FW_DRV_STATE_START_DONE);
1708                         /* START DONE */
1709                         break;
1710                 case BGE_RESET_SHUTDOWN:
1711                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1712                             BGE_FW_DRV_STATE_UNLOAD_DONE);
1713                         break;
1714                 }
1715         }
1716         if (type == BGE_RESET_SHUTDOWN)
1717                 bge_ape_driver_state_change(sc, type);
1718 }
1719
1720 static void
1721 bge_sig_legacy(struct bge_softc *sc, int type)
1722 {
1723
1724         if (sc->bge_asf_mode) {
1725                 switch (type) {
1726                 case BGE_RESET_START:
1727                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1728                             BGE_FW_DRV_STATE_START);
1729                         break;
1730                 case BGE_RESET_SHUTDOWN:
1731                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1732                             BGE_FW_DRV_STATE_UNLOAD);
1733                         break;
1734                 }
1735         }
1736 }
1737
1738 static void
1739 bge_stop_fw(struct bge_softc *sc)
1740 {
1741         int i;
1742
1743         if (sc->bge_asf_mode) {
1744                 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE);
1745                 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
1746                     CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT);
1747
1748                 for (i = 0; i < 100; i++ ) {
1749                         if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) &
1750                             BGE_RX_CPU_DRV_EVENT))
1751                                 break;
1752                         DELAY(10);
1753                 }
1754         }
1755 }
1756
1757 static uint32_t
1758 bge_dma_swap_options(struct bge_softc *sc)
1759 {
1760         uint32_t dma_options;
1761
1762         dma_options = BGE_MODECTL_WORDSWAP_NONFRAME |
1763             BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA;
1764 #if BYTE_ORDER == BIG_ENDIAN
1765         dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME;
1766 #endif
1767         return (dma_options);
1768 }
1769
1770 /*
1771  * Do endian, PCI and DMA initialization.
1772  */
1773 static int
1774 bge_chipinit(struct bge_softc *sc)
1775 {
1776         uint32_t dma_rw_ctl, misc_ctl, mode_ctl;
1777         uint16_t val;
1778         int i;
1779
1780         /* Set endianness before we access any non-PCI registers. */
1781         misc_ctl = BGE_INIT;
1782         if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS)
1783                 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS;
1784         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4);
1785
1786         /*
1787          * Clear the MAC statistics block in the NIC's
1788          * internal memory.
1789          */
1790         for (i = BGE_STATS_BLOCK;
1791             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1792                 BGE_MEMWIN_WRITE(sc, i, 0);
1793
1794         for (i = BGE_STATUS_BLOCK;
1795             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1796                 BGE_MEMWIN_WRITE(sc, i, 0);
1797
1798         if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1799                 /*
1800                  *  Fix data corruption caused by non-qword write with WB.
1801                  *  Fix master abort in PCI mode.
1802                  *  Fix PCI latency timer.
1803                  */
1804                 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1805                 val |= (1 << 10) | (1 << 12) | (1 << 13);
1806                 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1807         }
1808
1809         if (sc->bge_asicrev == BGE_ASICREV_BCM57765 ||
1810             sc->bge_asicrev == BGE_ASICREV_BCM57766) {
1811                 /*
1812                  * For the 57766 and non Ax versions of 57765, bootcode
1813                  * needs to setup the PCIE Fast Training Sequence (FTS)
1814                  * value to prevent transmit hangs.
1815                  */
1816                 if (sc->bge_chiprev != BGE_CHIPREV_57765_AX) {
1817                         CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL,
1818                             CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL) |
1819                             BGE_CPMU_PADRNG_CTL_RDIV2);
1820                 }
1821         }
1822
1823         /*
1824          * Set up the PCI DMA control register.
1825          */
1826         dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) |
1827             BGE_PCIDMARWCTL_WR_CMD_SHIFT(7);
1828         if (sc->bge_flags & BGE_FLAG_PCIE) {
1829                 if (sc->bge_mps >= 256)
1830                         dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1831                 else
1832                         dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1833         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1834                 if (BGE_IS_5714_FAMILY(sc)) {
1835                         /* 256 bytes for read and write. */
1836                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
1837                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
1838                         dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
1839                             BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL :
1840                             BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1841                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1842                         /*
1843                          * In the BCM5703, the DMA read watermark should
1844                          * be set to less than or equal to the maximum
1845                          * memory read byte count of the PCI-X command
1846                          * register.
1847                          */
1848                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) |
1849                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1850                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1851                         /* 1536 bytes for read, 384 bytes for write. */
1852                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1853                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1854                 } else {
1855                         /* 384 bytes for read and write. */
1856                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
1857                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
1858                             0x0F;
1859                 }
1860                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1861                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1862                         uint32_t tmp;
1863
1864                         /* Set ONE_DMA_AT_ONCE for hardware workaround. */
1865                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
1866                         if (tmp == 6 || tmp == 7)
1867                                 dma_rw_ctl |=
1868                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1869
1870                         /* Set PCI-X DMA write workaround. */
1871                         dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1872                 }
1873         } else {
1874                 /* Conventional PCI bus: 256 bytes for read and write. */
1875                 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1876                     BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1877
1878                 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1879                     sc->bge_asicrev != BGE_ASICREV_BCM5750)
1880                         dma_rw_ctl |= 0x0F;
1881         }
1882         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1883             sc->bge_asicrev == BGE_ASICREV_BCM5701)
1884                 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1885                     BGE_PCIDMARWCTL_ASRT_ALL_BE;
1886         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1887             sc->bge_asicrev == BGE_ASICREV_BCM5704)
1888                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1889         if (BGE_IS_5717_PLUS(sc)) {
1890                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1891                 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
1892                         dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1893                 /*
1894                  * Enable HW workaround for controllers that misinterpret
1895                  * a status tag update and leave interrupts permanently
1896                  * disabled.
1897                  */
1898                 if (!BGE_IS_57765_PLUS(sc) &&
1899                     sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
1900                     sc->bge_asicrev != BGE_ASICREV_BCM5762)
1901                         dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1902         }
1903         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1904
1905         /*
1906          * Set up general mode register.
1907          */
1908         mode_ctl = bge_dma_swap_options(sc);
1909         if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
1910             sc->bge_asicrev == BGE_ASICREV_BCM5762) {
1911                 /* Retain Host-2-BMC settings written by APE firmware. */
1912                 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) &
1913                     (BGE_MODECTL_BYTESWAP_B2HRX_DATA |
1914                     BGE_MODECTL_WORDSWAP_B2HRX_DATA |
1915                     BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE);
1916         }
1917         mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
1918             BGE_MODECTL_TX_NO_PHDR_CSUM;
1919
1920         /*
1921          * BCM5701 B5 have a bug causing data corruption when using
1922          * 64-bit DMA reads, which can be terminated early and then
1923          * completed later as 32-bit accesses, in combination with
1924          * certain bridges.
1925          */
1926         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1927             sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1928                 mode_ctl |= BGE_MODECTL_FORCE_PCI32;
1929
1930         /*
1931          * Tell the firmware the driver is running
1932          */
1933         if (sc->bge_asf_mode & ASF_STACKUP)
1934                 mode_ctl |= BGE_MODECTL_STACKUP;
1935
1936         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1937
1938         /*
1939          * Disable memory write invalidate.  Apparently it is not supported
1940          * properly by these devices.  Also ensure that INTx isn't disabled,
1941          * as these chips need it even when using MSI.
1942          */
1943         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD,
1944             PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4);
1945
1946         /* Set the timer prescaler (always 66 MHz). */
1947         CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
1948
1949         /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */
1950         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1951                 DELAY(40);      /* XXX */
1952
1953                 /* Put PHY into ready state */
1954                 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1955                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1956                 DELAY(40);
1957         }
1958
1959         return (0);
1960 }
1961
1962 static int
1963 bge_blockinit(struct bge_softc *sc)
1964 {
1965         struct bge_rcb *rcb;
1966         bus_size_t vrcb;
1967         bge_hostaddr taddr;
1968         uint32_t dmactl, rdmareg, val;
1969         int i, limit;
1970
1971         /*
1972          * Initialize the memory window pointer register so that
1973          * we can access the first 32K of internal NIC RAM. This will
1974          * allow us to set up the TX send ring RCBs and the RX return
1975          * ring RCBs, plus other things which live in NIC memory.
1976          */
1977         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1978
1979         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1980
1981         if (!(BGE_IS_5705_PLUS(sc))) {
1982                 /* Configure mbuf memory pool */
1983                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1984                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1985                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1986                 else
1987                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1988
1989                 /* Configure DMA resource pool */
1990                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1991                     BGE_DMA_DESCRIPTORS);
1992                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1993         }
1994
1995         /* Configure mbuf pool watermarks */
1996         if (BGE_IS_5717_PLUS(sc)) {
1997                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1998                 if (sc->bge_ifp->if_mtu > ETHERMTU) {
1999                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
2000                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
2001                 } else {
2002                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
2003                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
2004                 }
2005         } else if (!BGE_IS_5705_PLUS(sc)) {
2006                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
2007                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
2008                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
2009         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2010                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
2011                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
2012                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
2013         } else {
2014                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
2015                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
2016                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
2017         }
2018
2019         /* Configure DMA resource watermarks */
2020         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
2021         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
2022
2023         /* Enable buffer manager */
2024         val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
2025         /*
2026          * Change the arbitration algorithm of TXMBUF read request to
2027          * round-robin instead of priority based for BCM5719.  When
2028          * TXFIFO is almost empty, RDMA will hold its request until
2029          * TXFIFO is not almost empty.
2030          */
2031         if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
2032                 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
2033         CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
2034
2035         /* Poll for buffer manager start indication */
2036         for (i = 0; i < BGE_TIMEOUT; i++) {
2037                 DELAY(10);
2038                 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
2039                         break;
2040         }
2041
2042         if (i == BGE_TIMEOUT) {
2043                 device_printf(sc->bge_dev, "buffer manager failed to start\n");
2044                 return (ENXIO);
2045         }
2046
2047         /* Enable flow-through queues */
2048         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
2049         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
2050
2051         /* Wait until queue initialization is complete */
2052         for (i = 0; i < BGE_TIMEOUT; i++) {
2053                 DELAY(10);
2054                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
2055                         break;
2056         }
2057
2058         if (i == BGE_TIMEOUT) {
2059                 device_printf(sc->bge_dev, "flow-through queue init failed\n");
2060                 return (ENXIO);
2061         }
2062
2063         /*
2064          * Summary of rings supported by the controller:
2065          *
2066          * Standard Receive Producer Ring
2067          * - This ring is used to feed receive buffers for "standard"
2068          *   sized frames (typically 1536 bytes) to the controller.
2069          *
2070          * Jumbo Receive Producer Ring
2071          * - This ring is used to feed receive buffers for jumbo sized
2072          *   frames (i.e. anything bigger than the "standard" frames)
2073          *   to the controller.
2074          *
2075          * Mini Receive Producer Ring
2076          * - This ring is used to feed receive buffers for "mini"
2077          *   sized frames to the controller.
2078          * - This feature required external memory for the controller
2079          *   but was never used in a production system.  Should always
2080          *   be disabled.
2081          *
2082          * Receive Return Ring
2083          * - After the controller has placed an incoming frame into a
2084          *   receive buffer that buffer is moved into a receive return
2085          *   ring.  The driver is then responsible to passing the
2086          *   buffer up to the stack.  Many versions of the controller
2087          *   support multiple RR rings.
2088          *
2089          * Send Ring
2090          * - This ring is used for outgoing frames.  Many versions of
2091          *   the controller support multiple send rings.
2092          */
2093
2094         /* Initialize the standard receive producer ring control block. */
2095         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
2096         rcb->bge_hostaddr.bge_addr_lo =
2097             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
2098         rcb->bge_hostaddr.bge_addr_hi =
2099             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
2100         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2101             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
2102         if (BGE_IS_5717_PLUS(sc)) {
2103                 /*
2104                  * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
2105                  * Bits 15-2 : Maximum RX frame size
2106                  * Bit 1     : 1 = Ring Disabled, 0 = Ring ENabled
2107                  * Bit 0     : Reserved
2108                  */
2109                 rcb->bge_maxlen_flags =
2110                     BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2);
2111         } else if (BGE_IS_5705_PLUS(sc)) {
2112                 /*
2113                  * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
2114                  * Bits 15-2 : Reserved (should be 0)
2115                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
2116                  * Bit 0     : Reserved
2117                  */
2118                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
2119         } else {
2120                 /*
2121                  * Ring size is always XXX entries
2122                  * Bits 31-16: Maximum RX frame size
2123                  * Bits 15-2 : Reserved (should be 0)
2124                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
2125                  * Bit 0     : Reserved
2126                  */
2127                 rcb->bge_maxlen_flags =
2128                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
2129         }
2130         if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2131             sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2132             sc->bge_asicrev == BGE_ASICREV_BCM5720)
2133                 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
2134         else
2135                 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
2136         /* Write the standard receive producer ring control block. */
2137         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
2138         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
2139         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
2140         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
2141
2142         /* Reset the standard receive producer ring producer index. */
2143         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
2144
2145         /*
2146          * Initialize the jumbo RX producer ring control
2147          * block.  We set the 'ring disabled' bit in the
2148          * flags field until we're actually ready to start
2149          * using this ring (i.e. once we set the MTU
2150          * high enough to require it).
2151          */
2152         if (BGE_IS_JUMBO_CAPABLE(sc)) {
2153                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
2154                 /* Get the jumbo receive producer ring RCB parameters. */
2155                 rcb->bge_hostaddr.bge_addr_lo =
2156                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
2157                 rcb->bge_hostaddr.bge_addr_hi =
2158                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
2159                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2160                     sc->bge_cdata.bge_rx_jumbo_ring_map,
2161                     BUS_DMASYNC_PREREAD);
2162                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
2163                     BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
2164                 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2165                     sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2166                     sc->bge_asicrev == BGE_ASICREV_BCM5720)
2167                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
2168                 else
2169                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
2170                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
2171                     rcb->bge_hostaddr.bge_addr_hi);
2172                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
2173                     rcb->bge_hostaddr.bge_addr_lo);
2174                 /* Program the jumbo receive producer ring RCB parameters. */
2175                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
2176                     rcb->bge_maxlen_flags);
2177                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
2178                 /* Reset the jumbo receive producer ring producer index. */
2179                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
2180         }
2181
2182         /* Disable the mini receive producer ring RCB. */
2183         if (BGE_IS_5700_FAMILY(sc)) {
2184                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
2185                 rcb->bge_maxlen_flags =
2186                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
2187                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
2188                     rcb->bge_maxlen_flags);
2189                 /* Reset the mini receive producer ring producer index. */
2190                 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
2191         }
2192
2193         /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
2194         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2195                 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
2196                     sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
2197                     sc->bge_chipid == BGE_CHIPID_BCM5906_A2)
2198                         CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
2199                             (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
2200         }
2201         /*
2202          * The BD ring replenish thresholds control how often the
2203          * hardware fetches new BD's from the producer rings in host
2204          * memory.  Setting the value too low on a busy system can
2205          * starve the hardware and recue the throughpout.
2206          *
2207          * Set the BD ring replentish thresholds. The recommended
2208          * values are 1/8th the number of descriptors allocated to
2209          * each ring.
2210          * XXX The 5754 requires a lower threshold, so it might be a
2211          * requirement of all 575x family chips.  The Linux driver sets
2212          * the lower threshold for all 5705 family chips as well, but there
2213          * are reports that it might not need to be so strict.
2214          *
2215          * XXX Linux does some extra fiddling here for the 5906 parts as
2216          * well.
2217          */
2218         if (BGE_IS_5705_PLUS(sc))
2219                 val = 8;
2220         else
2221                 val = BGE_STD_RX_RING_CNT / 8;
2222         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
2223         if (BGE_IS_JUMBO_CAPABLE(sc))
2224                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
2225                     BGE_JUMBO_RX_RING_CNT/8);
2226         if (BGE_IS_5717_PLUS(sc)) {
2227                 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
2228                 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
2229         }
2230
2231         /*
2232          * Disable all send rings by setting the 'ring disabled' bit
2233          * in the flags field of all the TX send ring control blocks,
2234          * located in NIC memory.
2235          */
2236         if (!BGE_IS_5705_PLUS(sc))
2237                 /* 5700 to 5704 had 16 send rings. */
2238                 limit = BGE_TX_RINGS_EXTSSRAM_MAX;
2239         else if (BGE_IS_57765_PLUS(sc) ||
2240             sc->bge_asicrev == BGE_ASICREV_BCM5762)
2241                 limit = 2;
2242         else if (BGE_IS_5717_PLUS(sc))
2243                 limit = 4;
2244         else
2245                 limit = 1;
2246         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
2247         for (i = 0; i < limit; i++) {
2248                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2249                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
2250                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2251                 vrcb += sizeof(struct bge_rcb);
2252         }
2253
2254         /* Configure send ring RCB 0 (we use only the first ring) */
2255         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
2256         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
2257         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
2258         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
2259         if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2260             sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2261             sc->bge_asicrev == BGE_ASICREV_BCM5720)
2262                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
2263         else
2264                 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
2265                     BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
2266         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2267             BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
2268
2269         /*
2270          * Disable all receive return rings by setting the
2271          * 'ring diabled' bit in the flags field of all the receive
2272          * return ring control blocks, located in NIC memory.
2273          */
2274         if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2275             sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2276             sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2277                 /* Should be 17, use 16 until we get an SRAM map. */
2278                 limit = 16;
2279         } else if (!BGE_IS_5705_PLUS(sc))
2280                 limit = BGE_RX_RINGS_MAX;
2281         else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2282             sc->bge_asicrev == BGE_ASICREV_BCM5762 ||
2283             BGE_IS_57765_PLUS(sc))
2284                 limit = 4;
2285         else
2286                 limit = 1;
2287         /* Disable all receive return rings. */
2288         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
2289         for (i = 0; i < limit; i++) {
2290                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
2291                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
2292                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2293                     BGE_RCB_FLAG_RING_DISABLED);
2294                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2295                 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
2296                     (i * (sizeof(uint64_t))), 0);
2297                 vrcb += sizeof(struct bge_rcb);
2298         }
2299
2300         /*
2301          * Set up receive return ring 0.  Note that the NIC address
2302          * for RX return rings is 0x0.  The return rings live entirely
2303          * within the host, so the nicaddr field in the RCB isn't used.
2304          */
2305         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
2306         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
2307         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
2308         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
2309         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2310         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2311             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
2312
2313         /* Set random backoff seed for TX */
2314         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
2315             (IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
2316             IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
2317             IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5]) &
2318             BGE_TX_BACKOFF_SEED_MASK);
2319
2320         /* Set inter-packet gap */
2321         val = 0x2620;
2322         if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
2323             sc->bge_asicrev == BGE_ASICREV_BCM5762)
2324                 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
2325                     (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
2326         CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
2327
2328         /*
2329          * Specify which ring to use for packets that don't match
2330          * any RX rules.
2331          */
2332         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
2333
2334         /*
2335          * Configure number of RX lists. One interrupt distribution
2336          * list, sixteen active lists, one bad frames class.
2337          */
2338         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
2339
2340         /* Inialize RX list placement stats mask. */
2341         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
2342         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
2343
2344         /* Disable host coalescing until we get it set up */
2345         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
2346
2347         /* Poll to make sure it's shut down. */
2348         for (i = 0; i < BGE_TIMEOUT; i++) {
2349                 DELAY(10);
2350                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
2351                         break;
2352         }
2353
2354         if (i == BGE_TIMEOUT) {
2355                 device_printf(sc->bge_dev,
2356                     "host coalescing engine failed to idle\n");
2357                 return (ENXIO);
2358         }
2359
2360         /* Set up host coalescing defaults */
2361         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
2362         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
2363         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
2364         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
2365         if (!(BGE_IS_5705_PLUS(sc))) {
2366                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
2367                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
2368         }
2369         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
2370         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
2371
2372         /* Set up address of statistics block */
2373         if (!(BGE_IS_5705_PLUS(sc))) {
2374                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
2375                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
2376                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
2377                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
2378                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
2379                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
2380                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
2381         }
2382
2383         /* Set up address of status block */
2384         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
2385             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
2386         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
2387             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
2388
2389         /* Set up status block size. */
2390         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2391             sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
2392                 val = BGE_STATBLKSZ_FULL;
2393                 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
2394         } else {
2395                 val = BGE_STATBLKSZ_32BYTE;
2396                 bzero(sc->bge_ldata.bge_status_block, 32);
2397         }
2398         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2399             sc->bge_cdata.bge_status_map,
2400             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2401
2402         /* Turn on host coalescing state machine */
2403         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
2404
2405         /* Turn on RX BD completion state machine and enable attentions */
2406         CSR_WRITE_4(sc, BGE_RBDC_MODE,
2407             BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
2408
2409         /* Turn on RX list placement state machine */
2410         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
2411
2412         /* Turn on RX list selector state machine. */
2413         if (!(BGE_IS_5705_PLUS(sc)))
2414                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
2415
2416         /* Turn on DMA, clear stats. */
2417         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
2418             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
2419             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
2420             BGE_MACMODE_FRMHDR_DMA_ENB;
2421
2422         if (sc->bge_flags & BGE_FLAG_TBI)
2423                 val |= BGE_PORTMODE_TBI;
2424         else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
2425                 val |= BGE_PORTMODE_GMII;
2426         else
2427                 val |= BGE_PORTMODE_MII;
2428
2429         /* Allow APE to send/receive frames. */
2430         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
2431                 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
2432
2433         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
2434         DELAY(40);
2435
2436         /* Set misc. local control, enable interrupts on attentions */
2437         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
2438
2439 #ifdef notdef
2440         /* Assert GPIO pins for PHY reset */
2441         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 |
2442             BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2);
2443         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 |
2444             BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2);
2445 #endif
2446
2447         /* Turn on DMA completion state machine */
2448         if (!(BGE_IS_5705_PLUS(sc)))
2449                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
2450
2451         val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
2452
2453         /* Enable host coalescing bug fix. */
2454         if (BGE_IS_5755_PLUS(sc))
2455                 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
2456
2457         /* Request larger DMA burst size to get better performance. */
2458         if (sc->bge_asicrev == BGE_ASICREV_BCM5785)
2459                 val |= BGE_WDMAMODE_BURST_ALL_DATA;
2460
2461         /* Turn on write DMA state machine */
2462         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
2463         DELAY(40);
2464
2465         /* Turn on read DMA state machine */
2466         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
2467
2468         if (sc->bge_asicrev == BGE_ASICREV_BCM5717)
2469                 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
2470
2471         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2472             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2473             sc->bge_asicrev == BGE_ASICREV_BCM57780)
2474                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
2475                     BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
2476                     BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
2477         if (sc->bge_flags & BGE_FLAG_PCIE)
2478                 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
2479         if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
2480                 val |= BGE_RDMAMODE_TSO4_ENABLE;
2481                 if (sc->bge_flags & BGE_FLAG_TSO3 ||
2482                     sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2483                     sc->bge_asicrev == BGE_ASICREV_BCM57780)
2484                         val |= BGE_RDMAMODE_TSO6_ENABLE;
2485         }
2486
2487         if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
2488             sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2489                 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
2490                         BGE_RDMAMODE_H2BNC_VLAN_DET;
2491                 /*
2492                  * Allow multiple outstanding read requests from
2493                  * non-LSO read DMA engine.
2494                  */
2495                 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
2496         }
2497
2498         if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2499             sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2500             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2501             sc->bge_asicrev == BGE_ASICREV_BCM57780 ||
2502             BGE_IS_5717_PLUS(sc) || BGE_IS_57765_PLUS(sc)) {
2503                 if (sc->bge_asicrev == BGE_ASICREV_BCM5762)
2504                         rdmareg = BGE_RDMA_RSRVCTRL_REG2;
2505                 else
2506                         rdmareg = BGE_RDMA_RSRVCTRL;
2507                 dmactl = CSR_READ_4(sc, rdmareg);
2508                 /*
2509                  * Adjust tx margin to prevent TX data corruption and
2510                  * fix internal FIFO overflow.
2511                  */
2512                 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 ||
2513                     sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2514                         dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
2515                             BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
2516                             BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
2517                         dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
2518                             BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
2519                             BGE_RDMA_RSRVCTRL_TXMRGN_320B;
2520                 }
2521                 /*
2522                  * Enable fix for read DMA FIFO overruns.
2523                  * The fix is to limit the number of RX BDs
2524                  * the hardware would fetch at a fime.
2525                  */
2526                 CSR_WRITE_4(sc, rdmareg, dmactl |
2527                     BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
2528         }
2529
2530         if (sc->bge_asicrev == BGE_ASICREV_BCM5719) {
2531                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2532                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2533                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
2534                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2535         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2536                 /*
2537                  * Allow 4KB burst length reads for non-LSO frames.
2538                  * Enable 512B burst length reads for buffer descriptors.
2539                  */
2540                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2541                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2542                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
2543                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2544         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2545                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2,
2546                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) |
2547                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
2548                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2549         }
2550
2551         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
2552         DELAY(40);
2553
2554         if (sc->bge_flags & BGE_FLAG_RDMA_BUG) {
2555                 for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) {
2556                         val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4);
2557                         if ((val & 0xFFFF) > BGE_FRAMELEN)
2558                                 break;
2559                         if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN)
2560                                 break;
2561                 }
2562                 if (i != BGE_NUM_RDMA_CHANNELS / 2) {
2563                         val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
2564                         if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
2565                                 val |= BGE_RDMA_TX_LENGTH_WA_5719;
2566                         else
2567                                 val |= BGE_RDMA_TX_LENGTH_WA_5720;
2568                         CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
2569                 }
2570         }
2571
2572         /* Turn on RX data completion state machine */
2573         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
2574
2575         /* Turn on RX BD initiator state machine */
2576         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
2577
2578         /* Turn on RX data and RX BD initiator state machine */
2579         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
2580
2581         /* Turn on Mbuf cluster free state machine */
2582         if (!(BGE_IS_5705_PLUS(sc)))
2583                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
2584
2585         /* Turn on send BD completion state machine */
2586         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
2587
2588         /* Turn on send data completion state machine */
2589         val = BGE_SDCMODE_ENABLE;
2590         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
2591                 val |= BGE_SDCMODE_CDELAY;
2592         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
2593
2594         /* Turn on send data initiator state machine */
2595         if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3))
2596                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
2597                     BGE_SDIMODE_HW_LSO_PRE_DMA);
2598         else
2599                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
2600
2601         /* Turn on send BD initiator state machine */
2602         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
2603
2604         /* Turn on send BD selector state machine */
2605         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
2606
2607         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
2608         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
2609             BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
2610
2611         /* ack/clear link change events */
2612         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2613             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2614             BGE_MACSTAT_LINK_CHANGED);
2615         CSR_WRITE_4(sc, BGE_MI_STS, 0);
2616
2617         /*
2618          * Enable attention when the link has changed state for
2619          * devices that use auto polling.
2620          */
2621         if (sc->bge_flags & BGE_FLAG_TBI) {
2622                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
2623         } else {
2624                 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
2625                         CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
2626                         DELAY(80);
2627                 }
2628                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2629                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
2630                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2631                             BGE_EVTENB_MI_INTERRUPT);
2632         }
2633
2634         /*
2635          * Clear any pending link state attention.
2636          * Otherwise some link state change events may be lost until attention
2637          * is cleared by bge_intr() -> bge_link_upd() sequence.
2638          * It's not necessary on newer BCM chips - perhaps enabling link
2639          * state change attentions implies clearing pending attention.
2640          */
2641         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2642             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2643             BGE_MACSTAT_LINK_CHANGED);
2644
2645         /* Enable link state change attentions. */
2646         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
2647
2648         return (0);
2649 }
2650
2651 static const struct bge_revision *
2652 bge_lookup_rev(uint32_t chipid)
2653 {
2654         const struct bge_revision *br;
2655
2656         for (br = bge_revisions; br->br_name != NULL; br++) {
2657                 if (br->br_chipid == chipid)
2658                         return (br);
2659         }
2660
2661         for (br = bge_majorrevs; br->br_name != NULL; br++) {
2662                 if (br->br_chipid == BGE_ASICREV(chipid))
2663                         return (br);
2664         }
2665
2666         return (NULL);
2667 }
2668
2669 static const struct bge_vendor *
2670 bge_lookup_vendor(uint16_t vid)
2671 {
2672         const struct bge_vendor *v;
2673
2674         for (v = bge_vendors; v->v_name != NULL; v++)
2675                 if (v->v_id == vid)
2676                         return (v);
2677
2678         return (NULL);
2679 }
2680
2681 static uint32_t
2682 bge_chipid(device_t dev)
2683 {
2684         uint32_t id;
2685
2686         id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2687             BGE_PCIMISCCTL_ASICREV_SHIFT;
2688         if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) {
2689                 /*
2690                  * Find the ASCI revision.  Different chips use different
2691                  * registers.
2692                  */
2693                 switch (pci_get_device(dev)) {
2694                 case BCOM_DEVICEID_BCM5717:
2695                 case BCOM_DEVICEID_BCM5718:
2696                 case BCOM_DEVICEID_BCM5719:
2697                 case BCOM_DEVICEID_BCM5720:
2698                 case BCOM_DEVICEID_BCM5725:
2699                 case BCOM_DEVICEID_BCM5727:
2700                 case BCOM_DEVICEID_BCM5762:
2701                 case BCOM_DEVICEID_BCM57764:
2702                 case BCOM_DEVICEID_BCM57767:
2703                 case BCOM_DEVICEID_BCM57787:
2704                         id = pci_read_config(dev,
2705                             BGE_PCI_GEN2_PRODID_ASICREV, 4);
2706                         break;
2707                 case BCOM_DEVICEID_BCM57761:
2708                 case BCOM_DEVICEID_BCM57762:
2709                 case BCOM_DEVICEID_BCM57765:
2710                 case BCOM_DEVICEID_BCM57766:
2711                 case BCOM_DEVICEID_BCM57781:
2712                 case BCOM_DEVICEID_BCM57782:
2713                 case BCOM_DEVICEID_BCM57785:
2714                 case BCOM_DEVICEID_BCM57786:
2715                 case BCOM_DEVICEID_BCM57791:
2716                 case BCOM_DEVICEID_BCM57795:
2717                         id = pci_read_config(dev,
2718                             BGE_PCI_GEN15_PRODID_ASICREV, 4);
2719                         break;
2720                 default:
2721                         id = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
2722                 }
2723         }
2724         return (id);
2725 }
2726
2727 /*
2728  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
2729  * against our list and return its name if we find a match.
2730  *
2731  * Note that since the Broadcom controller contains VPD support, we
2732  * try to get the device name string from the controller itself instead
2733  * of the compiled-in string. It guarantees we'll always announce the
2734  * right product name. We fall back to the compiled-in string when
2735  * VPD is unavailable or corrupt.
2736  */
2737 static int
2738 bge_probe(device_t dev)
2739 {
2740         char buf[96];
2741         char model[64];
2742         const struct bge_revision *br;
2743         const char *pname;
2744         struct bge_softc *sc;
2745         const struct bge_type *t = bge_devs;
2746         const struct bge_vendor *v;
2747         uint32_t id;
2748         uint16_t did, vid;
2749
2750         sc = device_get_softc(dev);
2751         sc->bge_dev = dev;
2752         vid = pci_get_vendor(dev);
2753         did = pci_get_device(dev);
2754         while(t->bge_vid != 0) {
2755                 if ((vid == t->bge_vid) && (did == t->bge_did)) {
2756                         id = bge_chipid(dev);
2757                         br = bge_lookup_rev(id);
2758                         if (bge_has_eaddr(sc) &&
2759                             pci_get_vpd_ident(dev, &pname) == 0)
2760                                 snprintf(model, sizeof(model), "%s", pname);
2761                         else {
2762                                 v = bge_lookup_vendor(vid);
2763                                 snprintf(model, sizeof(model), "%s %s",
2764                                     v != NULL ? v->v_name : "Unknown",
2765                                     br != NULL ? br->br_name :
2766                                     "NetXtreme/NetLink Ethernet Controller");
2767                         }
2768                         snprintf(buf, sizeof(buf), "%s, %sASIC rev. %#08x",
2769                             model, br != NULL ? "" : "unknown ", id);
2770                         device_set_desc_copy(dev, buf);
2771                         return (BUS_PROBE_DEFAULT);
2772                 }
2773                 t++;
2774         }
2775
2776         return (ENXIO);
2777 }
2778
2779 static void
2780 bge_dma_free(struct bge_softc *sc)
2781 {
2782         int i;
2783
2784         /* Destroy DMA maps for RX buffers. */
2785         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2786                 if (sc->bge_cdata.bge_rx_std_dmamap[i])
2787                         bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2788                             sc->bge_cdata.bge_rx_std_dmamap[i]);
2789         }
2790         if (sc->bge_cdata.bge_rx_std_sparemap)
2791                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2792                     sc->bge_cdata.bge_rx_std_sparemap);
2793
2794         /* Destroy DMA maps for jumbo RX buffers. */
2795         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2796                 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
2797                         bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2798                             sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2799         }
2800         if (sc->bge_cdata.bge_rx_jumbo_sparemap)
2801                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2802                     sc->bge_cdata.bge_rx_jumbo_sparemap);
2803
2804         /* Destroy DMA maps for TX buffers. */
2805         for (i = 0; i < BGE_TX_RING_CNT; i++) {
2806                 if (sc->bge_cdata.bge_tx_dmamap[i])
2807                         bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
2808                             sc->bge_cdata.bge_tx_dmamap[i]);
2809         }
2810
2811         if (sc->bge_cdata.bge_rx_mtag)
2812                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
2813         if (sc->bge_cdata.bge_mtag_jumbo)
2814                 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag_jumbo);
2815         if (sc->bge_cdata.bge_tx_mtag)
2816                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
2817
2818         /* Destroy standard RX ring. */
2819         if (sc->bge_cdata.bge_rx_std_ring_map)
2820                 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
2821                     sc->bge_cdata.bge_rx_std_ring_map);
2822         if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring)
2823                 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
2824                     sc->bge_ldata.bge_rx_std_ring,
2825                     sc->bge_cdata.bge_rx_std_ring_map);
2826
2827         if (sc->bge_cdata.bge_rx_std_ring_tag)
2828                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
2829
2830         /* Destroy jumbo RX ring. */
2831         if (sc->bge_cdata.bge_rx_jumbo_ring_map)
2832                 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2833                     sc->bge_cdata.bge_rx_jumbo_ring_map);
2834
2835         if (sc->bge_cdata.bge_rx_jumbo_ring_map &&
2836             sc->bge_ldata.bge_rx_jumbo_ring)
2837                 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2838                     sc->bge_ldata.bge_rx_jumbo_ring,
2839                     sc->bge_cdata.bge_rx_jumbo_ring_map);
2840
2841         if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
2842                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
2843
2844         /* Destroy RX return ring. */
2845         if (sc->bge_cdata.bge_rx_return_ring_map)
2846                 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
2847                     sc->bge_cdata.bge_rx_return_ring_map);
2848
2849         if (sc->bge_cdata.bge_rx_return_ring_map &&
2850             sc->bge_ldata.bge_rx_return_ring)
2851                 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
2852                     sc->bge_ldata.bge_rx_return_ring,
2853                     sc->bge_cdata.bge_rx_return_ring_map);
2854
2855         if (sc->bge_cdata.bge_rx_return_ring_tag)
2856                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
2857
2858         /* Destroy TX ring. */
2859         if (sc->bge_cdata.bge_tx_ring_map)
2860                 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
2861                     sc->bge_cdata.bge_tx_ring_map);
2862
2863         if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring)
2864                 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
2865                     sc->bge_ldata.bge_tx_ring,
2866                     sc->bge_cdata.bge_tx_ring_map);
2867
2868         if (sc->bge_cdata.bge_tx_ring_tag)
2869                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
2870
2871         /* Destroy status block. */
2872         if (sc->bge_cdata.bge_status_map)
2873                 bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
2874                     sc->bge_cdata.bge_status_map);
2875
2876         if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block)
2877                 bus_dmamem_free(sc->bge_cdata.bge_status_tag,
2878                     sc->bge_ldata.bge_status_block,
2879                     sc->bge_cdata.bge_status_map);
2880
2881         if (sc->bge_cdata.bge_status_tag)
2882                 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
2883
2884         /* Destroy statistics block. */
2885         if (sc->bge_cdata.bge_stats_map)
2886                 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
2887                     sc->bge_cdata.bge_stats_map);
2888
2889         if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats)
2890                 bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
2891                     sc->bge_ldata.bge_stats,
2892                     sc->bge_cdata.bge_stats_map);
2893
2894         if (sc->bge_cdata.bge_stats_tag)
2895                 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
2896
2897         if (sc->bge_cdata.bge_buffer_tag)
2898                 bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag);
2899
2900         /* Destroy the parent tag. */
2901         if (sc->bge_cdata.bge_parent_tag)
2902                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
2903 }
2904
2905 static int
2906 bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment,
2907     bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map,
2908     bus_addr_t *paddr, const char *msg)
2909 {
2910         struct bge_dmamap_arg ctx;
2911         int error;
2912
2913         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2914             alignment, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2915             NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag);
2916         if (error != 0) {
2917                 device_printf(sc->bge_dev,
2918                     "could not create %s dma tag\n", msg);
2919                 return (ENOMEM);
2920         }
2921         /* Allocate DMA'able memory for ring. */
2922         error = bus_dmamem_alloc(*tag, (void **)ring,
2923             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map);
2924         if (error != 0) {
2925                 device_printf(sc->bge_dev,
2926                     "could not allocate DMA'able memory for %s\n", msg);
2927                 return (ENOMEM);
2928         }
2929         /* Load the address of the ring. */
2930         ctx.bge_busaddr = 0;
2931         error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr,
2932             &ctx, BUS_DMA_NOWAIT);
2933         if (error != 0) {
2934                 device_printf(sc->bge_dev,
2935                     "could not load DMA'able memory for %s\n", msg);
2936                 return (ENOMEM);
2937         }
2938         *paddr = ctx.bge_busaddr;
2939         return (0);
2940 }
2941
2942 static int
2943 bge_dma_alloc(struct bge_softc *sc)
2944 {
2945         bus_addr_t lowaddr;
2946         bus_size_t rxmaxsegsz, sbsz, txsegsz, txmaxsegsz;
2947         int i, error;
2948
2949         lowaddr = BUS_SPACE_MAXADDR;
2950         if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0)
2951                 lowaddr = BGE_DMA_MAXADDR;
2952         /*
2953          * Allocate the parent bus DMA tag appropriate for PCI.
2954          */
2955         error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
2956             1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
2957             NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
2958             0, NULL, NULL, &sc->bge_cdata.bge_parent_tag);
2959         if (error != 0) {
2960                 device_printf(sc->bge_dev,
2961                     "could not allocate parent dma tag\n");
2962                 return (ENOMEM);
2963         }
2964
2965         /* Create tag for standard RX ring. */
2966         error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ,
2967             &sc->bge_cdata.bge_rx_std_ring_tag,
2968             (uint8_t **)&sc->bge_ldata.bge_rx_std_ring,
2969             &sc->bge_cdata.bge_rx_std_ring_map,
2970             &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring");
2971         if (error)
2972                 return (error);
2973
2974         /* Create tag for RX return ring. */
2975         error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc),
2976             &sc->bge_cdata.bge_rx_return_ring_tag,
2977             (uint8_t **)&sc->bge_ldata.bge_rx_return_ring,
2978             &sc->bge_cdata.bge_rx_return_ring_map,
2979             &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring");
2980         if (error)
2981                 return (error);
2982
2983         /* Create tag for TX ring. */
2984         error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ,
2985             &sc->bge_cdata.bge_tx_ring_tag,
2986             (uint8_t **)&sc->bge_ldata.bge_tx_ring,
2987             &sc->bge_cdata.bge_tx_ring_map,
2988             &sc->bge_ldata.bge_tx_ring_paddr, "TX ring");
2989         if (error)
2990                 return (error);
2991
2992         /*
2993          * Create tag for status block.
2994          * Because we only use single Tx/Rx/Rx return ring, use
2995          * minimum status block size except BCM5700 AX/BX which
2996          * seems to want to see full status block size regardless
2997          * of configured number of ring.
2998          */
2999         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3000             sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
3001                 sbsz = BGE_STATUS_BLK_SZ;
3002         else
3003                 sbsz = 32;
3004         error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz,
3005             &sc->bge_cdata.bge_status_tag,
3006             (uint8_t **)&sc->bge_ldata.bge_status_block,
3007             &sc->bge_cdata.bge_status_map,
3008             &sc->bge_ldata.bge_status_block_paddr, "status block");
3009         if (error)
3010                 return (error);
3011
3012         /* Create tag for statistics block. */
3013         error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ,
3014             &sc->bge_cdata.bge_stats_tag,
3015             (uint8_t **)&sc->bge_ldata.bge_stats,
3016             &sc->bge_cdata.bge_stats_map,
3017             &sc->bge_ldata.bge_stats_paddr, "statistics block");
3018         if (error)
3019                 return (error);
3020
3021         /* Create tag for jumbo RX ring. */
3022         if (BGE_IS_JUMBO_CAPABLE(sc)) {
3023                 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ,
3024                     &sc->bge_cdata.bge_rx_jumbo_ring_tag,
3025                     (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring,
3026                     &sc->bge_cdata.bge_rx_jumbo_ring_map,
3027                     &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring");
3028                 if (error)
3029                         return (error);
3030         }
3031
3032         /* Create parent tag for buffers. */
3033         if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) {
3034                 /*
3035                  * XXX
3036                  * watchdog timeout issue was observed on BCM5704 which
3037                  * lives behind PCI-X bridge(e.g AMD 8131 PCI-X bridge).
3038                  * Both limiting DMA address space to 32bits and flushing
3039                  * mailbox write seem to address the issue.
3040                  */
3041                 if (sc->bge_pcixcap != 0)
3042                         lowaddr = BUS_SPACE_MAXADDR_32BIT;
3043         }
3044         error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 1, 0, lowaddr,
3045             BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0,
3046             BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL,
3047             &sc->bge_cdata.bge_buffer_tag);
3048         if (error != 0) {
3049                 device_printf(sc->bge_dev,
3050                     "could not allocate buffer dma tag\n");
3051                 return (ENOMEM);
3052         }
3053         /* Create tag for Tx mbufs. */
3054         if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
3055                 txsegsz = BGE_TSOSEG_SZ;
3056                 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header);
3057         } else {
3058                 txsegsz = MCLBYTES;
3059                 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW;
3060         }
3061         error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1,
3062             0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
3063             txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL,
3064             &sc->bge_cdata.bge_tx_mtag);
3065
3066         if (error) {
3067                 device_printf(sc->bge_dev, "could not allocate TX dma tag\n");
3068                 return (ENOMEM);
3069         }
3070
3071         /* Create tag for Rx mbufs. */
3072         if (sc->bge_flags & BGE_FLAG_JUMBO_STD)
3073                 rxmaxsegsz = MJUM9BYTES;
3074         else
3075                 rxmaxsegsz = MCLBYTES;
3076         error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0,
3077             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, rxmaxsegsz, 1,
3078             rxmaxsegsz, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag);
3079
3080         if (error) {
3081                 device_printf(sc->bge_dev, "could not allocate RX dma tag\n");
3082                 return (ENOMEM);
3083         }
3084
3085         /* Create DMA maps for RX buffers. */
3086         error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
3087             &sc->bge_cdata.bge_rx_std_sparemap);
3088         if (error) {
3089                 device_printf(sc->bge_dev,
3090                     "can't create spare DMA map for RX\n");
3091                 return (ENOMEM);
3092         }
3093         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3094                 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
3095                             &sc->bge_cdata.bge_rx_std_dmamap[i]);
3096                 if (error) {
3097                         device_printf(sc->bge_dev,
3098                             "can't create DMA map for RX\n");
3099                         return (ENOMEM);
3100                 }
3101         }
3102
3103         /* Create DMA maps for TX buffers. */
3104         for (i = 0; i < BGE_TX_RING_CNT; i++) {
3105                 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0,
3106                             &sc->bge_cdata.bge_tx_dmamap[i]);
3107                 if (error) {
3108                         device_printf(sc->bge_dev,
3109                             "can't create DMA map for TX\n");
3110                         return (ENOMEM);
3111                 }
3112         }
3113
3114         /* Create tags for jumbo RX buffers. */
3115         if (BGE_IS_JUMBO_CAPABLE(sc)) {
3116                 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag,
3117                     1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
3118                     NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE,
3119                     0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
3120                 if (error) {
3121                         device_printf(sc->bge_dev,
3122                             "could not allocate jumbo dma tag\n");
3123                         return (ENOMEM);
3124                 }
3125                 /* Create DMA maps for jumbo RX buffers. */
3126                 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
3127                     0, &sc->bge_cdata.bge_rx_jumbo_sparemap);
3128                 if (error) {
3129                         device_printf(sc->bge_dev,
3130                             "can't create spare DMA map for jumbo RX\n");
3131                         return (ENOMEM);
3132                 }
3133                 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
3134                         error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
3135                                     0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
3136                         if (error) {
3137                                 device_printf(sc->bge_dev,
3138                                     "can't create DMA map for jumbo RX\n");
3139                                 return (ENOMEM);
3140                         }
3141                 }
3142         }
3143
3144         return (0);
3145 }
3146
3147 /*
3148  * Return true if this device has more than one port.
3149  */
3150 static int
3151 bge_has_multiple_ports(struct bge_softc *sc)
3152 {
3153         device_t dev = sc->bge_dev;
3154         u_int b, d, f, fscan, s;
3155
3156         d = pci_get_domain(dev);
3157         b = pci_get_bus(dev);
3158         s = pci_get_slot(dev);
3159         f = pci_get_function(dev);
3160         for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++)
3161                 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL)
3162                         return (1);
3163         return (0);
3164 }
3165
3166 /*
3167  * Return true if MSI can be used with this device.
3168  */
3169 static int
3170 bge_can_use_msi(struct bge_softc *sc)
3171 {
3172         int can_use_msi = 0;
3173
3174         if (sc->bge_msi == 0)
3175                 return (0);
3176
3177         /* Disable MSI for polling(4). */
3178 #ifdef DEVICE_POLLING
3179         return (0);
3180 #endif
3181         switch (sc->bge_asicrev) {
3182         case BGE_ASICREV_BCM5714_A0:
3183         case BGE_ASICREV_BCM5714:
3184                 /*
3185                  * Apparently, MSI doesn't work when these chips are
3186                  * configured in single-port mode.
3187                  */
3188                 if (bge_has_multiple_ports(sc))
3189                         can_use_msi = 1;
3190                 break;
3191         case BGE_ASICREV_BCM5750:
3192                 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX &&
3193                     sc->bge_chiprev != BGE_CHIPREV_5750_BX)
3194                         can_use_msi = 1;
3195                 break;
3196         default:
3197                 if (BGE_IS_575X_PLUS(sc))
3198                         can_use_msi = 1;
3199         }
3200         return (can_use_msi);
3201 }
3202
3203 static int
3204 bge_mbox_reorder(struct bge_softc *sc)
3205 {
3206         /* Lists of PCI bridges that are known to reorder mailbox writes. */
3207         static const struct mbox_reorder {
3208                 const uint16_t vendor;
3209                 const uint16_t device;
3210                 const char *desc;
3211         } mbox_reorder_lists[] = {
3212                 { 0x1022, 0x7450, "AMD-8131 PCI-X Bridge" },
3213         };
3214         devclass_t pci, pcib;
3215         device_t bus, dev;
3216         int i;
3217
3218         pci = devclass_find("pci");
3219         pcib = devclass_find("pcib");
3220         dev = sc->bge_dev;
3221         bus = device_get_parent(dev);
3222         for (;;) {
3223                 dev = device_get_parent(bus);
3224                 bus = device_get_parent(dev);
3225                 if (device_get_devclass(dev) != pcib)
3226                         break;
3227                 for (i = 0; i < nitems(mbox_reorder_lists); i++) {
3228                         if (pci_get_vendor(dev) ==
3229                             mbox_reorder_lists[i].vendor &&
3230                             pci_get_device(dev) ==
3231                             mbox_reorder_lists[i].device) {
3232                                 device_printf(sc->bge_dev,
3233                                     "enabling MBOX workaround for %s\n",
3234                                     mbox_reorder_lists[i].desc);
3235                                 return (1);
3236                         }
3237                 }
3238                 if (device_get_devclass(bus) != pci)
3239                         break;
3240         }
3241         return (0);
3242 }
3243
3244 static void
3245 bge_devinfo(struct bge_softc *sc)
3246 {
3247         uint32_t cfg, clk;
3248
3249         device_printf(sc->bge_dev,
3250             "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; ",
3251             sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev);
3252         if (sc->bge_flags & BGE_FLAG_PCIE)
3253                 printf("PCI-E\n");
3254         else if (sc->bge_flags & BGE_FLAG_PCIX) {
3255                 printf("PCI-X ");
3256                 cfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
3257                 if (cfg == BGE_MISCCFG_BOARD_ID_5704CIOBE)
3258                         clk = 133;
3259                 else {
3260                         clk = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
3261                         switch (clk) {
3262                         case 0:
3263                                 clk = 33;
3264                                 break;
3265                         case 2:
3266                                 clk = 50;
3267                                 break;
3268                         case 4:
3269                                 clk = 66;
3270                                 break;
3271                         case 6:
3272                                 clk = 100;
3273                                 break;
3274                         case 7:
3275                                 clk = 133;
3276                                 break;
3277                         }
3278                 }
3279                 printf("%u MHz\n", clk);
3280         } else {
3281                 if (sc->bge_pcixcap != 0)
3282                         printf("PCI on PCI-X ");
3283                 else
3284                         printf("PCI ");
3285                 cfg = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4);
3286                 if (cfg & BGE_PCISTATE_PCI_BUSSPEED)
3287                         clk = 66;
3288                 else
3289                         clk = 33;
3290                 if (cfg & BGE_PCISTATE_32BIT_BUS)
3291                         printf("%u MHz; 32bit\n", clk);
3292                 else
3293                         printf("%u MHz; 64bit\n", clk);
3294         }
3295 }
3296
3297 static int
3298 bge_attach(device_t dev)
3299 {
3300         struct ifnet *ifp;
3301         struct bge_softc *sc;
3302         uint32_t hwcfg = 0, misccfg, pcistate;
3303         u_char eaddr[ETHER_ADDR_LEN];
3304         int capmask, error, msicount, reg, rid, trys;
3305
3306         sc = device_get_softc(dev);
3307         sc->bge_dev = dev;
3308
3309         BGE_LOCK_INIT(sc, device_get_nameunit(dev));
3310         TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc);
3311         callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
3312
3313         /*
3314          * Map control/status registers.
3315          */
3316         pci_enable_busmaster(dev);
3317
3318         rid = PCIR_BAR(0);
3319         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
3320             RF_ACTIVE);
3321
3322         if (sc->bge_res == NULL) {
3323                 device_printf (sc->bge_dev, "couldn't map BAR0 memory\n");
3324                 error = ENXIO;
3325                 goto fail;
3326         }
3327
3328         /* Save various chip information. */
3329         sc->bge_func_addr = pci_get_function(dev);
3330         sc->bge_chipid = bge_chipid(dev);
3331         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
3332         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
3333
3334         /* Set default PHY address. */
3335         sc->bge_phy_addr = 1;
3336          /*
3337           * PHY address mapping for various devices.
3338           *
3339           *          | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
3340           * ---------+-------+-------+-------+-------+
3341           * BCM57XX  |   1   |   X   |   X   |   X   |
3342           * BCM5704  |   1   |   X   |   1   |   X   |
3343           * BCM5717  |   1   |   8   |   2   |   9   |
3344           * BCM5719  |   1   |   8   |   2   |   9   |
3345           * BCM5720  |   1   |   8   |   2   |   9   |
3346           *
3347           *          | F2 Cu | F2 Sr | F3 Cu | F3 Sr |
3348           * ---------+-------+-------+-------+-------+
3349           * BCM57XX  |   X   |   X   |   X   |   X   |
3350           * BCM5704  |   X   |   X   |   X   |   X   |
3351           * BCM5717  |   X   |   X   |   X   |   X   |
3352           * BCM5719  |   3   |   10  |   4   |   11  |
3353           * BCM5720  |   X   |   X   |   X   |   X   |
3354           *
3355           * Other addresses may respond but they are not
3356           * IEEE compliant PHYs and should be ignored.
3357           */
3358         if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
3359             sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3360             sc->bge_asicrev == BGE_ASICREV_BCM5720) {
3361                 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) {
3362                         if (CSR_READ_4(sc, BGE_SGDIG_STS) &
3363                             BGE_SGDIGSTS_IS_SERDES)
3364                                 sc->bge_phy_addr = sc->bge_func_addr + 8;
3365                         else
3366                                 sc->bge_phy_addr = sc->bge_func_addr + 1;
3367                 } else {
3368                         if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
3369                             BGE_CPMU_PHY_STRAP_IS_SERDES)
3370                                 sc->bge_phy_addr = sc->bge_func_addr + 8;
3371                         else
3372                                 sc->bge_phy_addr = sc->bge_func_addr + 1;
3373                 }
3374         }
3375
3376         if (bge_has_eaddr(sc))
3377                 sc->bge_flags |= BGE_FLAG_EADDR;
3378
3379         /* Save chipset family. */
3380         switch (sc->bge_asicrev) {
3381         case BGE_ASICREV_BCM5762:
3382         case BGE_ASICREV_BCM57765:
3383         case BGE_ASICREV_BCM57766:
3384                 sc->bge_flags |= BGE_FLAG_57765_PLUS;
3385                 /* FALLTHROUGH */
3386         case BGE_ASICREV_BCM5717:
3387         case BGE_ASICREV_BCM5719:
3388         case BGE_ASICREV_BCM5720:
3389                 sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS |
3390                     BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO |
3391                     BGE_FLAG_JUMBO_FRAME;
3392                 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3393                     sc->bge_asicrev == BGE_ASICREV_BCM5720) {
3394                         /*
3395                          * Enable work around for DMA engine miscalculation
3396                          * of TXMBUF available space.
3397                          */
3398                         sc->bge_flags |= BGE_FLAG_RDMA_BUG;
3399                         if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
3400                             sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
3401                                 /* Jumbo frame on BCM5719 A0 does not work. */
3402                                 sc->bge_flags &= ~BGE_FLAG_JUMBO;
3403                         }
3404                 }
3405                 break;
3406         case BGE_ASICREV_BCM5755:
3407         case BGE_ASICREV_BCM5761:
3408         case BGE_ASICREV_BCM5784:
3409         case BGE_ASICREV_BCM5785:
3410         case BGE_ASICREV_BCM5787:
3411         case BGE_ASICREV_BCM57780:
3412                 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
3413                     BGE_FLAG_5705_PLUS;
3414                 break;
3415         case BGE_ASICREV_BCM5700:
3416         case BGE_ASICREV_BCM5701:
3417         case BGE_ASICREV_BCM5703:
3418         case BGE_ASICREV_BCM5704:
3419                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
3420                 break;
3421         case BGE_ASICREV_BCM5714_A0:
3422         case BGE_ASICREV_BCM5780:
3423         case BGE_ASICREV_BCM5714:
3424                 sc->bge_flags |= BGE_FLAG_5714_FAMILY | BGE_FLAG_JUMBO_STD;
3425                 /* FALLTHROUGH */
3426         case BGE_ASICREV_BCM5750:
3427         case BGE_ASICREV_BCM5752:
3428         case BGE_ASICREV_BCM5906:
3429                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
3430                 /* FALLTHROUGH */
3431         case BGE_ASICREV_BCM5705:
3432                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
3433                 break;
3434         }
3435
3436         /* Identify chips with APE processor. */
3437         switch (sc->bge_asicrev) {
3438         case BGE_ASICREV_BCM5717:
3439         case BGE_ASICREV_BCM5719:
3440         case BGE_ASICREV_BCM5720:
3441         case BGE_ASICREV_BCM5761:
3442         case BGE_ASICREV_BCM5762:
3443                 sc->bge_flags |= BGE_FLAG_APE;
3444                 break;
3445         }
3446
3447         /* Chips with APE need BAR2 access for APE registers/memory. */
3448         if ((sc->bge_flags & BGE_FLAG_APE) != 0) {
3449                 rid = PCIR_BAR(2);
3450                 sc->bge_res2 = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
3451                     RF_ACTIVE);
3452                 if (sc->bge_res2 == NULL) {
3453                         device_printf (sc->bge_dev,
3454                             "couldn't map BAR2 memory\n");
3455                         error = ENXIO;
3456                         goto fail;
3457                 }
3458
3459                 /* Enable APE register/memory access by host driver. */
3460                 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
3461                 pcistate |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
3462                     BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
3463                     BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
3464                 pci_write_config(dev, BGE_PCI_PCISTATE, pcistate, 4);
3465
3466                 bge_ape_lock_init(sc);
3467                 bge_ape_read_fw_ver(sc);
3468         }
3469
3470         /* Add SYSCTLs, requires the chipset family to be set. */
3471         bge_add_sysctls(sc);
3472
3473         /* Identify the chips that use an CPMU. */
3474         if (BGE_IS_5717_PLUS(sc) ||
3475             sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
3476             sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
3477             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
3478             sc->bge_asicrev == BGE_ASICREV_BCM57780)
3479                 sc->bge_flags |= BGE_FLAG_CPMU_PRESENT;
3480         if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0)
3481                 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
3482         else
3483                 sc->bge_mi_mode = BGE_MIMODE_BASE;
3484         /* Enable auto polling for BCM570[0-5]. */
3485         if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705)
3486                 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL;
3487
3488         /*
3489          * All Broadcom controllers have 4GB boundary DMA bug.
3490          * Whenever an address crosses a multiple of the 4GB boundary
3491          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3492          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3493          * state machine will lockup and cause the device to hang.
3494          */
3495         sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG;
3496
3497         /* BCM5755 or higher and BCM5906 have short DMA bug. */
3498         if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
3499                 sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG;
3500
3501         /*
3502          * BCM5719 cannot handle DMA requests for DMA segments that
3503          * have larger than 4KB in size.  However the maximum DMA
3504          * segment size created in DMA tag is 4KB for TSO, so we
3505          * wouldn't encounter the issue here.
3506          */
3507         if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
3508                 sc->bge_flags |= BGE_FLAG_4K_RDMA_BUG;
3509
3510         misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
3511         if (sc->bge_asicrev == BGE_ASICREV_BCM5705) {
3512                 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
3513                     misccfg == BGE_MISCCFG_BOARD_ID_5788M)
3514                         sc->bge_flags |= BGE_FLAG_5788;
3515         }
3516
3517         capmask = BMSR_DEFCAPMASK;
3518         if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 &&
3519             (misccfg == 0x4000 || misccfg == 0x8000)) ||
3520             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
3521             pci_get_vendor(dev) == BCOM_VENDORID &&
3522             (pci_get_device(dev) == BCOM_DEVICEID_BCM5901 ||
3523             pci_get_device(dev) == BCOM_DEVICEID_BCM5901A2 ||
3524             pci_get_device(dev) == BCOM_DEVICEID_BCM5705F)) ||
3525             (pci_get_vendor(dev) == BCOM_VENDORID &&
3526             (pci_get_device(dev) == BCOM_DEVICEID_BCM5751F ||
3527             pci_get_device(dev) == BCOM_DEVICEID_BCM5753F ||
3528             pci_get_device(dev) == BCOM_DEVICEID_BCM5787F)) ||
3529             pci_get_device(dev) == BCOM_DEVICEID_BCM57790 ||
3530             pci_get_device(dev) == BCOM_DEVICEID_BCM57791 ||
3531             pci_get_device(dev) == BCOM_DEVICEID_BCM57795 ||
3532             sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3533                 /* These chips are 10/100 only. */
3534                 capmask &= ~BMSR_EXTSTAT;
3535                 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3536         }
3537
3538         /*
3539          * Some controllers seem to require a special firmware to use
3540          * TSO. But the firmware is not available to FreeBSD and Linux
3541          * claims that the TSO performed by the firmware is slower than
3542          * hardware based TSO. Moreover the firmware based TSO has one
3543          * known bug which can't handle TSO if Ethernet header + IP/TCP
3544          * header is greater than 80 bytes. A workaround for the TSO
3545          * bug exist but it seems it's too expensive than not using
3546          * TSO at all. Some hardwares also have the TSO bug so limit
3547          * the TSO to the controllers that are not affected TSO issues
3548          * (e.g. 5755 or higher).
3549          */
3550         if (BGE_IS_5717_PLUS(sc)) {
3551                 /* BCM5717 requires different TSO configuration. */
3552                 sc->bge_flags |= BGE_FLAG_TSO3;
3553                 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
3554                     sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
3555                         /* TSO on BCM5719 A0 does not work. */
3556                         sc->bge_flags &= ~BGE_FLAG_TSO3;
3557                 }
3558         } else if (BGE_IS_5755_PLUS(sc)) {
3559                 /*
3560                  * BCM5754 and BCM5787 shares the same ASIC id so
3561                  * explicit device id check is required.
3562                  * Due to unknown reason TSO does not work on BCM5755M.
3563                  */
3564                 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 &&
3565                     pci_get_device(dev) != BCOM_DEVICEID_BCM5754M &&
3566                     pci_get_device(dev) != BCOM_DEVICEID_BCM5755M)
3567                         sc->bge_flags |= BGE_FLAG_TSO;
3568         }
3569
3570         /*
3571          * Check if this is a PCI-X or PCI Express device.
3572          */
3573         if (pci_find_cap(dev, PCIY_EXPRESS, &reg) == 0) {
3574                 /*
3575                  * Found a PCI Express capabilities register, this
3576                  * must be a PCI Express device.
3577                  */
3578                 sc->bge_flags |= BGE_FLAG_PCIE;
3579                 sc->bge_expcap = reg;
3580                 /* Extract supported maximum payload size. */
3581                 sc->bge_mps = pci_read_config(dev, sc->bge_expcap +
3582                     PCIER_DEVICE_CAP, 2);
3583                 sc->bge_mps = 128 << (sc->bge_mps & PCIEM_CAP_MAX_PAYLOAD);
3584                 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3585                     sc->bge_asicrev == BGE_ASICREV_BCM5720)
3586                         sc->bge_expmrq = 2048;
3587                 else
3588                         sc->bge_expmrq = 4096;
3589                 pci_set_max_read_req(dev, sc->bge_expmrq);
3590         } else {
3591                 /*
3592                  * Check if the device is in PCI-X Mode.
3593                  * (This bit is not valid on PCI Express controllers.)
3594                  */
3595                 if (pci_find_cap(dev, PCIY_PCIX, &reg) == 0)
3596                         sc->bge_pcixcap = reg;
3597                 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
3598                     BGE_PCISTATE_PCI_BUSMODE) == 0)
3599                         sc->bge_flags |= BGE_FLAG_PCIX;
3600         }
3601
3602         /*
3603          * The 40bit DMA bug applies to the 5714/5715 controllers and is
3604          * not actually a MAC controller bug but an issue with the embedded
3605          * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
3606          */
3607         if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
3608                 sc->bge_flags |= BGE_FLAG_40BIT_BUG;
3609         /*
3610          * Some PCI-X bridges are known to trigger write reordering to
3611          * the mailbox registers. Typical phenomena is watchdog timeouts
3612          * caused by out-of-order TX completions.  Enable workaround for
3613          * PCI-X devices that live behind these bridges.
3614          * Note, PCI-X controllers can run in PCI mode so we can't use
3615          * BGE_FLAG_PCIX flag to detect PCI-X controllers.
3616          */
3617         if (sc->bge_pcixcap != 0 && bge_mbox_reorder(sc) != 0)
3618                 sc->bge_flags |= BGE_FLAG_MBOX_REORDER;
3619         /*
3620          * Allocate the interrupt, using MSI if possible.  These devices
3621          * support 8 MSI messages, but only the first one is used in
3622          * normal operation.
3623          */
3624         rid = 0;
3625         if (pci_find_cap(sc->bge_dev, PCIY_MSI, &reg) == 0) {
3626                 sc->bge_msicap = reg;
3627                 if (bge_can_use_msi(sc)) {
3628                         msicount = pci_msi_count(dev);
3629                         if (msicount > 1)
3630                                 msicount = 1;
3631                 } else
3632                         msicount = 0;
3633                 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) {
3634                         rid = 1;
3635                         sc->bge_flags |= BGE_FLAG_MSI;
3636                 }
3637         }
3638
3639         /*
3640          * All controllers except BCM5700 supports tagged status but
3641          * we use tagged status only for MSI case on BCM5717. Otherwise
3642          * MSI on BCM5717 does not work.
3643          */
3644 #ifndef DEVICE_POLLING
3645         if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc))
3646                 sc->bge_flags |= BGE_FLAG_TAGGED_STATUS;
3647 #endif
3648
3649         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
3650             RF_SHAREABLE | RF_ACTIVE);
3651
3652         if (sc->bge_irq == NULL) {
3653                 device_printf(sc->bge_dev, "couldn't map interrupt\n");
3654                 error = ENXIO;
3655                 goto fail;
3656         }
3657
3658         bge_devinfo(sc);
3659
3660         sc->bge_asf_mode = 0;
3661         /* No ASF if APE present. */
3662         if ((sc->bge_flags & BGE_FLAG_APE) == 0) {
3663                 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) ==
3664                     BGE_SRAM_DATA_SIG_MAGIC)) {
3665                         if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) &
3666                             BGE_HWCFG_ASF) {
3667                                 sc->bge_asf_mode |= ASF_ENABLE;
3668                                 sc->bge_asf_mode |= ASF_STACKUP;
3669                                 if (BGE_IS_575X_PLUS(sc))
3670                                         sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
3671                         }
3672                 }
3673         }
3674
3675         bge_stop_fw(sc);
3676         bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
3677         if (bge_reset(sc)) {
3678                 device_printf(sc->bge_dev, "chip reset failed\n");
3679                 error = ENXIO;
3680                 goto fail;
3681         }
3682
3683         bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
3684         bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
3685
3686         if (bge_chipinit(sc)) {
3687                 device_printf(sc->bge_dev, "chip initialization failed\n");
3688                 error = ENXIO;
3689                 goto fail;
3690         }
3691
3692         error = bge_get_eaddr(sc, eaddr);
3693         if (error) {
3694                 device_printf(sc->bge_dev,
3695                     "failed to read station address\n");
3696                 error = ENXIO;
3697                 goto fail;
3698         }
3699
3700         /* 5705 limits RX return ring to 512 entries. */
3701         if (BGE_IS_5717_PLUS(sc))
3702                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3703         else if (BGE_IS_5705_PLUS(sc))
3704                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
3705         else
3706                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3707
3708         if (bge_dma_alloc(sc)) {
3709                 device_printf(sc->bge_dev,
3710                     "failed to allocate DMA resources\n");
3711                 error = ENXIO;
3712                 goto fail;
3713         }
3714
3715         /* Set default tuneable values. */
3716         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
3717         sc->bge_rx_coal_ticks = 150;
3718         sc->bge_tx_coal_ticks = 150;
3719         sc->bge_rx_max_coal_bds = 10;
3720         sc->bge_tx_max_coal_bds = 10;
3721
3722         /* Initialize checksum features to use. */
3723         sc->bge_csum_features = BGE_CSUM_FEATURES;
3724         if (sc->bge_forced_udpcsum != 0)
3725                 sc->bge_csum_features |= CSUM_UDP;
3726
3727         /* Set up ifnet structure */
3728         ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
3729         if (ifp == NULL) {
3730                 device_printf(sc->bge_dev, "failed to if_alloc()\n");
3731                 error = ENXIO;
3732                 goto fail;
3733         }
3734         ifp->if_softc = sc;
3735         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
3736         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
3737         ifp->if_ioctl = bge_ioctl;
3738         ifp->if_start = bge_start;
3739         ifp->if_init = bge_init;
3740         ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1;
3741         IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
3742         IFQ_SET_READY(&ifp->if_snd);
3743         ifp->if_hwassist = sc->bge_csum_features;
3744         ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
3745             IFCAP_VLAN_MTU;
3746         if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) {
3747                 ifp->if_hwassist |= CSUM_TSO;
3748                 ifp->if_capabilities |= IFCAP_TSO4 | IFCAP_VLAN_HWTSO;
3749         }
3750 #ifdef IFCAP_VLAN_HWCSUM
3751         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
3752 #endif
3753         ifp->if_capenable = ifp->if_capabilities;
3754 #ifdef DEVICE_POLLING
3755         ifp->if_capabilities |= IFCAP_POLLING;
3756 #endif
3757
3758         /*
3759          * 5700 B0 chips do not support checksumming correctly due
3760          * to hardware bugs.
3761          */
3762         if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) {
3763                 ifp->if_capabilities &= ~IFCAP_HWCSUM;
3764                 ifp->if_capenable &= ~IFCAP_HWCSUM;
3765                 ifp->if_hwassist = 0;
3766         }
3767
3768         /*
3769          * Figure out what sort of media we have by checking the
3770          * hardware config word in the first 32k of NIC internal memory,
3771          * or fall back to examining the EEPROM if necessary.
3772          * Note: on some BCM5700 cards, this value appears to be unset.
3773          * If that's the case, we have to rely on identifying the NIC
3774          * by its PCI subsystem ID, as we do below for the SysKonnect
3775          * SK-9D41.
3776          */
3777         if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC)
3778                 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG);
3779         else if ((sc->bge_flags & BGE_FLAG_EADDR) &&
3780             (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
3781                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
3782                     sizeof(hwcfg))) {
3783                         device_printf(sc->bge_dev, "failed to read EEPROM\n");
3784                         error = ENXIO;
3785                         goto fail;
3786                 }
3787                 hwcfg = ntohl(hwcfg);
3788         }
3789
3790         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
3791         if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) ==
3792             SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
3793                 if (BGE_IS_5705_PLUS(sc)) {
3794                         sc->bge_flags |= BGE_FLAG_MII_SERDES;
3795                         sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3796                 } else
3797                         sc->bge_flags |= BGE_FLAG_TBI;
3798         }
3799
3800         /* Set various PHY bug flags. */
3801         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
3802             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
3803                 sc->bge_phy_flags |= BGE_PHY_CRC_BUG;
3804         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
3805             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
3806                 sc->bge_phy_flags |= BGE_PHY_ADC_BUG;
3807         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
3808                 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG;
3809         if (pci_get_subvendor(dev) == DELL_VENDORID)
3810                 sc->bge_phy_flags |= BGE_PHY_NO_3LED;
3811         if ((BGE_IS_5705_PLUS(sc)) &&
3812             sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
3813             sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
3814             sc->bge_asicrev != BGE_ASICREV_BCM57780 &&
3815             !BGE_IS_5717_PLUS(sc)) {
3816                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
3817                     sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
3818                     sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
3819                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
3820                         if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 &&
3821                             pci_get_device(dev) != BCOM_DEVICEID_BCM5756)
3822                                 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG;
3823                         if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M)
3824                                 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM;
3825                 } else
3826                         sc->bge_phy_flags |= BGE_PHY_BER_BUG;
3827         }
3828
3829         /*
3830          * Don't enable Ethernet@WireSpeed for the 5700 or the
3831          * 5705 A0 and A1 chips.
3832          */
3833         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3834             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
3835             (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
3836             sc->bge_chipid != BGE_CHIPID_BCM5705_A1)))
3837                 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3838
3839         if (sc->bge_flags & BGE_FLAG_TBI) {
3840                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
3841                     bge_ifmedia_sts);
3842                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
3843                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX,
3844                     0, NULL);
3845                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
3846                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
3847                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
3848         } else {
3849                 /*
3850                  * Do transceiver setup and tell the firmware the
3851                  * driver is down so we can try to get access the
3852                  * probe if ASF is running.  Retry a couple of times
3853                  * if we get a conflict with the ASF firmware accessing
3854                  * the PHY.
3855                  */
3856                 trys = 0;
3857                 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3858 again:
3859                 bge_asf_driver_up(sc);
3860
3861                 error = mii_attach(dev, &sc->bge_miibus, ifp, bge_ifmedia_upd,
3862                     bge_ifmedia_sts, capmask, sc->bge_phy_addr, MII_OFFSET_ANY,
3863                     MIIF_DOPAUSE);
3864                 if (error != 0) {
3865                         if (trys++ < 4) {
3866                                 device_printf(sc->bge_dev, "Try again\n");
3867                                 bge_miibus_writereg(sc->bge_dev,
3868                                     sc->bge_phy_addr, MII_BMCR, BMCR_RESET);
3869                                 goto again;
3870                         }
3871                         device_printf(sc->bge_dev, "attaching PHYs failed\n");
3872                         goto fail;
3873                 }
3874
3875                 /*
3876                  * Now tell the firmware we are going up after probing the PHY
3877                  */
3878                 if (sc->bge_asf_mode & ASF_STACKUP)
3879                         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3880         }
3881
3882         /*
3883          * When using the BCM5701 in PCI-X mode, data corruption has
3884          * been observed in the first few bytes of some received packets.
3885          * Aligning the packet buffer in memory eliminates the corruption.
3886          * Unfortunately, this misaligns the packet payloads.  On platforms
3887          * which do not support unaligned accesses, we will realign the
3888          * payloads by copying the received packets.
3889          */
3890         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
3891             sc->bge_flags & BGE_FLAG_PCIX)
3892                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
3893
3894         /*
3895          * Call MI attach routine.
3896          */
3897         ether_ifattach(ifp, eaddr);
3898
3899         /* Tell upper layer we support long frames. */
3900         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
3901
3902         /*
3903          * Hookup IRQ last.
3904          */
3905         if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) {
3906                 /* Take advantage of single-shot MSI. */
3907                 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) &
3908                     ~BGE_MSIMODE_ONE_SHOT_DISABLE);
3909                 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK,
3910                     taskqueue_thread_enqueue, &sc->bge_tq);
3911                 if (sc->bge_tq == NULL) {
3912                         device_printf(dev, "could not create taskqueue.\n");
3913                         ether_ifdetach(ifp);
3914                         error = ENOMEM;
3915                         goto fail;
3916                 }
3917                 error = taskqueue_start_threads(&sc->bge_tq, 1, PI_NET,
3918                     "%s taskq", device_get_nameunit(sc->bge_dev));
3919                 if (error != 0) {
3920                         device_printf(dev, "could not start threads.\n");
3921                         ether_ifdetach(ifp);
3922                         goto fail;
3923                 }
3924                 error = bus_setup_intr(dev, sc->bge_irq,
3925                     INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc,
3926                     &sc->bge_intrhand);
3927         } else
3928                 error = bus_setup_intr(dev, sc->bge_irq,
3929                     INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc,
3930                     &sc->bge_intrhand);
3931
3932         if (error) {
3933                 ether_ifdetach(ifp);
3934                 device_printf(sc->bge_dev, "couldn't set up irq\n");
3935         }
3936
3937 fail:
3938         if (error)
3939                 bge_detach(dev);
3940         return (error);
3941 }
3942
3943 static int
3944 bge_detach(device_t dev)
3945 {
3946         struct bge_softc *sc;
3947         struct ifnet *ifp;
3948
3949         sc = device_get_softc(dev);
3950         ifp = sc->bge_ifp;
3951
3952 #ifdef DEVICE_POLLING
3953         if (ifp->if_capenable & IFCAP_POLLING)
3954                 ether_poll_deregister(ifp);
3955 #endif
3956
3957         if (device_is_attached(dev)) {
3958                 ether_ifdetach(ifp);
3959                 BGE_LOCK(sc);
3960                 bge_stop(sc);
3961                 BGE_UNLOCK(sc);
3962                 callout_drain(&sc->bge_stat_ch);
3963         }
3964
3965         if (sc->bge_tq)
3966                 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task);
3967
3968         if (sc->bge_flags & BGE_FLAG_TBI)
3969                 ifmedia_removeall(&sc->bge_ifmedia);
3970         else if (sc->bge_miibus != NULL) {
3971                 bus_generic_detach(dev);
3972                 device_delete_child(dev, sc->bge_miibus);
3973         }
3974
3975         bge_release_resources(sc);
3976
3977         return (0);
3978 }
3979
3980 static void
3981 bge_release_resources(struct bge_softc *sc)
3982 {
3983         device_t dev;
3984
3985         dev = sc->bge_dev;
3986
3987         if (sc->bge_tq != NULL)
3988                 taskqueue_free(sc->bge_tq);
3989
3990         if (sc->bge_intrhand != NULL)
3991                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
3992
3993         if (sc->bge_irq != NULL)
3994                 bus_release_resource(dev, SYS_RES_IRQ,
3995                     sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq);
3996
3997         if (sc->bge_flags & BGE_FLAG_MSI)
3998                 pci_release_msi(dev);
3999
4000         if (sc->bge_res != NULL)
4001                 bus_release_resource(dev, SYS_RES_MEMORY,
4002                     PCIR_BAR(0), sc->bge_res);
4003
4004         if (sc->bge_res2 != NULL)
4005                 bus_release_resource(dev, SYS_RES_MEMORY,
4006                     PCIR_BAR(2), sc->bge_res2);
4007
4008         if (sc->bge_ifp != NULL)
4009                 if_free(sc->bge_ifp);
4010
4011         bge_dma_free(sc);
4012
4013         if (mtx_initialized(&sc->bge_mtx))      /* XXX */
4014                 BGE_LOCK_DESTROY(sc);
4015 }
4016
4017 static int
4018 bge_reset(struct bge_softc *sc)
4019 {
4020         device_t dev;
4021         uint32_t cachesize, command, mac_mode, mac_mode_mask, reset, val;
4022         void (*write_op)(struct bge_softc *, int, int);
4023         uint16_t devctl;
4024         int i;
4025
4026         dev = sc->bge_dev;
4027
4028         mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE;
4029         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
4030                 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
4031         mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask;
4032
4033         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
4034             (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
4035                 if (sc->bge_flags & BGE_FLAG_PCIE)
4036                         write_op = bge_writemem_direct;
4037                 else
4038                         write_op = bge_writemem_ind;
4039         } else
4040                 write_op = bge_writereg_ind;
4041
4042         if (sc->bge_asicrev != BGE_ASICREV_BCM5700 &&
4043             sc->bge_asicrev != BGE_ASICREV_BCM5701) {
4044                 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
4045                 for (i = 0; i < 8000; i++) {
4046                         if (CSR_READ_4(sc, BGE_NVRAM_SWARB) &
4047                             BGE_NVRAMSWARB_GNT1)
4048                                 break;
4049                         DELAY(20);
4050                 }
4051                 if (i == 8000) {
4052                         if (bootverbose)
4053                                 device_printf(dev, "NVRAM lock timedout!\n");
4054                 }
4055         }
4056         /* Take APE lock when performing reset. */
4057         bge_ape_lock(sc, BGE_APE_LOCK_GRC);
4058
4059         /* Save some important PCI state. */
4060         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
4061         command = pci_read_config(dev, BGE_PCI_CMD, 4);
4062
4063         pci_write_config(dev, BGE_PCI_MISC_CTL,
4064             BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
4065             BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
4066
4067         /* Disable fastboot on controllers that support it. */
4068         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
4069             BGE_IS_5755_PLUS(sc)) {
4070                 if (bootverbose)
4071                         device_printf(dev, "Disabling fastboot\n");
4072                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
4073         }
4074
4075         /*
4076          * Write the magic number to SRAM at offset 0xB50.
4077          * When firmware finishes its initialization it will
4078          * write ~BGE_SRAM_FW_MB_MAGIC to the same location.
4079          */
4080         bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
4081
4082         reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
4083
4084         /* XXX: Broadcom Linux driver. */
4085         if (sc->bge_flags & BGE_FLAG_PCIE) {
4086                 if (sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
4087                     (sc->bge_flags & BGE_FLAG_5717_PLUS) == 0) {
4088                         if (CSR_READ_4(sc, 0x7E2C) == 0x60)     /* PCIE 1.0 */
4089                                 CSR_WRITE_4(sc, 0x7E2C, 0x20);
4090                 }
4091                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
4092                         /* Prevent PCIE link training during global reset */
4093                         CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
4094                         reset |= 1 << 29;
4095                 }
4096         }
4097
4098         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
4099                 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
4100                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
4101                     val | BGE_VCPU_STATUS_DRV_RESET);
4102                 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
4103                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
4104                     val & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
4105         }
4106
4107         /*
4108          * Set GPHY Power Down Override to leave GPHY
4109          * powered up in D0 uninitialized.
4110          */
4111         if (BGE_IS_5705_PLUS(sc) &&
4112             (sc->bge_flags & BGE_FLAG_CPMU_PRESENT) == 0)
4113                 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
4114
4115         /* Issue global reset */
4116         write_op(sc, BGE_MISC_CFG, reset);
4117
4118         if (sc->bge_flags & BGE_FLAG_PCIE)
4119                 DELAY(100 * 1000);
4120         else
4121                 DELAY(1000);
4122
4123         /* XXX: Broadcom Linux driver. */
4124         if (sc->bge_flags & BGE_FLAG_PCIE) {
4125                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
4126                         DELAY(500000); /* wait for link training to complete */
4127                         val = pci_read_config(dev, 0xC4, 4);
4128                         pci_write_config(dev, 0xC4, val | (1 << 15), 4);
4129                 }
4130                 devctl = pci_read_config(dev,
4131                     sc->bge_expcap + PCIER_DEVICE_CTL, 2);
4132                 /* Clear enable no snoop and disable relaxed ordering. */
4133                 devctl &= ~(PCIEM_CTL_RELAXED_ORD_ENABLE |
4134                     PCIEM_CTL_NOSNOOP_ENABLE);
4135                 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_CTL,
4136                     devctl, 2);
4137                 pci_set_max_read_req(dev, sc->bge_expmrq);
4138                 /* Clear error status. */
4139                 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_STA,
4140                     PCIEM_STA_CORRECTABLE_ERROR |
4141                     PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR |
4142                     PCIEM_STA_UNSUPPORTED_REQ, 2);
4143         }
4144
4145         /* Reset some of the PCI state that got zapped by reset. */
4146         pci_write_config(dev, BGE_PCI_MISC_CTL,
4147             BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
4148             BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
4149         val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE;
4150         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 &&
4151             (sc->bge_flags & BGE_FLAG_PCIX) != 0)
4152                 val |= BGE_PCISTATE_RETRY_SAME_DMA;
4153         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
4154                 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
4155                     BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
4156                     BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
4157         pci_write_config(dev, BGE_PCI_PCISTATE, val, 4);
4158         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
4159         pci_write_config(dev, BGE_PCI_CMD, command, 4);
4160         /*
4161          * Disable PCI-X relaxed ordering to ensure status block update
4162          * comes first then packet buffer DMA. Otherwise driver may
4163          * read stale status block.
4164          */
4165         if (sc->bge_flags & BGE_FLAG_PCIX) {
4166                 devctl = pci_read_config(dev,
4167                     sc->bge_pcixcap + PCIXR_COMMAND, 2);
4168                 devctl &= ~PCIXM_COMMAND_ERO;
4169                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
4170                         devctl &= ~PCIXM_COMMAND_MAX_READ;
4171                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
4172                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
4173                         devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
4174                             PCIXM_COMMAND_MAX_READ);
4175                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
4176                 }
4177                 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
4178                     devctl, 2);
4179         }
4180         /* Re-enable MSI, if necessary, and enable the memory arbiter. */
4181         if (BGE_IS_5714_FAMILY(sc)) {
4182                 /* This chip disables MSI on reset. */
4183                 if (sc->bge_flags & BGE_FLAG_MSI) {
4184                         val = pci_read_config(dev,
4185                             sc->bge_msicap + PCIR_MSI_CTRL, 2);
4186                         pci_write_config(dev,
4187                             sc->bge_msicap + PCIR_MSI_CTRL,
4188                             val | PCIM_MSICTRL_MSI_ENABLE, 2);
4189                         val = CSR_READ_4(sc, BGE_MSI_MODE);
4190                         CSR_WRITE_4(sc, BGE_MSI_MODE,
4191                             val | BGE_MSIMODE_ENABLE);
4192                 }
4193                 val = CSR_READ_4(sc, BGE_MARB_MODE);
4194                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
4195         } else
4196                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
4197
4198         /* Fix up byte swapping. */
4199         CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc));
4200
4201         val = CSR_READ_4(sc, BGE_MAC_MODE);
4202         val = (val & ~mac_mode_mask) | mac_mode;
4203         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
4204         DELAY(40);
4205
4206         bge_ape_unlock(sc, BGE_APE_LOCK_GRC);
4207
4208         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
4209                 for (i = 0; i < BGE_TIMEOUT; i++) {
4210                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
4211                         if (val & BGE_VCPU_STATUS_INIT_DONE)
4212                                 break;
4213                         DELAY(100);
4214                 }
4215                 if (i == BGE_TIMEOUT) {
4216                         device_printf(dev, "reset timed out\n");
4217                         return (1);
4218                 }
4219         } else {
4220                 /*
4221                  * Poll until we see the 1's complement of the magic number.
4222                  * This indicates that the firmware initialization is complete.
4223                  * We expect this to fail if no chip containing the Ethernet
4224                  * address is fitted though.
4225                  */
4226                 for (i = 0; i < BGE_TIMEOUT; i++) {
4227                         DELAY(10);
4228                         val = bge_readmem_ind(sc, BGE_SRAM_FW_MB);
4229                         if (val == ~BGE_SRAM_FW_MB_MAGIC)
4230                                 break;
4231                 }
4232
4233                 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT)
4234                         device_printf(dev,
4235                             "firmware handshake timed out, found 0x%08x\n",
4236                             val);
4237                 /* BCM57765 A0 needs additional time before accessing. */
4238                 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
4239                         DELAY(10 * 1000);       /* XXX */
4240         }
4241
4242         /*
4243          * The 5704 in TBI mode apparently needs some special
4244          * adjustment to insure the SERDES drive level is set
4245          * to 1.2V.
4246          */
4247         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
4248             sc->bge_flags & BGE_FLAG_TBI) {
4249                 val = CSR_READ_4(sc, BGE_SERDES_CFG);
4250                 val = (val & ~0xFFF) | 0x880;
4251                 CSR_WRITE_4(sc, BGE_SERDES_CFG, val);
4252         }
4253
4254         /* XXX: Broadcom Linux driver. */
4255         if (sc->bge_flags & BGE_FLAG_PCIE &&
4256             !BGE_IS_5717_PLUS(sc) &&
4257             sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
4258             sc->bge_asicrev != BGE_ASICREV_BCM5785) {
4259                 /* Enable Data FIFO protection. */
4260                 val = CSR_READ_4(sc, 0x7C00);
4261                 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
4262         }
4263
4264         if (sc->bge_asicrev == BGE_ASICREV_BCM5720)
4265                 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
4266                     CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
4267
4268         return (0);
4269 }
4270
4271 static __inline void
4272 bge_rxreuse_std(struct bge_softc *sc, int i)
4273 {
4274         struct bge_rx_bd *r;
4275
4276         r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
4277         r->bge_flags = BGE_RXBDFLAG_END;
4278         r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i];
4279         r->bge_idx = i;
4280         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
4281 }
4282
4283 static __inline void
4284 bge_rxreuse_jumbo(struct bge_softc *sc, int i)
4285 {
4286         struct bge_extrx_bd *r;
4287
4288         r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
4289         r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
4290         r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0];
4291         r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1];
4292         r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2];
4293         r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3];
4294         r->bge_idx = i;
4295         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
4296 }
4297
4298 /*
4299  * Frame reception handling. This is called if there's a frame
4300  * on the receive return list.
4301  *
4302  * Note: we have to be able to handle two possibilities here:
4303  * 1) the frame is from the jumbo receive ring
4304  * 2) the frame is from the standard receive ring
4305  */
4306
4307 static int
4308 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck)
4309 {
4310         struct ifnet *ifp;
4311         int rx_npkts = 0, stdcnt = 0, jumbocnt = 0;
4312         uint16_t rx_cons;
4313
4314         rx_cons = sc->bge_rx_saved_considx;
4315
4316         /* Nothing to do. */
4317         if (rx_cons == rx_prod)
4318                 return (rx_npkts);
4319
4320         ifp = sc->bge_ifp;
4321
4322         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
4323             sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
4324         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
4325             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE);
4326         if (BGE_IS_JUMBO_CAPABLE(sc) &&
4327             ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
4328             (MCLBYTES - ETHER_ALIGN))
4329                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
4330                     sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE);
4331
4332         while (rx_cons != rx_prod) {
4333                 struct bge_rx_bd        *cur_rx;
4334                 uint32_t                rxidx;
4335                 struct mbuf             *m = NULL;
4336                 uint16_t                vlan_tag = 0;
4337                 int                     have_tag = 0;
4338
4339 #ifdef DEVICE_POLLING
4340                 if (ifp->if_capenable & IFCAP_POLLING) {
4341                         if (sc->rxcycles <= 0)
4342                                 break;
4343                         sc->rxcycles--;
4344                 }
4345 #endif
4346
4347                 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons];
4348
4349                 rxidx = cur_rx->bge_idx;
4350                 BGE_INC(rx_cons, sc->bge_return_ring_cnt);
4351
4352                 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING &&
4353                     cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
4354                         have_tag = 1;
4355                         vlan_tag = cur_rx->bge_vlan_tag;
4356                 }
4357
4358                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
4359                         jumbocnt++;
4360                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
4361                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
4362                                 bge_rxreuse_jumbo(sc, rxidx);
4363                                 continue;
4364                         }
4365                         if (bge_newbuf_jumbo(sc, rxidx) != 0) {
4366                                 bge_rxreuse_jumbo(sc, rxidx);
4367                                 ifp->if_iqdrops++;
4368                                 continue;
4369                         }
4370                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
4371                 } else {
4372                         stdcnt++;
4373                         m = sc->bge_cdata.bge_rx_std_chain[rxidx];
4374                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
4375                                 bge_rxreuse_std(sc, rxidx);
4376                                 continue;
4377                         }
4378                         if (bge_newbuf_std(sc, rxidx) != 0) {
4379                                 bge_rxreuse_std(sc, rxidx);
4380                                 ifp->if_iqdrops++;
4381                                 continue;
4382                         }
4383                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
4384                 }
4385
4386                 ifp->if_ipackets++;
4387 #ifndef __NO_STRICT_ALIGNMENT
4388                 /*
4389                  * For architectures with strict alignment we must make sure
4390                  * the payload is aligned.
4391                  */
4392                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
4393                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
4394                             cur_rx->bge_len);
4395                         m->m_data += ETHER_ALIGN;
4396                 }
4397 #endif
4398                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
4399                 m->m_pkthdr.rcvif = ifp;
4400
4401                 if (ifp->if_capenable & IFCAP_RXCSUM)
4402                         bge_rxcsum(sc, cur_rx, m);
4403
4404                 /*
4405                  * If we received a packet with a vlan tag,
4406                  * attach that information to the packet.
4407                  */
4408                 if (have_tag) {
4409                         m->m_pkthdr.ether_vtag = vlan_tag;
4410                         m->m_flags |= M_VLANTAG;
4411                 }
4412
4413                 if (holdlck != 0) {
4414                         BGE_UNLOCK(sc);
4415                         (*ifp->if_input)(ifp, m);
4416                         BGE_LOCK(sc);
4417                 } else
4418                         (*ifp->if_input)(ifp, m);
4419                 rx_npkts++;
4420
4421                 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
4422                         return (rx_npkts);
4423         }
4424
4425         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
4426             sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD);
4427         if (stdcnt > 0)
4428                 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
4429                     sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
4430
4431         if (jumbocnt > 0)
4432                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
4433                     sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
4434
4435         sc->bge_rx_saved_considx = rx_cons;
4436         bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
4437         if (stdcnt)
4438                 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std +
4439                     BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT);
4440         if (jumbocnt)
4441                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo +
4442                     BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT);
4443 #ifdef notyet
4444         /*
4445          * This register wraps very quickly under heavy packet drops.
4446          * If you need correct statistics, you can enable this check.
4447          */
4448         if (BGE_IS_5705_PLUS(sc))
4449                 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4450 #endif
4451         return (rx_npkts);
4452 }
4453
4454 static void
4455 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m)
4456 {
4457
4458         if (BGE_IS_5717_PLUS(sc)) {
4459                 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
4460                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
4461                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
4462                                 if ((cur_rx->bge_error_flag &
4463                                     BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
4464                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
4465                         }
4466                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
4467                                 m->m_pkthdr.csum_data =
4468                                     cur_rx->bge_tcp_udp_csum;
4469                                 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
4470                                     CSUM_PSEUDO_HDR;
4471                         }
4472                 }
4473         } else {
4474                 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
4475                         m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
4476                         if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0)
4477                                 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
4478                 }
4479                 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
4480                     m->m_pkthdr.len >= ETHER_MIN_NOPAD) {
4481                         m->m_pkthdr.csum_data =
4482                             cur_rx->bge_tcp_udp_csum;
4483                         m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
4484                             CSUM_PSEUDO_HDR;
4485                 }
4486         }
4487 }
4488
4489 static void
4490 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
4491 {
4492         struct bge_tx_bd *cur_tx;
4493         struct ifnet *ifp;
4494
4495         BGE_LOCK_ASSERT(sc);
4496
4497         /* Nothing to do. */
4498         if (sc->bge_tx_saved_considx == tx_cons)
4499                 return;
4500
4501         ifp = sc->bge_ifp;
4502
4503         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
4504             sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE);
4505         /*
4506          * Go through our tx ring and free mbufs for those
4507          * frames that have been sent.
4508          */
4509         while (sc->bge_tx_saved_considx != tx_cons) {
4510                 uint32_t                idx;
4511
4512                 idx = sc->bge_tx_saved_considx;
4513                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
4514                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
4515                         ifp->if_opackets++;
4516                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
4517                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
4518                             sc->bge_cdata.bge_tx_dmamap[idx],
4519                             BUS_DMASYNC_POSTWRITE);
4520                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
4521                             sc->bge_cdata.bge_tx_dmamap[idx]);
4522                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
4523                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
4524                 }
4525                 sc->bge_txcnt--;
4526                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
4527         }
4528
4529         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4530         if (sc->bge_txcnt == 0)
4531                 sc->bge_timer = 0;
4532 }
4533
4534 #ifdef DEVICE_POLLING
4535 static int
4536 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
4537 {
4538         struct bge_softc *sc = ifp->if_softc;
4539         uint16_t rx_prod, tx_cons;
4540         uint32_t statusword;
4541         int rx_npkts = 0;
4542
4543         BGE_LOCK(sc);
4544         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
4545                 BGE_UNLOCK(sc);
4546                 return (rx_npkts);
4547         }
4548
4549         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4550             sc->bge_cdata.bge_status_map,
4551             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4552         /* Fetch updates from the status block. */
4553         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4554         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4555
4556         statusword = sc->bge_ldata.bge_status_block->bge_status;
4557         /* Clear the status so the next pass only sees the changes. */
4558         sc->bge_ldata.bge_status_block->bge_status = 0;
4559
4560         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4561             sc->bge_cdata.bge_status_map,
4562             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4563
4564         /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */
4565         if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED)
4566                 sc->bge_link_evt++;
4567
4568         if (cmd == POLL_AND_CHECK_STATUS)
4569                 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4570                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4571                     sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
4572                         bge_link_upd(sc);
4573
4574         sc->rxcycles = count;
4575         rx_npkts = bge_rxeof(sc, rx_prod, 1);
4576         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
4577                 BGE_UNLOCK(sc);
4578                 return (rx_npkts);
4579         }
4580         bge_txeof(sc, tx_cons);
4581         if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
4582                 bge_start_locked(ifp);
4583
4584         BGE_UNLOCK(sc);
4585         return (rx_npkts);
4586 }
4587 #endif /* DEVICE_POLLING */
4588
4589 static int
4590 bge_msi_intr(void *arg)
4591 {
4592         struct bge_softc *sc;
4593
4594         sc = (struct bge_softc *)arg;
4595         /*
4596          * This interrupt is not shared and controller already
4597          * disabled further interrupt.
4598          */
4599         taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task);
4600         return (FILTER_HANDLED);
4601 }
4602
4603 static void
4604 bge_intr_task(void *arg, int pending)
4605 {
4606         struct bge_softc *sc;
4607         struct ifnet *ifp;
4608         uint32_t status, status_tag;
4609         uint16_t rx_prod, tx_cons;
4610
4611         sc = (struct bge_softc *)arg;
4612         ifp = sc->bge_ifp;
4613
4614         BGE_LOCK(sc);
4615         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
4616                 BGE_UNLOCK(sc);
4617                 return;
4618         }
4619
4620         /* Get updated status block. */
4621         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4622             sc->bge_cdata.bge_status_map,
4623             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4624
4625         /* Save producer/consumer indices. */
4626         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4627         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4628         status = sc->bge_ldata.bge_status_block->bge_status;
4629         status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24;
4630         /* Dirty the status flag. */
4631         sc->bge_ldata.bge_status_block->bge_status = 0;
4632         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4633             sc->bge_cdata.bge_status_map,
4634             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4635         if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0)
4636                 status_tag = 0;
4637
4638         if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0)
4639                 bge_link_upd(sc);
4640
4641         /* Let controller work. */
4642         bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag);
4643
4644         if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
4645             sc->bge_rx_saved_considx != rx_prod) {
4646                 /* Check RX return ring producer/consumer. */
4647                 BGE_UNLOCK(sc);
4648                 bge_rxeof(sc, rx_prod, 0);
4649                 BGE_LOCK(sc);
4650         }
4651         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4652                 /* Check TX ring producer/consumer. */
4653                 bge_txeof(sc, tx_cons);
4654                 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
4655                         bge_start_locked(ifp);
4656         }
4657         BGE_UNLOCK(sc);
4658 }
4659
4660 static void
4661 bge_intr(void *xsc)
4662 {
4663         struct bge_softc *sc;
4664         struct ifnet *ifp;
4665         uint32_t statusword;
4666         uint16_t rx_prod, tx_cons;
4667
4668         sc = xsc;
4669
4670         BGE_LOCK(sc);
4671
4672         ifp = sc->bge_ifp;
4673
4674 #ifdef DEVICE_POLLING
4675         if (ifp->if_capenable & IFCAP_POLLING) {
4676                 BGE_UNLOCK(sc);
4677                 return;
4678         }
4679 #endif
4680
4681         /*
4682          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
4683          * disable interrupts by writing nonzero like we used to, since with
4684          * our current organization this just gives complications and
4685          * pessimizations for re-enabling interrupts.  We used to have races
4686          * instead of the necessary complications.  Disabling interrupts
4687          * would just reduce the chance of a status update while we are
4688          * running (by switching to the interrupt-mode coalescence
4689          * parameters), but this chance is already very low so it is more
4690          * efficient to get another interrupt than prevent it.
4691          *
4692          * We do the ack first to ensure another interrupt if there is a
4693          * status update after the ack.  We don't check for the status
4694          * changing later because it is more efficient to get another
4695          * interrupt than prevent it, not quite as above (not checking is
4696          * a smaller optimization than not toggling the interrupt enable,
4697          * since checking doesn't involve PCI accesses and toggling require
4698          * the status check).  So toggling would probably be a pessimization
4699          * even with MSI.  It would only be needed for using a task queue.
4700          */
4701         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4702
4703         /*
4704          * Do the mandatory PCI flush as well as get the link status.
4705          */
4706         statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
4707
4708         /* Make sure the descriptor ring indexes are coherent. */
4709         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4710             sc->bge_cdata.bge_status_map,
4711             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4712         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4713         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4714         sc->bge_ldata.bge_status_block->bge_status = 0;
4715         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4716             sc->bge_cdata.bge_status_map,
4717             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4718
4719         if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4720             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4721             statusword || sc->bge_link_evt)
4722                 bge_link_upd(sc);
4723
4724         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4725                 /* Check RX return ring producer/consumer. */
4726                 bge_rxeof(sc, rx_prod, 1);
4727         }
4728
4729         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4730                 /* Check TX ring producer/consumer. */
4731                 bge_txeof(sc, tx_cons);
4732         }
4733
4734         if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
4735             !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
4736                 bge_start_locked(ifp);
4737
4738         BGE_UNLOCK(sc);
4739 }
4740
4741 static void
4742 bge_asf_driver_up(struct bge_softc *sc)
4743 {
4744         if (sc->bge_asf_mode & ASF_STACKUP) {
4745                 /* Send ASF heartbeat aprox. every 2s */
4746                 if (sc->bge_asf_count)
4747                         sc->bge_asf_count --;
4748                 else {
4749                         sc->bge_asf_count = 2;
4750                         bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB,
4751                             BGE_FW_CMD_DRV_ALIVE);
4752                         bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4);
4753                         bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB,
4754                             BGE_FW_HB_TIMEOUT_SEC);
4755                         CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
4756                             CSR_READ_4(sc, BGE_RX_CPU_EVENT) |
4757                             BGE_RX_CPU_DRV_EVENT);
4758                 }
4759         }
4760 }
4761
4762 static void
4763 bge_tick(void *xsc)
4764 {
4765         struct bge_softc *sc = xsc;
4766         struct mii_data *mii = NULL;
4767
4768         BGE_LOCK_ASSERT(sc);
4769
4770         /* Synchronize with possible callout reset/stop. */
4771         if (callout_pending(&sc->bge_stat_ch) ||
4772             !callout_active(&sc->bge_stat_ch))
4773                 return;
4774
4775         if (BGE_IS_5705_PLUS(sc))
4776                 bge_stats_update_regs(sc);
4777         else
4778                 bge_stats_update(sc);
4779
4780         /* XXX Add APE heartbeat check here? */
4781
4782         if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
4783                 mii = device_get_softc(sc->bge_miibus);
4784                 /*
4785                  * Do not touch PHY if we have link up. This could break
4786                  * IPMI/ASF mode or produce extra input errors
4787                  * (extra errors was reported for bcm5701 & bcm5704).
4788                  */
4789                 if (!sc->bge_link)
4790                         mii_tick(mii);
4791         } else {
4792                 /*
4793                  * Since in TBI mode auto-polling can't be used we should poll
4794                  * link status manually. Here we register pending link event
4795                  * and trigger interrupt.
4796                  */
4797 #ifdef DEVICE_POLLING
4798                 /* In polling mode we poll link state in bge_poll(). */
4799                 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING))
4800 #endif
4801                 {
4802                 sc->bge_link_evt++;
4803                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
4804                     sc->bge_flags & BGE_FLAG_5788)
4805                         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4806                 else
4807                         BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
4808                 }
4809         }
4810
4811         bge_asf_driver_up(sc);
4812         bge_watchdog(sc);
4813
4814         callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
4815 }
4816
4817 static void
4818 bge_stats_update_regs(struct bge_softc *sc)
4819 {
4820         struct ifnet *ifp;
4821         struct bge_mac_stats *stats;
4822         uint32_t val;
4823
4824         ifp = sc->bge_ifp;
4825         stats = &sc->bge_mac_stats;
4826
4827         stats->ifHCOutOctets +=
4828             CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4829         stats->etherStatsCollisions +=
4830             CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4831         stats->outXonSent +=
4832             CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4833         stats->outXoffSent +=
4834             CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4835         stats->dot3StatsInternalMacTransmitErrors +=
4836             CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4837         stats->dot3StatsSingleCollisionFrames +=
4838             CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4839         stats->dot3StatsMultipleCollisionFrames +=
4840             CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4841         stats->dot3StatsDeferredTransmissions +=
4842             CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4843         stats->dot3StatsExcessiveCollisions +=
4844             CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4845         stats->dot3StatsLateCollisions +=
4846             CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4847         stats->ifHCOutUcastPkts +=
4848             CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4849         stats->ifHCOutMulticastPkts +=
4850             CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4851         stats->ifHCOutBroadcastPkts +=
4852             CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4853
4854         stats->ifHCInOctets +=
4855             CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4856         stats->etherStatsFragments +=
4857             CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4858         stats->ifHCInUcastPkts +=
4859             CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4860         stats->ifHCInMulticastPkts +=
4861             CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4862         stats->ifHCInBroadcastPkts +=
4863             CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4864         stats->dot3StatsFCSErrors +=
4865             CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4866         stats->dot3StatsAlignmentErrors +=
4867             CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4868         stats->xonPauseFramesReceived +=
4869             CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4870         stats->xoffPauseFramesReceived +=
4871             CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4872         stats->macControlFramesReceived +=
4873             CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4874         stats->xoffStateEntered +=
4875             CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4876         stats->dot3StatsFramesTooLong +=
4877             CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4878         stats->etherStatsJabbers +=
4879             CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4880         stats->etherStatsUndersizePkts +=
4881             CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4882
4883         stats->FramesDroppedDueToFilters +=
4884             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4885         stats->DmaWriteQueueFull +=
4886             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4887         stats->DmaWriteHighPriQueueFull +=
4888             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4889         stats->NoMoreRxBDs +=
4890             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4891         /*
4892          * XXX
4893          * Unlike other controllers, BGE_RXLP_LOCSTAT_IFIN_DROPS
4894          * counter of BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0
4895          * includes number of unwanted multicast frames.  This comes
4896          * from silicon bug and known workaround to get rough(not
4897          * exact) counter is to enable interrupt on MBUF low water
4898          * attention.  This can be accomplished by setting
4899          * BGE_HCCMODE_ATTN bit of BGE_HCC_MODE,
4900          * BGE_BMANMODE_LOMBUF_ATTN bit of BGE_BMAN_MODE and
4901          * BGE_MODECTL_FLOWCTL_ATTN_INTR bit of BGE_MODE_CTL.
4902          * However that change would generate more interrupts and
4903          * there are still possibilities of losing multiple frames
4904          * during BGE_MODECTL_FLOWCTL_ATTN_INTR interrupt handling.
4905          * Given that the workaround still would not get correct
4906          * counter I don't think it's worth to implement it.  So
4907          * ignore reading the counter on controllers that have the
4908          * silicon bug.
4909          */
4910         if (sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
4911             sc->bge_chipid != BGE_CHIPID_BCM5719_A0 &&
4912             sc->bge_chipid != BGE_CHIPID_BCM5720_A0)
4913                 stats->InputDiscards +=
4914                     CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4915         stats->InputErrors +=
4916             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4917         stats->RecvThresholdHit +=
4918             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4919
4920         ifp->if_collisions = (u_long)stats->etherStatsCollisions;
4921         ifp->if_ierrors = (u_long)(stats->NoMoreRxBDs + stats->InputDiscards +
4922             stats->InputErrors);
4923
4924         if (sc->bge_flags & BGE_FLAG_RDMA_BUG) {
4925                 /*
4926                  * If controller transmitted more than BGE_NUM_RDMA_CHANNELS
4927                  * frames, it's safe to disable workaround for DMA engine's
4928                  * miscalculation of TXMBUF space.
4929                  */
4930                 if (stats->ifHCOutUcastPkts + stats->ifHCOutMulticastPkts +
4931                     stats->ifHCOutBroadcastPkts > BGE_NUM_RDMA_CHANNELS) {
4932                         val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
4933                         if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
4934                                 val &= ~BGE_RDMA_TX_LENGTH_WA_5719;
4935                         else
4936                                 val &= ~BGE_RDMA_TX_LENGTH_WA_5720;
4937                         CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
4938                         sc->bge_flags &= ~BGE_FLAG_RDMA_BUG;
4939                 }
4940         }
4941 }
4942
4943 static void
4944 bge_stats_clear_regs(struct bge_softc *sc)
4945 {
4946
4947         CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4948         CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4949         CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4950         CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4951         CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4952         CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4953         CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4954         CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4955         CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4956         CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4957         CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4958         CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4959         CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4960
4961         CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4962         CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4963         CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4964         CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4965         CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4966         CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4967         CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4968         CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4969         CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4970         CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4971         CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4972         CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4973         CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4974         CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4975
4976         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4977         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4978         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4979         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4980         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4981         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4982         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4983 }
4984
4985 static void
4986 bge_stats_update(struct bge_softc *sc)
4987 {
4988         struct ifnet *ifp;
4989         bus_size_t stats;
4990         uint32_t cnt;   /* current register value */
4991
4992         ifp = sc->bge_ifp;
4993
4994         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
4995
4996 #define READ_STAT(sc, stats, stat) \
4997         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
4998
4999         cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
5000         ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions);
5001         sc->bge_tx_collisions = cnt;
5002
5003         cnt = READ_STAT(sc, stats, nicNoMoreRxBDs.bge_addr_lo);
5004         ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_nobds);
5005         sc->bge_rx_nobds = cnt;
5006         cnt = READ_STAT(sc, stats, ifInErrors.bge_addr_lo);
5007         ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_inerrs);
5008         sc->bge_rx_inerrs = cnt;
5009         cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
5010         ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards);
5011         sc->bge_rx_discards = cnt;
5012
5013         cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
5014         ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards);
5015         sc->bge_tx_discards = cnt;
5016
5017 #undef  READ_STAT
5018 }
5019
5020 /*
5021  * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
5022  * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
5023  * but when such padded frames employ the bge IP/TCP checksum offload,
5024  * the hardware checksum assist gives incorrect results (possibly
5025  * from incorporating its own padding into the UDP/TCP checksum; who knows).
5026  * If we pad such runts with zeros, the onboard checksum comes out correct.
5027  */
5028 static __inline int
5029 bge_cksum_pad(struct mbuf *m)
5030 {
5031         int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len;
5032         struct mbuf *last;
5033
5034         /* If there's only the packet-header and we can pad there, use it. */
5035         if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) &&
5036             M_TRAILINGSPACE(m) >= padlen) {
5037                 last = m;
5038         } else {
5039                 /*
5040                  * Walk packet chain to find last mbuf. We will either
5041                  * pad there, or append a new mbuf and pad it.
5042                  */
5043                 for (last = m; last->m_next != NULL; last = last->m_next);
5044                 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) {
5045                         /* Allocate new empty mbuf, pad it. Compact later. */
5046                         struct mbuf *n;
5047
5048                         MGET(n, M_NOWAIT, MT_DATA);
5049                         if (n == NULL)
5050                                 return (ENOBUFS);
5051                         n->m_len = 0;
5052                         last->m_next = n;
5053                         last = n;
5054                 }
5055         }
5056
5057         /* Now zero the pad area, to avoid the bge cksum-assist bug. */
5058         memset(mtod(last, caddr_t) + last->m_len, 0, padlen);
5059         last->m_len += padlen;
5060         m->m_pkthdr.len += padlen;
5061
5062         return (0);
5063 }
5064
5065 static struct mbuf *
5066 bge_check_short_dma(struct mbuf *m)
5067 {
5068         struct mbuf *n;
5069         int found;
5070
5071         /*
5072          * If device receive two back-to-back send BDs with less than
5073          * or equal to 8 total bytes then the device may hang.  The two
5074          * back-to-back send BDs must in the same frame for this failure
5075          * to occur.  Scan mbuf chains and see whether two back-to-back
5076          * send BDs are there. If this is the case, allocate new mbuf
5077          * and copy the frame to workaround the silicon bug.
5078          */
5079         for (n = m, found = 0; n != NULL; n = n->m_next) {
5080                 if (n->m_len < 8) {
5081                         found++;
5082                         if (found > 1)
5083                                 break;
5084                         continue;
5085                 }
5086                 found = 0;
5087         }
5088
5089         if (found > 1) {
5090                 n = m_defrag(m, M_NOWAIT);
5091                 if (n == NULL)
5092                         m_freem(m);
5093         } else
5094                 n = m;
5095         return (n);
5096 }
5097
5098 static struct mbuf *
5099 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss,
5100     uint16_t *flags)
5101 {
5102         struct ip *ip;
5103         struct tcphdr *tcp;
5104         struct mbuf *n;
5105         uint16_t hlen;
5106         uint32_t poff;
5107
5108         if (M_WRITABLE(m) == 0) {
5109                 /* Get a writable copy. */
5110                 n = m_dup(m, M_NOWAIT);
5111                 m_freem(m);
5112                 if (n == NULL)
5113                         return (NULL);
5114                 m = n;
5115         }
5116         m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip));
5117         if (m == NULL)
5118                 return (NULL);
5119         ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
5120         poff = sizeof(struct ether_header) + (ip->ip_hl << 2);
5121         m = m_pullup(m, poff + sizeof(struct tcphdr));
5122         if (m == NULL)
5123                 return (NULL);
5124         tcp = (struct tcphdr *)(mtod(m, char *) + poff);
5125         m = m_pullup(m, poff + (tcp->th_off << 2));
5126         if (m == NULL)
5127                 return (NULL);
5128         /*
5129          * It seems controller doesn't modify IP length and TCP pseudo
5130          * checksum. These checksum computed by upper stack should be 0.
5131          */
5132         *mss = m->m_pkthdr.tso_segsz;
5133         ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
5134         ip->ip_sum = 0;
5135         ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2));
5136         /* Clear pseudo checksum computed by TCP stack. */
5137         tcp = (struct tcphdr *)(mtod(m, char *) + poff);
5138         tcp->th_sum = 0;
5139         /*
5140          * Broadcom controllers uses different descriptor format for
5141          * TSO depending on ASIC revision. Due to TSO-capable firmware
5142          * license issue and lower performance of firmware based TSO
5143          * we only support hardware based TSO.
5144          */
5145         /* Calculate header length, incl. TCP/IP options, in 32 bit units. */
5146         hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2;
5147         if (sc->bge_flags & BGE_FLAG_TSO3) {
5148                 /*
5149                  * For BCM5717 and newer controllers, hardware based TSO
5150                  * uses the 14 lower bits of the bge_mss field to store the
5151                  * MSS and the upper 2 bits to store the lowest 2 bits of
5152                  * the IP/TCP header length.  The upper 6 bits of the header
5153                  * length are stored in the bge_flags[14:10,4] field.  Jumbo
5154                  * frames are supported.
5155                  */
5156                 *mss |= ((hlen & 0x3) << 14);
5157                 *flags |= ((hlen & 0xF8) << 7) | ((hlen & 0x4) << 2);
5158         } else {
5159                 /*
5160                  * For BCM5755 and newer controllers, hardware based TSO uses
5161                  * the lower 11 bits to store the MSS and the upper 5 bits to
5162                  * store the IP/TCP header length. Jumbo frames are not
5163                  * supported.
5164                  */
5165                 *mss |= (hlen << 11);
5166         }
5167         return (m);
5168 }
5169
5170 /*
5171  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
5172  * pointers to descriptors.
5173  */
5174 static int
5175 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
5176 {
5177         bus_dma_segment_t       segs[BGE_NSEG_NEW];
5178         bus_dmamap_t            map;
5179         struct bge_tx_bd        *d;
5180         struct mbuf             *m = *m_head;
5181         uint32_t                idx = *txidx;
5182         uint16_t                csum_flags, mss, vlan_tag;
5183         int                     nsegs, i, error;
5184
5185         csum_flags = 0;
5186         mss = 0;
5187         vlan_tag = 0;
5188         if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 &&
5189             m->m_next != NULL) {
5190                 *m_head = bge_check_short_dma(m);
5191                 if (*m_head == NULL)
5192                         return (ENOBUFS);
5193                 m = *m_head;
5194         }
5195         if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
5196                 *m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags);
5197                 if (*m_head == NULL)
5198                         return (ENOBUFS);
5199                 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA |
5200                     BGE_TXBDFLAG_CPU_POST_DMA;
5201         } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) {
5202                 if (m->m_pkthdr.csum_flags & CSUM_IP)
5203                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
5204                 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {
5205                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
5206                         if (m->m_pkthdr.len < ETHER_MIN_NOPAD &&
5207                             (error = bge_cksum_pad(m)) != 0) {
5208                                 m_freem(m);
5209                                 *m_head = NULL;
5210                                 return (error);
5211                         }
5212                 }
5213         }
5214
5215         if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) {
5216                 if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME &&
5217                     m->m_pkthdr.len > ETHER_MAX_LEN)
5218                         csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME;
5219                 if (sc->bge_forced_collapse > 0 &&
5220                     (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) {
5221                         /*
5222                          * Forcedly collapse mbuf chains to overcome hardware
5223                          * limitation which only support a single outstanding
5224                          * DMA read operation.
5225                          */
5226                         if (sc->bge_forced_collapse == 1)
5227                                 m = m_defrag(m, M_NOWAIT);
5228                         else
5229                                 m = m_collapse(m, M_NOWAIT,
5230                                     sc->bge_forced_collapse);
5231                         if (m == NULL)
5232                                 m = *m_head;
5233                         *m_head = m;
5234                 }
5235         }
5236
5237         map = sc->bge_cdata.bge_tx_dmamap[idx];
5238         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs,
5239             &nsegs, BUS_DMA_NOWAIT);
5240         if (error == EFBIG) {
5241                 m = m_collapse(m, M_NOWAIT, BGE_NSEG_NEW);
5242                 if (m == NULL) {
5243                         m_freem(*m_head);
5244                         *m_head = NULL;
5245                         return (ENOBUFS);
5246                 }
5247                 *m_head = m;
5248                 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map,
5249                     m, segs, &nsegs, BUS_DMA_NOWAIT);
5250                 if (error) {
5251                         m_freem(m);
5252                         *m_head = NULL;
5253                         return (error);
5254                 }
5255         } else if (error != 0)
5256                 return (error);
5257
5258         /* Check if we have enough free send BDs. */
5259         if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) {
5260                 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
5261                 return (ENOBUFS);
5262         }
5263
5264         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
5265
5266         if (m->m_flags & M_VLANTAG) {
5267                 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
5268                 vlan_tag = m->m_pkthdr.ether_vtag;
5269         }
5270
5271         if (sc->bge_asicrev == BGE_ASICREV_BCM5762 &&
5272             (m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
5273                 /*
5274                  * 5725 family of devices corrupts TSO packets when TSO DMA
5275                  * buffers cross into regions which are within MSS bytes of
5276                  * a 4GB boundary.  If we encounter the condition, drop the
5277                  * packet.
5278                  */
5279                 for (i = 0; ; i++) {
5280                         d = &sc->bge_ldata.bge_tx_ring[idx];
5281                         d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
5282                         d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
5283                         d->bge_len = segs[i].ds_len;
5284                         if (d->bge_addr.bge_addr_lo + segs[i].ds_len + mss <
5285                             d->bge_addr.bge_addr_lo)
5286                                 break;
5287                         d->bge_flags = csum_flags;
5288                         d->bge_vlan_tag = vlan_tag;
5289                         d->bge_mss = mss;
5290                         if (i == nsegs - 1)
5291                                 break;
5292                         BGE_INC(idx, BGE_TX_RING_CNT);
5293                 }
5294                 if (i != nsegs - 1) {
5295                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map,
5296                             BUS_DMASYNC_POSTWRITE);
5297                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
5298                         m_freem(*m_head);
5299                         *m_head = NULL;
5300                         return (EIO);
5301                 }
5302         } else {
5303                 for (i = 0; ; i++) {
5304                         d = &sc->bge_ldata.bge_tx_ring[idx];
5305                         d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
5306                         d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
5307                         d->bge_len = segs[i].ds_len;
5308                         d->bge_flags = csum_flags;
5309                         d->bge_vlan_tag = vlan_tag;
5310                         d->bge_mss = mss;
5311                         if (i == nsegs - 1)
5312                                 break;
5313                         BGE_INC(idx, BGE_TX_RING_CNT);
5314                 }
5315         }
5316
5317         /* Mark the last segment as end of packet... */
5318         d->bge_flags |= BGE_TXBDFLAG_END;
5319
5320         /*
5321          * Insure that the map for this transmission
5322          * is placed at the array index of the last descriptor
5323          * in this chain.
5324          */
5325         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
5326         sc->bge_cdata.bge_tx_dmamap[idx] = map;
5327         sc->bge_cdata.bge_tx_chain[idx] = m;
5328         sc->bge_txcnt += nsegs;
5329
5330         BGE_INC(idx, BGE_TX_RING_CNT);
5331         *txidx = idx;
5332
5333         return (0);
5334 }
5335
5336 /*
5337  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
5338  * to the mbuf data regions directly in the transmit descriptors.
5339  */
5340 static void
5341 bge_start_locked(struct ifnet *ifp)
5342 {
5343         struct bge_softc *sc;
5344         struct mbuf *m_head;
5345         uint32_t prodidx;
5346         int count;
5347
5348         sc = ifp->if_softc;
5349         BGE_LOCK_ASSERT(sc);
5350
5351         if (!sc->bge_link ||
5352             (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
5353             IFF_DRV_RUNNING)
5354                 return;
5355
5356         prodidx = sc->bge_tx_prodidx;
5357
5358         for (count = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) {
5359                 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) {
5360                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
5361                         break;
5362                 }
5363                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
5364                 if (m_head == NULL)
5365                         break;
5366
5367                 /*
5368                  * Pack the data into the transmit ring. If we
5369                  * don't have room, set the OACTIVE flag and wait
5370                  * for the NIC to drain the ring.
5371                  */
5372                 if (bge_encap(sc, &m_head, &prodidx)) {
5373                         if (m_head == NULL)
5374                                 break;
5375                         IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
5376                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
5377                         break;
5378                 }
5379                 ++count;
5380
5381                 /*
5382                  * If there's a BPF listener, bounce a copy of this frame
5383                  * to him.
5384                  */
5385 #ifdef ETHER_BPF_MTAP
5386                 ETHER_BPF_MTAP(ifp, m_head);
5387 #else
5388                 BPF_MTAP(ifp, m_head);
5389 #endif
5390         }
5391
5392         if (count > 0) {
5393                 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
5394                     sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
5395                 /* Transmit. */
5396                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
5397                 /* 5700 b2 errata */
5398                 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
5399                         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
5400
5401                 sc->bge_tx_prodidx = prodidx;
5402
5403                 /*
5404                  * Set a timeout in case the chip goes out to lunch.
5405                  */
5406                 sc->bge_timer = BGE_TX_TIMEOUT;
5407         }
5408 }
5409
5410 /*
5411  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
5412  * to the mbuf data regions directly in the transmit descriptors.
5413  */
5414 static void
5415 bge_start(struct ifnet *ifp)
5416 {
5417         struct bge_softc *sc;
5418
5419         sc = ifp->if_softc;
5420         BGE_LOCK(sc);
5421         bge_start_locked(ifp);
5422         BGE_UNLOCK(sc);
5423 }
5424
5425 static void
5426 bge_init_locked(struct bge_softc *sc)
5427 {
5428         struct ifnet *ifp;
5429         uint16_t *m;
5430         uint32_t mode;
5431
5432         BGE_LOCK_ASSERT(sc);
5433
5434         ifp = sc->bge_ifp;
5435
5436         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
5437                 return;
5438
5439         /* Cancel pending I/O and flush buffers. */
5440         bge_stop(sc);
5441
5442         bge_stop_fw(sc);
5443         bge_sig_pre_reset(sc, BGE_RESET_START);
5444         bge_reset(sc);
5445         bge_sig_legacy(sc, BGE_RESET_START);
5446         bge_sig_post_reset(sc, BGE_RESET_START);
5447
5448         bge_chipinit(sc);
5449
5450         /*
5451          * Init the various state machines, ring
5452          * control blocks and firmware.
5453          */
5454         if (bge_blockinit(sc)) {
5455                 device_printf(sc->bge_dev, "initialization failure\n");
5456                 return;
5457         }
5458
5459         ifp = sc->bge_ifp;
5460
5461         /* Specify MTU. */
5462         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
5463             ETHER_HDR_LEN + ETHER_CRC_LEN +
5464             (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0));
5465
5466         /* Load our MAC address. */
5467         m = (uint16_t *)IF_LLADDR(sc->bge_ifp);
5468         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
5469         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
5470
5471         /* Program promiscuous mode. */
5472         bge_setpromisc(sc);
5473
5474         /* Program multicast filter. */
5475         bge_setmulti(sc);
5476
5477         /* Program VLAN tag stripping. */
5478         bge_setvlan(sc);
5479
5480         /* Override UDP checksum offloading. */
5481         if (sc->bge_forced_udpcsum == 0)
5482                 sc->bge_csum_features &= ~CSUM_UDP;
5483         else
5484                 sc->bge_csum_features |= CSUM_UDP;
5485         if (ifp->if_capabilities & IFCAP_TXCSUM &&
5486             ifp->if_capenable & IFCAP_TXCSUM) {
5487                 ifp->if_hwassist &= ~(BGE_CSUM_FEATURES | CSUM_UDP);
5488                 ifp->if_hwassist |= sc->bge_csum_features;
5489         }
5490
5491         /* Init RX ring. */
5492         if (bge_init_rx_ring_std(sc) != 0) {
5493                 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
5494                 bge_stop(sc);
5495                 return;
5496         }
5497
5498         /*
5499          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
5500          * memory to insure that the chip has in fact read the first
5501          * entry of the ring.
5502          */
5503         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
5504                 uint32_t                v, i;
5505                 for (i = 0; i < 10; i++) {
5506                         DELAY(20);
5507                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
5508                         if (v == (MCLBYTES - ETHER_ALIGN))
5509                                 break;
5510                 }
5511                 if (i == 10)
5512                         device_printf (sc->bge_dev,
5513                             "5705 A0 chip failed to load RX ring\n");
5514         }
5515
5516         /* Init jumbo RX ring. */
5517         if (BGE_IS_JUMBO_CAPABLE(sc) &&
5518             ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
5519             (MCLBYTES - ETHER_ALIGN)) {
5520                 if (bge_init_rx_ring_jumbo(sc) != 0) {
5521                         device_printf(sc->bge_dev,
5522                             "no memory for jumbo Rx buffers.\n");
5523                         bge_stop(sc);
5524                         return;
5525                 }
5526         }
5527
5528         /* Init our RX return ring index. */
5529         sc->bge_rx_saved_considx = 0;
5530
5531         /* Init our RX/TX stat counters. */
5532         sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0;
5533
5534         /* Init TX ring. */
5535         bge_init_tx_ring(sc);
5536
5537         /* Enable TX MAC state machine lockup fix. */
5538         mode = CSR_READ_4(sc, BGE_TX_MODE);
5539         if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
5540                 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
5541         if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
5542             sc->bge_asicrev == BGE_ASICREV_BCM5762) {
5543                 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
5544                 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
5545                     (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
5546         }
5547         /* Turn on transmitter. */
5548         CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
5549         DELAY(100);
5550
5551         /* Turn on receiver. */
5552         mode = CSR_READ_4(sc, BGE_RX_MODE);
5553         if (BGE_IS_5755_PLUS(sc))
5554                 mode |= BGE_RXMODE_IPV6_ENABLE;
5555         if (sc->bge_asicrev == BGE_ASICREV_BCM5762)
5556                 mode |= BGE_RXMODE_IPV4_FRAG_FIX;
5557         CSR_WRITE_4(sc,BGE_RX_MODE, mode | BGE_RXMODE_ENABLE);
5558         DELAY(10);
5559
5560         /*
5561          * Set the number of good frames to receive after RX MBUF
5562          * Low Watermark has been reached. After the RX MAC receives
5563          * this number of frames, it will drop subsequent incoming
5564          * frames until the MBUF High Watermark is reached.
5565          */
5566         if (BGE_IS_57765_PLUS(sc))
5567                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
5568         else
5569                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
5570
5571         /* Clear MAC statistics. */
5572         if (BGE_IS_5705_PLUS(sc))
5573                 bge_stats_clear_regs(sc);
5574
5575         /* Tell firmware we're alive. */
5576         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
5577
5578 #ifdef DEVICE_POLLING
5579         /* Disable interrupts if we are polling. */
5580         if (ifp->if_capenable & IFCAP_POLLING) {
5581                 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5582                     BGE_PCIMISCCTL_MASK_PCI_INTR);
5583                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5584         } else
5585 #endif
5586
5587         /* Enable host interrupts. */
5588         {
5589         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
5590         BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5591         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5592         }
5593
5594         ifp->if_drv_flags |= IFF_DRV_RUNNING;
5595         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
5596
5597         bge_ifmedia_upd_locked(ifp);
5598
5599         callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
5600 }
5601
5602 static void
5603 bge_init(void *xsc)
5604 {
5605         struct bge_softc *sc = xsc;
5606
5607         BGE_LOCK(sc);
5608         bge_init_locked(sc);
5609         BGE_UNLOCK(sc);
5610 }
5611
5612 /*
5613  * Set media options.
5614  */
5615 static int
5616 bge_ifmedia_upd(struct ifnet *ifp)
5617 {
5618         struct bge_softc *sc = ifp->if_softc;
5619         int res;
5620
5621         BGE_LOCK(sc);
5622         res = bge_ifmedia_upd_locked(ifp);
5623         BGE_UNLOCK(sc);
5624
5625         return (res);
5626 }
5627
5628 static int
5629 bge_ifmedia_upd_locked(struct ifnet *ifp)
5630 {
5631         struct bge_softc *sc = ifp->if_softc;
5632         struct mii_data *mii;
5633         struct mii_softc *miisc;
5634         struct ifmedia *ifm;
5635
5636         BGE_LOCK_ASSERT(sc);
5637
5638         ifm = &sc->bge_ifmedia;
5639
5640         /* If this is a 1000baseX NIC, enable the TBI port. */
5641         if (sc->bge_flags & BGE_FLAG_TBI) {
5642                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
5643                         return (EINVAL);
5644                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
5645                 case IFM_AUTO:
5646                         /*
5647                          * The BCM5704 ASIC appears to have a special
5648                          * mechanism for programming the autoneg
5649                          * advertisement registers in TBI mode.
5650                          */
5651                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
5652                                 uint32_t sgdig;
5653                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
5654                                 if (sgdig & BGE_SGDIGSTS_DONE) {
5655                                         CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
5656                                         sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
5657                                         sgdig |= BGE_SGDIGCFG_AUTO |
5658                                             BGE_SGDIGCFG_PAUSE_CAP |
5659                                             BGE_SGDIGCFG_ASYM_PAUSE;
5660                                         CSR_WRITE_4(sc, BGE_SGDIG_CFG,
5661                                             sgdig | BGE_SGDIGCFG_SEND);
5662                                         DELAY(5);
5663                                         CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
5664                                 }
5665                         }
5666                         break;
5667                 case IFM_1000_SX:
5668                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
5669                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
5670                                     BGE_MACMODE_HALF_DUPLEX);
5671                         } else {
5672                                 BGE_SETBIT(sc, BGE_MAC_MODE,
5673                                     BGE_MACMODE_HALF_DUPLEX);
5674                         }
5675                         DELAY(40);
5676                         break;
5677                 default:
5678                         return (EINVAL);
5679                 }
5680                 return (0);
5681         }
5682
5683         sc->bge_link_evt++;
5684         mii = device_get_softc(sc->bge_miibus);
5685         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
5686                 PHY_RESET(miisc);
5687         mii_mediachg(mii);
5688
5689         /*
5690          * Force an interrupt so that we will call bge_link_upd
5691          * if needed and clear any pending link state attention.
5692          * Without this we are not getting any further interrupts
5693          * for link state changes and thus will not UP the link and
5694          * not be able to send in bge_start_locked. The only
5695          * way to get things working was to receive a packet and
5696          * get an RX intr.
5697          * bge_tick should help for fiber cards and we might not
5698          * need to do this here if BGE_FLAG_TBI is set but as
5699          * we poll for fiber anyway it should not harm.
5700          */
5701         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
5702             sc->bge_flags & BGE_FLAG_5788)
5703                 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
5704         else
5705                 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
5706
5707         return (0);
5708 }
5709
5710 /*
5711  * Report current media status.
5712  */
5713 static void
5714 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
5715 {
5716         struct bge_softc *sc = ifp->if_softc;
5717         struct mii_data *mii;
5718
5719         BGE_LOCK(sc);
5720
5721         if ((ifp->if_flags & IFF_UP) == 0) {
5722                 BGE_UNLOCK(sc);
5723                 return;
5724         }
5725         if (sc->bge_flags & BGE_FLAG_TBI) {
5726                 ifmr->ifm_status = IFM_AVALID;
5727                 ifmr->ifm_active = IFM_ETHER;
5728                 if (CSR_READ_4(sc, BGE_MAC_STS) &
5729                     BGE_MACSTAT_TBI_PCS_SYNCHED)
5730                         ifmr->ifm_status |= IFM_ACTIVE;
5731                 else {
5732                         ifmr->ifm_active |= IFM_NONE;
5733                         BGE_UNLOCK(sc);
5734                         return;
5735                 }
5736                 ifmr->ifm_active |= IFM_1000_SX;
5737                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
5738                         ifmr->ifm_active |= IFM_HDX;
5739                 else
5740                         ifmr->ifm_active |= IFM_FDX;
5741                 BGE_UNLOCK(sc);
5742                 return;
5743         }
5744
5745         mii = device_get_softc(sc->bge_miibus);
5746         mii_pollstat(mii);
5747         ifmr->ifm_active = mii->mii_media_active;
5748         ifmr->ifm_status = mii->mii_media_status;
5749
5750         BGE_UNLOCK(sc);
5751 }
5752
5753 static int
5754 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
5755 {
5756         struct bge_softc *sc = ifp->if_softc;
5757         struct ifreq *ifr = (struct ifreq *) data;
5758         struct mii_data *mii;
5759         int flags, mask, error = 0;
5760
5761         switch (command) {
5762         case SIOCSIFMTU:
5763                 if (BGE_IS_JUMBO_CAPABLE(sc) ||
5764                     (sc->bge_flags & BGE_FLAG_JUMBO_STD)) {
5765                         if (ifr->ifr_mtu < ETHERMIN ||
5766                             ifr->ifr_mtu > BGE_JUMBO_MTU) {
5767                                 error = EINVAL;
5768                                 break;
5769                         }
5770                 } else if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) {
5771                         error = EINVAL;
5772                         break;
5773                 }
5774                 BGE_LOCK(sc);
5775                 if (ifp->if_mtu != ifr->ifr_mtu) {
5776                         ifp->if_mtu = ifr->ifr_mtu;
5777                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5778                                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5779                                 bge_init_locked(sc);
5780                         }
5781                 }
5782                 BGE_UNLOCK(sc);
5783                 break;
5784         case SIOCSIFFLAGS:
5785                 BGE_LOCK(sc);
5786                 if (ifp->if_flags & IFF_UP) {
5787                         /*
5788                          * If only the state of the PROMISC flag changed,
5789                          * then just use the 'set promisc mode' command
5790                          * instead of reinitializing the entire NIC. Doing
5791                          * a full re-init means reloading the firmware and
5792                          * waiting for it to start up, which may take a
5793                          * second or two.  Similarly for ALLMULTI.
5794                          */
5795                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5796                                 flags = ifp->if_flags ^ sc->bge_if_flags;
5797                                 if (flags & IFF_PROMISC)
5798                                         bge_setpromisc(sc);
5799                                 if (flags & IFF_ALLMULTI)
5800                                         bge_setmulti(sc);
5801                         } else
5802                                 bge_init_locked(sc);
5803                 } else {
5804                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5805                                 bge_stop(sc);
5806                         }
5807                 }
5808                 sc->bge_if_flags = ifp->if_flags;
5809                 BGE_UNLOCK(sc);
5810                 error = 0;
5811                 break;
5812         case SIOCADDMULTI:
5813         case SIOCDELMULTI:
5814                 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5815                         BGE_LOCK(sc);
5816                         bge_setmulti(sc);
5817                         BGE_UNLOCK(sc);
5818                         error = 0;
5819                 }
5820                 break;
5821         case SIOCSIFMEDIA:
5822         case SIOCGIFMEDIA:
5823                 if (sc->bge_flags & BGE_FLAG_TBI) {
5824                         error = ifmedia_ioctl(ifp, ifr,
5825                             &sc->bge_ifmedia, command);
5826                 } else {
5827                         mii = device_get_softc(sc->bge_miibus);
5828                         error = ifmedia_ioctl(ifp, ifr,
5829                             &mii->mii_media, command);
5830                 }
5831                 break;
5832         case SIOCSIFCAP:
5833                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
5834 #ifdef DEVICE_POLLING
5835                 if (mask & IFCAP_POLLING) {
5836                         if (ifr->ifr_reqcap & IFCAP_POLLING) {
5837                                 error = ether_poll_register(bge_poll, ifp);
5838                                 if (error)
5839                                         return (error);
5840                                 BGE_LOCK(sc);
5841                                 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5842                                     BGE_PCIMISCCTL_MASK_PCI_INTR);
5843                                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5844                                 ifp->if_capenable |= IFCAP_POLLING;
5845                                 BGE_UNLOCK(sc);
5846                         } else {
5847                                 error = ether_poll_deregister(ifp);
5848                                 /* Enable interrupt even in error case */
5849                                 BGE_LOCK(sc);
5850                                 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
5851                                     BGE_PCIMISCCTL_MASK_PCI_INTR);
5852                                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5853                                 ifp->if_capenable &= ~IFCAP_POLLING;
5854                                 BGE_UNLOCK(sc);
5855                         }
5856                 }
5857 #endif
5858                 if ((mask & IFCAP_TXCSUM) != 0 &&
5859                     (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
5860                         ifp->if_capenable ^= IFCAP_TXCSUM;
5861                         if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
5862                                 ifp->if_hwassist |= sc->bge_csum_features;
5863                         else
5864                                 ifp->if_hwassist &= ~sc->bge_csum_features;
5865                 }
5866
5867                 if ((mask & IFCAP_RXCSUM) != 0 &&
5868                     (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
5869                         ifp->if_capenable ^= IFCAP_RXCSUM;
5870
5871                 if ((mask & IFCAP_TSO4) != 0 &&
5872                     (ifp->if_capabilities & IFCAP_TSO4) != 0) {
5873                         ifp->if_capenable ^= IFCAP_TSO4;
5874                         if ((ifp->if_capenable & IFCAP_TSO4) != 0)
5875                                 ifp->if_hwassist |= CSUM_TSO;
5876                         else
5877                                 ifp->if_hwassist &= ~CSUM_TSO;
5878                 }
5879
5880                 if (mask & IFCAP_VLAN_MTU) {
5881                         ifp->if_capenable ^= IFCAP_VLAN_MTU;
5882                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5883                         bge_init(sc);
5884                 }
5885
5886                 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
5887                     (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
5888                         ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
5889                 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
5890                     (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
5891                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
5892                         if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
5893                                 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
5894                         BGE_LOCK(sc);
5895                         bge_setvlan(sc);
5896                         BGE_UNLOCK(sc);
5897                 }
5898 #ifdef VLAN_CAPABILITIES
5899                 VLAN_CAPABILITIES(ifp);
5900 #endif
5901                 break;
5902         default:
5903                 error = ether_ioctl(ifp, command, data);
5904                 break;
5905         }
5906
5907         return (error);
5908 }
5909
5910 static void
5911 bge_watchdog(struct bge_softc *sc)
5912 {
5913         struct ifnet *ifp;
5914         uint32_t status;
5915
5916         BGE_LOCK_ASSERT(sc);
5917
5918         if (sc->bge_timer == 0 || --sc->bge_timer)
5919                 return;
5920
5921         /* If pause frames are active then don't reset the hardware. */
5922         if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) {
5923                 status = CSR_READ_4(sc, BGE_RX_STS);
5924                 if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) {
5925                         /*
5926                          * If link partner has us in XOFF state then wait for
5927                          * the condition to clear.
5928                          */
5929                         CSR_WRITE_4(sc, BGE_RX_STS, status);
5930                         sc->bge_timer = BGE_TX_TIMEOUT;
5931                         return;
5932                 } else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 &&
5933                     (status & BGE_RXSTAT_RCVD_XON) != 0) {
5934                         /*
5935                          * If link partner has us in XOFF state then wait for
5936                          * the condition to clear.
5937                          */
5938                         CSR_WRITE_4(sc, BGE_RX_STS, status);
5939                         sc->bge_timer = BGE_TX_TIMEOUT;
5940                         return;
5941                 }
5942                 /*
5943                  * Any other condition is unexpected and the controller
5944                  * should be reset.
5945                  */
5946         }
5947
5948         ifp = sc->bge_ifp;
5949
5950         if_printf(ifp, "watchdog timeout -- resetting\n");
5951
5952         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5953         bge_init_locked(sc);
5954
5955         ifp->if_oerrors++;
5956 }
5957
5958 static void
5959 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit)
5960 {
5961         int i;
5962
5963         BGE_CLRBIT(sc, reg, bit);
5964
5965         for (i = 0; i < BGE_TIMEOUT; i++) {
5966                 if ((CSR_READ_4(sc, reg) & bit) == 0)
5967                         return;
5968                 DELAY(100);
5969         }
5970 }
5971
5972 /*
5973  * Stop the adapter and free any mbufs allocated to the
5974  * RX and TX lists.
5975  */
5976 static void
5977 bge_stop(struct bge_softc *sc)
5978 {
5979         struct ifnet *ifp;
5980
5981         BGE_LOCK_ASSERT(sc);
5982
5983         ifp = sc->bge_ifp;
5984
5985         callout_stop(&sc->bge_stat_ch);
5986
5987         /* Disable host interrupts. */
5988         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5989         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5990
5991         /*
5992          * Tell firmware we're shutting down.
5993          */
5994         bge_stop_fw(sc);
5995         bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
5996
5997         /*
5998          * Disable all of the receiver blocks.
5999          */
6000         bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
6001         bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
6002         bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
6003         if (BGE_IS_5700_FAMILY(sc))
6004                 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
6005         bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
6006         bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
6007         bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
6008
6009         /*
6010          * Disable all of the transmit blocks.
6011          */
6012         bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
6013         bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
6014         bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
6015         bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
6016         bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
6017         if (BGE_IS_5700_FAMILY(sc))
6018                 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
6019         bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
6020
6021         /*
6022          * Shut down all of the memory managers and related
6023          * state machines.
6024          */
6025         bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
6026         bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
6027         if (BGE_IS_5700_FAMILY(sc))
6028                 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
6029
6030         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
6031         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
6032         if (!(BGE_IS_5705_PLUS(sc))) {
6033                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
6034                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
6035         }
6036         /* Update MAC statistics. */
6037         if (BGE_IS_5705_PLUS(sc))
6038                 bge_stats_update_regs(sc);
6039
6040         bge_reset(sc);
6041         bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
6042         bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
6043
6044         /*
6045          * Keep the ASF firmware running if up.
6046          */
6047         if (sc->bge_asf_mode & ASF_STACKUP)
6048                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
6049         else
6050                 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
6051
6052         /* Free the RX lists. */
6053         bge_free_rx_ring_std(sc);
6054
6055         /* Free jumbo RX list. */
6056         if (BGE_IS_JUMBO_CAPABLE(sc))
6057                 bge_free_rx_ring_jumbo(sc);
6058
6059         /* Free TX buffers. */
6060         bge_free_tx_ring(sc);
6061
6062         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
6063
6064         /* Clear MAC's link state (PHY may still have link UP). */
6065         if (bootverbose && sc->bge_link)
6066                 if_printf(sc->bge_ifp, "link DOWN\n");
6067         sc->bge_link = 0;
6068
6069         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
6070 }
6071
6072 /*
6073  * Stop all chip I/O so that the kernel's probe routines don't
6074  * get confused by errant DMAs when rebooting.
6075  */
6076 static int
6077 bge_shutdown(device_t dev)
6078 {
6079         struct bge_softc *sc;
6080
6081         sc = device_get_softc(dev);
6082         BGE_LOCK(sc);
6083         bge_stop(sc);
6084         BGE_UNLOCK(sc);
6085
6086         return (0);
6087 }
6088
6089 static int
6090 bge_suspend(device_t dev)
6091 {
6092         struct bge_softc *sc;
6093
6094         sc = device_get_softc(dev);
6095         BGE_LOCK(sc);
6096         bge_stop(sc);
6097         BGE_UNLOCK(sc);
6098
6099         return (0);
6100 }
6101
6102 static int
6103 bge_resume(device_t dev)
6104 {
6105         struct bge_softc *sc;
6106         struct ifnet *ifp;
6107
6108         sc = device_get_softc(dev);
6109         BGE_LOCK(sc);
6110         ifp = sc->bge_ifp;
6111         if (ifp->if_flags & IFF_UP) {
6112                 bge_init_locked(sc);
6113                 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
6114                         bge_start_locked(ifp);
6115         }
6116         BGE_UNLOCK(sc);
6117
6118         return (0);
6119 }
6120
6121 static void
6122 bge_link_upd(struct bge_softc *sc)
6123 {
6124         struct mii_data *mii;
6125         uint32_t link, status;
6126
6127         BGE_LOCK_ASSERT(sc);
6128
6129         /* Clear 'pending link event' flag. */
6130         sc->bge_link_evt = 0;
6131
6132         /*
6133          * Process link state changes.
6134          * Grrr. The link status word in the status block does
6135          * not work correctly on the BCM5700 rev AX and BX chips,
6136          * according to all available information. Hence, we have
6137          * to enable MII interrupts in order to properly obtain
6138          * async link changes. Unfortunately, this also means that
6139          * we have to read the MAC status register to detect link
6140          * changes, thereby adding an additional register access to
6141          * the interrupt handler.
6142          *
6143          * XXX: perhaps link state detection procedure used for
6144          * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
6145          */
6146
6147         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
6148             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
6149                 status = CSR_READ_4(sc, BGE_MAC_STS);
6150                 if (status & BGE_MACSTAT_MI_INTERRUPT) {
6151                         mii = device_get_softc(sc->bge_miibus);
6152                         mii_pollstat(mii);
6153                         if (!sc->bge_link &&
6154                             mii->mii_media_status & IFM_ACTIVE &&
6155                             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
6156                                 sc->bge_link++;
6157                                 if (bootverbose)
6158                                         if_printf(sc->bge_ifp, "link UP\n");
6159                         } else if (sc->bge_link &&
6160                             (!(mii->mii_media_status & IFM_ACTIVE) ||
6161                             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
6162                                 sc->bge_link = 0;
6163                                 if (bootverbose)
6164                                         if_printf(sc->bge_ifp, "link DOWN\n");
6165                         }
6166
6167                         /* Clear the interrupt. */
6168                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
6169                             BGE_EVTENB_MI_INTERRUPT);
6170                         bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr,
6171                             BRGPHY_MII_ISR);
6172                         bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr,
6173                             BRGPHY_MII_IMR, BRGPHY_INTRS);
6174                 }
6175                 return;
6176         }
6177
6178         if (sc->bge_flags & BGE_FLAG_TBI) {
6179                 status = CSR_READ_4(sc, BGE_MAC_STS);
6180                 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
6181                         if (!sc->bge_link) {
6182                                 sc->bge_link++;
6183                                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
6184                                         BGE_CLRBIT(sc, BGE_MAC_MODE,
6185                                             BGE_MACMODE_TBI_SEND_CFGS);
6186                                         DELAY(40);
6187                                 }
6188                                 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
6189                                 if (bootverbose)
6190                                         if_printf(sc->bge_ifp, "link UP\n");
6191                                 if_link_state_change(sc->bge_ifp,
6192                                     LINK_STATE_UP);
6193                         }
6194                 } else if (sc->bge_link) {
6195                         sc->bge_link = 0;
6196                         if (bootverbose)
6197                                 if_printf(sc->bge_ifp, "link DOWN\n");
6198                         if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
6199                 }
6200         } else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
6201                 /*
6202                  * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
6203                  * in status word always set. Workaround this bug by reading
6204                  * PHY link status directly.
6205                  */
6206                 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
6207
6208                 if (link != sc->bge_link ||
6209                     sc->bge_asicrev == BGE_ASICREV_BCM5700) {
6210                         mii = device_get_softc(sc->bge_miibus);
6211                         mii_pollstat(mii);
6212                         if (!sc->bge_link &&
6213                             mii->mii_media_status & IFM_ACTIVE &&
6214                             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
6215                                 sc->bge_link++;
6216                                 if (bootverbose)
6217                                         if_printf(sc->bge_ifp, "link UP\n");
6218                         } else if (sc->bge_link &&
6219                             (!(mii->mii_media_status & IFM_ACTIVE) ||
6220                             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
6221                                 sc->bge_link = 0;
6222                                 if (bootverbose)
6223                                         if_printf(sc->bge_ifp, "link DOWN\n");
6224                         }
6225                 }
6226         } else {
6227                 /*
6228                  * For controllers that call mii_tick, we have to poll
6229                  * link status.
6230                  */
6231                 mii = device_get_softc(sc->bge_miibus);
6232                 mii_pollstat(mii);
6233                 bge_miibus_statchg(sc->bge_dev);
6234         }
6235
6236         /* Disable MAC attention when link is up. */
6237         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
6238             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
6239             BGE_MACSTAT_LINK_CHANGED);
6240 }
6241
6242 static void
6243 bge_add_sysctls(struct bge_softc *sc)
6244 {
6245         struct sysctl_ctx_list *ctx;
6246         struct sysctl_oid_list *children;
6247         char tn[32];
6248         int unit;
6249
6250         ctx = device_get_sysctl_ctx(sc->bge_dev);
6251         children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
6252
6253 #ifdef BGE_REGISTER_DEBUG
6254         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info",
6255             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I",
6256             "Debug Information");
6257
6258         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
6259             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I",
6260             "MAC Register Read");
6261
6262         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ape_read",
6263             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_ape_read, "I",
6264             "APE Register Read");
6265
6266         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read",
6267             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I",
6268             "Memory Read");
6269
6270 #endif
6271
6272         unit = device_get_unit(sc->bge_dev);
6273         /*
6274          * A common design characteristic for many Broadcom client controllers
6275          * is that they only support a single outstanding DMA read operation
6276          * on the PCIe bus. This means that it will take twice as long to fetch
6277          * a TX frame that is split into header and payload buffers as it does
6278          * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For
6279          * these controllers, coalescing buffers to reduce the number of memory
6280          * reads is effective way to get maximum performance(about 940Mbps).
6281          * Without collapsing TX buffers the maximum TCP bulk transfer
6282          * performance is about 850Mbps. However forcing coalescing mbufs
6283          * consumes a lot of CPU cycles, so leave it off by default.
6284          */
6285         sc->bge_forced_collapse = 0;
6286         snprintf(tn, sizeof(tn), "dev.bge.%d.forced_collapse", unit);
6287         TUNABLE_INT_FETCH(tn, &sc->bge_forced_collapse);
6288         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse",
6289             CTLFLAG_RW, &sc->bge_forced_collapse, 0,
6290             "Number of fragmented TX buffers of a frame allowed before "
6291             "forced collapsing");
6292
6293         sc->bge_msi = 1;
6294         snprintf(tn, sizeof(tn), "dev.bge.%d.msi", unit);
6295         TUNABLE_INT_FETCH(tn, &sc->bge_msi);
6296         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "msi",
6297             CTLFLAG_RD, &sc->bge_msi, 0, "Enable MSI");
6298
6299         /*
6300          * It seems all Broadcom controllers have a bug that can generate UDP
6301          * datagrams with checksum value 0 when TX UDP checksum offloading is
6302          * enabled.  Generating UDP checksum value 0 is RFC 768 violation.
6303          * Even though the probability of generating such UDP datagrams is
6304          * low, I don't want to see FreeBSD boxes to inject such datagrams
6305          * into network so disable UDP checksum offloading by default.  Users
6306          * still override this behavior by setting a sysctl variable,
6307          * dev.bge.0.forced_udpcsum.
6308          */
6309         sc->bge_forced_udpcsum = 0;
6310         snprintf(tn, sizeof(tn), "dev.bge.%d.bge_forced_udpcsum", unit);
6311         TUNABLE_INT_FETCH(tn, &sc->bge_forced_udpcsum);
6312         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum",
6313             CTLFLAG_RW, &sc->bge_forced_udpcsum, 0,
6314             "Enable UDP checksum offloading even if controller can "
6315             "generate UDP checksum value 0");
6316
6317         if (BGE_IS_5705_PLUS(sc))
6318                 bge_add_sysctl_stats_regs(sc, ctx, children);
6319         else
6320                 bge_add_sysctl_stats(sc, ctx, children);
6321 }
6322
6323 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \
6324         SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \
6325             sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \
6326             desc)
6327
6328 static void
6329 bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
6330     struct sysctl_oid_list *parent)
6331 {
6332         struct sysctl_oid *tree;
6333         struct sysctl_oid_list *children, *schildren;
6334
6335         tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD,
6336             NULL, "BGE Statistics");
6337         schildren = children = SYSCTL_CHILDREN(tree);
6338         BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters",
6339             children, COSFramesDroppedDueToFilters,
6340             "FramesDroppedDueToFilters");
6341         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full",
6342             children, nicDmaWriteQueueFull, "DmaWriteQueueFull");
6343         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full",
6344             children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull");
6345         BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors",
6346             children, nicNoMoreRxBDs, "NoMoreRxBDs");
6347         BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames",
6348             children, ifInDiscards, "InputDiscards");
6349         BGE_SYSCTL_STAT(sc, ctx, "Input Errors",
6350             children, ifInErrors, "InputErrors");
6351         BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit",
6352             children, nicRecvThresholdHit, "RecvThresholdHit");
6353         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full",
6354             children, nicDmaReadQueueFull, "DmaReadQueueFull");
6355         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full",
6356             children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull");
6357         BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full",
6358             children, nicSendDataCompQueueFull, "SendDataCompQueueFull");
6359         BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index",
6360             children, nicRingSetSendProdIndex, "RingSetSendProdIndex");
6361         BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update",
6362             children, nicRingStatusUpdate, "RingStatusUpdate");
6363         BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts",
6364             children, nicInterrupts, "Interrupts");
6365         BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts",
6366             children, nicAvoidedInterrupts, "AvoidedInterrupts");
6367         BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit",
6368             children, nicSendThresholdHit, "SendThresholdHit");
6369
6370         tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD,
6371             NULL, "BGE RX Statistics");
6372         children = SYSCTL_CHILDREN(tree);
6373         BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets",
6374             children, rxstats.ifHCInOctets, "ifHCInOctets");
6375         BGE_SYSCTL_STAT(sc, ctx, "Fragments",
6376             children, rxstats.etherStatsFragments, "Fragments");
6377         BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets",
6378             children, rxstats.ifHCInUcastPkts, "UnicastPkts");
6379         BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets",
6380             children, rxstats.ifHCInMulticastPkts, "MulticastPkts");
6381         BGE_SYSCTL_STAT(sc, ctx, "FCS Errors",
6382             children, rxstats.dot3StatsFCSErrors, "FCSErrors");
6383         BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors",
6384             children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors");
6385         BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received",
6386             children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived");
6387         BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received",
6388             children, rxstats.xoffPauseFramesReceived,
6389             "xoffPauseFramesReceived");
6390         BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received",
6391             children, rxstats.macControlFramesReceived,
6392             "ControlFramesReceived");
6393         BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered",
6394             children, rxstats.xoffStateEntered, "xoffStateEntered");
6395         BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long",
6396             children, rxstats.dot3StatsFramesTooLong, "FramesTooLong");
6397         BGE_SYSCTL_STAT(sc, ctx, "Jabbers",
6398             children, rxstats.etherStatsJabbers, "Jabbers");
6399         BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets",
6400             children, rxstats.etherStatsUndersizePkts, "UndersizePkts");
6401         BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors",
6402             children, rxstats.inRangeLengthError, "inRangeLengthError");
6403         BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors",
6404             children, rxstats.outRangeLengthError, "outRangeLengthError");
6405
6406         tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD,
6407             NULL, "BGE TX Statistics");
6408         children = SYSCTL_CHILDREN(tree);
6409         BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets",
6410             children, txstats.ifHCOutOctets, "ifHCOutOctets");
6411         BGE_SYSCTL_STAT(sc, ctx, "TX Collisions",
6412             children, txstats.etherStatsCollisions, "Collisions");
6413         BGE_SYSCTL_STAT(sc, ctx, "XON Sent",
6414             children, txstats.outXonSent, "XonSent");
6415         BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent",
6416             children, txstats.outXoffSent, "XoffSent");
6417         BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done",
6418             children, txstats.flowControlDone, "flowControlDone");
6419         BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors",
6420             children, txstats.dot3StatsInternalMacTransmitErrors,
6421             "InternalMacTransmitErrors");
6422         BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames",
6423             children, txstats.dot3StatsSingleCollisionFrames,
6424             "SingleCollisionFrames");
6425         BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames",
6426             children, txstats.dot3StatsMultipleCollisionFrames,
6427             "MultipleCollisionFrames");
6428         BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions",
6429             children, txstats.dot3StatsDeferredTransmissions,
6430             "DeferredTransmissions");
6431         BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions",
6432             children, txstats.dot3StatsExcessiveCollisions,
6433             "ExcessiveCollisions");
6434         BGE_SYSCTL_STAT(sc, ctx, "Late Collisions",
6435             children, txstats.dot3StatsLateCollisions,
6436             "LateCollisions");
6437         BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets",
6438             children, txstats.ifHCOutUcastPkts, "UnicastPkts");
6439         BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets",
6440             children, txstats.ifHCOutMulticastPkts, "MulticastPkts");
6441         BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets",
6442             children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts");
6443         BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors",
6444             children, txstats.dot3StatsCarrierSenseErrors,
6445             "CarrierSenseErrors");
6446         BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards",
6447             children, txstats.ifOutDiscards, "Discards");
6448         BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors",
6449             children, txstats.ifOutErrors, "Errors");
6450 }
6451
6452 #undef BGE_SYSCTL_STAT
6453
6454 #define BGE_SYSCTL_STAT_ADD64(c, h, n, p, d)    \
6455             SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
6456
6457 static void
6458 bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
6459     struct sysctl_oid_list *parent)
6460 {
6461         struct sysctl_oid *tree;
6462         struct sysctl_oid_list *child, *schild;
6463         struct bge_mac_stats *stats;
6464
6465         stats = &sc->bge_mac_stats;
6466         tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD,
6467             NULL, "BGE Statistics");
6468         schild = child = SYSCTL_CHILDREN(tree);
6469         BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesDroppedDueToFilters",
6470             &stats->FramesDroppedDueToFilters, "Frames Dropped Due to Filters");
6471         BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteQueueFull",
6472             &stats->DmaWriteQueueFull, "NIC DMA Write Queue Full");
6473         BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteHighPriQueueFull",
6474             &stats->DmaWriteHighPriQueueFull,
6475             "NIC DMA Write High Priority Queue Full");
6476         BGE_SYSCTL_STAT_ADD64(ctx, child, "NoMoreRxBDs",
6477             &stats->NoMoreRxBDs, "NIC No More RX Buffer Descriptors");
6478         BGE_SYSCTL_STAT_ADD64(ctx, child, "InputDiscards",
6479             &stats->InputDiscards, "Discarded Input Frames");
6480         BGE_SYSCTL_STAT_ADD64(ctx, child, "InputErrors",
6481             &stats->InputErrors, "Input Errors");
6482         BGE_SYSCTL_STAT_ADD64(ctx, child, "RecvThresholdHit",
6483             &stats->RecvThresholdHit, "NIC Recv Threshold Hit");
6484
6485         tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD,
6486             NULL, "BGE RX Statistics");
6487         child = SYSCTL_CHILDREN(tree);
6488         BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCInOctets",
6489             &stats->ifHCInOctets, "Inbound Octets");
6490         BGE_SYSCTL_STAT_ADD64(ctx, child, "Fragments",
6491             &stats->etherStatsFragments, "Fragments");
6492         BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
6493             &stats->ifHCInUcastPkts, "Inbound Unicast Packets");
6494         BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
6495             &stats->ifHCInMulticastPkts, "Inbound Multicast Packets");
6496         BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
6497             &stats->ifHCInBroadcastPkts, "Inbound Broadcast Packets");
6498         BGE_SYSCTL_STAT_ADD64(ctx, child, "FCSErrors",
6499             &stats->dot3StatsFCSErrors, "FCS Errors");
6500         BGE_SYSCTL_STAT_ADD64(ctx, child, "AlignmentErrors",
6501             &stats->dot3StatsAlignmentErrors, "Alignment Errors");
6502         BGE_SYSCTL_STAT_ADD64(ctx, child, "xonPauseFramesReceived",
6503             &stats->xonPauseFramesReceived, "XON Pause Frames Received");
6504         BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffPauseFramesReceived",
6505             &stats->xoffPauseFramesReceived, "XOFF Pause Frames Received");
6506         BGE_SYSCTL_STAT_ADD64(ctx, child, "ControlFramesReceived",
6507             &stats->macControlFramesReceived, "MAC Control Frames Received");
6508         BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffStateEntered",
6509             &stats->xoffStateEntered, "XOFF State Entered");
6510         BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesTooLong",
6511             &stats->dot3StatsFramesTooLong, "Frames Too Long");
6512         BGE_SYSCTL_STAT_ADD64(ctx, child, "Jabbers",
6513             &stats->etherStatsJabbers, "Jabbers");
6514         BGE_SYSCTL_STAT_ADD64(ctx, child, "UndersizePkts",
6515             &stats->etherStatsUndersizePkts, "Undersized Packets");
6516
6517         tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD,
6518             NULL, "BGE TX Statistics");
6519         child = SYSCTL_CHILDREN(tree);
6520         BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCOutOctets",
6521             &stats->ifHCOutOctets, "Outbound Octets");
6522         BGE_SYSCTL_STAT_ADD64(ctx, child, "Collisions",
6523             &stats->etherStatsCollisions, "TX Collisions");
6524         BGE_SYSCTL_STAT_ADD64(ctx, child, "XonSent",
6525             &stats->outXonSent, "XON Sent");
6526         BGE_SYSCTL_STAT_ADD64(ctx, child, "XoffSent",
6527             &stats->outXoffSent, "XOFF Sent");
6528         BGE_SYSCTL_STAT_ADD64(ctx, child, "InternalMacTransmitErrors",
6529             &stats->dot3StatsInternalMacTransmitErrors,
6530             "Internal MAC TX Errors");
6531         BGE_SYSCTL_STAT_ADD64(ctx, child, "SingleCollisionFrames",
6532             &stats->dot3StatsSingleCollisionFrames, "Single Collision Frames");
6533         BGE_SYSCTL_STAT_ADD64(ctx, child, "MultipleCollisionFrames",
6534             &stats->dot3StatsMultipleCollisionFrames,
6535             "Multiple Collision Frames");
6536         BGE_SYSCTL_STAT_ADD64(ctx, child, "DeferredTransmissions",
6537             &stats->dot3StatsDeferredTransmissions, "Deferred Transmissions");
6538         BGE_SYSCTL_STAT_ADD64(ctx, child, "ExcessiveCollisions",
6539             &stats->dot3StatsExcessiveCollisions, "Excessive Collisions");
6540         BGE_SYSCTL_STAT_ADD64(ctx, child, "LateCollisions",
6541             &stats->dot3StatsLateCollisions, "Late Collisions");
6542         BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
6543             &stats->ifHCOutUcastPkts, "Outbound Unicast Packets");
6544         BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
6545             &stats->ifHCOutMulticastPkts, "Outbound Multicast Packets");
6546         BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
6547             &stats->ifHCOutBroadcastPkts, "Outbound Broadcast Packets");
6548 }
6549
6550 #undef  BGE_SYSCTL_STAT_ADD64
6551
6552 static int
6553 bge_sysctl_stats(SYSCTL_HANDLER_ARGS)
6554 {
6555         struct bge_softc *sc;
6556         uint32_t result;
6557         int offset;
6558
6559         sc = (struct bge_softc *)arg1;
6560         offset = arg2;
6561         result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset +
6562             offsetof(bge_hostaddr, bge_addr_lo));
6563         return (sysctl_handle_int(oidp, &result, 0, req));
6564 }
6565
6566 #ifdef BGE_REGISTER_DEBUG
6567 static int
6568 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
6569 {
6570         struct bge_softc *sc;
6571         uint16_t *sbdata;
6572         int error, result, sbsz;
6573         int i, j;
6574
6575         result = -1;
6576         error = sysctl_handle_int(oidp, &result, 0, req);
6577         if (error || (req->newptr == NULL))
6578                 return (error);
6579
6580         if (result == 1) {
6581                 sc = (struct bge_softc *)arg1;
6582
6583                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
6584                     sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
6585                         sbsz = BGE_STATUS_BLK_SZ;
6586                 else
6587                         sbsz = 32;
6588                 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
6589                 printf("Status Block:\n");
6590                 BGE_LOCK(sc);
6591                 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
6592                     sc->bge_cdata.bge_status_map,
6593                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6594                 for (i = 0x0; i < sbsz / sizeof(uint16_t); ) {
6595                         printf("%06x:", i);
6596                         for (j = 0; j < 8; j++)
6597                                 printf(" %04x", sbdata[i++]);
6598                         printf("\n");
6599                 }
6600
6601                 printf("Registers:\n");
6602                 for (i = 0x800; i < 0xA00; ) {
6603                         printf("%06x:", i);
6604                         for (j = 0; j < 8; j++) {
6605                                 printf(" %08x", CSR_READ_4(sc, i));
6606                                 i += 4;
6607                         }
6608                         printf("\n");
6609                 }
6610                 BGE_UNLOCK(sc);
6611
6612                 printf("Hardware Flags:\n");
6613                 if (BGE_IS_5717_PLUS(sc))
6614                         printf(" - 5717 Plus\n");
6615                 if (BGE_IS_5755_PLUS(sc))
6616                         printf(" - 5755 Plus\n");
6617                 if (BGE_IS_575X_PLUS(sc))
6618                         printf(" - 575X Plus\n");
6619                 if (BGE_IS_5705_PLUS(sc))
6620                         printf(" - 5705 Plus\n");
6621                 if (BGE_IS_5714_FAMILY(sc))
6622                         printf(" - 5714 Family\n");
6623                 if (BGE_IS_5700_FAMILY(sc))
6624                         printf(" - 5700 Family\n");
6625                 if (sc->bge_flags & BGE_FLAG_JUMBO)
6626                         printf(" - Supports Jumbo Frames\n");
6627                 if (sc->bge_flags & BGE_FLAG_PCIX)
6628                         printf(" - PCI-X Bus\n");
6629                 if (sc->bge_flags & BGE_FLAG_PCIE)
6630                         printf(" - PCI Express Bus\n");
6631                 if (sc->bge_phy_flags & BGE_PHY_NO_3LED)
6632                         printf(" - No 3 LEDs\n");
6633                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
6634                         printf(" - RX Alignment Bug\n");
6635         }
6636
6637         return (error);
6638 }
6639
6640 static int
6641 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
6642 {
6643         struct bge_softc *sc;
6644         int error;
6645         uint16_t result;
6646         uint32_t val;
6647
6648         result = -1;
6649         error = sysctl_handle_int(oidp, &result, 0, req);
6650         if (error || (req->newptr == NULL))
6651                 return (error);
6652
6653         if (result < 0x8000) {
6654                 sc = (struct bge_softc *)arg1;
6655                 val = CSR_READ_4(sc, result);
6656                 printf("reg 0x%06X = 0x%08X\n", result, val);
6657         }
6658
6659         return (error);
6660 }
6661
6662 static int
6663 bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS)
6664 {
6665         struct bge_softc *sc;
6666         int error;
6667         uint16_t result;
6668         uint32_t val;
6669
6670         result = -1;
6671         error = sysctl_handle_int(oidp, &result, 0, req);
6672         if (error || (req->newptr == NULL))
6673                 return (error);
6674
6675         if (result < 0x8000) {
6676                 sc = (struct bge_softc *)arg1;
6677                 val = APE_READ_4(sc, result);
6678                 printf("reg 0x%06X = 0x%08X\n", result, val);
6679         }
6680
6681         return (error);
6682 }
6683
6684 static int
6685 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)
6686 {
6687         struct bge_softc *sc;
6688         int error;
6689         uint16_t result;
6690         uint32_t val;
6691
6692         result = -1;
6693         error = sysctl_handle_int(oidp, &result, 0, req);
6694         if (error || (req->newptr == NULL))
6695                 return (error);
6696
6697         if (result < 0x8000) {
6698                 sc = (struct bge_softc *)arg1;
6699                 val = bge_readmem_ind(sc, result);
6700                 printf("mem 0x%06X = 0x%08X\n", result, val);
6701         }
6702
6703         return (error);
6704 }
6705 #endif
6706
6707 static int
6708 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[])
6709 {
6710
6711         if (sc->bge_flags & BGE_FLAG_EADDR)
6712                 return (1);
6713
6714 #ifdef __sparc64__
6715         OF_getetheraddr(sc->bge_dev, ether_addr);
6716         return (0);
6717 #endif
6718         return (1);
6719 }
6720
6721 static int
6722 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
6723 {
6724         uint32_t mac_addr;
6725
6726         mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB);
6727         if ((mac_addr >> 16) == 0x484b) {
6728                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
6729                 ether_addr[1] = (uint8_t)mac_addr;
6730                 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB);
6731                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
6732                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
6733                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
6734                 ether_addr[5] = (uint8_t)mac_addr;
6735                 return (0);
6736         }
6737         return (1);
6738 }
6739
6740 static int
6741 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
6742 {
6743         int mac_offset = BGE_EE_MAC_OFFSET;
6744
6745         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6746                 mac_offset = BGE_EE_MAC_OFFSET_5906;
6747
6748         return (bge_read_nvram(sc, ether_addr, mac_offset + 2,
6749             ETHER_ADDR_LEN));
6750 }
6751
6752 static int
6753 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
6754 {
6755
6756         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6757                 return (1);
6758
6759         return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
6760            ETHER_ADDR_LEN));
6761 }
6762
6763 static int
6764 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
6765 {
6766         static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
6767                 /* NOTE: Order is critical */
6768                 bge_get_eaddr_fw,
6769                 bge_get_eaddr_mem,
6770                 bge_get_eaddr_nvram,
6771                 bge_get_eaddr_eeprom,
6772                 NULL
6773         };
6774         const bge_eaddr_fcn_t *func;
6775
6776         for (func = bge_eaddr_funcs; *func != NULL; ++func) {
6777                 if ((*func)(sc, eaddr) == 0)
6778                         break;
6779         }
6780         return (*func == NULL ? ENXIO : 0);
6781 }