sys/dev/bwn/if_bwnvar.h

   1 /*-
   2  * Copyright (c) 2009-2010 Weongyo Jeong <weongyo@freebsd.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer,
  10  *    without modification.
  11  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  12  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
  13  *    redistribution must be conditioned upon including a substantially
  14  *    similar Disclaimer requirement for further binary redistribution.
  15  *
  16  * NO WARRANTY
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
  20  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
  21  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
  22  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  23  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  24  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
  25  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  26  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  27  * THE POSSIBILITY OF SUCH DAMAGES.
  28  *
  29  * $FreeBSD$
  30  */
  31
  32 #ifndef _IF_BWNVAR_H
  33 #define _IF_BWNVAR_H
  34
  35 struct siba_dev_softc;
  36 struct bwn_softc;
  37 struct bwn_mac;
  38
  39 #define N(a)                    (sizeof(a) / sizeof(a[0]))
  40 #define BWN_ALIGN                       0x1000
  41 #define BWN_BUS_SPACE_MAXADDR_30BIT     0x3fffffff
  42 #define BWN_RETRY_SHORT                 7
  43 #define BWN_RETRY_LONG                  4
  44 #define BWN_STAID_MAX                   64
  45 #define BWN_TXPWR_IGNORE_TIME           (1 << 0)
  46 #define BWN_TXPWR_IGNORE_TSSI           (1 << 1)
  47 #define BWN_HAS_TXMAG(phy)                                              \
  48         (((phy)->rev >= 2) && ((phy)->rf_ver == 0x2050) &&              \
  49          ((phy)->rf_rev == 8))
  50 #define BWN_HAS_LOOPBACK(phy)                                           \
  51         (((phy)->rev > 1) || ((phy)->gmode))
  52 #define BWN_TXERROR_MAX                 1000
  53 #define BWN_GETTIME(v)  do {                                            \
  54         struct timespec ts;                                             \
  55         nanouptime(&ts);                                                \
  56         (v) = ts.tv_nsec / 1000000 + ts.tv_sec * 1000;                  \
  57 } while (0)
  58 #define BWN_ISOLDFMT(mac)               ((mac)->mac_fw.rev <= 351)
  59 #define BWN_TSSI2DBM(num, den)                                          \
  60         ((int32_t)((num < 0) ? num / den : (num + den / 2) / den))
  61 #define BWN_HDRSIZE(mac)                                                \
  62         ((BWN_ISOLDFMT(mac)) ? (100 + sizeof(struct bwn_plcp6)) :       \
  63             (104 + sizeof(struct bwn_plcp6)))
  64 #define BWN_PIO_COOKIE(tq, tp)                                          \
  65         ((uint16_t)((((uint16_t)tq->tq_index + 1) << 12) | tp->tp_index))
  66 #define BWN_DMA_COOKIE(dr, slot)                                        \
  67         ((uint16_t)(((uint16_t)dr->dr_index + 1) << 12) | (uint16_t)slot)
  68 #define BWN_READ_2(mac, o)              (siba_read_2(mac->mac_sc->sc_dev, o))
  69 #define BWN_READ_4(mac, o)              (siba_read_4(mac->mac_sc->sc_dev, o))
  70 #define BWN_WRITE_2(mac, o, v)                                          \
  71         (siba_write_2(mac->mac_sc->sc_dev, o, v))
  72 #define BWN_WRITE_4(mac, o, v)                                          \
  73         (siba_write_4(mac->mac_sc->sc_dev, o, v))
  74 #define BWN_PIO_TXQOFFSET(mac)                                          \
  75         ((siba_get_revid(mac->mac_sc->sc_dev) >= 11) ? 0x18 : 0)
  76 #define BWN_PIO_RXQOFFSET(mac)                                          \
  77         ((siba_get_revid(mac->mac_sc->sc_dev) >= 11) ? 0x38 : 8)
  78 #define BWN_SEC_NEWAPI(mac)             (mac->mac_fw.rev >= 351)
  79 #define BWN_SEC_KEY2FW(mac, idx)                                        \
  80         (BWN_SEC_NEWAPI(mac) ? idx : ((idx >= 4) ? idx - 4 : idx))
  81 #define BWN_RF_READ(mac, r)             (mac->mac_phy.rf_read(mac, r))
  82 #define BWN_RF_WRITE(mac, r, v)         (mac->mac_phy.rf_write(mac, r, v))
  83 #define BWN_RF_MASK(mac, o, m)                                          \
  84         BWN_RF_WRITE(mac, o, BWN_RF_READ(mac, o) & m)
  85 #define BWN_RF_SETMASK(mac, offset, mask, set)                          \
  86         BWN_RF_WRITE(mac, offset, (BWN_RF_READ(mac, offset) & mask) | set)
  87 #define BWN_RF_SET(mac, offset, set)                                    \
  88         BWN_RF_WRITE(mac, offset, BWN_RF_READ(mac, offset) | set)
  89 #define BWN_PHY_READ(mac, r)            (mac->mac_phy.phy_read(mac, r))
  90 #define BWN_PHY_WRITE(mac, r, v)                                        \
  91         (mac->mac_phy.phy_write(mac, r, v))
  92 #define BWN_PHY_SET(mac, offset, set)   do {                            \
  93         if (mac->mac_phy.phy_maskset != NULL) {                         \
  94                 KASSERT(mac->mac_status < BWN_MAC_STATUS_INITED ||      \
  95                     mac->mac_suspended > 0,                             \
  96                     ("dont access PHY or RF registers after turning on MAC")); \
  97                 mac->mac_phy.phy_maskset(mac, offset, 0xffff, set);     \
  98         } else                                                          \
  99                 BWN_PHY_WRITE(mac, offset,                              \
 100                     BWN_PHY_READ(mac, offset) | (set));                 \
 101 } while (0)
 102 #define BWN_PHY_SETMASK(mac, offset, mask, set) do {                    \
 103         if (mac->mac_phy.phy_maskset != NULL) {                         \
 104                 KASSERT(mac->mac_status < BWN_MAC_STATUS_INITED ||      \
 105                     mac->mac_suspended > 0,                             \
 106                     ("dont access PHY or RF registers after turning on MAC")); \
 107                 mac->mac_phy.phy_maskset(mac, offset, mask, set);       \
 108         } else                                                          \
 109                 BWN_PHY_WRITE(mac, offset,                              \
 110                     (BWN_PHY_READ(mac, offset) & (mask)) | (set));      \
 111 } while (0)
 112 #define BWN_PHY_MASK(mac, offset, mask) do {                            \
 113         if (mac->mac_phy.phy_maskset != NULL) {                         \
 114                 KASSERT(mac->mac_status < BWN_MAC_STATUS_INITED ||      \
 115                     mac->mac_suspended > 0,                             \
 116                     ("dont access PHY or RF registers after turning on MAC")); \
 117                 mac->mac_phy.phy_maskset(mac, offset, mask, 0);         \
 118         } else                                                          \
 119                 BWN_PHY_WRITE(mac, offset,                              \
 120                     BWN_PHY_READ(mac, offset) & mask);                  \
 121 } while (0)
 122 #define BWN_PHY_COPY(mac, dst, src)     do {                            \
 123         KASSERT(mac->mac_status < BWN_MAC_STATUS_INITED ||              \
 124             mac->mac_suspended > 0,                                     \
 125             ("dont access PHY or RF registers after turning on MAC"));  \
 126         BWN_PHY_WRITE(mac, dst, BWN_PHY_READ(mac, src));                \
 127 } while (0)
 128 #define BWN_LO_CALIB_EXPIRE             (1000 * (30 - 2))
 129 #define BWN_LO_PWRVEC_EXPIRE            (1000 * (30 - 2))
 130 #define BWN_LO_TXCTL_EXPIRE             (1000 * (180 - 4))
 131 #define BWN_DMA_BIT_MASK(n)             (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
 132 #define BWN_LPD(L, P, D)                (((L) << 2) | ((P) << 1) | ((D) << 0))
 133 #define BWN_BITREV4(tmp)                (BWN_BITREV8(tmp) >> 4)
 134 #define BWN_BITREV8(byte)               (bwn_bitrev_table[byte])
 135 #define BWN_BBATTCMP(a, b)              ((a)->att == (b)->att)
 136 #define BWN_RFATTCMP(a, b)                                              \
 137         (((a)->att == (b)->att) && ((a)->padmix == (b)->padmix))
 138 #define BWN_PIO_WRITE_2(mac, tq, offset, value)                         \
 139         BWN_WRITE_2(mac, (tq)->tq_base + offset, value)
 140 #define BWN_PIO_READ_4(mac, tq, offset)                                 \
 141         BWN_READ_4(mac, tq->tq_base + offset)
 142 #define BWN_ISCCKRATE(rate)                                             \
 143         (rate == BWN_CCK_RATE_1MB || rate == BWN_CCK_RATE_2MB ||        \
 144          rate == BWN_CCK_RATE_5MB || rate == BWN_CCK_RATE_11MB)
 145 #define BWN_ISOFDMRATE(rate)            (!BWN_ISCCKRATE(rate))
 146 #define BWN_BARRIER(mac, flags)         siba_barrier(mac->mac_sc->sc_dev, flags)
 147 #define BWN_DMA_READ(dr, offset)                                \
 148         (BWN_READ_4(dr->dr_mac, dr->dr_base + offset))
 149 #define BWN_DMA_WRITE(dr, offset, value)                        \
 150         (BWN_WRITE_4(dr->dr_mac, dr->dr_base + offset, value))
 151
 152 struct bwn_rate {
 153         uint16_t                        rateid;
 154         uint32_t                        flags;
 155 };
 156
 157 #define BWN_ANT0                        0
 158 #define BWN_ANT1                        1
 159 #define BWN_ANTAUTO0                    2
 160 #define BWN_ANTAUTO1                    3
 161 #define BWN_ANT2                        4
 162 #define BWN_ANT3                        8
 163 #define BWN_ANTAUTO                     BWN_ANTAUTO0
 164 #define BWN_ANT_DEFAULT                 BWN_ANTAUTO
 165 #define BWN_TX_SLOTS_PER_FRAME          2
 166
 167 struct bwn_channel {
 168         unsigned                        freq;
 169         unsigned                        ieee;
 170         unsigned                        maxTxPow;
 171 };
 172
 173 struct bwn_channelinfo {
 174         struct bwn_channel              channels[IEEE80211_CHAN_MAX];
 175         unsigned                        nchannels;
 176 };
 177
 178 struct bwn_bbatt {
 179         uint8_t                         att;
 180 };
 181
 182 struct bwn_bbatt_list {
 183         const struct bwn_bbatt          *array;
 184         uint8_t                         len;
 185         uint8_t                         min;
 186         uint8_t                         max;
 187 };
 188
 189 struct bwn_rfatt {
 190         uint8_t                         att;
 191         int                             padmix;
 192 };
 193
 194 struct bwn_rfatt_list {
 195         const struct bwn_rfatt          *array;
 196         uint8_t                         len;
 197         uint8_t                         min;
 198         uint8_t                         max;
 199 };
 200
 201 #define BWN_DC_LT_SIZE                  32
 202
 203 struct bwn_loctl {
 204         int8_t                          i;
 205         int8_t                          q;
 206 };
 207
 208 struct bwn_lo_calib {
 209         struct bwn_bbatt                bbatt;
 210         struct bwn_rfatt                rfatt;
 211         struct bwn_loctl                ctl;
 212         unsigned long                   calib_time;
 213         TAILQ_ENTRY(bwn_lo_calib)       list;
 214 };
 215
 216 struct bwn_rxhdr4 {
 217         uint16_t                        frame_len;
 218         uint8_t                         pad1[2];
 219         uint16_t                        phy_status0;
 220         union {
 221                 struct {
 222                         uint8_t         rssi;
 223                         uint8_t         sig_qual;
 224                 } __packed abg;
 225                 struct {
 226                         int8_t          power0;
 227                         int8_t          power1;
 228                 } __packed n;
 229         } __packed phy;
 230         uint16_t                        phy_status2;
 231         uint16_t                        phy_status3;
 232         uint32_t                        mac_status;
 233         uint16_t                        mac_time;
 234         uint16_t                        channel;
 235 } __packed;
 236
 237 struct bwn_txstatus {
 238         uint16_t                        cookie;
 239         uint16_t                        seq;
 240         uint8_t                         phy_stat;
 241         uint8_t                         framecnt;
 242         uint8_t                         rtscnt;
 243         uint8_t                         sreason;
 244         uint8_t                         pm;
 245         uint8_t                         im;
 246         uint8_t                         ampdu;
 247         uint8_t                         ack;
 248 };
 249
 250 #define BWN_TXCTL_PA3DB                 0x40
 251 #define BWN_TXCTL_PA2DB                 0x20
 252 #define BWN_TXCTL_TXMIX                 0x10
 253
 254 struct bwn_txpwr_loctl {
 255         struct bwn_rfatt_list           rfatt;
 256         struct bwn_bbatt_list           bbatt;
 257         uint16_t                        dc_lt[BWN_DC_LT_SIZE];
 258         TAILQ_HEAD(, bwn_lo_calib)      calib_list;
 259         unsigned long                   pwr_vec_read_time;
 260         unsigned long                   txctl_measured_time;
 261         uint8_t                         tx_bias;
 262         uint8_t                         tx_magn;
 263         uint64_t                        power_vector;
 264 };
 265
 266 #define BWN_OFDMTAB_DIR_UNKNOWN         0
 267 #define BWN_OFDMTAB_DIR_READ            1
 268 #define BWN_OFDMTAB_DIR_WRITE           2
 269
 270 struct bwn_phy_g {
 271         unsigned                        pg_flags;
 272 #define BWN_PHY_G_FLAG_TSSITABLE_ALLOC  (1 << 0)
 273 #define BWN_PHY_G_FLAG_RADIOCTX_VALID   (1 << 1)
 274         int                             pg_aci_enable;
 275         int                             pg_aci_wlan_automatic;
 276         int                             pg_aci_hw_rssi;
 277         int                             pg_rf_on;
 278         uint16_t                        pg_radioctx_over;
 279         uint16_t                        pg_radioctx_overval;
 280         uint16_t                        pg_minlowsig[2];
 281         uint16_t                        pg_minlowsigpos[2];
 282         int8_t                          *pg_tssi2dbm;
 283         int                             pg_idletssi;
 284         int                             pg_curtssi;
 285         uint8_t                         pg_avgtssi;
 286         struct bwn_bbatt                pg_bbatt;
 287         struct bwn_rfatt                pg_rfatt;
 288         uint8_t                         pg_txctl;
 289         int                             pg_bbatt_delta;
 290         int                             pg_rfatt_delta;
 291
 292         struct bwn_txpwr_loctl          pg_loctl;
 293         int16_t                         pg_max_lb_gain;
 294         int16_t                         pg_trsw_rx_gain;
 295         int16_t                         pg_lna_lod_gain;
 296         int16_t                         pg_lna_gain;
 297         int16_t                         pg_pga_gain;
 298         int                             pg_immode;
 299 #define BWN_INTERFSTACK_SIZE    26
 300         uint32_t                        pg_interfstack[BWN_INTERFSTACK_SIZE];
 301
 302         int16_t                         pg_nrssi[2];
 303         int32_t                         pg_nrssi_slope;
 304         int8_t                          pg_nrssi_lt[64];
 305
 306         uint16_t                        pg_lofcal;
 307
 308         uint16_t                        pg_initval;
 309         uint16_t                        pg_ofdmtab_addr;
 310         unsigned                        pg_ofdmtab_dir;
 311 };
 312
 313 #define BWN_IMMODE_NONE                 0
 314 #define BWN_IMMODE_NONWLAN              1
 315 #define BWN_IMMODE_MANUAL               2
 316 #define BWN_IMMODE_AUTO                 3
 317 #define BWN_TXPWR_RES_NEED_ADJUST       0
 318 #define BWN_TXPWR_RES_DONE              1
 319
 320 #define BWN_PHYLP_TXPCTL_UNKNOWN        0
 321 #define BWN_PHYLP_TXPCTL_OFF            1
 322 #define BWN_PHYLP_TXPCTL_ON_SW          2
 323 #define BWN_PHYLP_TXPCTL_ON_HW          3
 324
 325 struct bwn_phy_lp {
 326         uint8_t                         plp_chan;
 327         uint8_t                         plp_chanfullcal;
 328         int32_t                         plp_antenna;
 329         uint8_t                         plp_txpctlmode;
 330         uint8_t                         plp_txisoband_h;
 331         uint8_t                         plp_txisoband_m;
 332         uint8_t                         plp_txisoband_l;
 333         uint8_t                         plp_rxpwroffset;
 334         int8_t                          plp_txpwridx;
 335         uint16_t                        plp_tssiidx;
 336         uint16_t                        plp_tssinpt;
 337         uint8_t                         plp_rssivf;
 338         uint8_t                         plp_rssivc;
 339         uint8_t                         plp_rssigs;
 340         uint8_t                         plp_rccap;
 341         uint8_t                         plp_bxarch;
 342         uint8_t                         plp_crsusr_off;
 343         uint8_t                         plp_crssys_off;
 344         uint32_t                        plp_div;
 345         int32_t                         plp_tonefreq;
 346         uint16_t                        plp_digfilt[9];
 347 };
 348
 349 /* for LP */
 350 struct bwn_txgain {
 351         uint16_t                        tg_gm;
 352         uint16_t                        tg_pga;
 353         uint16_t                        tg_pad;
 354         uint16_t                        tg_dac;
 355 };
 356
 357 struct bwn_rxcompco {
 358         uint8_t                         rc_chan;
 359         int8_t                          rc_c1;
 360         int8_t                          rc_c0;
 361 };
 362
 363 struct bwn_phy_lp_iq_est {
 364         uint32_t                        ie_iqprod;
 365         uint32_t                        ie_ipwr;
 366         uint32_t                        ie_qpwr;
 367 };
 368
 369 struct bwn_txgain_entry {
 370         uint8_t                         te_gm;
 371         uint8_t                         te_pga;
 372         uint8_t                         te_pad;
 373         uint8_t                         te_dac;
 374         uint8_t                         te_bbmult;
 375 };
 376
 377 /* only for LP PHY */
 378 struct bwn_stxtable {
 379         uint16_t                        st_phyoffset;
 380         uint16_t                        st_physhift;
 381         uint16_t                        st_rfaddr;
 382         uint16_t                        st_rfshift;
 383         uint16_t                        st_mask;
 384 };
 385
 386 struct bwn_b206x_chan {
 387         uint8_t                         bc_chan;
 388         uint16_t                        bc_freq;
 389         const uint8_t                   *bc_data;
 390 };
 391
 392 struct bwn_b206x_rfinit_entry {
 393         uint16_t                        br_offset;
 394         uint16_t                        br_valuea;
 395         uint16_t                        br_valueg;
 396         uint8_t                         br_flags;
 397 };
 398
 399 struct bwn_phy {
 400         uint8_t                         type;
 401         uint8_t                         rev;
 402         uint8_t                         analog;
 403
 404         int                             supports_2ghz;
 405         int                             supports_5ghz;
 406
 407         int                             gmode;
 408         struct bwn_phy_g                phy_g;
 409         struct bwn_phy_lp               phy_lp;
 410
 411         uint16_t                        rf_manuf;
 412         uint16_t                        rf_ver;
 413         uint8_t                         rf_rev;
 414         int                             rf_on;
 415
 416         int                             txpower;
 417         int                             hwpctl;
 418         unsigned long                   nexttime;
 419         unsigned int                    chan;
 420         int                             txerrors;
 421
 422         int                             (*attach)(struct bwn_mac *);
 423         void                            (*detach)(struct bwn_mac *);
 424         int                             (*prepare_hw)(struct bwn_mac *);
 425         void                            (*init_pre)(struct bwn_mac *);
 426         int                             (*init)(struct bwn_mac *);
 427         void                            (*exit)(struct bwn_mac *);
 428         uint16_t                        (*phy_read)(struct bwn_mac *, uint16_t);
 429         void                            (*phy_write)(struct bwn_mac *, uint16_t,
 430                                             uint16_t);
 431         void                            (*phy_maskset)(struct bwn_mac *,
 432                                             uint16_t, uint16_t, uint16_t);
 433         uint16_t                        (*rf_read)(struct bwn_mac *, uint16_t);
 434         void                            (*rf_write)(struct bwn_mac *, uint16_t,
 435                                             uint16_t);
 436         int                             (*use_hwpctl)(struct bwn_mac *);
 437         void                            (*rf_onoff)(struct bwn_mac *, int);
 438         void                            (*switch_analog)(struct bwn_mac *, int);
 439         int                             (*switch_channel)(struct bwn_mac *,
 440                                             unsigned int);
 441         uint32_t                        (*get_default_chan)(struct bwn_mac *);
 442         void                            (*set_antenna)(struct bwn_mac *, int);
 443         int                             (*set_im)(struct bwn_mac *, int);
 444         int                             (*recalc_txpwr)(struct bwn_mac *, int);
 445         void                            (*set_txpwr)(struct bwn_mac *);
 446         void                            (*task_15s)(struct bwn_mac *);
 447         void                            (*task_60s)(struct bwn_mac *);
 448 };
 449
 450 struct bwn_chan_band {
 451         uint32_t                        flags;
 452         uint8_t                         nchan;
 453 #define BWN_MAX_CHAN_PER_BAND           14
 454         uint8_t                         chan[BWN_MAX_CHAN_PER_BAND];
 455 };
 456
 457 #define BWN_NR_WMEPARAMS                16
 458 enum {
 459         BWN_WMEPARAM_TXOP = 0,
 460         BWN_WMEPARAM_CWMIN,
 461         BWN_WMEPARAM_CWMAX,
 462         BWN_WMEPARAM_CWCUR,
 463         BWN_WMEPARAM_AIFS,
 464         BWN_WMEPARAM_BSLOTS,
 465         BWN_WMEPARAM_REGGAP,
 466         BWN_WMEPARAM_STATUS,
 467 };
 468
 469 #define BWN_WME_PARAMS(queue)   \
 470         (BWN_SHARED_EDCFQ + (BWN_NR_WMEPARAMS * sizeof(uint16_t) * (queue)))
 471 #define BWN_WME_BACKGROUND      BWN_WME_PARAMS(0)
 472 #define BWN_WME_BESTEFFORT      BWN_WME_PARAMS(1)
 473 #define BWN_WME_VIDEO           BWN_WME_PARAMS(2)
 474 #define BWN_WME_VOICE           BWN_WME_PARAMS(3)
 475
 476 /*
 477  * Radio capture format.
 478  */
 479 #define BWN_RX_RADIOTAP_PRESENT (               \
 480         (1 << IEEE80211_RADIOTAP_TSFT)          | \
 481         (1 << IEEE80211_RADIOTAP_FLAGS)         | \
 482         (1 << IEEE80211_RADIOTAP_RATE)          | \
 483         (1 << IEEE80211_RADIOTAP_CHANNEL)       | \
 484         (1 << IEEE80211_RADIOTAP_ANTENNA)       | \
 485         (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \
 486         (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE)  | \
 487         0)
 488
 489 struct bwn_rx_radiotap_header {
 490         struct ieee80211_radiotap_header wr_ihdr;
 491         uint64_t                        wr_tsf;
 492         u_int8_t                        wr_flags;
 493         u_int8_t                        wr_rate;
 494         u_int16_t                       wr_chan_freq;
 495         u_int16_t                       wr_chan_flags;
 496         int8_t                          wr_antsignal;
 497         int8_t                          wr_antnoise;
 498         u_int8_t                        wr_antenna;
 499 };
 500
 501 #define BWN_TX_RADIOTAP_PRESENT (               \
 502         (1 << IEEE80211_RADIOTAP_FLAGS)         | \
 503         (1 << IEEE80211_RADIOTAP_RATE)          | \
 504         (1 << IEEE80211_RADIOTAP_CHANNEL)       | \
 505         (1 << IEEE80211_RADIOTAP_DBM_TX_POWER)  | \
 506         (1 << IEEE80211_RADIOTAP_ANTENNA)       | \
 507         0)
 508
 509 struct bwn_tx_radiotap_header {
 510         struct ieee80211_radiotap_header wt_ihdr;
 511         u_int8_t                        wt_flags;
 512         u_int8_t                        wt_rate;
 513         u_int16_t                       wt_chan_freq;
 514         u_int16_t                       wt_chan_flags;
 515         u_int8_t                        wt_txpower;
 516         u_int8_t                        wt_antenna;
 517 };
 518
 519 struct bwn_stats {
 520         int32_t                         rtsfail;
 521         int32_t                         rts;
 522         int32_t                         link_noise;
 523 };
 524
 525 /* Noise Calculation (Link Quality) */
 526 struct bwn_noise {
 527         uint8_t                         noi_running;
 528         uint8_t                         noi_nsamples;
 529         int8_t                          noi_samples[8][4];
 530 };
 531
 532 #define BWN_DMA_30BIT                   30
 533 #define BWN_DMA_32BIT                   32
 534 #define BWN_DMA_64BIT                   64
 535
 536 struct bwn_dmadesc_meta {
 537         bus_dmamap_t                    mt_dmap;
 538         bus_addr_t                      mt_paddr;
 539         struct mbuf                     *mt_m;
 540         struct ieee80211_node           *mt_ni;
 541         uint8_t                         mt_txtype;
 542 #define BWN_DMADESC_METATYPE_HEADER     0
 543 #define BWN_DMADESC_METATYPE_BODY       1
 544         uint8_t                         mt_islast;
 545 };
 546
 547 #define BWN_DMAINTR_FATALMASK   \
 548         ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 14) | (1 << 15))
 549 #define BWN_DMAINTR_NONFATALMASK        (1 << 13)
 550 #define BWN_DMAINTR_RX_DONE             (1 << 16)
 551
 552 #define BWN_DMA32_DCTL_BYTECNT          0x00001fff
 553 #define BWN_DMA32_DCTL_ADDREXT_MASK     0x00030000
 554 #define BWN_DMA32_DCTL_ADDREXT_SHIFT    16
 555 #define BWN_DMA32_DCTL_DTABLEEND        0x10000000
 556 #define BWN_DMA32_DCTL_IRQ              0x20000000
 557 #define BWN_DMA32_DCTL_FRAMEEND         0x40000000
 558 #define BWN_DMA32_DCTL_FRAMESTART       0x80000000
 559 struct bwn_dmadesc32 {
 560         uint32_t                        control;
 561         uint32_t                        address;
 562 } __packed;
 563
 564 #define BWN_DMA64_DCTL0_DTABLEEND       0x10000000
 565 #define BWN_DMA64_DCTL0_IRQ             0x20000000
 566 #define BWN_DMA64_DCTL0_FRAMEEND        0x40000000
 567 #define BWN_DMA64_DCTL0_FRAMESTART      0x80000000
 568 #define BWN_DMA64_DCTL1_BYTECNT         0x00001fff
 569 #define BWN_DMA64_DCTL1_ADDREXT_MASK    0x00030000
 570 #define BWN_DMA64_DCTL1_ADDREXT_SHIFT   16
 571 struct bwn_dmadesc64 {
 572         uint32_t                        control0;
 573         uint32_t                        control1;
 574         uint32_t                        address_low;
 575         uint32_t                        address_high;
 576 } __packed;
 577
 578 struct bwn_dmadesc_generic {
 579         union {
 580                 struct bwn_dmadesc32 dma32;
 581                 struct bwn_dmadesc64 dma64;
 582         } __packed dma;
 583 } __packed;
 584
 585 struct bwn_dma_ring;
 586
 587 struct bwn_dma_ring {
 588         struct bwn_mac                  *dr_mac;
 589         const struct bwn_dma_ops        *dr_ops;
 590         struct bwn_dmadesc_meta         *dr_meta;
 591         void                            *dr_txhdr_cache;
 592         bus_dma_tag_t                   dr_ring_dtag;
 593         bus_dma_tag_t                   dr_txring_dtag;
 594         bus_dmamap_t                    dr_spare_dmap; /* only for RX */
 595         bus_dmamap_t                    dr_ring_dmap;
 596         bus_addr_t                      dr_txring_paddr;
 597         void                            *dr_ring_descbase;
 598         bus_addr_t                      dr_ring_dmabase;
 599         int                             dr_numslots;
 600         int                             dr_usedslot;
 601         int                             dr_curslot;
 602         uint32_t                        dr_frameoffset;
 603         uint16_t                        dr_rx_bufsize;
 604         uint16_t                        dr_base;
 605         int                             dr_index;
 606         uint8_t                         dr_tx;
 607         uint8_t                         dr_stop;
 608         int                             dr_type;
 609
 610         void                            (*getdesc)(struct bwn_dma_ring *,
 611                                             int, struct bwn_dmadesc_generic **,
 612                                             struct bwn_dmadesc_meta **);
 613         void                            (*setdesc)(struct bwn_dma_ring *,
 614                                             struct bwn_dmadesc_generic *,
 615                                             bus_addr_t, uint16_t, int, int,
 616                                             int);
 617         void                            (*start_transfer)(struct bwn_dma_ring *,
 618                                             int);
 619         void                            (*suspend)(struct bwn_dma_ring *);
 620         void                            (*resume)(struct bwn_dma_ring *);
 621         int                             (*get_curslot)(struct bwn_dma_ring *);
 622         void                            (*set_curslot)(struct bwn_dma_ring *,
 623                                             int);
 624 };
 625
 626 struct bwn_dma {
 627         int                             dmatype;
 628         bus_dma_tag_t                   parent_dtag;
 629         bus_dma_tag_t                   rxbuf_dtag;
 630         bus_dma_tag_t                   txbuf_dtag;
 631
 632         struct bwn_dma_ring             *wme[5];
 633         struct bwn_dma_ring             *mcast;
 634         struct bwn_dma_ring             *rx;
 635         uint64_t                        lastseq;        /* XXX FIXME */
 636 };
 637
 638 struct bwn_pio_rxqueue {
 639         struct bwn_mac                  *prq_mac;
 640         uint16_t                        prq_base;
 641         uint8_t                         prq_rev;
 642 };
 643
 644 struct bwn_pio_txqueue;
 645 struct bwn_pio_txpkt {
 646         struct bwn_pio_txqueue          *tp_queue;
 647         struct ieee80211_node           *tp_ni;
 648         struct mbuf                     *tp_m;
 649         uint8_t                         tp_index;
 650         TAILQ_ENTRY(bwn_pio_txpkt)      tp_list;
 651 };
 652
 653 #define BWN_PIO_MAX_TXPACKETS           32
 654 struct bwn_pio_txqueue {
 655         uint16_t                        tq_base;
 656         uint16_t                        tq_size;
 657         uint16_t                        tq_used;
 658         uint16_t                        tq_free;
 659         uint8_t                         tq_stop;
 660         uint8_t                         tq_index;
 661         struct bwn_pio_txpkt            tq_pkts[BWN_PIO_MAX_TXPACKETS];
 662         TAILQ_HEAD(, bwn_pio_txpkt)     tq_pktlist;
 663 };
 664
 665 struct bwn_pio {
 666         struct bwn_pio_txqueue          wme[5];
 667         struct bwn_pio_txqueue          mcast;
 668         struct bwn_pio_rxqueue          rx;
 669 };
 670
 671 struct bwn_plcp4 {
 672         union {
 673                 uint32_t                data;
 674                 uint8_t                 raw[4];
 675         } __packed o;
 676 } __packed;
 677
 678 struct bwn_plcp6 {
 679         union {
 680                 uint32_t                data;
 681                 uint8_t                 raw[6];
 682         } __packed o;
 683 } __packed;
 684
 685 struct bwn_txhdr {
 686         uint32_t                        macctl;
 687         uint8_t                         macfc[2];
 688         uint16_t                        tx_festime;
 689         uint16_t                        phyctl;
 690         uint16_t                        phyctl_1;
 691         uint16_t                        phyctl_1fb;
 692         uint16_t                        phyctl_1rts;
 693         uint16_t                        phyctl_1rtsfb;
 694         uint8_t                         phyrate;
 695         uint8_t                         phyrate_rts;
 696         uint8_t                         eftypes;        /* extra frame types */
 697         uint8_t                         chan;
 698         uint8_t                         iv[16];
 699         uint8_t                         addr1[IEEE80211_ADDR_LEN];
 700         uint16_t                        tx_festime_fb;
 701         struct bwn_plcp6                rts_plcp_fb;
 702         uint16_t                        rts_dur_fb;
 703         struct bwn_plcp6                plcp_fb;
 704         uint16_t                        dur_fb;
 705         uint16_t                        mimo_modelen;
 706         uint16_t                        mimo_ratelen_fb;
 707         uint32_t                        timeout;
 708
 709         union {
 710                 /* format <= r351 */
 711                 struct {
 712                         uint8_t         pad0[2];
 713                         uint16_t        cookie;
 714                         uint16_t        tx_status;
 715                         struct bwn_plcp6        rts_plcp;
 716                         uint8_t         rts_frame[16];
 717                         uint8_t         pad1[2];
 718                         struct bwn_plcp6        plcp;
 719                 } __packed old;
 720                 /* format > r410 */
 721                 struct {
 722                         uint16_t        mimo_antenna;
 723                         uint16_t        preload_size;
 724                         uint8_t         pad0[2];
 725                         uint16_t        cookie;
 726                         uint16_t        tx_status;
 727                         struct bwn_plcp6        rts_plcp;
 728                         uint8_t         rts_frame[16];
 729                         uint8_t         pad1[2];
 730                         struct bwn_plcp6        plcp;
 731                 } __packed new;
 732         } __packed body;
 733 } __packed;
 734
 735 #define BWN_FWTYPE_UCODE                'u'
 736 #define BWN_FWTYPE_PCM                  'p'
 737 #define BWN_FWTYPE_IV                   'i'
 738 struct bwn_fwhdr {
 739         uint8_t                         type;
 740         uint8_t                         ver;
 741         uint8_t                         pad[2];
 742         uint32_t                        size;
 743 } __packed;
 744
 745 #define BWN_FWINITVALS_OFFSET_MASK      0x7fff
 746 #define BWN_FWINITVALS_32BIT            0x8000
 747 struct bwn_fwinitvals {
 748         uint16_t                        offset_size;
 749         union {
 750                 uint16_t                d16;
 751                 uint32_t                d32;
 752         } __packed data;
 753 } __packed;
 754
 755 enum bwn_fwtype {
 756         BWN_FWTYPE_DEFAULT,
 757         BWN_FWTYPE_OPENSOURCE,
 758         BWN_NR_FWTYPES,
 759 };
 760
 761 struct bwn_fwfile {
 762         const char                      *filename;
 763         const struct firmware           *fw;
 764         enum bwn_fwtype                 type;
 765 };
 766
 767 struct bwn_key {
 768         void                            *keyconf;
 769         uint8_t                         algorithm;
 770 };
 771
 772 struct bwn_fw {
 773         struct bwn_fwfile               ucode;
 774         struct bwn_fwfile               pcm;
 775         struct bwn_fwfile               initvals;
 776         struct bwn_fwfile               initvals_band;
 777
 778         uint16_t                        rev;
 779         uint16_t                        patch;
 780         uint8_t                         opensource;
 781         uint8_t                         no_pcmfile;
 782 };
 783
 784 struct bwn_lo_g_sm {
 785         int                             curstate;
 786         int                             nmeasure;
 787         int                             multipler;
 788         uint16_t                        feedth;
 789         struct bwn_loctl                loctl;
 790 };
 791
 792 struct bwn_lo_g_value {
 793         uint8_t                         old_channel;
 794         uint16_t                        phy_lomask;
 795         uint16_t                        phy_extg;
 796         uint16_t                        phy_dacctl_hwpctl;
 797         uint16_t                        phy_dacctl;
 798         uint16_t                        phy_hpwr_tssictl;
 799         uint16_t                        phy_analogover;
 800         uint16_t                        phy_analogoverval;
 801         uint16_t                        phy_rfover;
 802         uint16_t                        phy_rfoverval;
 803         uint16_t                        phy_classctl;
 804         uint16_t                        phy_crs0;
 805         uint16_t                        phy_pgactl;
 806         uint16_t                        phy_syncctl;
 807         uint16_t                        phy_cck0;
 808         uint16_t                        phy_cck1;
 809         uint16_t                        phy_cck2;
 810         uint16_t                        phy_cck3;
 811         uint16_t                        phy_cck4;
 812         uint16_t                        reg0;
 813         uint16_t                        reg1;
 814         uint16_t                        rf0;
 815         uint16_t                        rf1;
 816         uint16_t                        rf2;
 817 };
 818
 819 #define BWN_LED_MAX                     4
 820
 821 #define BWN_LED_EVENT_NONE              -1
 822 #define BWN_LED_EVENT_POLL              0
 823 #define BWN_LED_EVENT_TX                1
 824 #define BWN_LED_EVENT_RX                2
 825 #define BWN_LED_SLOWDOWN(dur)           (dur) = (((dur) * 3) / 2)
 826
 827 struct bwn_led {
 828         uint8_t                         led_flags;      /* BWN_LED_F_ */
 829         uint8_t                         led_act;        /* BWN_LED_ACT_ */
 830         uint8_t                         led_mask;
 831 };
 832
 833 #define BWN_LED_F_ACTLOW                0x1
 834 #define BWN_LED_F_BLINK                 0x2
 835 #define BWN_LED_F_POLLABLE              0x4
 836 #define BWN_LED_F_SLOW                  0x8
 837
 838 struct bwn_mac {
 839         struct bwn_softc                *mac_sc;
 840         unsigned                        mac_status;
 841 #define BWN_MAC_STATUS_UNINIT           0
 842 #define BWN_MAC_STATUS_INITED           1
 843 #define BWN_MAC_STATUS_STARTED          2
 844         unsigned                        mac_flags;
 845         /* use "Bad Frames Preemption" */
 846 #define BWN_MAC_FLAG_BADFRAME_PREEMP    (1 << 0)
 847 #define BWN_MAC_FLAG_DFQVALID           (1 << 1)
 848 #define BWN_MAC_FLAG_RADIO_ON           (1 << 2)
 849 #define BWN_MAC_FLAG_DMA                (1 << 3)
 850 #define BWN_MAC_FLAG_WME                (1 << 4)
 851 #define BWN_MAC_FLAG_HWCRYPTO           (1 << 5)
 852
 853         struct resource_spec            *mac_intr_spec;
 854 #define BWN_MSI_MESSAGES                1
 855         struct resource                 *mac_res_irq[BWN_MSI_MESSAGES];
 856         void                            *mac_intrhand[BWN_MSI_MESSAGES];
 857         int                             mac_msi;
 858
 859         struct bwn_noise                mac_noise;
 860         struct bwn_phy                  mac_phy;
 861         struct bwn_stats                mac_stats;
 862         uint32_t                        mac_reason_intr;
 863         uint32_t                        mac_reason[6];
 864         uint32_t                        mac_intr_mask;
 865         int                             mac_suspended;
 866
 867         struct bwn_fw                   mac_fw;
 868
 869         union {
 870                 struct bwn_dma          dma;
 871                 struct bwn_pio          pio;
 872         } mac_method;
 873
 874         uint16_t                        mac_ktp;        /* Key table pointer */
 875         uint8_t                         mac_max_nr_keys;
 876         struct bwn_key                  mac_key[58];
 877
 878         unsigned int                    mac_task_state;
 879         struct task                     mac_intrtask;
 880         struct task                     mac_hwreset;
 881         struct task                     mac_txpower;
 882
 883         TAILQ_ENTRY(bwn_mac)    mac_list;
 884 };
 885
 886 /*
 887  * Driver-specific vap state.
 888  */
 889 struct bwn_vap {
 890         struct ieee80211vap             bv_vap; /* base class */
 891         int                             (*bv_newstate)(struct ieee80211vap *,
 892                                             enum ieee80211_state, int);
 893 };
 894 #define BWN_VAP(vap)                    ((struct bwn_vap *)(vap))
 895 #define BWN_VAP_CONST(vap)              ((const struct mwl_vap *)(vap))
 896
 897 struct bwn_softc {
 898         device_t                        sc_dev;
 899         struct mtx                      sc_mtx;
 900         struct ifnet                    *sc_ifp;
 901         unsigned                        sc_flags;
 902 #define BWN_FLAG_ATTACHED               (1 << 0)
 903 #define BWN_FLAG_INVALID                (1 << 1)
 904 #define BWN_FLAG_NEED_BEACON_TP         (1 << 2)
 905         unsigned                        sc_debug;
 906
 907         struct bwn_mac          *sc_curmac;
 908         TAILQ_HEAD(, bwn_mac)   sc_maclist;
 909
 910         uint8_t                         sc_macaddr[IEEE80211_ADDR_LEN];
 911         uint8_t                         sc_bssid[IEEE80211_ADDR_LEN];
 912         unsigned int                    sc_filters;
 913         uint8_t                         sc_beacons[2];
 914         uint8_t                         sc_rf_enabled;
 915
 916         struct wmeParams                sc_wmeParams[4];
 917
 918         struct callout                  sc_rfswitch_ch; /* for laptop */
 919         struct callout                  sc_task_ch;
 920         struct callout                  sc_watchdog_ch;
 921         int                             sc_watchdog_timer;
 922         struct taskqueue                *sc_tq; /* private task queue */
 923         int                             (*sc_newstate)(struct ieee80211com *,
 924                                             enum ieee80211_state, int);
 925         void                            (*sc_node_cleanup)(
 926                                             struct ieee80211_node *);
 927
 928         int                             sc_rx_rate;
 929         int                             sc_tx_rate;
 930
 931         int                             sc_led_blinking;
 932         int                             sc_led_ticks;
 933         struct bwn_led                  *sc_blink_led;
 934         struct callout                  sc_led_blink_ch;
 935         int                             sc_led_blink_offdur;
 936         struct bwn_led                  sc_leds[BWN_LED_MAX];
 937         int                             sc_led_idle;
 938         int                             sc_led_blink;
 939
 940         struct bwn_tx_radiotap_header   sc_tx_th;
 941         struct bwn_rx_radiotap_header   sc_rx_th;
 942 };
 943
 944 #define BWN_LOCK_INIT(sc) \
 945         mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->sc_dev), \
 946             MTX_NETWORK_LOCK, MTX_DEF)
 947 #define BWN_LOCK_DESTROY(sc)    mtx_destroy(&(sc)->sc_mtx)
 948 #define BWN_LOCK(sc)            mtx_lock(&(sc)->sc_mtx)
 949 #define BWN_UNLOCK(sc)          mtx_unlock(&(sc)->sc_mtx)
 950 #define BWN_ASSERT_LOCKED(sc)   mtx_assert(&(sc)->sc_mtx, MA_OWNED)
 951
 952 #endif  /* !_IF_BWNVAR_H */