2 * Copyright (C) 2009-2011 Semihalf.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * CESA SRAM Memory Map:
30 * +------------------------+ <= sc->sc_sram_base + CESA_SRAM_SIZE
34 * +------------------------+ <= sc->sc_sram_base + CESA_DATA(0)
35 * | struct cesa_sa_data |
36 * +------------------------+
37 * | struct cesa_sa_hdesc |
38 * +------------------------+ <= sc->sc_sram_base
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
44 #include <sys/param.h>
45 #include <sys/systm.h>
47 #include <sys/endian.h>
48 #include <sys/kernel.h>
51 #include <sys/module.h>
52 #include <sys/mutex.h>
55 #include <machine/bus.h>
56 #include <machine/intr.h>
57 #include <machine/resource.h>
59 #include <dev/fdt/fdt_common.h>
60 #include <dev/ofw/ofw_bus.h>
61 #include <dev/ofw/ofw_bus_subr.h>
64 #include <crypto/sha1.h>
65 #include <crypto/rijndael/rijndael.h>
66 #include <opencrypto/cryptodev.h>
67 #include "cryptodev_if.h"
69 #include <arm/mv/mvreg.h>
70 #include <arm/mv/mvwin.h>
71 #include <arm/mv/mvvar.h>
76 static int cesa_probe(device_t);
77 static int cesa_attach(device_t);
78 static int cesa_detach(device_t);
79 static void cesa_intr(void *);
80 static int cesa_newsession(device_t, u_int32_t *, struct cryptoini *);
81 static int cesa_freesession(device_t, u_int64_t);
82 static int cesa_process(device_t, struct cryptop *, int);
83 static int decode_win_cesa_setup(struct cesa_softc *sc);
85 static struct resource_spec cesa_res_spec[] = {
86 { SYS_RES_MEMORY, 0, RF_ACTIVE },
87 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
91 static device_method_t cesa_methods[] = {
92 /* Device interface */
93 DEVMETHOD(device_probe, cesa_probe),
94 DEVMETHOD(device_attach, cesa_attach),
95 DEVMETHOD(device_detach, cesa_detach),
97 /* Crypto device methods */
98 DEVMETHOD(cryptodev_newsession, cesa_newsession),
99 DEVMETHOD(cryptodev_freesession,cesa_freesession),
100 DEVMETHOD(cryptodev_process, cesa_process),
105 static driver_t cesa_driver = {
108 sizeof (struct cesa_softc)
110 static devclass_t cesa_devclass;
112 DRIVER_MODULE(cesa, simplebus, cesa_driver, cesa_devclass, 0, 0);
113 MODULE_DEPEND(cesa, crypto, 1, 1, 1);
116 cesa_dump_cshd(struct cesa_softc *sc, struct cesa_sa_hdesc *cshd)
122 device_printf(dev, "CESA SA Hardware Descriptor:\n");
123 device_printf(dev, "\t\tconfig: 0x%08X\n", cshd->cshd_config);
124 device_printf(dev, "\t\te_src: 0x%08X\n", cshd->cshd_enc_src);
125 device_printf(dev, "\t\te_dst: 0x%08X\n", cshd->cshd_enc_dst);
126 device_printf(dev, "\t\te_dlen: 0x%08X\n", cshd->cshd_enc_dlen);
127 device_printf(dev, "\t\te_key: 0x%08X\n", cshd->cshd_enc_key);
128 device_printf(dev, "\t\te_iv_1: 0x%08X\n", cshd->cshd_enc_iv);
129 device_printf(dev, "\t\te_iv_2: 0x%08X\n", cshd->cshd_enc_iv_buf);
130 device_printf(dev, "\t\tm_src: 0x%08X\n", cshd->cshd_mac_src);
131 device_printf(dev, "\t\tm_dst: 0x%08X\n", cshd->cshd_mac_dst);
132 device_printf(dev, "\t\tm_dlen: 0x%08X\n", cshd->cshd_mac_dlen);
133 device_printf(dev, "\t\tm_tlen: 0x%08X\n", cshd->cshd_mac_total_dlen);
134 device_printf(dev, "\t\tm_iv_i: 0x%08X\n", cshd->cshd_mac_iv_in);
135 device_printf(dev, "\t\tm_iv_o: 0x%08X\n", cshd->cshd_mac_iv_out);
140 cesa_alloc_dma_mem_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
142 struct cesa_dma_mem *cdm;
147 KASSERT(nseg == 1, ("Got wrong number of DMA segments, should be 1."));
149 cdm->cdm_paddr = segs->ds_addr;
153 cesa_alloc_dma_mem(struct cesa_softc *sc, struct cesa_dma_mem *cdm,
158 KASSERT(cdm->cdm_vaddr == NULL,
159 ("%s(): DMA memory descriptor in use.", __func__));
161 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */
162 PAGE_SIZE, 0, /* alignment, boundary */
163 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
164 BUS_SPACE_MAXADDR, /* highaddr */
165 NULL, NULL, /* filtfunc, filtfuncarg */
166 size, 1, /* maxsize, nsegments */
167 size, 0, /* maxsegsz, flags */
168 NULL, NULL, /* lockfunc, lockfuncarg */
169 &cdm->cdm_tag); /* dmat */
171 device_printf(sc->sc_dev, "failed to allocate busdma tag, error"
177 error = bus_dmamem_alloc(cdm->cdm_tag, &cdm->cdm_vaddr,
178 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &cdm->cdm_map);
180 device_printf(sc->sc_dev, "failed to allocate DMA safe"
181 " memory, error %i!\n", error);
186 error = bus_dmamap_load(cdm->cdm_tag, cdm->cdm_map, cdm->cdm_vaddr,
187 size, cesa_alloc_dma_mem_cb, cdm, BUS_DMA_NOWAIT);
189 device_printf(sc->sc_dev, "cannot get address of the DMA"
190 " memory, error %i\n", error);
197 bus_dmamem_free(cdm->cdm_tag, cdm->cdm_vaddr, cdm->cdm_map);
199 bus_dma_tag_destroy(cdm->cdm_tag);
201 cdm->cdm_vaddr = NULL;
206 cesa_free_dma_mem(struct cesa_dma_mem *cdm)
209 bus_dmamap_unload(cdm->cdm_tag, cdm->cdm_map);
210 bus_dmamem_free(cdm->cdm_tag, cdm->cdm_vaddr, cdm->cdm_map);
211 bus_dma_tag_destroy(cdm->cdm_tag);
212 cdm->cdm_vaddr = NULL;
216 cesa_sync_dma_mem(struct cesa_dma_mem *cdm, bus_dmasync_op_t op)
219 /* Sync only if dma memory is valid */
220 if (cdm->cdm_vaddr != NULL)
221 bus_dmamap_sync(cdm->cdm_tag, cdm->cdm_map, op);
225 cesa_sync_desc(struct cesa_softc *sc, bus_dmasync_op_t op)
228 cesa_sync_dma_mem(&sc->sc_tdesc_cdm, op);
229 cesa_sync_dma_mem(&sc->sc_sdesc_cdm, op);
230 cesa_sync_dma_mem(&sc->sc_requests_cdm, op);
233 static struct cesa_session *
234 cesa_alloc_session(struct cesa_softc *sc)
236 struct cesa_session *cs;
238 CESA_GENERIC_ALLOC_LOCKED(sc, cs, sessions);
243 static struct cesa_session *
244 cesa_get_session(struct cesa_softc *sc, uint32_t sid)
247 if (sid >= CESA_SESSIONS)
250 return (&sc->sc_sessions[sid]);
254 cesa_free_session(struct cesa_softc *sc, struct cesa_session *cs)
257 CESA_GENERIC_FREE_LOCKED(sc, cs, sessions);
260 static struct cesa_request *
261 cesa_alloc_request(struct cesa_softc *sc)
263 struct cesa_request *cr;
265 CESA_GENERIC_ALLOC_LOCKED(sc, cr, requests);
269 STAILQ_INIT(&cr->cr_tdesc);
270 STAILQ_INIT(&cr->cr_sdesc);
276 cesa_free_request(struct cesa_softc *sc, struct cesa_request *cr)
279 /* Free TDMA descriptors assigned to this request */
280 CESA_LOCK(sc, tdesc);
281 STAILQ_CONCAT(&sc->sc_free_tdesc, &cr->cr_tdesc);
282 CESA_UNLOCK(sc, tdesc);
284 /* Free SA descriptors assigned to this request */
285 CESA_LOCK(sc, sdesc);
286 STAILQ_CONCAT(&sc->sc_free_sdesc, &cr->cr_sdesc);
287 CESA_UNLOCK(sc, sdesc);
289 /* Unload DMA memory asociated with request */
290 if (cr->cr_dmap_loaded) {
291 bus_dmamap_unload(sc->sc_data_dtag, cr->cr_dmap);
292 cr->cr_dmap_loaded = 0;
295 CESA_GENERIC_FREE_LOCKED(sc, cr, requests);
299 cesa_enqueue_request(struct cesa_softc *sc, struct cesa_request *cr)
302 CESA_LOCK(sc, requests);
303 STAILQ_INSERT_TAIL(&sc->sc_ready_requests, cr, cr_stq);
304 CESA_UNLOCK(sc, requests);
307 static struct cesa_tdma_desc *
308 cesa_alloc_tdesc(struct cesa_softc *sc)
310 struct cesa_tdma_desc *ctd;
312 CESA_GENERIC_ALLOC_LOCKED(sc, ctd, tdesc);
315 device_printf(sc->sc_dev, "TDMA descriptors pool exhaused. "
316 "Consider increasing CESA_TDMA_DESCRIPTORS.\n");
321 static struct cesa_sa_desc *
322 cesa_alloc_sdesc(struct cesa_softc *sc, struct cesa_request *cr)
324 struct cesa_sa_desc *csd;
326 CESA_GENERIC_ALLOC_LOCKED(sc, csd, sdesc);
328 device_printf(sc->sc_dev, "SA descriptors pool exhaused. "
329 "Consider increasing CESA_SA_DESCRIPTORS.\n");
333 STAILQ_INSERT_TAIL(&cr->cr_sdesc, csd, csd_stq);
335 /* Fill-in SA descriptor with default values */
336 csd->csd_cshd->cshd_enc_key = CESA_SA_DATA(csd_key);
337 csd->csd_cshd->cshd_enc_iv = CESA_SA_DATA(csd_iv);
338 csd->csd_cshd->cshd_enc_iv_buf = CESA_SA_DATA(csd_iv);
339 csd->csd_cshd->cshd_enc_src = 0;
340 csd->csd_cshd->cshd_enc_dst = 0;
341 csd->csd_cshd->cshd_enc_dlen = 0;
342 csd->csd_cshd->cshd_mac_dst = CESA_SA_DATA(csd_hash);
343 csd->csd_cshd->cshd_mac_iv_in = CESA_SA_DATA(csd_hiv_in);
344 csd->csd_cshd->cshd_mac_iv_out = CESA_SA_DATA(csd_hiv_out);
345 csd->csd_cshd->cshd_mac_src = 0;
346 csd->csd_cshd->cshd_mac_dlen = 0;
351 static struct cesa_tdma_desc *
352 cesa_tdma_copy(struct cesa_softc *sc, bus_addr_t dst, bus_addr_t src,
355 struct cesa_tdma_desc *ctd;
357 ctd = cesa_alloc_tdesc(sc);
361 ctd->ctd_cthd->cthd_dst = dst;
362 ctd->ctd_cthd->cthd_src = src;
363 ctd->ctd_cthd->cthd_byte_count = size;
365 /* Handle special control packet */
367 ctd->ctd_cthd->cthd_flags = CESA_CTHD_OWNED;
369 ctd->ctd_cthd->cthd_flags = 0;
374 static struct cesa_tdma_desc *
375 cesa_tdma_copyin_sa_data(struct cesa_softc *sc, struct cesa_request *cr)
378 return (cesa_tdma_copy(sc, sc->sc_sram_base +
379 sizeof(struct cesa_sa_hdesc), cr->cr_csd_paddr,
380 sizeof(struct cesa_sa_data)));
383 static struct cesa_tdma_desc *
384 cesa_tdma_copyout_sa_data(struct cesa_softc *sc, struct cesa_request *cr)
387 return (cesa_tdma_copy(sc, cr->cr_csd_paddr, sc->sc_sram_base +
388 sizeof(struct cesa_sa_hdesc), sizeof(struct cesa_sa_data)));
391 static struct cesa_tdma_desc *
392 cesa_tdma_copy_sdesc(struct cesa_softc *sc, struct cesa_sa_desc *csd)
395 return (cesa_tdma_copy(sc, sc->sc_sram_base, csd->csd_cshd_paddr,
396 sizeof(struct cesa_sa_hdesc)));
400 cesa_append_tdesc(struct cesa_request *cr, struct cesa_tdma_desc *ctd)
402 struct cesa_tdma_desc *ctd_prev;
404 if (!STAILQ_EMPTY(&cr->cr_tdesc)) {
405 ctd_prev = STAILQ_LAST(&cr->cr_tdesc, cesa_tdma_desc, ctd_stq);
406 ctd_prev->ctd_cthd->cthd_next = ctd->ctd_cthd_paddr;
409 ctd->ctd_cthd->cthd_next = 0;
410 STAILQ_INSERT_TAIL(&cr->cr_tdesc, ctd, ctd_stq);
414 cesa_append_packet(struct cesa_softc *sc, struct cesa_request *cr,
415 struct cesa_packet *cp, struct cesa_sa_desc *csd)
417 struct cesa_tdma_desc *ctd, *tmp;
419 /* Copy SA descriptor for this packet */
420 ctd = cesa_tdma_copy_sdesc(sc, csd);
424 cesa_append_tdesc(cr, ctd);
426 /* Copy data to be processed */
427 STAILQ_FOREACH_SAFE(ctd, &cp->cp_copyin, ctd_stq, tmp)
428 cesa_append_tdesc(cr, ctd);
429 STAILQ_INIT(&cp->cp_copyin);
431 /* Insert control descriptor */
432 ctd = cesa_tdma_copy(sc, 0, 0, 0);
436 cesa_append_tdesc(cr, ctd);
438 /* Copy back results */
439 STAILQ_FOREACH_SAFE(ctd, &cp->cp_copyout, ctd_stq, tmp)
440 cesa_append_tdesc(cr, ctd);
441 STAILQ_INIT(&cp->cp_copyout);
447 cesa_set_mkey(struct cesa_session *cs, int alg, const uint8_t *mkey, int mklen)
449 uint8_t ipad[CESA_MAX_HMAC_BLOCK_LEN];
450 uint8_t opad[CESA_MAX_HMAC_BLOCK_LEN];
457 memset(ipad, HMAC_IPAD_VAL, CESA_MAX_HMAC_BLOCK_LEN);
458 memset(opad, HMAC_OPAD_VAL, CESA_MAX_HMAC_BLOCK_LEN);
459 for (i = 0; i < mklen; i++) {
464 hin = (uint32_t *)cs->cs_hiv_in;
465 hout = (uint32_t *)cs->cs_hiv_out;
468 case CRYPTO_MD5_HMAC:
470 MD5Update(&md5ctx, ipad, MD5_HMAC_BLOCK_LEN);
471 memcpy(hin, md5ctx.state, sizeof(md5ctx.state));
473 MD5Update(&md5ctx, opad, MD5_HMAC_BLOCK_LEN);
474 memcpy(hout, md5ctx.state, sizeof(md5ctx.state));
476 case CRYPTO_SHA1_HMAC:
478 SHA1Update(&sha1ctx, ipad, SHA1_HMAC_BLOCK_LEN);
479 memcpy(hin, sha1ctx.h.b32, sizeof(sha1ctx.h.b32));
481 SHA1Update(&sha1ctx, opad, SHA1_HMAC_BLOCK_LEN);
482 memcpy(hout, sha1ctx.h.b32, sizeof(sha1ctx.h.b32));
488 for (i = 0; i < CESA_MAX_HASH_LEN / sizeof(uint32_t); i++) {
489 hin[i] = htobe32(hin[i]);
490 hout[i] = htobe32(hout[i]);
497 cesa_prep_aes_key(struct cesa_session *cs)
499 uint32_t ek[4 * (RIJNDAEL_MAXNR + 1)];
503 rijndaelKeySetupEnc(ek, cs->cs_key, cs->cs_klen * 8);
505 cs->cs_config &= ~CESA_CSH_AES_KLEN_MASK;
506 dkey = (uint32_t *)cs->cs_aes_dkey;
508 switch (cs->cs_klen) {
510 cs->cs_config |= CESA_CSH_AES_KLEN_128;
511 for (i = 0; i < 4; i++)
512 *dkey++ = htobe32(ek[4 * 10 + i]);
515 cs->cs_config |= CESA_CSH_AES_KLEN_192;
516 for (i = 0; i < 4; i++)
517 *dkey++ = htobe32(ek[4 * 12 + i]);
518 for (i = 0; i < 2; i++)
519 *dkey++ = htobe32(ek[4 * 11 + 2 + i]);
522 cs->cs_config |= CESA_CSH_AES_KLEN_256;
523 for (i = 0; i < 4; i++)
524 *dkey++ = htobe32(ek[4 * 14 + i]);
525 for (i = 0; i < 4; i++)
526 *dkey++ = htobe32(ek[4 * 13 + i]);
536 cesa_is_hash(int alg)
541 case CRYPTO_MD5_HMAC:
543 case CRYPTO_SHA1_HMAC:
551 cesa_start_packet(struct cesa_packet *cp, unsigned int size)
556 STAILQ_INIT(&cp->cp_copyin);
557 STAILQ_INIT(&cp->cp_copyout);
561 cesa_fill_packet(struct cesa_softc *sc, struct cesa_packet *cp,
562 bus_dma_segment_t *seg)
564 struct cesa_tdma_desc *ctd;
567 /* Calculate size of block copy */
568 bsize = MIN(seg->ds_len, cp->cp_size - cp->cp_offset);
571 ctd = cesa_tdma_copy(sc, sc->sc_sram_base +
572 CESA_DATA(cp->cp_offset), seg->ds_addr, bsize);
576 STAILQ_INSERT_TAIL(&cp->cp_copyin, ctd, ctd_stq);
578 ctd = cesa_tdma_copy(sc, seg->ds_addr, sc->sc_sram_base +
579 CESA_DATA(cp->cp_offset), bsize);
583 STAILQ_INSERT_TAIL(&cp->cp_copyout, ctd, ctd_stq);
585 seg->ds_len -= bsize;
586 seg->ds_addr += bsize;
587 cp->cp_offset += bsize;
594 cesa_create_chain_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
596 unsigned int mpsize, fragmented;
597 unsigned int mlen, mskip, tmlen;
598 struct cesa_chain_info *cci;
599 unsigned int elen, eskip;
600 unsigned int skip, len;
601 struct cesa_sa_desc *csd;
602 struct cesa_request *cr;
603 struct cesa_softc *sc;
604 struct cesa_packet cp;
605 bus_dma_segment_t seg;
614 cci->cci_error = error;
618 elen = cci->cci_enc ? cci->cci_enc->crd_len : 0;
619 eskip = cci->cci_enc ? cci->cci_enc->crd_skip : 0;
620 mlen = cci->cci_mac ? cci->cci_mac->crd_len : 0;
621 mskip = cci->cci_mac ? cci->cci_mac->crd_skip : 0;
624 ((eskip > mskip && ((eskip - mskip) & (cr->cr_cs->cs_ivlen - 1))) ||
625 (mskip > eskip && ((mskip - eskip) & (cr->cr_cs->cs_mblen - 1))) ||
626 (eskip > (mskip + mlen)) || (mskip > (eskip + elen)))) {
628 * Data alignment in the request does not meet CESA requiremnts
629 * for combined encryption/decryption and hashing. We have to
630 * split the request to separate operations and process them
633 config = cci->cci_config;
634 if ((config & CESA_CSHD_OP_MASK) == CESA_CSHD_MAC_AND_ENC) {
635 config &= ~CESA_CSHD_OP_MASK;
637 cci->cci_config = config | CESA_CSHD_MAC;
639 cci->cci_mac = cr->cr_mac;
640 cesa_create_chain_cb(cci, segs, nseg, cci->cci_error);
642 cci->cci_config = config | CESA_CSHD_ENC;
643 cci->cci_enc = cr->cr_enc;
645 cesa_create_chain_cb(cci, segs, nseg, cci->cci_error);
647 config &= ~CESA_CSHD_OP_MASK;
649 cci->cci_config = config | CESA_CSHD_ENC;
650 cci->cci_enc = cr->cr_enc;
652 cesa_create_chain_cb(cci, segs, nseg, cci->cci_error);
654 cci->cci_config = config | CESA_CSHD_MAC;
656 cci->cci_mac = cr->cr_mac;
657 cesa_create_chain_cb(cci, segs, nseg, cci->cci_error);
665 mpsize = CESA_MAX_PACKET_SIZE;
666 mpsize &= ~((cr->cr_cs->cs_ivlen - 1) | (cr->cr_cs->cs_mblen - 1));
669 skip = MIN(eskip, mskip);
670 len = MAX(elen + eskip, mlen + mskip) - skip;
679 /* Start first packet in chain */
680 cesa_start_packet(&cp, MIN(mpsize, len));
682 while (nseg-- && len > 0) {
686 * Skip data in buffer on which neither ENC nor MAC operation
690 size = MIN(skip, seg.ds_len);
708 * Fill in current packet with data. Break if there is
709 * no more data in current DMA segment or an error
712 size = cesa_fill_packet(sc, &cp, &seg);
720 /* If packet is full, append it to the chain */
721 if (cp.cp_size == cp.cp_offset) {
722 csd = cesa_alloc_sdesc(sc, cr);
728 /* Create SA descriptor for this packet */
729 csd->csd_cshd->cshd_config = cci->cci_config;
730 csd->csd_cshd->cshd_mac_total_dlen = tmlen;
733 * Enable fragmentation if request will not fit
739 csd->csd_cshd->cshd_config |=
740 CESA_CSHD_FRAG_FIRST;
742 csd->csd_cshd->cshd_config |=
743 CESA_CSHD_FRAG_MIDDLE;
744 } else if (fragmented)
745 csd->csd_cshd->cshd_config |=
748 if (eskip < cp.cp_size && elen > 0) {
749 csd->csd_cshd->cshd_enc_src =
751 csd->csd_cshd->cshd_enc_dst =
753 csd->csd_cshd->cshd_enc_dlen =
754 MIN(elen, cp.cp_size - eskip);
757 if (mskip < cp.cp_size && mlen > 0) {
758 csd->csd_cshd->cshd_mac_src =
760 csd->csd_cshd->cshd_mac_dlen =
761 MIN(mlen, cp.cp_size - mskip);
764 elen -= csd->csd_cshd->cshd_enc_dlen;
765 eskip -= MIN(eskip, cp.cp_size);
766 mlen -= csd->csd_cshd->cshd_mac_dlen;
767 mskip -= MIN(mskip, cp.cp_size);
769 cesa_dump_cshd(sc, csd->csd_cshd);
771 /* Append packet to the request */
772 error = cesa_append_packet(sc, cr, &cp, csd);
776 /* Start a new packet, as current is full */
777 cesa_start_packet(&cp, MIN(mpsize, len));
787 * Move all allocated resources to the request. They will be
790 STAILQ_CONCAT(&cr->cr_tdesc, &cp.cp_copyin);
791 STAILQ_CONCAT(&cr->cr_tdesc, &cp.cp_copyout);
792 cci->cci_error = error;
797 cesa_create_chain_cb2(void *arg, bus_dma_segment_t *segs, int nseg,
798 bus_size_t size, int error)
801 cesa_create_chain_cb(arg, segs, nseg, error);
805 cesa_create_chain(struct cesa_softc *sc, struct cesa_request *cr)
807 struct cesa_chain_info cci;
808 struct cesa_tdma_desc *ctd;
813 CESA_LOCK_ASSERT(sc, sessions);
815 /* Create request metadata */
817 if (cr->cr_enc->crd_alg == CRYPTO_AES_CBC &&
818 (cr->cr_enc->crd_flags & CRD_F_ENCRYPT) == 0)
819 memcpy(cr->cr_csd->csd_key, cr->cr_cs->cs_aes_dkey,
822 memcpy(cr->cr_csd->csd_key, cr->cr_cs->cs_key,
827 memcpy(cr->cr_csd->csd_hiv_in, cr->cr_cs->cs_hiv_in,
829 memcpy(cr->cr_csd->csd_hiv_out, cr->cr_cs->cs_hiv_out,
833 ctd = cesa_tdma_copyin_sa_data(sc, cr);
837 cesa_append_tdesc(cr, ctd);
839 /* Prepare SA configuration */
840 config = cr->cr_cs->cs_config;
842 if (cr->cr_enc && (cr->cr_enc->crd_flags & CRD_F_ENCRYPT) == 0)
843 config |= CESA_CSHD_DECRYPT;
844 if (cr->cr_enc && !cr->cr_mac)
845 config |= CESA_CSHD_ENC;
846 if (!cr->cr_enc && cr->cr_mac)
847 config |= CESA_CSHD_MAC;
848 if (cr->cr_enc && cr->cr_mac)
849 config |= (config & CESA_CSHD_DECRYPT) ? CESA_CSHD_MAC_AND_ENC :
850 CESA_CSHD_ENC_AND_MAC;
852 /* Create data packets */
855 cci.cci_enc = cr->cr_enc;
856 cci.cci_mac = cr->cr_mac;
857 cci.cci_config = config;
860 if (cr->cr_crp->crp_flags & CRYPTO_F_IOV)
861 error = bus_dmamap_load_uio(sc->sc_data_dtag,
862 cr->cr_dmap, (struct uio *)cr->cr_crp->crp_buf,
863 cesa_create_chain_cb2, &cci, BUS_DMA_NOWAIT);
864 else if (cr->cr_crp->crp_flags & CRYPTO_F_IMBUF)
865 error = bus_dmamap_load_mbuf(sc->sc_data_dtag,
866 cr->cr_dmap, (struct mbuf *)cr->cr_crp->crp_buf,
867 cesa_create_chain_cb2, &cci, BUS_DMA_NOWAIT);
869 error = bus_dmamap_load(sc->sc_data_dtag,
870 cr->cr_dmap, cr->cr_crp->crp_buf,
871 cr->cr_crp->crp_ilen, cesa_create_chain_cb, &cci,
875 cr->cr_dmap_loaded = 1;
878 error = cci.cci_error;
883 /* Read back request metadata */
884 ctd = cesa_tdma_copyout_sa_data(sc, cr);
888 cesa_append_tdesc(cr, ctd);
894 cesa_execute(struct cesa_softc *sc)
896 struct cesa_tdma_desc *prev_ctd, *ctd;
897 struct cesa_request *prev_cr, *cr;
899 CESA_LOCK(sc, requests);
902 * If ready list is empty, there is nothing to execute. If queued list
903 * is not empty, the hardware is busy and we cannot start another
906 if (STAILQ_EMPTY(&sc->sc_ready_requests) ||
907 !STAILQ_EMPTY(&sc->sc_queued_requests)) {
908 CESA_UNLOCK(sc, requests);
912 /* Move all ready requests to queued list */
913 STAILQ_CONCAT(&sc->sc_queued_requests, &sc->sc_ready_requests);
914 STAILQ_INIT(&sc->sc_ready_requests);
916 /* Create one execution chain from all requests on the list */
917 if (STAILQ_FIRST(&sc->sc_queued_requests) !=
918 STAILQ_LAST(&sc->sc_queued_requests, cesa_request, cr_stq)) {
920 cesa_sync_dma_mem(&sc->sc_tdesc_cdm, BUS_DMASYNC_POSTREAD |
921 BUS_DMASYNC_POSTWRITE);
923 STAILQ_FOREACH(cr, &sc->sc_queued_requests, cr_stq) {
925 ctd = STAILQ_FIRST(&cr->cr_tdesc);
926 prev_ctd = STAILQ_LAST(&prev_cr->cr_tdesc,
927 cesa_tdma_desc, ctd_stq);
929 prev_ctd->ctd_cthd->cthd_next =
936 cesa_sync_dma_mem(&sc->sc_tdesc_cdm, BUS_DMASYNC_PREREAD |
937 BUS_DMASYNC_PREWRITE);
940 /* Start chain execution in hardware */
941 cr = STAILQ_FIRST(&sc->sc_queued_requests);
942 ctd = STAILQ_FIRST(&cr->cr_tdesc);
944 CESA_WRITE(sc, CESA_TDMA_ND, ctd->ctd_cthd_paddr);
945 CESA_WRITE(sc, CESA_SA_CMD, CESA_SA_CMD_ACTVATE);
947 CESA_UNLOCK(sc, requests);
951 cesa_setup_sram(struct cesa_softc *sc)
954 ihandle_t sram_ihandle;
955 pcell_t sram_handle, sram_reg;
957 if (OF_getprop(ofw_bus_get_node(sc->sc_dev), "sram-handle",
958 (void *)&sram_handle, sizeof(sram_handle)) <= 0)
961 sram_ihandle = (ihandle_t)sram_handle;
962 sram_ihandle = fdt32_to_cpu(sram_ihandle);
963 sram_node = OF_instance_to_package(sram_ihandle);
965 if (OF_getprop(sram_node, "reg", (void *)&sram_reg,
966 sizeof(sram_reg)) <= 0)
969 sc->sc_sram_base = fdt32_to_cpu(sram_reg);
975 cesa_probe(device_t dev)
977 if (!ofw_bus_is_compatible(dev, "mrvl,cesa"))
980 device_set_desc(dev, "Marvell Cryptographic Engine and Security "
983 return (BUS_PROBE_DEFAULT);
987 cesa_attach(device_t dev)
989 struct cesa_softc *sc;
994 sc = device_get_softc(dev);
999 /* Check if CESA peripheral device has power turned on */
1000 if (soc_power_ctrl_get(CPU_PM_CTRL_CRYPTO) != CPU_PM_CTRL_CRYPTO) {
1001 device_printf(dev, "not powered on\n");
1008 case MV_DEV_88F6281:
1009 case MV_DEV_88F6282:
1012 case MV_DEV_MV78100:
1013 case MV_DEV_MV78100_Z0:
1014 sc->sc_tperr = CESA_ICR_TPERR;
1020 /* Initialize mutexes */
1021 mtx_init(&sc->sc_sc_lock, device_get_nameunit(dev),
1022 "CESA Shared Data", MTX_DEF);
1023 mtx_init(&sc->sc_tdesc_lock, device_get_nameunit(dev),
1024 "CESA TDMA Descriptors Pool", MTX_DEF);
1025 mtx_init(&sc->sc_sdesc_lock, device_get_nameunit(dev),
1026 "CESA SA Descriptors Pool", MTX_DEF);
1027 mtx_init(&sc->sc_requests_lock, device_get_nameunit(dev),
1028 "CESA Requests Pool", MTX_DEF);
1029 mtx_init(&sc->sc_sessions_lock, device_get_nameunit(dev),
1030 "CESA Sessions Pool", MTX_DEF);
1032 /* Allocate I/O and IRQ resources */
1033 error = bus_alloc_resources(dev, cesa_res_spec, sc->sc_res);
1035 device_printf(dev, "could not allocate resources\n");
1039 sc->sc_bsh = rman_get_bushandle(*(sc->sc_res));
1040 sc->sc_bst = rman_get_bustag(*(sc->sc_res));
1042 /* Setup CESA decoding windows */
1043 error = decode_win_cesa_setup(sc);
1045 device_printf(dev, "could not setup decoding windows\n");
1049 /* Acquire SRAM base address */
1050 error = cesa_setup_sram(sc);
1052 device_printf(dev, "could not setup SRAM\n");
1056 /* Setup interrupt handler */
1057 error = bus_setup_intr(dev, sc->sc_res[1], INTR_TYPE_NET | INTR_MPSAFE,
1058 NULL, cesa_intr, sc, &(sc->sc_icookie));
1060 device_printf(dev, "could not setup engine completion irq\n");
1064 /* Create DMA tag for processed data */
1065 error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1066 1, 0, /* alignment, boundary */
1067 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1068 BUS_SPACE_MAXADDR, /* highaddr */
1069 NULL, NULL, /* filtfunc, filtfuncarg */
1070 CESA_MAX_REQUEST_SIZE, /* maxsize */
1071 CESA_MAX_FRAGMENTS, /* nsegments */
1072 CESA_MAX_REQUEST_SIZE, 0, /* maxsegsz, flags */
1073 NULL, NULL, /* lockfunc, lockfuncarg */
1074 &sc->sc_data_dtag); /* dmat */
1078 /* Initialize data structures: TDMA Descriptors Pool */
1079 error = cesa_alloc_dma_mem(sc, &sc->sc_tdesc_cdm,
1080 CESA_TDMA_DESCRIPTORS * sizeof(struct cesa_tdma_hdesc));
1084 STAILQ_INIT(&sc->sc_free_tdesc);
1085 for (i = 0; i < CESA_TDMA_DESCRIPTORS; i++) {
1086 sc->sc_tdesc[i].ctd_cthd =
1087 (struct cesa_tdma_hdesc *)(sc->sc_tdesc_cdm.cdm_vaddr) + i;
1088 sc->sc_tdesc[i].ctd_cthd_paddr = sc->sc_tdesc_cdm.cdm_paddr +
1089 (i * sizeof(struct cesa_tdma_hdesc));
1090 STAILQ_INSERT_TAIL(&sc->sc_free_tdesc, &sc->sc_tdesc[i],
1094 /* Initialize data structures: SA Descriptors Pool */
1095 error = cesa_alloc_dma_mem(sc, &sc->sc_sdesc_cdm,
1096 CESA_SA_DESCRIPTORS * sizeof(struct cesa_sa_hdesc));
1100 STAILQ_INIT(&sc->sc_free_sdesc);
1101 for (i = 0; i < CESA_SA_DESCRIPTORS; i++) {
1102 sc->sc_sdesc[i].csd_cshd =
1103 (struct cesa_sa_hdesc *)(sc->sc_sdesc_cdm.cdm_vaddr) + i;
1104 sc->sc_sdesc[i].csd_cshd_paddr = sc->sc_sdesc_cdm.cdm_paddr +
1105 (i * sizeof(struct cesa_sa_hdesc));
1106 STAILQ_INSERT_TAIL(&sc->sc_free_sdesc, &sc->sc_sdesc[i],
1110 /* Initialize data structures: Requests Pool */
1111 error = cesa_alloc_dma_mem(sc, &sc->sc_requests_cdm,
1112 CESA_REQUESTS * sizeof(struct cesa_sa_data));
1116 STAILQ_INIT(&sc->sc_free_requests);
1117 STAILQ_INIT(&sc->sc_ready_requests);
1118 STAILQ_INIT(&sc->sc_queued_requests);
1119 for (i = 0; i < CESA_REQUESTS; i++) {
1120 sc->sc_requests[i].cr_csd =
1121 (struct cesa_sa_data *)(sc->sc_requests_cdm.cdm_vaddr) + i;
1122 sc->sc_requests[i].cr_csd_paddr =
1123 sc->sc_requests_cdm.cdm_paddr +
1124 (i * sizeof(struct cesa_sa_data));
1126 /* Preallocate DMA maps */
1127 error = bus_dmamap_create(sc->sc_data_dtag, 0,
1128 &sc->sc_requests[i].cr_dmap);
1129 if (error && i > 0) {
1132 bus_dmamap_destroy(sc->sc_data_dtag,
1133 sc->sc_requests[i].cr_dmap);
1139 STAILQ_INSERT_TAIL(&sc->sc_free_requests, &sc->sc_requests[i],
1143 /* Initialize data structures: Sessions Pool */
1144 STAILQ_INIT(&sc->sc_free_sessions);
1145 for (i = 0; i < CESA_SESSIONS; i++) {
1146 sc->sc_sessions[i].cs_sid = i;
1147 STAILQ_INSERT_TAIL(&sc->sc_free_sessions, &sc->sc_sessions[i],
1153 * - Burst limit: 128 bytes,
1154 * - Outstanding reads enabled,
1157 CESA_WRITE(sc, CESA_TDMA_CR, CESA_TDMA_CR_DBL128 | CESA_TDMA_CR_SBL128 |
1158 CESA_TDMA_CR_ORDEN | CESA_TDMA_CR_NBS | CESA_TDMA_CR_ENABLE);
1162 * - SA descriptor is present at beginning of CESA SRAM,
1163 * - Multi-packet chain mode,
1164 * - Cooperation with TDMA enabled.
1166 CESA_WRITE(sc, CESA_SA_DPR, 0);
1167 CESA_WRITE(sc, CESA_SA_CR, CESA_SA_CR_ACTIVATE_TDMA |
1168 CESA_SA_CR_WAIT_FOR_TDMA | CESA_SA_CR_MULTI_MODE);
1170 /* Unmask interrupts */
1171 CESA_WRITE(sc, CESA_ICR, 0);
1172 CESA_WRITE(sc, CESA_ICM, CESA_ICM_ACCTDMA | sc->sc_tperr);
1173 CESA_WRITE(sc, CESA_TDMA_ECR, 0);
1174 CESA_WRITE(sc, CESA_TDMA_EMR, CESA_TDMA_EMR_MISS |
1175 CESA_TDMA_EMR_DOUBLE_HIT | CESA_TDMA_EMR_BOTH_HIT |
1176 CESA_TDMA_EMR_DATA_ERROR);
1178 /* Register in OCF */
1179 sc->sc_cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE);
1181 device_printf(dev, "could not get crypto driver id\n");
1185 crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0);
1186 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0);
1187 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0);
1188 crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0);
1189 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0);
1190 crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0);
1191 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0);
1195 for (i = 0; i < CESA_REQUESTS; i++)
1196 bus_dmamap_destroy(sc->sc_data_dtag,
1197 sc->sc_requests[i].cr_dmap);
1199 cesa_free_dma_mem(&sc->sc_requests_cdm);
1201 cesa_free_dma_mem(&sc->sc_sdesc_cdm);
1203 cesa_free_dma_mem(&sc->sc_tdesc_cdm);
1205 bus_dma_tag_destroy(sc->sc_data_dtag);
1207 bus_teardown_intr(dev, sc->sc_res[1], sc->sc_icookie);
1209 bus_release_resources(dev, cesa_res_spec, sc->sc_res);
1211 mtx_destroy(&sc->sc_sessions_lock);
1212 mtx_destroy(&sc->sc_requests_lock);
1213 mtx_destroy(&sc->sc_sdesc_lock);
1214 mtx_destroy(&sc->sc_tdesc_lock);
1215 mtx_destroy(&sc->sc_sc_lock);
1220 cesa_detach(device_t dev)
1222 struct cesa_softc *sc;
1225 sc = device_get_softc(dev);
1227 /* TODO: Wait for queued requests completion before shutdown. */
1229 /* Mask interrupts */
1230 CESA_WRITE(sc, CESA_ICM, 0);
1231 CESA_WRITE(sc, CESA_TDMA_EMR, 0);
1233 /* Unregister from OCF */
1234 crypto_unregister_all(sc->sc_cid);
1237 for (i = 0; i < CESA_REQUESTS; i++)
1238 bus_dmamap_destroy(sc->sc_data_dtag,
1239 sc->sc_requests[i].cr_dmap);
1241 /* Free DMA Memory */
1242 cesa_free_dma_mem(&sc->sc_requests_cdm);
1243 cesa_free_dma_mem(&sc->sc_sdesc_cdm);
1244 cesa_free_dma_mem(&sc->sc_tdesc_cdm);
1247 bus_dma_tag_destroy(sc->sc_data_dtag);
1249 /* Stop interrupt */
1250 bus_teardown_intr(dev, sc->sc_res[1], sc->sc_icookie);
1252 /* Relase I/O and IRQ resources */
1253 bus_release_resources(dev, cesa_res_spec, sc->sc_res);
1255 /* Destory mutexes */
1256 mtx_destroy(&sc->sc_sessions_lock);
1257 mtx_destroy(&sc->sc_requests_lock);
1258 mtx_destroy(&sc->sc_sdesc_lock);
1259 mtx_destroy(&sc->sc_tdesc_lock);
1260 mtx_destroy(&sc->sc_sc_lock);
1266 cesa_intr(void *arg)
1268 STAILQ_HEAD(, cesa_request) requests;
1269 struct cesa_request *cr, *tmp;
1270 struct cesa_softc *sc;
1277 ecr = CESA_READ(sc, CESA_TDMA_ECR);
1278 CESA_WRITE(sc, CESA_TDMA_ECR, 0);
1279 icr = CESA_READ(sc, CESA_ICR);
1280 CESA_WRITE(sc, CESA_ICR, 0);
1282 /* Check for TDMA errors */
1283 if (ecr & CESA_TDMA_ECR_MISS) {
1284 device_printf(sc->sc_dev, "TDMA Miss error detected!\n");
1288 if (ecr & CESA_TDMA_ECR_DOUBLE_HIT) {
1289 device_printf(sc->sc_dev, "TDMA Double Hit error detected!\n");
1293 if (ecr & CESA_TDMA_ECR_BOTH_HIT) {
1294 device_printf(sc->sc_dev, "TDMA Both Hit error detected!\n");
1298 if (ecr & CESA_TDMA_ECR_DATA_ERROR) {
1299 device_printf(sc->sc_dev, "TDMA Data error detected!\n");
1303 /* Check for CESA errors */
1304 if (icr & sc->sc_tperr) {
1305 device_printf(sc->sc_dev, "CESA SRAM Parity error detected!\n");
1309 /* If there is nothing more to do, return */
1310 if ((icr & CESA_ICR_ACCTDMA) == 0)
1313 /* Get all finished requests */
1314 CESA_LOCK(sc, requests);
1315 STAILQ_INIT(&requests);
1316 STAILQ_CONCAT(&requests, &sc->sc_queued_requests);
1317 STAILQ_INIT(&sc->sc_queued_requests);
1318 CESA_UNLOCK(sc, requests);
1320 /* Execute all ready requests */
1323 /* Process completed requests */
1324 cesa_sync_dma_mem(&sc->sc_requests_cdm, BUS_DMASYNC_POSTREAD |
1325 BUS_DMASYNC_POSTWRITE);
1327 STAILQ_FOREACH_SAFE(cr, &requests, cr_stq, tmp) {
1328 bus_dmamap_sync(sc->sc_data_dtag, cr->cr_dmap,
1329 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1331 cr->cr_crp->crp_etype = sc->sc_error;
1333 crypto_copyback(cr->cr_crp->crp_flags,
1334 cr->cr_crp->crp_buf, cr->cr_mac->crd_inject,
1335 cr->cr_cs->cs_hlen, cr->cr_csd->csd_hash);
1337 crypto_done(cr->cr_crp);
1338 cesa_free_request(sc, cr);
1341 cesa_sync_dma_mem(&sc->sc_requests_cdm, BUS_DMASYNC_PREREAD |
1342 BUS_DMASYNC_PREWRITE);
1346 /* Unblock driver if it ran out of resources */
1348 blocked = sc->sc_blocked;
1350 CESA_UNLOCK(sc, sc);
1353 crypto_unblock(sc->sc_cid, blocked);
1357 cesa_newsession(device_t dev, uint32_t *sidp, struct cryptoini *cri)
1359 struct cesa_session *cs;
1360 struct cesa_softc *sc;
1361 struct cryptoini *enc;
1362 struct cryptoini *mac;
1365 sc = device_get_softc(dev);
1370 /* Check and parse input */
1371 if (cesa_is_hash(cri->cri_alg))
1376 cri = cri->cri_next;
1379 if (!enc && !cesa_is_hash(cri->cri_alg))
1382 if (!mac && cesa_is_hash(cri->cri_alg))
1385 if (cri->cri_next || !(enc && mac))
1389 if ((enc && (enc->cri_klen / 8) > CESA_MAX_KEY_LEN) ||
1390 (mac && (mac->cri_klen / 8) > CESA_MAX_MKEY_LEN))
1393 /* Allocate session */
1394 cs = cesa_alloc_session(sc);
1398 /* Prepare CESA configuration */
1404 switch (enc->cri_alg) {
1405 case CRYPTO_AES_CBC:
1406 cs->cs_config |= CESA_CSHD_AES | CESA_CSHD_CBC;
1407 cs->cs_ivlen = AES_BLOCK_LEN;
1409 case CRYPTO_DES_CBC:
1410 cs->cs_config |= CESA_CSHD_DES | CESA_CSHD_CBC;
1411 cs->cs_ivlen = DES_BLOCK_LEN;
1413 case CRYPTO_3DES_CBC:
1414 cs->cs_config |= CESA_CSHD_3DES | CESA_CSHD_3DES_EDE |
1416 cs->cs_ivlen = DES3_BLOCK_LEN;
1424 if (!error && mac) {
1425 switch (mac->cri_alg) {
1427 cs->cs_config |= CESA_CSHD_MD5;
1429 cs->cs_hlen = MD5_HASH_LEN;
1431 case CRYPTO_MD5_HMAC:
1432 cs->cs_config |= CESA_CSHD_MD5_HMAC;
1433 cs->cs_mblen = MD5_HMAC_BLOCK_LEN;
1434 cs->cs_hlen = CESA_HMAC_HASH_LENGTH;
1437 cs->cs_config |= CESA_CSHD_SHA1;
1439 cs->cs_hlen = SHA1_HASH_LEN;
1441 case CRYPTO_SHA1_HMAC:
1442 cs->cs_config |= CESA_CSHD_SHA1_HMAC;
1443 cs->cs_mblen = SHA1_HMAC_BLOCK_LEN;
1444 cs->cs_hlen = CESA_HMAC_HASH_LENGTH;
1452 /* Save cipher key */
1453 if (!error && enc && enc->cri_key) {
1454 cs->cs_klen = enc->cri_klen / 8;
1455 memcpy(cs->cs_key, enc->cri_key, cs->cs_klen);
1456 if (enc->cri_alg == CRYPTO_AES_CBC)
1457 error = cesa_prep_aes_key(cs);
1460 /* Save digest key */
1461 if (!error && mac && mac->cri_key)
1462 error = cesa_set_mkey(cs, mac->cri_alg, mac->cri_key,
1466 cesa_free_session(sc, cs);
1476 cesa_freesession(device_t dev, uint64_t tid)
1478 struct cesa_session *cs;
1479 struct cesa_softc *sc;
1481 sc = device_get_softc(dev);
1482 cs = cesa_get_session(sc, CRYPTO_SESID2LID(tid));
1487 cesa_free_session(sc, cs);
1493 cesa_process(device_t dev, struct cryptop *crp, int hint)
1495 struct cesa_request *cr;
1496 struct cesa_session *cs;
1497 struct cryptodesc *crd;
1498 struct cryptodesc *enc;
1499 struct cryptodesc *mac;
1500 struct cesa_softc *sc;
1503 sc = device_get_softc(dev);
1504 crd = crp->crp_desc;
1509 /* Check session ID */
1510 cs = cesa_get_session(sc, CRYPTO_SESID2LID(crp->crp_sid));
1512 crp->crp_etype = EINVAL;
1517 /* Check and parse input */
1518 if (crp->crp_ilen > CESA_MAX_REQUEST_SIZE) {
1519 crp->crp_etype = E2BIG;
1524 if (cesa_is_hash(crd->crd_alg))
1529 crd = crd->crd_next;
1532 if (!enc && !cesa_is_hash(crd->crd_alg))
1535 if (!mac && cesa_is_hash(crd->crd_alg))
1538 if (crd->crd_next || !(enc && mac)) {
1539 crp->crp_etype = EINVAL;
1546 * Get request descriptor. Block driver if there is no free
1547 * descriptors in pool.
1549 cr = cesa_alloc_request(sc);
1552 sc->sc_blocked = CRYPTO_SYMQ;
1553 CESA_UNLOCK(sc, sc);
1557 /* Prepare request */
1563 CESA_LOCK(sc, sessions);
1564 cesa_sync_desc(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1566 if (enc && enc->crd_flags & CRD_F_ENCRYPT) {
1567 if (enc->crd_flags & CRD_F_IV_EXPLICIT)
1568 memcpy(cr->cr_csd->csd_iv, enc->crd_iv, cs->cs_ivlen);
1570 arc4rand(cr->cr_csd->csd_iv, cs->cs_ivlen, 0);
1572 if ((enc->crd_flags & CRD_F_IV_PRESENT) == 0)
1573 crypto_copyback(crp->crp_flags, crp->crp_buf,
1574 enc->crd_inject, cs->cs_ivlen, cr->cr_csd->csd_iv);
1576 if (enc->crd_flags & CRD_F_IV_EXPLICIT)
1577 memcpy(cr->cr_csd->csd_iv, enc->crd_iv, cs->cs_ivlen);
1579 crypto_copydata(crp->crp_flags, crp->crp_buf,
1580 enc->crd_inject, cs->cs_ivlen, cr->cr_csd->csd_iv);
1583 if (enc && enc->crd_flags & CRD_F_KEY_EXPLICIT) {
1584 if ((enc->crd_klen / 8) <= CESA_MAX_KEY_LEN) {
1585 cs->cs_klen = enc->crd_klen / 8;
1586 memcpy(cs->cs_key, enc->crd_key, cs->cs_klen);
1587 if (enc->crd_alg == CRYPTO_AES_CBC)
1588 error = cesa_prep_aes_key(cs);
1593 if (!error && mac && mac->crd_flags & CRD_F_KEY_EXPLICIT) {
1594 if ((mac->crd_klen / 8) <= CESA_MAX_MKEY_LEN)
1595 error = cesa_set_mkey(cs, mac->crd_alg, mac->crd_key,
1601 /* Convert request to chain of TDMA and SA descriptors */
1603 error = cesa_create_chain(sc, cr);
1605 cesa_sync_desc(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1606 CESA_UNLOCK(sc, sessions);
1609 cesa_free_request(sc, cr);
1610 crp->crp_etype = error;
1615 bus_dmamap_sync(sc->sc_data_dtag, cr->cr_dmap, BUS_DMASYNC_PREREAD |
1616 BUS_DMASYNC_PREWRITE);
1618 /* Enqueue request to execution */
1619 cesa_enqueue_request(sc, cr);
1621 /* Start execution, if we have no more requests in queue */
1622 if ((hint & CRYPTO_HINT_MORE) == 0)
1629 * Set CESA TDMA decode windows.
1632 decode_win_cesa_setup(struct cesa_softc *sc)
1634 struct mem_region availmem_regions[FDT_MEM_REGIONS];
1635 int availmem_regions_sz;
1636 uint32_t memsize, br, cr, i;
1638 /* Grab physical memory regions information from DTS */
1639 if (fdt_get_mem_regions(availmem_regions, &availmem_regions_sz,
1643 if (availmem_regions_sz > MV_WIN_CESA_MAX) {
1644 device_printf(sc->sc_dev, "Too much memory regions, cannot "
1645 " set CESA windows to cover whole DRAM \n");
1649 /* Disable and clear all CESA windows */
1650 for (i = 0; i < MV_WIN_CESA_MAX; i++) {
1651 CESA_WRITE(sc, MV_WIN_CESA_BASE(i), 0);
1652 CESA_WRITE(sc, MV_WIN_CESA_CTRL(i), 0);
1655 /* Fill CESA TDMA decoding windows with information acquired from DTS */
1656 for (i = 0; i < availmem_regions_sz; i++) {
1657 br = availmem_regions[i].mr_start;
1658 cr = availmem_regions[i].mr_size;
1660 /* Don't add entries with size lower than 64KB */
1661 if (cr & 0xffff0000) {
1662 cr = (((cr - 1) & 0xffff0000) |
1663 (MV_WIN_DDR_ATTR(i) << MV_WIN_CPU_ATTR_SHIFT) |
1664 (MV_WIN_DDR_TARGET << MV_WIN_CPU_TARGET_SHIFT) |
1665 MV_WIN_CPU_ENABLE_BIT);
1666 CESA_WRITE(sc, MV_WIN_CESA_BASE(i), br);
1667 CESA_WRITE(sc, MV_WIN_CESA_CTRL(i), cr);