2 * Copyright (c) 2011 Chelsio Communications, Inc.
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30 #ifndef __T4_REGS_VALUES_H__
31 #define __T4_REGS_VALUES_H__
34 * This file contains definitions for various T4 register value hardware
35 * constants. The types of values encoded here are predominantly those for
36 * register fields which control "modal" behavior. For the most part, we do
37 * not include definitions for register fields which are simple numeric
40 * These new "modal values" use a naming convention which matches the
41 * currently existing macros in t4_reg.h. For register field FOO which would
42 * have S_FOO, M_FOO, V_FOO() and G_FOO() macros, we introduce X_FOO_{MODE}
43 * definitions. These can be used as V_FOO(X_FOO_MODE) or as (G_FOO(x) ==
46 * Note that this should all be part of t4_regs.h but the toolset used to
47 * generate that file doesn't [yet] have the capability of collecting these
57 * SGE register field values.
60 /* CONTROL register */
61 #define X_FLSPLITMODE_FLSPLITMIN 0
62 #define X_FLSPLITMODE_ETHHDR 1
63 #define X_FLSPLITMODE_IPHDR 2
64 #define X_FLSPLITMODE_TCPHDR 3
66 #define X_DCASYSTYPE_FSB 0
67 #define X_DCASYSTYPE_CSI 1
69 #define X_EGSTATPAGESIZE_64B 0
70 #define X_EGSTATPAGESIZE_128B 1
72 #define X_RXPKTCPLMODE_DATA 0
73 #define X_RXPKTCPLMODE_SPLIT 1
75 #define X_INGPCIEBOUNDARY_SHIFT 5
76 #define X_INGPCIEBOUNDARY_32B 0
77 #define X_INGPCIEBOUNDARY_64B 1
78 #define X_INGPCIEBOUNDARY_128B 2
79 #define X_INGPCIEBOUNDARY_256B 3
80 #define X_INGPCIEBOUNDARY_512B 4
81 #define X_INGPCIEBOUNDARY_1024B 5
82 #define X_INGPCIEBOUNDARY_2048B 6
83 #define X_INGPCIEBOUNDARY_4096B 7
85 #define X_INGPADBOUNDARY_SHIFT 5
86 #define X_INGPADBOUNDARY_32B 0
87 #define X_INGPADBOUNDARY_64B 1
88 #define X_INGPADBOUNDARY_128B 2
89 #define X_INGPADBOUNDARY_256B 3
90 #define X_INGPADBOUNDARY_512B 4
91 #define X_INGPADBOUNDARY_1024B 5
92 #define X_INGPADBOUNDARY_2048B 6
93 #define X_INGPADBOUNDARY_4096B 7
95 #define X_EGRPCIEBOUNDARY_SHIFT 5
96 #define X_EGRPCIEBOUNDARY_32B 0
97 #define X_EGRPCIEBOUNDARY_64B 1
98 #define X_EGRPCIEBOUNDARY_128B 2
99 #define X_EGRPCIEBOUNDARY_256B 3
100 #define X_EGRPCIEBOUNDARY_512B 4
101 #define X_EGRPCIEBOUNDARY_1024B 5
102 #define X_EGRPCIEBOUNDARY_2048B 6
103 #define X_EGRPCIEBOUNDARY_4096B 7
106 #define SGE_TIMERREGS 6
107 #define X_TIMERREG_COUNTER0 0
108 #define X_TIMERREG_COUNTER1 1
109 #define X_TIMERREG_COUNTER2 2
110 #define X_TIMERREG_COUNTER3 3
111 #define X_TIMERREG_COUNTER4 4
112 #define X_TIMERREG_COUNTER5 5
113 #define X_TIMERREG_RESTART_COUNTER 6
114 #define X_TIMERREG_UPDATE_CIDX 7
117 * Egress Context field values
119 #define EC_WR_UNITS 16
121 #define X_FETCHBURSTMIN_SHIFT 4
122 #define X_FETCHBURSTMIN_16B 0
123 #define X_FETCHBURSTMIN_32B 1
124 #define X_FETCHBURSTMIN_64B 2
125 #define X_FETCHBURSTMIN_128B 3
127 #define X_FETCHBURSTMAX_SHIFT 6
128 #define X_FETCHBURSTMAX_64B 0
129 #define X_FETCHBURSTMAX_128B 1
130 #define X_FETCHBURSTMAX_256B 2
131 #define X_FETCHBURSTMAX_512B 3
133 #define X_HOSTFCMODE_NONE 0
134 #define X_HOSTFCMODE_INGRESS_QUEUE 1
135 #define X_HOSTFCMODE_STATUS_PAGE 2
136 #define X_HOSTFCMODE_BOTH 3
138 #define X_HOSTFCOWNER_UP 0
139 #define X_HOSTFCOWNER_SGE 1
141 #define X_CIDXFLUSHTHRESH_1 0
142 #define X_CIDXFLUSHTHRESH_2 1
143 #define X_CIDXFLUSHTHRESH_4 2
144 #define X_CIDXFLUSHTHRESH_8 3
145 #define X_CIDXFLUSHTHRESH_16 4
146 #define X_CIDXFLUSHTHRESH_32 5
147 #define X_CIDXFLUSHTHRESH_64 6
148 #define X_CIDXFLUSHTHRESH_128 7
150 #define X_IDXSIZE_UNIT 64
152 #define X_BASEADDRESS_ALIGN 512
155 * Ingress Context field values
157 #define X_UPDATESCHEDULING_TIMER 0
158 #define X_UPDATESCHEDULING_COUNTER_OPTTIMER 1
160 #define X_UPDATEDELIVERY_NONE 0
161 #define X_UPDATEDELIVERY_INTERRUPT 1
162 #define X_UPDATEDELIVERY_STATUS_PAGE 2
163 #define X_UPDATEDELIVERY_BOTH 3
165 #define X_INTERRUPTDESTINATION_PCIE 0
166 #define X_INTERRUPTDESTINATION_IQ 1
168 #define X_QUEUEENTRYSIZE_16B 0
169 #define X_QUEUEENTRYSIZE_32B 1
170 #define X_QUEUEENTRYSIZE_64B 2
171 #define X_QUEUEENTRYSIZE_128B 3
173 #define IC_SIZE_UNIT 16
174 #define IC_BASEADDRESS_ALIGN 512
176 #define X_RSPD_TYPE_FLBUF 0
177 #define X_RSPD_TYPE_CPL 1
178 #define X_RSPD_TYPE_INTR 2
186 * CIM register field values.
188 #define X_MBOWNER_NONE 0
189 #define X_MBOWNER_FW 1
190 #define X_MBOWNER_PL 2
197 #define X_WINDOW_SHIFT 10
198 #define X_PCIEOFST_SHIFT 10
206 * TP_VLAN_PRI_MAP controls which subset of fields will be present in the
207 * Compressed Filter Tuple for LE filters. Each bit set in TP_VLAN_PRI_MAP
208 * selects for a particular field being present. These fields, when present
209 * in the Compressed Filter Tuple, have the following widths in bits.
213 #define W_FT_VNIC_ID 17
216 #define W_FT_PROTOCOL 8
217 #define W_FT_ETHERTYPE 16
218 #define W_FT_MACMATCH 9
219 #define W_FT_MPSHITTYPE 3
220 #define W_FT_FRAGMENTATION 1
223 * Some of the Compressed Filter Tuple fields have internal structure. These
224 * bit shifts/masks describe those structures. All shifts are relative to the
225 * base position of the fields within the Compressed Filter Tuple
227 #define S_FT_VLAN_VLD 16
228 #define V_FT_VLAN_VLD(x) ((x) << S_FT_VLAN_VLD)
229 #define F_FT_VLAN_VLD V_FT_VLAN_VLD(1U)
231 #define S_FT_VNID_ID_VF 0
232 #define M_FT_VNID_ID_VF 0x7fU
233 #define V_FT_VNID_ID_VF(x) ((x) << S_FT_VNID_ID_VF)
234 #define G_FT_VNID_ID_VF(x) (((x) >> S_FT_VNID_ID_VF) & M_FT_VNID_ID_VF)
236 #define S_FT_VNID_ID_PF 7
237 #define M_FT_VNID_ID_PF 0x7U
238 #define V_FT_VNID_ID_PF(x) ((x) << S_FT_VNID_ID_PF)
239 #define G_FT_VNID_ID_PF(x) (((x) >> S_FT_VNID_ID_PF) & M_FT_VNID_ID_PF)
241 #define S_FT_VNID_ID_VLD 16
242 #define V_FT_VNID_ID_VLD(x) ((x) << S_FT_VNID_ID_VLD)
243 #define F_FT_VNID_ID_VLD(x) V_FT_VNID_ID_VLD(1U)
245 #endif /* __T4_REGS_VALUES_H__ */