sys/dev/drm/mga_state.c

   1 /* mga_state.c -- State support for MGA G200/G400 -*- linux-c -*-
   2  * Created: Thu Jan 27 02:53:43 2000 by jhartmann@precisioninsight.com
   3  */
   4 /*-
   5  * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
   6  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
   7  * All Rights Reserved.
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  24  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  25  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  26  * OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  * Authors:
  29  *    Jeff Hartmann <jhartmann@valinux.com>
  30  *    Keith Whitwell <keith@tungstengraphics.com>
  31  *
  32  * Rewritten by:
  33  *    Gareth Hughes <gareth@valinux.com>
  34  */
  35
  36 #include <sys/cdefs.h>
  37 __FBSDID("$FreeBSD$");
  38
  39 #include "dev/drm/drmP.h"
  40 #include "dev/drm/drm.h"
  41 #include "dev/drm/mga_drm.h"
  42 #include "dev/drm/mga_drv.h"
  43
  44 /* ================================================================
  45  * DMA hardware state programming functions
  46  */
  47
  48 static void mga_emit_clip_rect(drm_mga_private_t * dev_priv,
  49                                struct drm_clip_rect * box)
  50 {
  51         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
  52         drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
  53         unsigned int pitch = dev_priv->front_pitch;
  54         DMA_LOCALS;
  55
  56         BEGIN_DMA(2);
  57
  58         /* Force reset of DWGCTL on G400 (eliminates clip disable bit).
  59          */
  60         if (dev_priv->chipset >= MGA_CARD_TYPE_G400) {
  61                 DMA_BLOCK(MGA_DWGCTL, ctx->dwgctl,
  62                           MGA_LEN + MGA_EXEC, 0x80000000,
  63                           MGA_DWGCTL, ctx->dwgctl,
  64                           MGA_LEN + MGA_EXEC, 0x80000000);
  65         }
  66         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
  67                   MGA_CXBNDRY, ((box->x2 - 1) << 16) | box->x1,
  68                   MGA_YTOP, box->y1 * pitch, MGA_YBOT, (box->y2 - 1) * pitch);
  69
  70         ADVANCE_DMA();
  71 }
  72
  73 static __inline__ void mga_g200_emit_context(drm_mga_private_t * dev_priv)
  74 {
  75         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
  76         drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
  77         DMA_LOCALS;
  78
  79         BEGIN_DMA(3);
  80
  81         DMA_BLOCK(MGA_DSTORG, ctx->dstorg,
  82                   MGA_MACCESS, ctx->maccess,
  83                   MGA_PLNWT, ctx->plnwt, MGA_DWGCTL, ctx->dwgctl);
  84
  85         DMA_BLOCK(MGA_ALPHACTRL, ctx->alphactrl,
  86                   MGA_FOGCOL, ctx->fogcolor,
  87                   MGA_WFLAG, ctx->wflag, MGA_ZORG, dev_priv->depth_offset);
  88
  89         DMA_BLOCK(MGA_FCOL, ctx->fcol,
  90                   MGA_DMAPAD, 0x00000000,
  91                   MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
  92
  93         ADVANCE_DMA();
  94 }
  95
  96 static __inline__ void mga_g400_emit_context(drm_mga_private_t * dev_priv)
  97 {
  98         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
  99         drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
 100         DMA_LOCALS;
 101
 102         BEGIN_DMA(4);
 103
 104         DMA_BLOCK(MGA_DSTORG, ctx->dstorg,
 105                   MGA_MACCESS, ctx->maccess,
 106                   MGA_PLNWT, ctx->plnwt,
 107                   MGA_DWGCTL, ctx->dwgctl);
 108
 109         DMA_BLOCK(MGA_ALPHACTRL, ctx->alphactrl,
 110                   MGA_FOGCOL, ctx->fogcolor,
 111                   MGA_WFLAG, ctx->wflag,
 112                   MGA_ZORG, dev_priv->depth_offset);
 113
 114         DMA_BLOCK(MGA_WFLAG1, ctx->wflag,
 115                   MGA_TDUALSTAGE0, ctx->tdualstage0,
 116                   MGA_TDUALSTAGE1, ctx->tdualstage1,
 117                   MGA_FCOL, ctx->fcol);
 118
 119         DMA_BLOCK(MGA_STENCIL, ctx->stencil,
 120                   MGA_STENCILCTL, ctx->stencilctl,
 121                   MGA_DMAPAD, 0x00000000,
 122                   MGA_DMAPAD, 0x00000000);
 123
 124         ADVANCE_DMA();
 125 }
 126
 127 static __inline__ void mga_g200_emit_tex0(drm_mga_private_t * dev_priv)
 128 {
 129         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 130         drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
 131         DMA_LOCALS;
 132
 133         BEGIN_DMA(4);
 134
 135         DMA_BLOCK(MGA_TEXCTL2, tex->texctl2,
 136                   MGA_TEXCTL, tex->texctl,
 137                   MGA_TEXFILTER, tex->texfilter,
 138                   MGA_TEXBORDERCOL, tex->texbordercol);
 139
 140         DMA_BLOCK(MGA_TEXORG, tex->texorg,
 141                   MGA_TEXORG1, tex->texorg1,
 142                   MGA_TEXORG2, tex->texorg2,
 143                   MGA_TEXORG3, tex->texorg3);
 144
 145         DMA_BLOCK(MGA_TEXORG4, tex->texorg4,
 146                   MGA_TEXWIDTH, tex->texwidth,
 147                   MGA_TEXHEIGHT, tex->texheight,
 148                   MGA_WR24, tex->texwidth);
 149
 150         DMA_BLOCK(MGA_WR34, tex->texheight,
 151                   MGA_TEXTRANS, 0x0000ffff,
 152                   MGA_TEXTRANSHIGH, 0x0000ffff,
 153                   MGA_DMAPAD, 0x00000000);
 154
 155         ADVANCE_DMA();
 156 }
 157
 158 static __inline__ void mga_g400_emit_tex0(drm_mga_private_t * dev_priv)
 159 {
 160         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 161         drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
 162         DMA_LOCALS;
 163
 164 /*      printk("mga_g400_emit_tex0 %x %x %x\n", tex->texorg, */
 165 /*             tex->texctl, tex->texctl2); */
 166
 167         BEGIN_DMA(6);
 168
 169         DMA_BLOCK(MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC,
 170                   MGA_TEXCTL, tex->texctl,
 171                   MGA_TEXFILTER, tex->texfilter,
 172                   MGA_TEXBORDERCOL, tex->texbordercol);
 173
 174         DMA_BLOCK(MGA_TEXORG, tex->texorg,
 175                   MGA_TEXORG1, tex->texorg1,
 176                   MGA_TEXORG2, tex->texorg2,
 177                   MGA_TEXORG3, tex->texorg3);
 178
 179         DMA_BLOCK(MGA_TEXORG4, tex->texorg4,
 180                   MGA_TEXWIDTH, tex->texwidth,
 181                   MGA_TEXHEIGHT, tex->texheight,
 182                   MGA_WR49, 0x00000000);
 183
 184         DMA_BLOCK(MGA_WR57, 0x00000000,
 185                   MGA_WR53, 0x00000000,
 186                   MGA_WR61, 0x00000000,
 187                   MGA_WR52, MGA_G400_WR_MAGIC);
 188
 189         DMA_BLOCK(MGA_WR60, MGA_G400_WR_MAGIC,
 190                   MGA_WR54, tex->texwidth | MGA_G400_WR_MAGIC,
 191                   MGA_WR62, tex->texheight | MGA_G400_WR_MAGIC,
 192                   MGA_DMAPAD, 0x00000000);
 193
 194         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 195                   MGA_DMAPAD, 0x00000000,
 196                   MGA_TEXTRANS, 0x0000ffff,
 197                   MGA_TEXTRANSHIGH, 0x0000ffff);
 198
 199         ADVANCE_DMA();
 200 }
 201
 202 static __inline__ void mga_g400_emit_tex1(drm_mga_private_t * dev_priv)
 203 {
 204         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 205         drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[1];
 206         DMA_LOCALS;
 207
 208 /*      printk("mga_g400_emit_tex1 %x %x %x\n", tex->texorg,  */
 209 /*             tex->texctl, tex->texctl2); */
 210
 211         BEGIN_DMA(5);
 212
 213         DMA_BLOCK(MGA_TEXCTL2, (tex->texctl2 |
 214                                 MGA_MAP1_ENABLE |
 215                                 MGA_G400_TC2_MAGIC),
 216                   MGA_TEXCTL, tex->texctl,
 217                   MGA_TEXFILTER, tex->texfilter,
 218                   MGA_TEXBORDERCOL, tex->texbordercol);
 219
 220         DMA_BLOCK(MGA_TEXORG, tex->texorg,
 221                   MGA_TEXORG1, tex->texorg1,
 222                   MGA_TEXORG2, tex->texorg2,
 223                   MGA_TEXORG3, tex->texorg3);
 224
 225         DMA_BLOCK(MGA_TEXORG4, tex->texorg4,
 226                   MGA_TEXWIDTH, tex->texwidth,
 227                   MGA_TEXHEIGHT, tex->texheight,
 228                   MGA_WR49, 0x00000000);
 229
 230         DMA_BLOCK(MGA_WR57, 0x00000000,
 231                   MGA_WR53, 0x00000000,
 232                   MGA_WR61, 0x00000000,
 233                   MGA_WR52, tex->texwidth | MGA_G400_WR_MAGIC);
 234
 235         DMA_BLOCK(MGA_WR60, tex->texheight | MGA_G400_WR_MAGIC,
 236                   MGA_TEXTRANS, 0x0000ffff,
 237                   MGA_TEXTRANSHIGH, 0x0000ffff,
 238                   MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC);
 239
 240         ADVANCE_DMA();
 241 }
 242
 243 static __inline__ void mga_g200_emit_pipe(drm_mga_private_t * dev_priv)
 244 {
 245         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 246         unsigned int pipe = sarea_priv->warp_pipe;
 247         DMA_LOCALS;
 248
 249         BEGIN_DMA(3);
 250
 251         DMA_BLOCK(MGA_WIADDR, MGA_WMODE_SUSPEND,
 252                   MGA_WVRTXSZ, 0x00000007,
 253                   MGA_WFLAG, 0x00000000,
 254                   MGA_WR24, 0x00000000);
 255
 256         DMA_BLOCK(MGA_WR25, 0x00000100,
 257                   MGA_WR34, 0x00000000,
 258                   MGA_WR42, 0x0000ffff,
 259                   MGA_WR60, 0x0000ffff);
 260
 261         /* Padding required to to hardware bug.
 262          */
 263         DMA_BLOCK(MGA_DMAPAD, 0xffffffff,
 264                   MGA_DMAPAD, 0xffffffff,
 265                   MGA_DMAPAD, 0xffffffff,
 266                   MGA_WIADDR, (dev_priv->warp_pipe_phys[pipe] |
 267                                MGA_WMODE_START | dev_priv->wagp_enable));
 268
 269         ADVANCE_DMA();
 270 }
 271
 272 static __inline__ void mga_g400_emit_pipe(drm_mga_private_t * dev_priv)
 273 {
 274         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 275         unsigned int pipe = sarea_priv->warp_pipe;
 276         DMA_LOCALS;
 277
 278 /*      printk("mga_g400_emit_pipe %x\n", pipe); */
 279
 280         BEGIN_DMA(10);
 281
 282         DMA_BLOCK(MGA_WIADDR2, MGA_WMODE_SUSPEND,
 283                   MGA_DMAPAD, 0x00000000,
 284                   MGA_DMAPAD, 0x00000000,
 285                   MGA_DMAPAD, 0x00000000);
 286
 287         if (pipe & MGA_T2) {
 288                 DMA_BLOCK(MGA_WVRTXSZ, 0x00001e09,
 289                           MGA_DMAPAD, 0x00000000,
 290                           MGA_DMAPAD, 0x00000000,
 291                           MGA_DMAPAD, 0x00000000);
 292
 293                 DMA_BLOCK(MGA_WACCEPTSEQ, 0x00000000,
 294                           MGA_WACCEPTSEQ, 0x00000000,
 295                           MGA_WACCEPTSEQ, 0x00000000,
 296                           MGA_WACCEPTSEQ, 0x1e000000);
 297         } else {
 298                 if (dev_priv->warp_pipe & MGA_T2) {
 299                         /* Flush the WARP pipe */
 300                         DMA_BLOCK(MGA_YDST, 0x00000000,
 301                                   MGA_FXLEFT, 0x00000000,
 302                                   MGA_FXRIGHT, 0x00000001,
 303                                   MGA_DWGCTL, MGA_DWGCTL_FLUSH);
 304
 305                         DMA_BLOCK(MGA_LEN + MGA_EXEC, 0x00000001,
 306                                   MGA_DWGSYNC, 0x00007000,
 307                                   MGA_TEXCTL2, MGA_G400_TC2_MAGIC,
 308                                   MGA_LEN + MGA_EXEC, 0x00000000);
 309
 310                         DMA_BLOCK(MGA_TEXCTL2, (MGA_DUALTEX |
 311                                                 MGA_G400_TC2_MAGIC),
 312                                   MGA_LEN + MGA_EXEC, 0x00000000,
 313                                   MGA_TEXCTL2, MGA_G400_TC2_MAGIC,
 314                                   MGA_DMAPAD, 0x00000000);
 315                 }
 316
 317                 DMA_BLOCK(MGA_WVRTXSZ, 0x00001807,
 318                           MGA_DMAPAD, 0x00000000,
 319                           MGA_DMAPAD, 0x00000000,
 320                           MGA_DMAPAD, 0x00000000);
 321
 322                 DMA_BLOCK(MGA_WACCEPTSEQ, 0x00000000,
 323                           MGA_WACCEPTSEQ, 0x00000000,
 324                           MGA_WACCEPTSEQ, 0x00000000,
 325                           MGA_WACCEPTSEQ, 0x18000000);
 326         }
 327
 328         DMA_BLOCK(MGA_WFLAG, 0x00000000,
 329                   MGA_WFLAG1, 0x00000000,
 330                   MGA_WR56, MGA_G400_WR56_MAGIC,
 331                   MGA_DMAPAD, 0x00000000);
 332
 333         DMA_BLOCK(MGA_WR49, 0x00000000, /* tex0              */
 334                   MGA_WR57, 0x00000000, /* tex0              */
 335                   MGA_WR53, 0x00000000, /* tex1              */
 336                   MGA_WR61, 0x00000000);        /* tex1              */
 337
 338         DMA_BLOCK(MGA_WR54, MGA_G400_WR_MAGIC,  /* tex0 width        */
 339                   MGA_WR62, MGA_G400_WR_MAGIC,  /* tex0 height       */
 340                   MGA_WR52, MGA_G400_WR_MAGIC,  /* tex1 width        */
 341                   MGA_WR60, MGA_G400_WR_MAGIC); /* tex1 height       */
 342
 343         /* Padding required to to hardware bug */
 344         DMA_BLOCK(MGA_DMAPAD, 0xffffffff,
 345                   MGA_DMAPAD, 0xffffffff,
 346                   MGA_DMAPAD, 0xffffffff,
 347                   MGA_WIADDR2, (dev_priv->warp_pipe_phys[pipe] |
 348                                 MGA_WMODE_START | dev_priv->wagp_enable));
 349
 350         ADVANCE_DMA();
 351 }
 352
 353 static void mga_g200_emit_state(drm_mga_private_t * dev_priv)
 354 {
 355         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 356         unsigned int dirty = sarea_priv->dirty;
 357
 358         if (sarea_priv->warp_pipe != dev_priv->warp_pipe) {
 359                 mga_g200_emit_pipe(dev_priv);
 360                 dev_priv->warp_pipe = sarea_priv->warp_pipe;
 361         }
 362
 363         if (dirty & MGA_UPLOAD_CONTEXT) {
 364                 mga_g200_emit_context(dev_priv);
 365                 sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT;
 366         }
 367
 368         if (dirty & MGA_UPLOAD_TEX0) {
 369                 mga_g200_emit_tex0(dev_priv);
 370                 sarea_priv->dirty &= ~MGA_UPLOAD_TEX0;
 371         }
 372 }
 373
 374 static void mga_g400_emit_state(drm_mga_private_t * dev_priv)
 375 {
 376         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 377         unsigned int dirty = sarea_priv->dirty;
 378         int multitex = sarea_priv->warp_pipe & MGA_T2;
 379
 380         if (sarea_priv->warp_pipe != dev_priv->warp_pipe) {
 381                 mga_g400_emit_pipe(dev_priv);
 382                 dev_priv->warp_pipe = sarea_priv->warp_pipe;
 383         }
 384
 385         if (dirty & MGA_UPLOAD_CONTEXT) {
 386                 mga_g400_emit_context(dev_priv);
 387                 sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT;
 388         }
 389
 390         if (dirty & MGA_UPLOAD_TEX0) {
 391                 mga_g400_emit_tex0(dev_priv);
 392                 sarea_priv->dirty &= ~MGA_UPLOAD_TEX0;
 393         }
 394
 395         if ((dirty & MGA_UPLOAD_TEX1) && multitex) {
 396                 mga_g400_emit_tex1(dev_priv);
 397                 sarea_priv->dirty &= ~MGA_UPLOAD_TEX1;
 398         }
 399 }
 400
 401 /* ================================================================
 402  * SAREA state verification
 403  */
 404
 405 /* Disallow all write destinations except the front and backbuffer.
 406  */
 407 static int mga_verify_context(drm_mga_private_t * dev_priv)
 408 {
 409         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 410         drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
 411
 412         if (ctx->dstorg != dev_priv->front_offset &&
 413             ctx->dstorg != dev_priv->back_offset) {
 414                 DRM_ERROR("*** bad DSTORG: %x (front %x, back %x)\n\n",
 415                           ctx->dstorg, dev_priv->front_offset,
 416                           dev_priv->back_offset);
 417                 ctx->dstorg = 0;
 418                 return -EINVAL;
 419         }
 420
 421         return 0;
 422 }
 423
 424 /* Disallow texture reads from PCI space.
 425  */
 426 static int mga_verify_tex(drm_mga_private_t * dev_priv, int unit)
 427 {
 428         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 429         drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[unit];
 430         unsigned int org;
 431
 432         org = tex->texorg & (MGA_TEXORGMAP_MASK | MGA_TEXORGACC_MASK);
 433
 434         if (org == (MGA_TEXORGMAP_SYSMEM | MGA_TEXORGACC_PCI)) {
 435                 DRM_ERROR("*** bad TEXORG: 0x%x, unit %d\n", tex->texorg, unit);
 436                 tex->texorg = 0;
 437                 return -EINVAL;
 438         }
 439
 440         return 0;
 441 }
 442
 443 static int mga_verify_state(drm_mga_private_t * dev_priv)
 444 {
 445         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 446         unsigned int dirty = sarea_priv->dirty;
 447         int ret = 0;
 448
 449         if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
 450                 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
 451
 452         if (dirty & MGA_UPLOAD_CONTEXT)
 453                 ret |= mga_verify_context(dev_priv);
 454
 455         if (dirty & MGA_UPLOAD_TEX0)
 456                 ret |= mga_verify_tex(dev_priv, 0);
 457
 458         if (dev_priv->chipset >= MGA_CARD_TYPE_G400) {
 459                 if (dirty & MGA_UPLOAD_TEX1)
 460                         ret |= mga_verify_tex(dev_priv, 1);
 461
 462                 if (dirty & MGA_UPLOAD_PIPE)
 463                         ret |= (sarea_priv->warp_pipe > MGA_MAX_G400_PIPES);
 464         } else {
 465                 if (dirty & MGA_UPLOAD_PIPE)
 466                         ret |= (sarea_priv->warp_pipe > MGA_MAX_G200_PIPES);
 467         }
 468
 469         return (ret == 0);
 470 }
 471
 472 static int mga_verify_iload(drm_mga_private_t * dev_priv,
 473                             unsigned int dstorg, unsigned int length)
 474 {
 475         if (dstorg < dev_priv->texture_offset ||
 476             dstorg + length > (dev_priv->texture_offset +
 477                                dev_priv->texture_size)) {
 478                 DRM_ERROR("*** bad iload DSTORG: 0x%x\n", dstorg);
 479                 return -EINVAL;
 480         }
 481
 482         if (length & MGA_ILOAD_MASK) {
 483                 DRM_ERROR("*** bad iload length: 0x%x\n",
 484                           length & MGA_ILOAD_MASK);
 485                 return -EINVAL;
 486         }
 487
 488         return 0;
 489 }
 490
 491 static int mga_verify_blit(drm_mga_private_t * dev_priv,
 492                            unsigned int srcorg, unsigned int dstorg)
 493 {
 494         if ((srcorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) ||
 495             (dstorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM)) {
 496                 DRM_ERROR("*** bad blit: src=0x%x dst=0x%x\n", srcorg, dstorg);
 497                 return -EINVAL;
 498         }
 499         return 0;
 500 }
 501
 502 /* ================================================================
 503  *
 504  */
 505
 506 static void mga_dma_dispatch_clear(struct drm_device * dev, drm_mga_clear_t * clear)
 507 {
 508         drm_mga_private_t *dev_priv = dev->dev_private;
 509         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 510         drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
 511         struct drm_clip_rect *pbox = sarea_priv->boxes;
 512         int nbox = sarea_priv->nbox;
 513         int i;
 514         DMA_LOCALS;
 515         DRM_DEBUG("\n");
 516
 517         BEGIN_DMA(1);
 518
 519         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 520                   MGA_DMAPAD, 0x00000000,
 521                   MGA_DWGSYNC, 0x00007100,
 522                   MGA_DWGSYNC, 0x00007000);
 523
 524         ADVANCE_DMA();
 525
 526         for (i = 0; i < nbox; i++) {
 527                 struct drm_clip_rect *box = &pbox[i];
 528                 u32 height = box->y2 - box->y1;
 529
 530                 DRM_DEBUG("   from=%d,%d to=%d,%d\n",
 531                           box->x1, box->y1, box->x2, box->y2);
 532
 533                 if (clear->flags & MGA_FRONT) {
 534                         BEGIN_DMA(2);
 535
 536                         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 537                                   MGA_PLNWT, clear->color_mask,
 538                                   MGA_YDSTLEN, (box->y1 << 16) | height,
 539                                   MGA_FXBNDRY, (box->x2 << 16) | box->x1);
 540
 541                         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 542                                   MGA_FCOL, clear->clear_color,
 543                                   MGA_DSTORG, dev_priv->front_offset,
 544                                   MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd);
 545
 546                         ADVANCE_DMA();
 547                 }
 548
 549                 if (clear->flags & MGA_BACK) {
 550                         BEGIN_DMA(2);
 551
 552                         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 553                                   MGA_PLNWT, clear->color_mask,
 554                                   MGA_YDSTLEN, (box->y1 << 16) | height,
 555                                   MGA_FXBNDRY, (box->x2 << 16) | box->x1);
 556
 557                         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 558                                   MGA_FCOL, clear->clear_color,
 559                                   MGA_DSTORG, dev_priv->back_offset,
 560                                   MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd);
 561
 562                         ADVANCE_DMA();
 563                 }
 564
 565                 if (clear->flags & MGA_DEPTH) {
 566                         BEGIN_DMA(2);
 567
 568                         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 569                                   MGA_PLNWT, clear->depth_mask,
 570                                   MGA_YDSTLEN, (box->y1 << 16) | height,
 571                                   MGA_FXBNDRY, (box->x2 << 16) | box->x1);
 572
 573                         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 574                                   MGA_FCOL, clear->clear_depth,
 575                                   MGA_DSTORG, dev_priv->depth_offset,
 576                                   MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd);
 577
 578                         ADVANCE_DMA();
 579                 }
 580
 581         }
 582
 583         BEGIN_DMA(1);
 584
 585         /* Force reset of DWGCTL */
 586         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 587                   MGA_DMAPAD, 0x00000000,
 588                   MGA_PLNWT, ctx->plnwt,
 589                   MGA_DWGCTL, ctx->dwgctl);
 590
 591         ADVANCE_DMA();
 592
 593         FLUSH_DMA();
 594 }
 595
 596 static void mga_dma_dispatch_swap(struct drm_device * dev)
 597 {
 598         drm_mga_private_t *dev_priv = dev->dev_private;
 599         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 600         drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
 601         struct drm_clip_rect *pbox = sarea_priv->boxes;
 602         int nbox = sarea_priv->nbox;
 603         int i;
 604         DMA_LOCALS;
 605         DRM_DEBUG("\n");
 606
 607         sarea_priv->last_frame.head = dev_priv->prim.tail;
 608         sarea_priv->last_frame.wrap = dev_priv->prim.last_wrap;
 609
 610         BEGIN_DMA(4 + nbox);
 611
 612         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 613                   MGA_DMAPAD, 0x00000000,
 614                   MGA_DWGSYNC, 0x00007100,
 615                   MGA_DWGSYNC, 0x00007000);
 616
 617         DMA_BLOCK(MGA_DSTORG, dev_priv->front_offset,
 618                   MGA_MACCESS, dev_priv->maccess,
 619                   MGA_SRCORG, dev_priv->back_offset,
 620                   MGA_AR5, dev_priv->front_pitch);
 621
 622         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 623                   MGA_DMAPAD, 0x00000000,
 624                   MGA_PLNWT, 0xffffffff,
 625                   MGA_DWGCTL, MGA_DWGCTL_COPY);
 626
 627         for (i = 0; i < nbox; i++) {
 628                 struct drm_clip_rect *box = &pbox[i];
 629                 u32 height = box->y2 - box->y1;
 630                 u32 start = box->y1 * dev_priv->front_pitch;
 631
 632                 DRM_DEBUG("   from=%d,%d to=%d,%d\n",
 633                           box->x1, box->y1, box->x2, box->y2);
 634
 635                 DMA_BLOCK(MGA_AR0, start + box->x2 - 1,
 636                           MGA_AR3, start + box->x1,
 637                           MGA_FXBNDRY, ((box->x2 - 1) << 16) | box->x1,
 638                           MGA_YDSTLEN + MGA_EXEC, (box->y1 << 16) | height);
 639         }
 640
 641         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 642                   MGA_PLNWT, ctx->plnwt,
 643                   MGA_SRCORG, dev_priv->front_offset,
 644                   MGA_DWGCTL, ctx->dwgctl);
 645
 646         ADVANCE_DMA();
 647
 648         FLUSH_DMA();
 649
 650         DRM_DEBUG("... done.\n");
 651 }
 652
 653 static void mga_dma_dispatch_vertex(struct drm_device * dev, struct drm_buf * buf)
 654 {
 655         drm_mga_private_t *dev_priv = dev->dev_private;
 656         drm_mga_buf_priv_t *buf_priv = buf->dev_private;
 657         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 658         u32 address = (u32) buf->bus_address;
 659         u32 length = (u32) buf->used;
 660         int i = 0;
 661         DMA_LOCALS;
 662         DRM_DEBUG("buf=%d used=%d\n", buf->idx, buf->used);
 663
 664         if (buf->used) {
 665                 buf_priv->dispatched = 1;
 666
 667                 MGA_EMIT_STATE(dev_priv, sarea_priv->dirty);
 668
 669                 do {
 670                         if (i < sarea_priv->nbox) {
 671                                 mga_emit_clip_rect(dev_priv,
 672                                                    &sarea_priv->boxes[i]);
 673                         }
 674
 675                         BEGIN_DMA(1);
 676
 677                         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 678                                   MGA_DMAPAD, 0x00000000,
 679                                   MGA_SECADDRESS, (address |
 680                                                    MGA_DMA_VERTEX),
 681                                   MGA_SECEND, ((address + length) |
 682                                                dev_priv->dma_access));
 683
 684                         ADVANCE_DMA();
 685                 } while (++i < sarea_priv->nbox);
 686         }
 687
 688         if (buf_priv->discard) {
 689                 AGE_BUFFER(buf_priv);
 690                 buf->pending = 0;
 691                 buf->used = 0;
 692                 buf_priv->dispatched = 0;
 693
 694                 mga_freelist_put(dev, buf);
 695         }
 696
 697         FLUSH_DMA();
 698 }
 699
 700 static void mga_dma_dispatch_indices(struct drm_device * dev, struct drm_buf * buf,
 701                                      unsigned int start, unsigned int end)
 702 {
 703         drm_mga_private_t *dev_priv = dev->dev_private;
 704         drm_mga_buf_priv_t *buf_priv = buf->dev_private;
 705         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 706         u32 address = (u32) buf->bus_address;
 707         int i = 0;
 708         DMA_LOCALS;
 709         DRM_DEBUG("buf=%d start=%d end=%d\n", buf->idx, start, end);
 710
 711         if (start != end) {
 712                 buf_priv->dispatched = 1;
 713
 714                 MGA_EMIT_STATE(dev_priv, sarea_priv->dirty);
 715
 716                 do {
 717                         if (i < sarea_priv->nbox) {
 718                                 mga_emit_clip_rect(dev_priv,
 719                                                    &sarea_priv->boxes[i]);
 720                         }
 721
 722                         BEGIN_DMA(1);
 723
 724                         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 725                                   MGA_DMAPAD, 0x00000000,
 726                                   MGA_SETUPADDRESS, address + start,
 727                                   MGA_SETUPEND, ((address + end) |
 728                                                  dev_priv->dma_access));
 729
 730                         ADVANCE_DMA();
 731                 } while (++i < sarea_priv->nbox);
 732         }
 733
 734         if (buf_priv->discard) {
 735                 AGE_BUFFER(buf_priv);
 736                 buf->pending = 0;
 737                 buf->used = 0;
 738                 buf_priv->dispatched = 0;
 739
 740                 mga_freelist_put(dev, buf);
 741         }
 742
 743         FLUSH_DMA();
 744 }
 745
 746 /* This copies a 64 byte aligned agp region to the frambuffer with a
 747  * standard blit, the ioctl needs to do checking.
 748  */
 749 static void mga_dma_dispatch_iload(struct drm_device * dev, struct drm_buf * buf,
 750                                    unsigned int dstorg, unsigned int length)
 751 {
 752         drm_mga_private_t *dev_priv = dev->dev_private;
 753         drm_mga_buf_priv_t *buf_priv = buf->dev_private;
 754         drm_mga_context_regs_t *ctx = &dev_priv->sarea_priv->context_state;
 755         u32 srcorg = buf->bus_address | dev_priv->dma_access | MGA_SRCMAP_SYSMEM;
 756         u32 y2;
 757         DMA_LOCALS;
 758         DRM_DEBUG("buf=%d used=%d\n", buf->idx, buf->used);
 759
 760         y2 = length / 64;
 761
 762         BEGIN_DMA(5);
 763
 764         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 765                   MGA_DMAPAD, 0x00000000,
 766                   MGA_DWGSYNC, 0x00007100,
 767                   MGA_DWGSYNC, 0x00007000);
 768
 769         DMA_BLOCK(MGA_DSTORG, dstorg,
 770                   MGA_MACCESS, 0x00000000,
 771                   MGA_SRCORG, srcorg,
 772                   MGA_AR5, 64);
 773
 774         DMA_BLOCK(MGA_PITCH, 64,
 775                   MGA_PLNWT, 0xffffffff,
 776                   MGA_DMAPAD, 0x00000000,
 777                   MGA_DWGCTL, MGA_DWGCTL_COPY);
 778
 779         DMA_BLOCK(MGA_AR0, 63,
 780                   MGA_AR3, 0,
 781                   MGA_FXBNDRY, (63 << 16) | 0,
 782                   MGA_YDSTLEN + MGA_EXEC, y2);
 783
 784         DMA_BLOCK(MGA_PLNWT, ctx->plnwt,
 785                   MGA_SRCORG, dev_priv->front_offset,
 786                   MGA_PITCH, dev_priv->front_pitch,
 787                   MGA_DWGSYNC, 0x00007000);
 788
 789         ADVANCE_DMA();
 790
 791         AGE_BUFFER(buf_priv);
 792
 793         buf->pending = 0;
 794         buf->used = 0;
 795         buf_priv->dispatched = 0;
 796
 797         mga_freelist_put(dev, buf);
 798
 799         FLUSH_DMA();
 800 }
 801
 802 static void mga_dma_dispatch_blit(struct drm_device * dev, drm_mga_blit_t * blit)
 803 {
 804         drm_mga_private_t *dev_priv = dev->dev_private;
 805         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 806         drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
 807         struct drm_clip_rect *pbox = sarea_priv->boxes;
 808         int nbox = sarea_priv->nbox;
 809         u32 scandir = 0, i;
 810         DMA_LOCALS;
 811         DRM_DEBUG("\n");
 812
 813         BEGIN_DMA(4 + nbox);
 814
 815         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 816                   MGA_DMAPAD, 0x00000000,
 817                   MGA_DWGSYNC, 0x00007100,
 818                   MGA_DWGSYNC, 0x00007000);
 819
 820         DMA_BLOCK(MGA_DWGCTL, MGA_DWGCTL_COPY,
 821                   MGA_PLNWT, blit->planemask,
 822                   MGA_SRCORG, blit->srcorg,
 823                   MGA_DSTORG, blit->dstorg);
 824
 825         DMA_BLOCK(MGA_SGN, scandir,
 826                   MGA_MACCESS, dev_priv->maccess,
 827                   MGA_AR5, blit->ydir * blit->src_pitch,
 828                   MGA_PITCH, blit->dst_pitch);
 829
 830         for (i = 0; i < nbox; i++) {
 831                 int srcx = pbox[i].x1 + blit->delta_sx;
 832                 int srcy = pbox[i].y1 + blit->delta_sy;
 833                 int dstx = pbox[i].x1 + blit->delta_dx;
 834                 int dsty = pbox[i].y1 + blit->delta_dy;
 835                 int h = pbox[i].y2 - pbox[i].y1;
 836                 int w = pbox[i].x2 - pbox[i].x1 - 1;
 837                 int start;
 838
 839                 if (blit->ydir == -1) {
 840                         srcy = blit->height - srcy - 1;
 841                 }
 842
 843                 start = srcy * blit->src_pitch + srcx;
 844
 845                 DMA_BLOCK(MGA_AR0, start + w,
 846                           MGA_AR3, start,
 847                           MGA_FXBNDRY, ((dstx + w) << 16) | (dstx & 0xffff),
 848                           MGA_YDSTLEN + MGA_EXEC, (dsty << 16) | h);
 849         }
 850
 851         /* Do something to flush AGP?
 852          */
 853
 854         /* Force reset of DWGCTL */
 855         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 856                   MGA_PLNWT, ctx->plnwt,
 857                   MGA_PITCH, dev_priv->front_pitch,
 858                   MGA_DWGCTL, ctx->dwgctl);
 859
 860         ADVANCE_DMA();
 861 }
 862
 863 /* ================================================================
 864  *
 865  */
 866
 867 static int mga_dma_clear(struct drm_device *dev, void *data, struct drm_file *file_priv)
 868 {
 869         drm_mga_private_t *dev_priv = dev->dev_private;
 870         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 871         drm_mga_clear_t *clear = data;
 872
 873         LOCK_TEST_WITH_RETURN(dev, file_priv);
 874
 875         if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
 876                 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
 877
 878         WRAP_TEST_WITH_RETURN(dev_priv);
 879
 880         mga_dma_dispatch_clear(dev, clear);
 881
 882         /* Make sure we restore the 3D state next time.
 883          */
 884         dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
 885
 886         return 0;
 887 }
 888
 889 static int mga_dma_swap(struct drm_device *dev, void *data, struct drm_file *file_priv)
 890 {
 891         drm_mga_private_t *dev_priv = dev->dev_private;
 892         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 893
 894         LOCK_TEST_WITH_RETURN(dev, file_priv);
 895
 896         if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
 897                 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
 898
 899         WRAP_TEST_WITH_RETURN(dev_priv);
 900
 901         mga_dma_dispatch_swap(dev);
 902
 903         /* Make sure we restore the 3D state next time.
 904          */
 905         dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
 906
 907         return 0;
 908 }
 909
 910 static int mga_dma_vertex(struct drm_device *dev, void *data, struct drm_file *file_priv)
 911 {
 912         drm_mga_private_t *dev_priv = dev->dev_private;
 913         struct drm_device_dma *dma = dev->dma;
 914         struct drm_buf *buf;
 915         drm_mga_buf_priv_t *buf_priv;
 916         drm_mga_vertex_t *vertex = data;
 917
 918         LOCK_TEST_WITH_RETURN(dev, file_priv);
 919
 920         if (vertex->idx < 0 || vertex->idx > dma->buf_count)
 921                 return -EINVAL;
 922         buf = dma->buflist[vertex->idx];
 923         buf_priv = buf->dev_private;
 924
 925         buf->used = vertex->used;
 926         buf_priv->discard = vertex->discard;
 927
 928         if (!mga_verify_state(dev_priv)) {
 929                 if (vertex->discard) {
 930                         if (buf_priv->dispatched == 1)
 931                                 AGE_BUFFER(buf_priv);
 932                         buf_priv->dispatched = 0;
 933                         mga_freelist_put(dev, buf);
 934                 }
 935                 return -EINVAL;
 936         }
 937
 938         WRAP_TEST_WITH_RETURN(dev_priv);
 939
 940         mga_dma_dispatch_vertex(dev, buf);
 941
 942         return 0;
 943 }
 944
 945 static int mga_dma_indices(struct drm_device *dev, void *data, struct drm_file *file_priv)
 946 {
 947         drm_mga_private_t *dev_priv = dev->dev_private;
 948         struct drm_device_dma *dma = dev->dma;
 949         struct drm_buf *buf;
 950         drm_mga_buf_priv_t *buf_priv;
 951         drm_mga_indices_t *indices = data;
 952
 953         LOCK_TEST_WITH_RETURN(dev, file_priv);
 954
 955         if (indices->idx < 0 || indices->idx > dma->buf_count)
 956                 return -EINVAL;
 957
 958         buf = dma->buflist[indices->idx];
 959         buf_priv = buf->dev_private;
 960
 961         buf_priv->discard = indices->discard;
 962
 963         if (!mga_verify_state(dev_priv)) {
 964                 if (indices->discard) {
 965                         if (buf_priv->dispatched == 1)
 966                                 AGE_BUFFER(buf_priv);
 967                         buf_priv->dispatched = 0;
 968                         mga_freelist_put(dev, buf);
 969                 }
 970                 return -EINVAL;
 971         }
 972
 973         WRAP_TEST_WITH_RETURN(dev_priv);
 974
 975         mga_dma_dispatch_indices(dev, buf, indices->start, indices->end);
 976
 977         return 0;
 978 }
 979
 980 static int mga_dma_iload(struct drm_device *dev, void *data, struct drm_file *file_priv)
 981 {
 982         struct drm_device_dma *dma = dev->dma;
 983         drm_mga_private_t *dev_priv = dev->dev_private;
 984         struct drm_buf *buf;
 985         drm_mga_buf_priv_t *buf_priv;
 986         drm_mga_iload_t *iload = data;
 987         DRM_DEBUG("\n");
 988
 989         LOCK_TEST_WITH_RETURN(dev, file_priv);
 990
 991 #if 0
 992         if (mga_do_wait_for_idle(dev_priv) < 0) {
 993                 if (MGA_DMA_DEBUG)
 994                         DRM_INFO("-EBUSY\n");
 995                 return -EBUSY;
 996         }
 997 #endif
 998         if (iload->idx < 0 || iload->idx > dma->buf_count)
 999                 return -EINVAL;
1000
1001         buf = dma->buflist[iload->idx];
1002         buf_priv = buf->dev_private;
1003
1004         if (mga_verify_iload(dev_priv, iload->dstorg, iload->length)) {
1005                 mga_freelist_put(dev, buf);
1006                 return -EINVAL;
1007         }
1008
1009         WRAP_TEST_WITH_RETURN(dev_priv);
1010
1011         mga_dma_dispatch_iload(dev, buf, iload->dstorg, iload->length);
1012
1013         /* Make sure we restore the 3D state next time.
1014          */
1015         dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
1016
1017         return 0;
1018 }
1019
1020 static int mga_dma_blit(struct drm_device *dev, void *data, struct drm_file *file_priv)
1021 {
1022         drm_mga_private_t *dev_priv = dev->dev_private;
1023         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
1024         drm_mga_blit_t *blit = data;
1025         DRM_DEBUG("\n");
1026
1027         LOCK_TEST_WITH_RETURN(dev, file_priv);
1028
1029         if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
1030                 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
1031
1032         if (mga_verify_blit(dev_priv, blit->srcorg, blit->dstorg))
1033                 return -EINVAL;
1034
1035         WRAP_TEST_WITH_RETURN(dev_priv);
1036
1037         mga_dma_dispatch_blit(dev, blit);
1038
1039         /* Make sure we restore the 3D state next time.
1040          */
1041         dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
1042
1043         return 0;
1044 }
1045
1046 static int mga_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv)
1047 {
1048         drm_mga_private_t *dev_priv = dev->dev_private;
1049         drm_mga_getparam_t *param = data;
1050         int value;
1051
1052         if (!dev_priv) {
1053                 DRM_ERROR("called with no initialization\n");
1054                 return -EINVAL;
1055         }
1056
1057         DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
1058
1059         switch (param->param) {
1060         case MGA_PARAM_IRQ_NR:
1061                 value = dev->irq;
1062                 break;
1063         case MGA_PARAM_CARD_TYPE:
1064                 value = dev_priv->chipset;
1065                 break;
1066         default:
1067                 return -EINVAL;
1068         }
1069
1070         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
1071                 DRM_ERROR("copy_to_user\n");
1072                 return -EFAULT;
1073         }
1074
1075         return 0;
1076 }
1077
1078 static int mga_set_fence(struct drm_device *dev, void *data, struct drm_file *file_priv)
1079 {
1080         drm_mga_private_t *dev_priv = dev->dev_private;
1081         u32 *fence = data;
1082         DMA_LOCALS;
1083
1084         if (!dev_priv) {
1085                 DRM_ERROR("called with no initialization\n");
1086                 return -EINVAL;
1087         }
1088
1089         DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
1090
1091         /* I would normal do this assignment in the declaration of fence,
1092          * but dev_priv may be NULL.
1093          */
1094
1095         *fence = dev_priv->next_fence_to_post;
1096         dev_priv->next_fence_to_post++;
1097
1098         BEGIN_DMA(1);
1099         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
1100                   MGA_DMAPAD, 0x00000000,
1101                   MGA_DMAPAD, 0x00000000,
1102                   MGA_SOFTRAP, 0x00000000);
1103         ADVANCE_DMA();
1104
1105         return 0;
1106 }
1107
1108 static int mga_wait_fence(struct drm_device *dev, void *data, struct drm_file *file_priv)
1109 {
1110         drm_mga_private_t *dev_priv = dev->dev_private;
1111         u32 *fence = data;
1112
1113         if (!dev_priv) {
1114                 DRM_ERROR("called with no initialization\n");
1115                 return -EINVAL;
1116         }
1117
1118         DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
1119
1120         mga_driver_fence_wait(dev, fence);
1121
1122         return 0;
1123 }
1124
1125 struct drm_ioctl_desc mga_ioctls[] = {
1126         DRM_IOCTL_DEF(DRM_MGA_INIT, mga_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1127         DRM_IOCTL_DEF(DRM_MGA_FLUSH, mga_dma_flush, DRM_AUTH),
1128         DRM_IOCTL_DEF(DRM_MGA_RESET, mga_dma_reset, DRM_AUTH),
1129         DRM_IOCTL_DEF(DRM_MGA_SWAP, mga_dma_swap, DRM_AUTH),
1130         DRM_IOCTL_DEF(DRM_MGA_CLEAR, mga_dma_clear, DRM_AUTH),
1131         DRM_IOCTL_DEF(DRM_MGA_VERTEX, mga_dma_vertex, DRM_AUTH),
1132         DRM_IOCTL_DEF(DRM_MGA_INDICES, mga_dma_indices, DRM_AUTH),
1133         DRM_IOCTL_DEF(DRM_MGA_ILOAD, mga_dma_iload, DRM_AUTH),
1134         DRM_IOCTL_DEF(DRM_MGA_BLIT, mga_dma_blit, DRM_AUTH),
1135         DRM_IOCTL_DEF(DRM_MGA_GETPARAM, mga_getparam, DRM_AUTH),
1136         DRM_IOCTL_DEF(DRM_MGA_SET_FENCE, mga_set_fence, DRM_AUTH),
1137         DRM_IOCTL_DEF(DRM_MGA_WAIT_FENCE, mga_wait_fence, DRM_AUTH),
1138         DRM_IOCTL_DEF(DRM_MGA_DMA_BOOTSTRAP, mga_dma_bootstrap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1139
1140 };
1141
1142 int mga_max_ioctl = DRM_ARRAY_SIZE(mga_ioctls);