sys/dev/drm2/i915/i915_suspend.c

   1 /*
   2  *
   3  * Copyright 2008 (c) Intel Corporation
   4  *   Jesse Barnes <jbarnes@virtuousgeek.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  */
  26
  27 #include <sys/cdefs.h>
  28 __FBSDID("$FreeBSD$");
  29
  30 #include <dev/drm2/drmP.h>
  31 #include <dev/drm2/drm.h>
  32 #include <dev/drm2/i915/i915_drm.h>
  33 #include <dev/drm2/i915/intel_drv.h>
  34
  35 static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
  36 {
  37         struct drm_i915_private *dev_priv = dev->dev_private;
  38         u32     dpll_reg;
  39
  40         /* On IVB, 3rd pipe shares PLL with another one */
  41         if (pipe > 1)
  42                 return false;
  43
  44         if (HAS_PCH_SPLIT(dev))
  45                 dpll_reg = PCH_DPLL(pipe);
  46         else
  47                 dpll_reg = (pipe == PIPE_A) ? _DPLL_A : _DPLL_B;
  48
  49         return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE);
  50 }
  51
  52 static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
  53 {
  54         struct drm_i915_private *dev_priv = dev->dev_private;
  55         unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
  56         u32 *array;
  57         int i;
  58
  59         if (!i915_pipe_enabled(dev, pipe))
  60                 return;
  61
  62         if (HAS_PCH_SPLIT(dev))
  63                 reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
  64
  65         if (pipe == PIPE_A)
  66                 array = dev_priv->save_palette_a;
  67         else
  68                 array = dev_priv->save_palette_b;
  69
  70         for (i = 0; i < 256; i++)
  71                 array[i] = I915_READ(reg + (i << 2));
  72 }
  73
  74 static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
  75 {
  76         struct drm_i915_private *dev_priv = dev->dev_private;
  77         unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
  78         u32 *array;
  79         int i;
  80
  81         if (!i915_pipe_enabled(dev, pipe))
  82                 return;
  83
  84         if (HAS_PCH_SPLIT(dev))
  85                 reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
  86
  87         if (pipe == PIPE_A)
  88                 array = dev_priv->save_palette_a;
  89         else
  90                 array = dev_priv->save_palette_b;
  91
  92         for (i = 0; i < 256; i++)
  93                 I915_WRITE(reg + (i << 2), array[i]);
  94 }
  95
  96 static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg)
  97 {
  98         struct drm_i915_private *dev_priv = dev->dev_private;
  99
 100         I915_WRITE8(index_port, reg);
 101         return I915_READ8(data_port);
 102 }
 103
 104 static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable)
 105 {
 106         struct drm_i915_private *dev_priv = dev->dev_private;
 107
 108         I915_READ8(st01);
 109         I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
 110         return I915_READ8(VGA_AR_DATA_READ);
 111 }
 112
 113 static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable)
 114 {
 115         struct drm_i915_private *dev_priv = dev->dev_private;
 116
 117         I915_READ8(st01);
 118         I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
 119         I915_WRITE8(VGA_AR_DATA_WRITE, val);
 120 }
 121
 122 static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val)
 123 {
 124         struct drm_i915_private *dev_priv = dev->dev_private;
 125
 126         I915_WRITE8(index_port, reg);
 127         I915_WRITE8(data_port, val);
 128 }
 129
 130 static void i915_save_vga(struct drm_device *dev)
 131 {
 132         struct drm_i915_private *dev_priv = dev->dev_private;
 133         int i;
 134         u16 cr_index, cr_data, st01;
 135
 136         /* VGA color palette registers */
 137         dev_priv->saveDACMASK = I915_READ8(VGA_DACMASK);
 138
 139         /* MSR bits */
 140         dev_priv->saveMSR = I915_READ8(VGA_MSR_READ);
 141         if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
 142                 cr_index = VGA_CR_INDEX_CGA;
 143                 cr_data = VGA_CR_DATA_CGA;
 144                 st01 = VGA_ST01_CGA;
 145         } else {
 146                 cr_index = VGA_CR_INDEX_MDA;
 147                 cr_data = VGA_CR_DATA_MDA;
 148                 st01 = VGA_ST01_MDA;
 149         }
 150
 151         /* CRT controller regs */
 152         i915_write_indexed(dev, cr_index, cr_data, 0x11,
 153                            i915_read_indexed(dev, cr_index, cr_data, 0x11) &
 154                            (~0x80));
 155         for (i = 0; i <= 0x24; i++)
 156                 dev_priv->saveCR[i] =
 157                         i915_read_indexed(dev, cr_index, cr_data, i);
 158         /* Make sure we don't turn off CR group 0 writes */
 159         dev_priv->saveCR[0x11] &= ~0x80;
 160
 161         /* Attribute controller registers */
 162         I915_READ8(st01);
 163         dev_priv->saveAR_INDEX = I915_READ8(VGA_AR_INDEX);
 164         for (i = 0; i <= 0x14; i++)
 165                 dev_priv->saveAR[i] = i915_read_ar(dev, st01, i, 0);
 166         I915_READ8(st01);
 167         I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX);
 168         I915_READ8(st01);
 169
 170         /* Graphics controller registers */
 171         for (i = 0; i < 9; i++)
 172                 dev_priv->saveGR[i] =
 173                         i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i);
 174
 175         dev_priv->saveGR[0x10] =
 176                 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10);
 177         dev_priv->saveGR[0x11] =
 178                 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11);
 179         dev_priv->saveGR[0x18] =
 180                 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18);
 181
 182         /* Sequencer registers */
 183         for (i = 0; i < 8; i++)
 184                 dev_priv->saveSR[i] =
 185                         i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i);
 186 }
 187
 188 static void i915_restore_vga(struct drm_device *dev)
 189 {
 190         struct drm_i915_private *dev_priv = dev->dev_private;
 191         int i;
 192         u16 cr_index, cr_data, st01;
 193
 194         /* MSR bits */
 195         I915_WRITE8(VGA_MSR_WRITE, dev_priv->saveMSR);
 196         if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
 197                 cr_index = VGA_CR_INDEX_CGA;
 198                 cr_data = VGA_CR_DATA_CGA;
 199                 st01 = VGA_ST01_CGA;
 200         } else {
 201                 cr_index = VGA_CR_INDEX_MDA;
 202                 cr_data = VGA_CR_DATA_MDA;
 203                 st01 = VGA_ST01_MDA;
 204         }
 205
 206         /* Sequencer registers, don't write SR07 */
 207         for (i = 0; i < 7; i++)
 208                 i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i,
 209                                    dev_priv->saveSR[i]);
 210
 211         /* CRT controller regs */
 212         /* Enable CR group 0 writes */
 213         i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
 214         for (i = 0; i <= 0x24; i++)
 215                 i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->saveCR[i]);
 216
 217         /* Graphics controller regs */
 218         for (i = 0; i < 9; i++)
 219                 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i,
 220                                    dev_priv->saveGR[i]);
 221
 222         i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10,
 223                            dev_priv->saveGR[0x10]);
 224         i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11,
 225                            dev_priv->saveGR[0x11]);
 226         i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18,
 227                            dev_priv->saveGR[0x18]);
 228
 229         /* Attribute controller registers */
 230         I915_READ8(st01); /* switch back to index mode */
 231         for (i = 0; i <= 0x14; i++)
 232                 i915_write_ar(dev, st01, i, dev_priv->saveAR[i], 0);
 233         I915_READ8(st01); /* switch back to index mode */
 234         I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX | 0x20);
 235         I915_READ8(st01);
 236
 237         /* VGA color palette registers */
 238         I915_WRITE8(VGA_DACMASK, dev_priv->saveDACMASK);
 239 }
 240
 241 static void i915_save_modeset_reg(struct drm_device *dev)
 242 {
 243         struct drm_i915_private *dev_priv = dev->dev_private;
 244         int i;
 245
 246         if (drm_core_check_feature(dev, DRIVER_MODESET))
 247                 return;
 248
 249         /* Cursor state */
 250         dev_priv->saveCURACNTR = I915_READ(_CURACNTR);
 251         dev_priv->saveCURAPOS = I915_READ(_CURAPOS);
 252         dev_priv->saveCURABASE = I915_READ(_CURABASE);
 253         dev_priv->saveCURBCNTR = I915_READ(_CURBCNTR);
 254         dev_priv->saveCURBPOS = I915_READ(_CURBPOS);
 255         dev_priv->saveCURBBASE = I915_READ(_CURBBASE);
 256         if (IS_GEN2(dev))
 257                 dev_priv->saveCURSIZE = I915_READ(CURSIZE);
 258
 259         if (HAS_PCH_SPLIT(dev)) {
 260                 dev_priv->savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL);
 261                 dev_priv->saveDISP_ARB_CTL = I915_READ(DISP_ARB_CTL);
 262         }
 263
 264         /* Pipe & plane A info */
 265         dev_priv->savePIPEACONF = I915_READ(_PIPEACONF);
 266         dev_priv->savePIPEASRC = I915_READ(_PIPEASRC);
 267         if (HAS_PCH_SPLIT(dev)) {
 268                 dev_priv->saveFPA0 = I915_READ(_PCH_FPA0);
 269                 dev_priv->saveFPA1 = I915_READ(_PCH_FPA1);
 270                 dev_priv->saveDPLL_A = I915_READ(_PCH_DPLL_A);
 271         } else {
 272                 dev_priv->saveFPA0 = I915_READ(_FPA0);
 273                 dev_priv->saveFPA1 = I915_READ(_FPA1);
 274                 dev_priv->saveDPLL_A = I915_READ(_DPLL_A);
 275         }
 276         if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
 277                 dev_priv->saveDPLL_A_MD = I915_READ(_DPLL_A_MD);
 278         dev_priv->saveHTOTAL_A = I915_READ(_HTOTAL_A);
 279         dev_priv->saveHBLANK_A = I915_READ(_HBLANK_A);
 280         dev_priv->saveHSYNC_A = I915_READ(_HSYNC_A);
 281         dev_priv->saveVTOTAL_A = I915_READ(_VTOTAL_A);
 282         dev_priv->saveVBLANK_A = I915_READ(_VBLANK_A);
 283         dev_priv->saveVSYNC_A = I915_READ(_VSYNC_A);
 284         if (!HAS_PCH_SPLIT(dev))
 285                 dev_priv->saveBCLRPAT_A = I915_READ(_BCLRPAT_A);
 286
 287         if (HAS_PCH_SPLIT(dev)) {
 288                 dev_priv->savePIPEA_DATA_M1 = I915_READ(_PIPEA_DATA_M1);
 289                 dev_priv->savePIPEA_DATA_N1 = I915_READ(_PIPEA_DATA_N1);
 290                 dev_priv->savePIPEA_LINK_M1 = I915_READ(_PIPEA_LINK_M1);
 291                 dev_priv->savePIPEA_LINK_N1 = I915_READ(_PIPEA_LINK_N1);
 292
 293                 dev_priv->saveFDI_TXA_CTL = I915_READ(_FDI_TXA_CTL);
 294                 dev_priv->saveFDI_RXA_CTL = I915_READ(_FDI_RXA_CTL);
 295
 296                 dev_priv->savePFA_CTL_1 = I915_READ(_PFA_CTL_1);
 297                 dev_priv->savePFA_WIN_SZ = I915_READ(_PFA_WIN_SZ);
 298                 dev_priv->savePFA_WIN_POS = I915_READ(_PFA_WIN_POS);
 299
 300                 dev_priv->saveTRANSACONF = I915_READ(_TRANSACONF);
 301                 dev_priv->saveTRANS_HTOTAL_A = I915_READ(_TRANS_HTOTAL_A);
 302                 dev_priv->saveTRANS_HBLANK_A = I915_READ(_TRANS_HBLANK_A);
 303                 dev_priv->saveTRANS_HSYNC_A = I915_READ(_TRANS_HSYNC_A);
 304                 dev_priv->saveTRANS_VTOTAL_A = I915_READ(_TRANS_VTOTAL_A);
 305                 dev_priv->saveTRANS_VBLANK_A = I915_READ(_TRANS_VBLANK_A);
 306                 dev_priv->saveTRANS_VSYNC_A = I915_READ(_TRANS_VSYNC_A);
 307         }
 308
 309         dev_priv->saveDSPACNTR = I915_READ(_DSPACNTR);
 310         dev_priv->saveDSPASTRIDE = I915_READ(_DSPASTRIDE);
 311         dev_priv->saveDSPASIZE = I915_READ(_DSPASIZE);
 312         dev_priv->saveDSPAPOS = I915_READ(_DSPAPOS);
 313         dev_priv->saveDSPAADDR = I915_READ(_DSPAADDR);
 314         if (INTEL_INFO(dev)->gen >= 4) {
 315                 dev_priv->saveDSPASURF = I915_READ(_DSPASURF);
 316                 dev_priv->saveDSPATILEOFF = I915_READ(_DSPATILEOFF);
 317         }
 318         i915_save_palette(dev, PIPE_A);
 319         dev_priv->savePIPEASTAT = I915_READ(_PIPEASTAT);
 320
 321         /* Pipe & plane B info */
 322         dev_priv->savePIPEBCONF = I915_READ(_PIPEBCONF);
 323         dev_priv->savePIPEBSRC = I915_READ(_PIPEBSRC);
 324         if (HAS_PCH_SPLIT(dev)) {
 325                 dev_priv->saveFPB0 = I915_READ(_PCH_FPB0);
 326                 dev_priv->saveFPB1 = I915_READ(_PCH_FPB1);
 327                 dev_priv->saveDPLL_B = I915_READ(_PCH_DPLL_B);
 328         } else {
 329                 dev_priv->saveFPB0 = I915_READ(_FPB0);
 330                 dev_priv->saveFPB1 = I915_READ(_FPB1);
 331                 dev_priv->saveDPLL_B = I915_READ(_DPLL_B);
 332         }
 333         if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
 334                 dev_priv->saveDPLL_B_MD = I915_READ(_DPLL_B_MD);
 335         dev_priv->saveHTOTAL_B = I915_READ(_HTOTAL_B);
 336         dev_priv->saveHBLANK_B = I915_READ(_HBLANK_B);
 337         dev_priv->saveHSYNC_B = I915_READ(_HSYNC_B);
 338         dev_priv->saveVTOTAL_B = I915_READ(_VTOTAL_B);
 339         dev_priv->saveVBLANK_B = I915_READ(_VBLANK_B);
 340         dev_priv->saveVSYNC_B = I915_READ(_VSYNC_B);
 341         if (!HAS_PCH_SPLIT(dev))
 342                 dev_priv->saveBCLRPAT_B = I915_READ(_BCLRPAT_B);
 343
 344         if (HAS_PCH_SPLIT(dev)) {
 345                 dev_priv->savePIPEB_DATA_M1 = I915_READ(_PIPEB_DATA_M1);
 346                 dev_priv->savePIPEB_DATA_N1 = I915_READ(_PIPEB_DATA_N1);
 347                 dev_priv->savePIPEB_LINK_M1 = I915_READ(_PIPEB_LINK_M1);
 348                 dev_priv->savePIPEB_LINK_N1 = I915_READ(_PIPEB_LINK_N1);
 349
 350                 dev_priv->saveFDI_TXB_CTL = I915_READ(_FDI_TXB_CTL);
 351                 dev_priv->saveFDI_RXB_CTL = I915_READ(_FDI_RXB_CTL);
 352
 353                 dev_priv->savePFB_CTL_1 = I915_READ(_PFB_CTL_1);
 354                 dev_priv->savePFB_WIN_SZ = I915_READ(_PFB_WIN_SZ);
 355                 dev_priv->savePFB_WIN_POS = I915_READ(_PFB_WIN_POS);
 356
 357                 dev_priv->saveTRANSBCONF = I915_READ(_TRANSBCONF);
 358                 dev_priv->saveTRANS_HTOTAL_B = I915_READ(_TRANS_HTOTAL_B);
 359                 dev_priv->saveTRANS_HBLANK_B = I915_READ(_TRANS_HBLANK_B);
 360                 dev_priv->saveTRANS_HSYNC_B = I915_READ(_TRANS_HSYNC_B);
 361                 dev_priv->saveTRANS_VTOTAL_B = I915_READ(_TRANS_VTOTAL_B);
 362                 dev_priv->saveTRANS_VBLANK_B = I915_READ(_TRANS_VBLANK_B);
 363                 dev_priv->saveTRANS_VSYNC_B = I915_READ(_TRANS_VSYNC_B);
 364         }
 365
 366         dev_priv->saveDSPBCNTR = I915_READ(_DSPBCNTR);
 367         dev_priv->saveDSPBSTRIDE = I915_READ(_DSPBSTRIDE);
 368         dev_priv->saveDSPBSIZE = I915_READ(_DSPBSIZE);
 369         dev_priv->saveDSPBPOS = I915_READ(_DSPBPOS);
 370         dev_priv->saveDSPBADDR = I915_READ(_DSPBADDR);
 371         if (INTEL_INFO(dev)->gen >= 4) {
 372                 dev_priv->saveDSPBSURF = I915_READ(_DSPBSURF);
 373                 dev_priv->saveDSPBTILEOFF = I915_READ(_DSPBTILEOFF);
 374         }
 375         i915_save_palette(dev, PIPE_B);
 376         dev_priv->savePIPEBSTAT = I915_READ(_PIPEBSTAT);
 377
 378         /* Fences */
 379         switch (INTEL_INFO(dev)->gen) {
 380         case 7:
 381         case 6:
 382                 for (i = 0; i < 16; i++)
 383                         dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
 384                 break;
 385         case 5:
 386         case 4:
 387                 for (i = 0; i < 16; i++)
 388                         dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
 389                 break;
 390         case 3:
 391                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
 392                         for (i = 0; i < 8; i++)
 393                                 dev_priv->saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
 394         case 2:
 395                 for (i = 0; i < 8; i++)
 396                         dev_priv->saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
 397                 break;
 398         }
 399
 400         return;
 401 }
 402
 403 static void i915_restore_modeset_reg(struct drm_device *dev)
 404 {
 405         struct drm_i915_private *dev_priv = dev->dev_private;
 406         int dpll_a_reg, fpa0_reg, fpa1_reg;
 407         int dpll_b_reg, fpb0_reg, fpb1_reg;
 408         int i;
 409
 410         if (drm_core_check_feature(dev, DRIVER_MODESET))
 411                 return;
 412
 413         /* Fences */
 414         switch (INTEL_INFO(dev)->gen) {
 415         case 7:
 416         case 6:
 417                 for (i = 0; i < 16; i++)
 418                         I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), dev_priv->saveFENCE[i]);
 419                 break;
 420         case 5:
 421         case 4:
 422                 for (i = 0; i < 16; i++)
 423                         I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->saveFENCE[i]);
 424                 break;
 425         case 3:
 426         case 2:
 427                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
 428                         for (i = 0; i < 8; i++)
 429                                 I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->saveFENCE[i+8]);
 430                 for (i = 0; i < 8; i++)
 431                         I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->saveFENCE[i]);
 432                 break;
 433         }
 434
 435
 436         if (HAS_PCH_SPLIT(dev)) {
 437                 dpll_a_reg = _PCH_DPLL_A;
 438                 dpll_b_reg = _PCH_DPLL_B;
 439                 fpa0_reg = _PCH_FPA0;
 440                 fpb0_reg = _PCH_FPB0;
 441                 fpa1_reg = _PCH_FPA1;
 442                 fpb1_reg = _PCH_FPB1;
 443         } else {
 444                 dpll_a_reg = _DPLL_A;
 445                 dpll_b_reg = _DPLL_B;
 446                 fpa0_reg = _FPA0;
 447                 fpb0_reg = _FPB0;
 448                 fpa1_reg = _FPA1;
 449                 fpb1_reg = _FPB1;
 450         }
 451
 452         if (HAS_PCH_SPLIT(dev)) {
 453                 I915_WRITE(PCH_DREF_CONTROL, dev_priv->savePCH_DREF_CONTROL);
 454                 I915_WRITE(DISP_ARB_CTL, dev_priv->saveDISP_ARB_CTL);
 455         }
 456
 457         /* Pipe & plane A info */
 458         /* Prime the clock */
 459         if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
 460                 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A &
 461                            ~DPLL_VCO_ENABLE);
 462                 POSTING_READ(dpll_a_reg);
 463                 DRM_UDELAY(150);
 464         }
 465         I915_WRITE(fpa0_reg, dev_priv->saveFPA0);
 466         I915_WRITE(fpa1_reg, dev_priv->saveFPA1);
 467         /* Actually enable it */
 468         I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A);
 469         POSTING_READ(dpll_a_reg);
 470         DRM_UDELAY(150);
 471         if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
 472                 I915_WRITE(_DPLL_A_MD, dev_priv->saveDPLL_A_MD);
 473                 POSTING_READ(_DPLL_A_MD);
 474         }
 475         DRM_UDELAY(150);
 476
 477         /* Restore mode */
 478         I915_WRITE(_HTOTAL_A, dev_priv->saveHTOTAL_A);
 479         I915_WRITE(_HBLANK_A, dev_priv->saveHBLANK_A);
 480         I915_WRITE(_HSYNC_A, dev_priv->saveHSYNC_A);
 481         I915_WRITE(_VTOTAL_A, dev_priv->saveVTOTAL_A);
 482         I915_WRITE(_VBLANK_A, dev_priv->saveVBLANK_A);
 483         I915_WRITE(_VSYNC_A, dev_priv->saveVSYNC_A);
 484         if (!HAS_PCH_SPLIT(dev))
 485                 I915_WRITE(_BCLRPAT_A, dev_priv->saveBCLRPAT_A);
 486
 487         if (HAS_PCH_SPLIT(dev)) {
 488                 I915_WRITE(_PIPEA_DATA_M1, dev_priv->savePIPEA_DATA_M1);
 489                 I915_WRITE(_PIPEA_DATA_N1, dev_priv->savePIPEA_DATA_N1);
 490                 I915_WRITE(_PIPEA_LINK_M1, dev_priv->savePIPEA_LINK_M1);
 491                 I915_WRITE(_PIPEA_LINK_N1, dev_priv->savePIPEA_LINK_N1);
 492
 493                 I915_WRITE(_FDI_RXA_CTL, dev_priv->saveFDI_RXA_CTL);
 494                 I915_WRITE(_FDI_TXA_CTL, dev_priv->saveFDI_TXA_CTL);
 495
 496                 I915_WRITE(_PFA_CTL_1, dev_priv->savePFA_CTL_1);
 497                 I915_WRITE(_PFA_WIN_SZ, dev_priv->savePFA_WIN_SZ);
 498                 I915_WRITE(_PFA_WIN_POS, dev_priv->savePFA_WIN_POS);
 499
 500                 I915_WRITE(_TRANSACONF, dev_priv->saveTRANSACONF);
 501                 I915_WRITE(_TRANS_HTOTAL_A, dev_priv->saveTRANS_HTOTAL_A);
 502                 I915_WRITE(_TRANS_HBLANK_A, dev_priv->saveTRANS_HBLANK_A);
 503                 I915_WRITE(_TRANS_HSYNC_A, dev_priv->saveTRANS_HSYNC_A);
 504                 I915_WRITE(_TRANS_VTOTAL_A, dev_priv->saveTRANS_VTOTAL_A);
 505                 I915_WRITE(_TRANS_VBLANK_A, dev_priv->saveTRANS_VBLANK_A);
 506                 I915_WRITE(_TRANS_VSYNC_A, dev_priv->saveTRANS_VSYNC_A);
 507         }
 508
 509         /* Restore plane info */
 510         I915_WRITE(_DSPASIZE, dev_priv->saveDSPASIZE);
 511         I915_WRITE(_DSPAPOS, dev_priv->saveDSPAPOS);
 512         I915_WRITE(_PIPEASRC, dev_priv->savePIPEASRC);
 513         I915_WRITE(_DSPAADDR, dev_priv->saveDSPAADDR);
 514         I915_WRITE(_DSPASTRIDE, dev_priv->saveDSPASTRIDE);
 515         if (INTEL_INFO(dev)->gen >= 4) {
 516                 I915_WRITE(_DSPASURF, dev_priv->saveDSPASURF);
 517                 I915_WRITE(_DSPATILEOFF, dev_priv->saveDSPATILEOFF);
 518         }
 519
 520         I915_WRITE(_PIPEACONF, dev_priv->savePIPEACONF);
 521
 522         i915_restore_palette(dev, PIPE_A);
 523         /* Enable the plane */
 524         I915_WRITE(_DSPACNTR, dev_priv->saveDSPACNTR);
 525         I915_WRITE(_DSPAADDR, I915_READ(_DSPAADDR));
 526
 527         /* Pipe & plane B info */
 528         if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
 529                 I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B &
 530                            ~DPLL_VCO_ENABLE);
 531                 POSTING_READ(dpll_b_reg);
 532                 DRM_UDELAY(150);
 533         }
 534         I915_WRITE(fpb0_reg, dev_priv->saveFPB0);
 535         I915_WRITE(fpb1_reg, dev_priv->saveFPB1);
 536         /* Actually enable it */
 537         I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B);
 538         POSTING_READ(dpll_b_reg);
 539         DRM_UDELAY(150);
 540         if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
 541                 I915_WRITE(_DPLL_B_MD, dev_priv->saveDPLL_B_MD);
 542                 POSTING_READ(_DPLL_B_MD);
 543         }
 544         DRM_UDELAY(150);
 545
 546         /* Restore mode */
 547         I915_WRITE(_HTOTAL_B, dev_priv->saveHTOTAL_B);
 548         I915_WRITE(_HBLANK_B, dev_priv->saveHBLANK_B);
 549         I915_WRITE(_HSYNC_B, dev_priv->saveHSYNC_B);
 550         I915_WRITE(_VTOTAL_B, dev_priv->saveVTOTAL_B);
 551         I915_WRITE(_VBLANK_B, dev_priv->saveVBLANK_B);
 552         I915_WRITE(_VSYNC_B, dev_priv->saveVSYNC_B);
 553         if (!HAS_PCH_SPLIT(dev))
 554                 I915_WRITE(_BCLRPAT_B, dev_priv->saveBCLRPAT_B);
 555
 556         if (HAS_PCH_SPLIT(dev)) {
 557                 I915_WRITE(_PIPEB_DATA_M1, dev_priv->savePIPEB_DATA_M1);
 558                 I915_WRITE(_PIPEB_DATA_N1, dev_priv->savePIPEB_DATA_N1);
 559                 I915_WRITE(_PIPEB_LINK_M1, dev_priv->savePIPEB_LINK_M1);
 560                 I915_WRITE(_PIPEB_LINK_N1, dev_priv->savePIPEB_LINK_N1);
 561
 562                 I915_WRITE(_FDI_RXB_CTL, dev_priv->saveFDI_RXB_CTL);
 563                 I915_WRITE(_FDI_TXB_CTL, dev_priv->saveFDI_TXB_CTL);
 564
 565                 I915_WRITE(_PFB_CTL_1, dev_priv->savePFB_CTL_1);
 566                 I915_WRITE(_PFB_WIN_SZ, dev_priv->savePFB_WIN_SZ);
 567                 I915_WRITE(_PFB_WIN_POS, dev_priv->savePFB_WIN_POS);
 568
 569                 I915_WRITE(_TRANSBCONF, dev_priv->saveTRANSBCONF);
 570                 I915_WRITE(_TRANS_HTOTAL_B, dev_priv->saveTRANS_HTOTAL_B);
 571                 I915_WRITE(_TRANS_HBLANK_B, dev_priv->saveTRANS_HBLANK_B);
 572                 I915_WRITE(_TRANS_HSYNC_B, dev_priv->saveTRANS_HSYNC_B);
 573                 I915_WRITE(_TRANS_VTOTAL_B, dev_priv->saveTRANS_VTOTAL_B);
 574                 I915_WRITE(_TRANS_VBLANK_B, dev_priv->saveTRANS_VBLANK_B);
 575                 I915_WRITE(_TRANS_VSYNC_B, dev_priv->saveTRANS_VSYNC_B);
 576         }
 577
 578         /* Restore plane info */
 579         I915_WRITE(_DSPBSIZE, dev_priv->saveDSPBSIZE);
 580         I915_WRITE(_DSPBPOS, dev_priv->saveDSPBPOS);
 581         I915_WRITE(_PIPEBSRC, dev_priv->savePIPEBSRC);
 582         I915_WRITE(_DSPBADDR, dev_priv->saveDSPBADDR);
 583         I915_WRITE(_DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
 584         if (INTEL_INFO(dev)->gen >= 4) {
 585                 I915_WRITE(_DSPBSURF, dev_priv->saveDSPBSURF);
 586                 I915_WRITE(_DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
 587         }
 588
 589         I915_WRITE(_PIPEBCONF, dev_priv->savePIPEBCONF);
 590
 591         i915_restore_palette(dev, PIPE_B);
 592         /* Enable the plane */
 593         I915_WRITE(_DSPBCNTR, dev_priv->saveDSPBCNTR);
 594         I915_WRITE(_DSPBADDR, I915_READ(_DSPBADDR));
 595
 596         /* Cursor state */
 597         I915_WRITE(_CURAPOS, dev_priv->saveCURAPOS);
 598         I915_WRITE(_CURACNTR, dev_priv->saveCURACNTR);
 599         I915_WRITE(_CURABASE, dev_priv->saveCURABASE);
 600         I915_WRITE(_CURBPOS, dev_priv->saveCURBPOS);
 601         I915_WRITE(_CURBCNTR, dev_priv->saveCURBCNTR);
 602         I915_WRITE(_CURBBASE, dev_priv->saveCURBBASE);
 603         if (IS_GEN2(dev))
 604                 I915_WRITE(CURSIZE, dev_priv->saveCURSIZE);
 605
 606         return;
 607 }
 608
 609 static void i915_save_display(struct drm_device *dev)
 610 {
 611         struct drm_i915_private *dev_priv = dev->dev_private;
 612
 613         /* Display arbitration control */
 614         dev_priv->saveDSPARB = I915_READ(DSPARB);
 615
 616         /* This is only meaningful in non-KMS mode */
 617         /* Don't save them in KMS mode */
 618         i915_save_modeset_reg(dev);
 619
 620         /* CRT state */
 621         if (HAS_PCH_SPLIT(dev)) {
 622                 dev_priv->saveADPA = I915_READ(PCH_ADPA);
 623         } else {
 624                 dev_priv->saveADPA = I915_READ(ADPA);
 625         }
 626
 627         /* LVDS state */
 628         if (HAS_PCH_SPLIT(dev)) {
 629                 dev_priv->savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
 630                 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
 631                 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
 632                 dev_priv->saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
 633                 dev_priv->saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
 634                 dev_priv->saveLVDS = I915_READ(PCH_LVDS);
 635         } else {
 636                 dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
 637                 dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
 638                 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
 639                 dev_priv->saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
 640                 if (INTEL_INFO(dev)->gen >= 4)
 641                         dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
 642                 if (IS_MOBILE(dev) && !IS_I830(dev))
 643                         dev_priv->saveLVDS = I915_READ(LVDS);
 644         }
 645
 646         if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
 647                 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
 648
 649         if (HAS_PCH_SPLIT(dev)) {
 650                 dev_priv->savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
 651                 dev_priv->savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
 652                 dev_priv->savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
 653         } else {
 654                 dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
 655                 dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
 656                 dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);
 657         }
 658
 659         /* Display Port state */
 660         if (SUPPORTS_INTEGRATED_DP(dev)) {
 661                 dev_priv->saveDP_B = I915_READ(DP_B);
 662                 dev_priv->saveDP_C = I915_READ(DP_C);
 663                 dev_priv->saveDP_D = I915_READ(DP_D);
 664                 dev_priv->savePIPEA_GMCH_DATA_M = I915_READ(_PIPEA_GMCH_DATA_M);
 665                 dev_priv->savePIPEB_GMCH_DATA_M = I915_READ(_PIPEB_GMCH_DATA_M);
 666                 dev_priv->savePIPEA_GMCH_DATA_N = I915_READ(_PIPEA_GMCH_DATA_N);
 667                 dev_priv->savePIPEB_GMCH_DATA_N = I915_READ(_PIPEB_GMCH_DATA_N);
 668                 dev_priv->savePIPEA_DP_LINK_M = I915_READ(_PIPEA_DP_LINK_M);
 669                 dev_priv->savePIPEB_DP_LINK_M = I915_READ(_PIPEB_DP_LINK_M);
 670                 dev_priv->savePIPEA_DP_LINK_N = I915_READ(_PIPEA_DP_LINK_N);
 671                 dev_priv->savePIPEB_DP_LINK_N = I915_READ(_PIPEB_DP_LINK_N);
 672         }
 673         /* FIXME: save TV & SDVO state */
 674
 675         /* Only save FBC state on the platform that supports FBC */
 676         if (I915_HAS_FBC(dev)) {
 677                 if (HAS_PCH_SPLIT(dev)) {
 678                         dev_priv->saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE);
 679                 } else if (IS_GM45(dev)) {
 680                         dev_priv->saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
 681                 } else {
 682                         dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
 683                         dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
 684                         dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
 685                         dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
 686                 }
 687         }
 688
 689         /* VGA state */
 690         dev_priv->saveVGA0 = I915_READ(VGA0);
 691         dev_priv->saveVGA1 = I915_READ(VGA1);
 692         dev_priv->saveVGA_PD = I915_READ(VGA_PD);
 693         if (HAS_PCH_SPLIT(dev))
 694                 dev_priv->saveVGACNTRL = I915_READ(CPU_VGACNTRL);
 695         else
 696                 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
 697
 698         i915_save_vga(dev);
 699 }
 700
 701 static void i915_restore_display(struct drm_device *dev)
 702 {
 703         struct drm_i915_private *dev_priv = dev->dev_private;
 704
 705         /* Display arbitration */
 706         I915_WRITE(DSPARB, dev_priv->saveDSPARB);
 707
 708         /* Display port ratios (must be done before clock is set) */
 709         if (SUPPORTS_INTEGRATED_DP(dev)) {
 710                 I915_WRITE(_PIPEA_GMCH_DATA_M, dev_priv->savePIPEA_GMCH_DATA_M);
 711                 I915_WRITE(_PIPEB_GMCH_DATA_M, dev_priv->savePIPEB_GMCH_DATA_M);
 712                 I915_WRITE(_PIPEA_GMCH_DATA_N, dev_priv->savePIPEA_GMCH_DATA_N);
 713                 I915_WRITE(_PIPEB_GMCH_DATA_N, dev_priv->savePIPEB_GMCH_DATA_N);
 714                 I915_WRITE(_PIPEA_DP_LINK_M, dev_priv->savePIPEA_DP_LINK_M);
 715                 I915_WRITE(_PIPEB_DP_LINK_M, dev_priv->savePIPEB_DP_LINK_M);
 716                 I915_WRITE(_PIPEA_DP_LINK_N, dev_priv->savePIPEA_DP_LINK_N);
 717                 I915_WRITE(_PIPEB_DP_LINK_N, dev_priv->savePIPEB_DP_LINK_N);
 718         }
 719
 720         /* This is only meaningful in non-KMS mode */
 721         /* Don't restore them in KMS mode */
 722         i915_restore_modeset_reg(dev);
 723
 724         /* CRT state */
 725         if (HAS_PCH_SPLIT(dev))
 726                 I915_WRITE(PCH_ADPA, dev_priv->saveADPA);
 727         else
 728                 I915_WRITE(ADPA, dev_priv->saveADPA);
 729
 730         /* LVDS state */
 731         if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
 732                 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
 733
 734         if (HAS_PCH_SPLIT(dev)) {
 735                 I915_WRITE(PCH_LVDS, dev_priv->saveLVDS);
 736         } else if (IS_MOBILE(dev) && !IS_I830(dev))
 737                 I915_WRITE(LVDS, dev_priv->saveLVDS);
 738
 739         if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
 740                 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
 741
 742         if (HAS_PCH_SPLIT(dev)) {
 743                 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->saveBLC_PWM_CTL);
 744                 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->saveBLC_PWM_CTL2);
 745                 I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->saveBLC_CPU_PWM_CTL);
 746                 I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->saveBLC_CPU_PWM_CTL2);
 747                 I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
 748                 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
 749                 I915_WRITE(PCH_PP_DIVISOR, dev_priv->savePP_DIVISOR);
 750                 I915_WRITE(PCH_PP_CONTROL, dev_priv->savePP_CONTROL);
 751                 I915_WRITE(RSTDBYCTL,
 752                            dev_priv->saveMCHBAR_RENDER_STANDBY);
 753         } else {
 754                 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
 755                 I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
 756                 I915_WRITE(BLC_HIST_CTL, dev_priv->saveBLC_HIST_CTL);
 757                 I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
 758                 I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
 759                 I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR);
 760                 I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
 761         }
 762
 763         /* Display Port state */
 764         if (SUPPORTS_INTEGRATED_DP(dev)) {
 765                 I915_WRITE(DP_B, dev_priv->saveDP_B);
 766                 I915_WRITE(DP_C, dev_priv->saveDP_C);
 767                 I915_WRITE(DP_D, dev_priv->saveDP_D);
 768         }
 769         /* FIXME: restore TV & SDVO state */
 770
 771         /* only restore FBC info on the platform that supports FBC*/
 772         intel_disable_fbc(dev);
 773         if (I915_HAS_FBC(dev)) {
 774                 if (HAS_PCH_SPLIT(dev)) {
 775                         I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE);
 776                 } else if (IS_GM45(dev)) {
 777                         I915_WRITE(DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE);
 778                 } else {
 779                         I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
 780                         I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
 781                         I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
 782                         I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
 783                 }
 784         }
 785         /* VGA state */
 786         if (HAS_PCH_SPLIT(dev))
 787                 I915_WRITE(CPU_VGACNTRL, dev_priv->saveVGACNTRL);
 788         else
 789                 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
 790
 791         I915_WRITE(VGA0, dev_priv->saveVGA0);
 792         I915_WRITE(VGA1, dev_priv->saveVGA1);
 793         I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
 794         POSTING_READ(VGA_PD);
 795         DRM_UDELAY(150);
 796
 797         i915_restore_vga(dev);
 798 }
 799
 800 int i915_save_state(struct drm_device *dev)
 801 {
 802         struct drm_i915_private *dev_priv = dev->dev_private;
 803         int i;
 804
 805         dev_priv->saveLBB = pci_read_config(dev->device, LBB, 1);
 806
 807         /* Hardware status page */
 808         dev_priv->saveHWS = I915_READ(HWS_PGA);
 809
 810         i915_save_display(dev);
 811
 812         /* Interrupt state */
 813         if (HAS_PCH_SPLIT(dev)) {
 814                 dev_priv->saveDEIER = I915_READ(DEIER);
 815                 dev_priv->saveDEIMR = I915_READ(DEIMR);
 816                 dev_priv->saveGTIER = I915_READ(GTIER);
 817                 dev_priv->saveGTIMR = I915_READ(GTIMR);
 818                 dev_priv->saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR);
 819                 dev_priv->saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);
 820                 dev_priv->saveMCHBAR_RENDER_STANDBY =
 821                         I915_READ(RSTDBYCTL);
 822                 dev_priv->savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG);
 823         } else {
 824                 dev_priv->saveIER = I915_READ(IER);
 825                 dev_priv->saveIMR = I915_READ(IMR);
 826         }
 827
 828         if (IS_IRONLAKE_M(dev))
 829                 ironlake_disable_drps(dev);
 830         if (INTEL_INFO(dev)->gen >= 6)
 831                 gen6_disable_rps(dev);
 832
 833         /* Cache mode state */
 834         dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
 835
 836         /* Memory Arbitration state */
 837         dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
 838
 839         /* Scratch space */
 840         for (i = 0; i < 16; i++) {
 841                 dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2));
 842                 dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
 843         }
 844         for (i = 0; i < 3; i++)
 845                 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
 846
 847         return 0;
 848 }
 849
 850 int i915_restore_state(struct drm_device *dev)
 851 {
 852         struct drm_i915_private *dev_priv = dev->dev_private;
 853         int i;
 854
 855         pci_write_config(dev->device, LBB, dev_priv->saveLBB, 1);
 856
 857
 858         /* Hardware status page */
 859         I915_WRITE(HWS_PGA, dev_priv->saveHWS);
 860
 861         i915_restore_display(dev);
 862
 863         /* Interrupt state */
 864         if (HAS_PCH_SPLIT(dev)) {
 865                 I915_WRITE(DEIER, dev_priv->saveDEIER);
 866                 I915_WRITE(DEIMR, dev_priv->saveDEIMR);
 867                 I915_WRITE(GTIER, dev_priv->saveGTIER);
 868                 I915_WRITE(GTIMR, dev_priv->saveGTIMR);
 869                 I915_WRITE(_FDI_RXA_IMR, dev_priv->saveFDI_RXA_IMR);
 870                 I915_WRITE(_FDI_RXB_IMR, dev_priv->saveFDI_RXB_IMR);
 871                 I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->savePCH_PORT_HOTPLUG);
 872         } else {
 873                 I915_WRITE(IER, dev_priv->saveIER);
 874                 I915_WRITE(IMR, dev_priv->saveIMR);
 875         }
 876         DRM_UNLOCK(dev);
 877
 878         if (drm_core_check_feature(dev, DRIVER_MODESET))
 879                 intel_init_clock_gating(dev);
 880
 881         if (IS_IRONLAKE_M(dev)) {
 882                 ironlake_enable_drps(dev);
 883                 intel_init_emon(dev);
 884         }
 885
 886         if (INTEL_INFO(dev)->gen >= 6) {
 887                 gen6_enable_rps(dev_priv);
 888                 gen6_update_ring_freq(dev_priv);
 889         }
 890
 891         DRM_LOCK(dev);
 892
 893         /* Cache mode state */
 894         I915_WRITE(CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
 895
 896         /* Memory arbitration state */
 897         I915_WRITE(MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);
 898
 899         for (i = 0; i < 16; i++) {
 900                 I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]);
 901                 I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i]);
 902         }
 903         for (i = 0; i < 3; i++)
 904                 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);
 905
 906         intel_iic_reset(dev);
 907
 908         return 0;
 909 }