sys/dev/drm2/i915/intel_iic.c

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2008,2010 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  *
  25  * Authors:
  26  *      Eric Anholt <eric@anholt.net>
  27  *      Chris Wilson <chris@chris-wilson.co.uk>
  28  *
  29  * Copyright (c) 2011 The FreeBSD Foundation
  30  * All rights reserved.
  31  *
  32  * This software was developed by Konstantin Belousov under sponsorship from
  33  * the FreeBSD Foundation.
  34  *
  35  * Redistribution and use in source and binary forms, with or without
  36  * modification, are permitted provided that the following conditions
  37  * are met:
  38  * 1. Redistributions of source code must retain the above copyright
  39  *    notice, this list of conditions and the following disclaimer.
  40  * 2. Redistributions in binary form must reproduce the above copyright
  41  *    notice, this list of conditions and the following disclaimer in the
  42  *    documentation and/or other materials provided with the distribution.
  43  *
  44  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  45  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  46  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  47  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  48  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  49  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  50  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  51  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  52  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  53  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  54  * SUCH DAMAGE.
  55  */
  56 #include <sys/cdefs.h>
  57 __FBSDID("$FreeBSD$");
  58
  59 #include <dev/drm2/drmP.h>
  60 #include <dev/drm2/drm.h>
  61 #include <dev/drm2/i915/i915_drm.h>
  62 #include <dev/drm2/i915/i915_drv.h>
  63 #include <dev/drm2/i915/intel_drv.h>
  64 #include <dev/iicbus/iic.h>
  65 #include <dev/iicbus/iiconf.h>
  66 #include <dev/iicbus/iicbus.h>
  67 #include "iicbus_if.h"
  68 #include "iicbb_if.h"
  69
  70 static int intel_iic_quirk_xfer(device_t idev, struct iic_msg *msgs, int nmsgs);
  71 static void intel_teardown_gmbus_m(struct drm_device *dev, int m);
  72
  73 /* Intel GPIO access functions */
  74
  75 #define I2C_RISEFALL_TIME 10
  76
  77 struct intel_iic_softc {
  78         struct drm_device *drm_dev;
  79         device_t iic_dev;
  80         bool force_bit_dev;
  81         char name[32];
  82         uint32_t reg;
  83         uint32_t reg0;
  84 };
  85
  86 static void
  87 intel_iic_quirk_set(struct drm_i915_private *dev_priv, bool enable)
  88 {
  89         u32 val;
  90
  91         /* When using bit bashing for I2C, this bit needs to be set to 1 */
  92         if (!IS_PINEVIEW(dev_priv->dev))
  93                 return;
  94
  95         val = I915_READ(DSPCLK_GATE_D);
  96         if (enable)
  97                 val |= DPCUNIT_CLOCK_GATE_DISABLE;
  98         else
  99                 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
 100         I915_WRITE(DSPCLK_GATE_D, val);
 101 }
 102
 103 static u32
 104 intel_iic_get_reserved(device_t idev)
 105 {
 106         struct intel_iic_softc *sc;
 107         struct drm_device *dev;
 108         struct drm_i915_private *dev_priv;
 109         u32 reserved;
 110
 111         sc = device_get_softc(idev);
 112         dev = sc->drm_dev;
 113         dev_priv = dev->dev_private;
 114
 115         if (!IS_I830(dev) && !IS_845G(dev)) {
 116                 reserved = I915_READ_NOTRACE(sc->reg) &
 117                     (GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_PULLUP_DISABLE);
 118         } else {
 119                 reserved = 0;
 120         }
 121
 122         return (reserved);
 123 }
 124
 125 void
 126 intel_iic_reset(struct drm_device *dev)
 127 {
 128         struct drm_i915_private *dev_priv;
 129
 130         dev_priv = dev->dev_private;
 131         if (HAS_PCH_SPLIT(dev))
 132                 I915_WRITE(PCH_GMBUS0, 0);
 133         else
 134                 I915_WRITE(GMBUS0, 0);
 135 }
 136
 137 static int
 138 intel_iicbus_reset(device_t idev, u_char speed, u_char addr, u_char *oldaddr)
 139 {
 140         struct intel_iic_softc *sc;
 141         struct drm_device *dev;
 142
 143         sc = device_get_softc(idev);
 144         dev = sc->drm_dev;
 145
 146         intel_iic_reset(dev);
 147         return (0);
 148 }
 149
 150 static void
 151 intel_iicbb_setsda(device_t idev, int val)
 152 {
 153         struct intel_iic_softc *sc;
 154         struct drm_i915_private *dev_priv;
 155         u32 reserved;
 156         u32 data_bits;
 157
 158         sc = device_get_softc(idev);
 159         dev_priv = sc->drm_dev->dev_private;
 160
 161         reserved = intel_iic_get_reserved(idev);
 162         if (val)
 163                 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
 164         else
 165                 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
 166                     GPIO_DATA_VAL_MASK;
 167
 168         I915_WRITE_NOTRACE(sc->reg, reserved | data_bits);
 169         POSTING_READ(sc->reg);
 170 }
 171
 172 static void
 173 intel_iicbb_setscl(device_t idev, int val)
 174 {
 175         struct intel_iic_softc *sc;
 176         struct drm_i915_private *dev_priv;
 177         u32 clock_bits, reserved;
 178
 179         sc = device_get_softc(idev);
 180         dev_priv = sc->drm_dev->dev_private;
 181
 182         reserved = intel_iic_get_reserved(idev);
 183         if (val)
 184                 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
 185         else
 186                 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
 187                     GPIO_CLOCK_VAL_MASK;
 188
 189         I915_WRITE_NOTRACE(sc->reg, reserved | clock_bits);
 190         POSTING_READ(sc->reg);
 191 }
 192
 193 static int
 194 intel_iicbb_getsda(device_t idev)
 195 {
 196         struct intel_iic_softc *sc;
 197         struct drm_i915_private *dev_priv;
 198         u32 reserved;
 199
 200         sc = device_get_softc(idev);
 201         dev_priv = sc->drm_dev->dev_private;
 202
 203         reserved = intel_iic_get_reserved(idev);
 204
 205         I915_WRITE_NOTRACE(sc->reg, reserved | GPIO_DATA_DIR_MASK);
 206         I915_WRITE_NOTRACE(sc->reg, reserved);
 207         return ((I915_READ_NOTRACE(sc->reg) & GPIO_DATA_VAL_IN) != 0);
 208 }
 209
 210 static int
 211 intel_iicbb_getscl(device_t idev)
 212 {
 213         struct intel_iic_softc *sc;
 214         struct drm_i915_private *dev_priv;
 215         u32 reserved;
 216
 217         sc = device_get_softc(idev);
 218         dev_priv = sc->drm_dev->dev_private;
 219
 220         reserved = intel_iic_get_reserved(idev);
 221
 222         I915_WRITE_NOTRACE(sc->reg, reserved | GPIO_CLOCK_DIR_MASK);
 223         I915_WRITE_NOTRACE(sc->reg, reserved);
 224         return ((I915_READ_NOTRACE(sc->reg) & GPIO_CLOCK_VAL_IN) != 0);
 225 }
 226
 227 static int
 228 intel_gmbus_transfer(device_t idev, struct iic_msg *msgs, uint32_t nmsgs)
 229 {
 230         struct intel_iic_softc *sc;
 231         struct drm_i915_private *dev_priv;
 232         u8 *buf;
 233         int error, i, reg_offset, unit;
 234         u32 val, loop;
 235         u16 len;
 236
 237         sc = device_get_softc(idev);
 238         dev_priv = sc->drm_dev->dev_private;
 239         unit = device_get_unit(idev);
 240
 241         sx_xlock(&dev_priv->gmbus_sx);
 242         if (sc->force_bit_dev) {
 243                 error = intel_iic_quirk_xfer(dev_priv->bbbus[unit], msgs, nmsgs);
 244                 goto out;
 245         }
 246
 247         reg_offset = HAS_PCH_SPLIT(dev_priv->dev) ? PCH_GMBUS0 - GMBUS0 : 0;
 248
 249         I915_WRITE(GMBUS0 + reg_offset, sc->reg0);
 250
 251         for (i = 0; i < nmsgs; i++) {
 252                 len = msgs[i].len;
 253                 buf = msgs[i].buf;
 254
 255                 if ((msgs[i].flags & IIC_M_RD) != 0) {
 256                         I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_WAIT |
 257                             (i + 1 == nmsgs ? GMBUS_CYCLE_STOP : 0) |
 258                             (len << GMBUS_BYTE_COUNT_SHIFT) |
 259                             (msgs[i].slave << (GMBUS_SLAVE_ADDR_SHIFT - 1)) |
 260                             GMBUS_SLAVE_READ | GMBUS_SW_RDY);
 261                         POSTING_READ(GMBUS2 + reg_offset);
 262                         do {
 263                                 loop = 0;
 264
 265                                 if (_intel_wait_for(sc->drm_dev,
 266                                     (I915_READ(GMBUS2 + reg_offset) &
 267                                         (GMBUS_SATOER | GMBUS_HW_RDY)) != 0,
 268                                     50, 1, "915gbr"))
 269                                         goto timeout;
 270                                 if ((I915_READ(GMBUS2 + reg_offset) &
 271                                     GMBUS_SATOER) != 0)
 272                                         goto clear_err;
 273
 274                                 val = I915_READ(GMBUS3 + reg_offset);
 275                                 do {
 276                                         *buf++ = val & 0xff;
 277                                         val >>= 8;
 278                                 } while (--len != 0 && ++loop < 4);
 279                         } while (len != 0);
 280                 } else {
 281                         val = loop = 0;
 282                         do {
 283                                 val |= *buf++ << (8 * loop);
 284                         } while (--len != 0 && ++loop < 4);
 285
 286                         I915_WRITE(GMBUS3 + reg_offset, val);
 287                         I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_WAIT |
 288                             (i + 1 == nmsgs ? GMBUS_CYCLE_STOP : 0) |
 289                             (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) |
 290                             (msgs[i].slave << (GMBUS_SLAVE_ADDR_SHIFT - 1)) |
 291                             GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
 292                         POSTING_READ(GMBUS2+reg_offset);
 293
 294                         while (len != 0) {
 295                                 if (_intel_wait_for(sc->drm_dev,
 296                                     (I915_READ(GMBUS2 + reg_offset) &
 297                                         (GMBUS_SATOER | GMBUS_HW_RDY)) != 0,
 298                                     50, 1, "915gbw"))
 299                                         goto timeout;
 300                                 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
 301                                         goto clear_err;
 302
 303                                 val = loop = 0;
 304                                 do {
 305                                         val |= *buf++ << (8 * loop);
 306                                 } while (--len != 0 && ++loop < 4);
 307
 308                                 I915_WRITE(GMBUS3 + reg_offset, val);
 309                                 POSTING_READ(GMBUS2 + reg_offset);
 310                         }
 311                 }
 312
 313                 if (i + 1 < nmsgs && _intel_wait_for(sc->drm_dev,
 314                     (I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER |
 315                         GMBUS_HW_WAIT_PHASE)) != 0,
 316                     50, 1, "915gbh"))
 317                         goto timeout;
 318                 if ((I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER) != 0)
 319                         goto clear_err;
 320         }
 321
 322         error = 0;
 323 done:
 324         /* Mark the GMBUS interface as disabled after waiting for idle.
 325          * We will re-enable it at the start of the next xfer,
 326          * till then let it sleep.
 327          */
 328         if (_intel_wait_for(dev,
 329             (I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0,
 330             10, 1, "915gbu"))
 331                 DRM_INFO("GMBUS timed out waiting for idle\n");
 332         I915_WRITE(GMBUS0 + reg_offset, 0);
 333 out:
 334         sx_xunlock(&dev_priv->gmbus_sx);
 335         return (error);
 336
 337 clear_err:
 338         /* Toggle the Software Clear Interrupt bit. This has the effect
 339          * of resetting the GMBUS controller and so clearing the
 340          * BUS_ERROR raised by the slave's NAK.
 341          */
 342         I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
 343         I915_WRITE(GMBUS1 + reg_offset, 0);
 344         error = EIO;
 345         goto done;
 346
 347 timeout:
 348         DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n",
 349             sc->reg0 & 0xff, sc->name);
 350         I915_WRITE(GMBUS0 + reg_offset, 0);
 351
 352         /*
 353          * Hardware may not support GMBUS over these pins?
 354          * Try GPIO bitbanging instead.
 355          */
 356         sc->force_bit_dev = true;
 357
 358         error = intel_iic_quirk_xfer(dev_priv->bbbus[unit], msgs, nmsgs);
 359         goto out;
 360 }
 361
 362 void
 363 intel_gmbus_set_speed(device_t idev, int speed)
 364 {
 365         struct intel_iic_softc *sc;
 366
 367         sc = device_get_softc(device_get_parent(idev));
 368
 369         sc->reg0 = (sc->reg0 & ~(0x3 << 8)) | speed;
 370 }
 371
 372 void
 373 intel_gmbus_force_bit(device_t idev, bool force_bit)
 374 {
 375         struct intel_iic_softc *sc;
 376
 377         sc = device_get_softc(device_get_parent(idev));
 378         sc->force_bit_dev = force_bit;
 379 }
 380
 381 static int
 382 intel_iic_quirk_xfer(device_t idev, struct iic_msg *msgs, int nmsgs)
 383 {
 384         device_t bridge_dev;
 385         struct intel_iic_softc *sc;
 386         struct drm_i915_private *dev_priv;
 387         int ret;
 388         int i;
 389
 390         bridge_dev = device_get_parent(device_get_parent(idev));
 391         sc = device_get_softc(bridge_dev);
 392         dev_priv = sc->drm_dev->dev_private;
 393
 394         intel_iic_reset(sc->drm_dev);
 395         intel_iic_quirk_set(dev_priv, true);
 396         IICBB_SETSDA(bridge_dev, 1);
 397         IICBB_SETSCL(bridge_dev, 1);
 398         DELAY(I2C_RISEFALL_TIME);
 399
 400         for (i = 0; i < nmsgs - 1; i++) {
 401                 /* force use of repeated start instead of default stop+start */
 402                 msgs[i].flags |= IIC_M_NOSTOP;
 403         }
 404         ret = iicbus_transfer(idev, msgs, nmsgs);
 405         IICBB_SETSDA(bridge_dev, 1);
 406         IICBB_SETSCL(bridge_dev, 1);
 407         intel_iic_quirk_set(dev_priv, false);
 408
 409         return (ret);
 410 }
 411
 412 static const char *gpio_names[GMBUS_NUM_PORTS] = {
 413         "disabled",
 414         "ssc",
 415         "vga",
 416         "panel",
 417         "dpc",
 418         "dpb",
 419         "reserved",
 420         "dpd",
 421 };
 422
 423 static int
 424 intel_gmbus_probe(device_t dev)
 425 {
 426
 427         return (BUS_PROBE_SPECIFIC);
 428 }
 429
 430 static int
 431 intel_gmbus_attach(device_t idev)
 432 {
 433         struct drm_i915_private *dev_priv;
 434         struct intel_iic_softc *sc;
 435         int pin;
 436
 437         sc = device_get_softc(idev);
 438         sc->drm_dev = device_get_softc(device_get_parent(idev));
 439         dev_priv = sc->drm_dev->dev_private;
 440         pin = device_get_unit(idev);
 441
 442         snprintf(sc->name, sizeof(sc->name), "gmbus bus %s", gpio_names[pin]);
 443         device_set_desc(idev, sc->name);
 444
 445         /* By default use a conservative clock rate */
 446         sc->reg0 = pin | GMBUS_RATE_100KHZ;
 447
 448         /* XXX force bit banging until GMBUS is fully debugged */
 449         if (IS_GEN2(sc->drm_dev)) {
 450                 sc->force_bit_dev = true;
 451         }
 452
 453         /* add bus interface device */
 454         sc->iic_dev = device_add_child(idev, "iicbus", -1);
 455         if (sc->iic_dev == NULL)
 456                 return (ENXIO);
 457         device_quiet(sc->iic_dev);
 458         bus_generic_attach(idev);
 459
 460         return (0);
 461 }
 462
 463 static int
 464 intel_gmbus_detach(device_t idev)
 465 {
 466         struct intel_iic_softc *sc;
 467         struct drm_i915_private *dev_priv;
 468         device_t child;
 469         int u;
 470
 471         sc = device_get_softc(idev);
 472         u = device_get_unit(idev);
 473         dev_priv = sc->drm_dev->dev_private;
 474
 475         child = sc->iic_dev;
 476         bus_generic_detach(idev);
 477         if (child != NULL)
 478                 device_delete_child(idev, child);
 479
 480         return (0);
 481 }
 482
 483 static int
 484 intel_iicbb_probe(device_t dev)
 485 {
 486
 487         return (BUS_PROBE_DEFAULT);
 488 }
 489
 490 static int
 491 intel_iicbb_attach(device_t idev)
 492 {
 493         static const int map_pin_to_reg[] = {
 494                 0,
 495                 GPIOB,
 496                 GPIOA,
 497                 GPIOC,
 498                 GPIOD,
 499                 GPIOE,
 500                 0,
 501                 GPIOF
 502         };
 503
 504         struct intel_iic_softc *sc;
 505         struct drm_i915_private *dev_priv;
 506         int pin;
 507
 508         sc = device_get_softc(idev);
 509         sc->drm_dev = device_get_softc(device_get_parent(idev));
 510         dev_priv = sc->drm_dev->dev_private;
 511         pin = device_get_unit(idev);
 512
 513         snprintf(sc->name, sizeof(sc->name), "i915 iicbb %s", gpio_names[pin]);
 514         device_set_desc(idev, sc->name);
 515
 516         sc->reg0 = pin | GMBUS_RATE_100KHZ;
 517         sc->reg = map_pin_to_reg[pin];
 518         if (HAS_PCH_SPLIT(dev_priv->dev))
 519                 sc->reg += PCH_GPIOA - GPIOA;
 520
 521         /* add generic bit-banging code */
 522         sc->iic_dev = device_add_child(idev, "iicbb", -1);
 523         if (sc->iic_dev == NULL)
 524                 return (ENXIO);
 525         device_quiet(sc->iic_dev);
 526         bus_generic_attach(idev);
 527
 528         return (0);
 529 }
 530
 531 static int
 532 intel_iicbb_detach(device_t idev)
 533 {
 534         struct intel_iic_softc *sc;
 535         device_t child;
 536
 537         sc = device_get_softc(idev);
 538         child = sc->iic_dev;
 539         bus_generic_detach(idev);
 540         if (child)
 541                 device_delete_child(idev, child);
 542         return (0);
 543 }
 544
 545 static device_method_t intel_gmbus_methods[] = {
 546         DEVMETHOD(device_probe,         intel_gmbus_probe),
 547         DEVMETHOD(device_attach,        intel_gmbus_attach),
 548         DEVMETHOD(device_detach,        intel_gmbus_detach),
 549         DEVMETHOD(iicbus_reset,         intel_iicbus_reset),
 550         DEVMETHOD(iicbus_transfer,      intel_gmbus_transfer),
 551         DEVMETHOD_END
 552 };
 553 static driver_t intel_gmbus_driver = {
 554         "intel_gmbus",
 555         intel_gmbus_methods,
 556         sizeof(struct intel_iic_softc)
 557 };
 558 static devclass_t intel_gmbus_devclass;
 559 DRIVER_MODULE_ORDERED(intel_gmbus, drmn, intel_gmbus_driver,
 560     intel_gmbus_devclass, 0, 0, SI_ORDER_FIRST);
 561 DRIVER_MODULE(iicbus, intel_gmbus, iicbus_driver, iicbus_devclass, 0, 0);
 562
 563 static device_method_t intel_iicbb_methods[] =  {
 564         DEVMETHOD(device_probe,         intel_iicbb_probe),
 565         DEVMETHOD(device_attach,        intel_iicbb_attach),
 566         DEVMETHOD(device_detach,        intel_iicbb_detach),
 567
 568         DEVMETHOD(bus_add_child,        bus_generic_add_child),
 569         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 570
 571         DEVMETHOD(iicbb_callback,       iicbus_null_callback),
 572         DEVMETHOD(iicbb_reset,          intel_iicbus_reset),
 573         DEVMETHOD(iicbb_setsda,         intel_iicbb_setsda),
 574         DEVMETHOD(iicbb_setscl,         intel_iicbb_setscl),
 575         DEVMETHOD(iicbb_getsda,         intel_iicbb_getsda),
 576         DEVMETHOD(iicbb_getscl,         intel_iicbb_getscl),
 577         DEVMETHOD_END
 578 };
 579 static driver_t intel_iicbb_driver = {
 580         "intel_iicbb",
 581         intel_iicbb_methods,
 582         sizeof(struct intel_iic_softc)
 583 };
 584 static devclass_t intel_iicbb_devclass;
 585 DRIVER_MODULE_ORDERED(intel_iicbb, drmn, intel_iicbb_driver,
 586     intel_iicbb_devclass, 0, 0, SI_ORDER_FIRST);
 587 DRIVER_MODULE(iicbb, intel_iicbb, iicbb_driver, iicbb_devclass, 0, 0);
 588
 589 int
 590 intel_setup_gmbus(struct drm_device *dev)
 591 {
 592         struct drm_i915_private *dev_priv;
 593         device_t iic_dev;
 594         int i, ret;
 595
 596         dev_priv = dev->dev_private;
 597         sx_init(&dev_priv->gmbus_sx, "gmbus");
 598         dev_priv->gmbus_bridge = malloc(sizeof(device_t) * GMBUS_NUM_PORTS,
 599             DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
 600         dev_priv->bbbus_bridge = malloc(sizeof(device_t) * GMBUS_NUM_PORTS,
 601             DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
 602         dev_priv->gmbus = malloc(sizeof(device_t) * GMBUS_NUM_PORTS,
 603             DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
 604         dev_priv->bbbus = malloc(sizeof(device_t) * GMBUS_NUM_PORTS,
 605             DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
 606
 607         /*
 608          * The Giant there is recursed, most likely.  Normally, the
 609          * intel_setup_gmbus() is called from the attach method of the
 610          * driver.
 611          */
 612         mtx_lock(&Giant);
 613         for (i = 0; i < GMBUS_NUM_PORTS; i++) {
 614                 /*
 615                  * Initialized bbbus_bridge before gmbus_bridge, since
 616                  * gmbus may decide to force quirk transfer in the
 617                  * attachment code.
 618                  */
 619                 dev_priv->bbbus_bridge[i] = device_add_child(dev->device,
 620                     "intel_iicbb", i);
 621                 if (dev_priv->bbbus_bridge[i] == NULL) {
 622                         DRM_ERROR("bbbus bridge %d creation failed\n", i);
 623                         ret = ENXIO;
 624                         goto err;
 625                 }
 626                 device_quiet(dev_priv->bbbus_bridge[i]);
 627                 ret = device_probe_and_attach(dev_priv->bbbus_bridge[i]);
 628                 if (ret != 0) {
 629                         DRM_ERROR("bbbus bridge %d attach failed, %d\n", i,
 630                             ret);
 631                         goto err;
 632                 }
 633
 634                 iic_dev = device_find_child(dev_priv->bbbus_bridge[i], "iicbb",
 635                     -1);
 636                 if (iic_dev == NULL) {
 637                         DRM_ERROR("bbbus bridge doesn't have iicbb child\n");
 638                         goto err;
 639                 }
 640                 iic_dev = device_find_child(iic_dev, "iicbus", -1);
 641                 if (iic_dev == NULL) {
 642                         DRM_ERROR(
 643                 "bbbus bridge doesn't have iicbus grandchild\n");
 644                         goto err;
 645                 }
 646
 647                 dev_priv->bbbus[i] = iic_dev;
 648
 649                 dev_priv->gmbus_bridge[i] = device_add_child(dev->device,
 650                     "intel_gmbus", i);
 651                 if (dev_priv->gmbus_bridge[i] == NULL) {
 652                         DRM_ERROR("gmbus bridge %d creation failed\n", i);
 653                         ret = ENXIO;
 654                         goto err;
 655                 }
 656                 device_quiet(dev_priv->gmbus_bridge[i]);
 657                 ret = device_probe_and_attach(dev_priv->gmbus_bridge[i]);
 658                 if (ret != 0) {
 659                         DRM_ERROR("gmbus bridge %d attach failed, %d\n", i,
 660                             ret);
 661                         ret = ENXIO;
 662                         goto err;
 663                 }
 664
 665                 iic_dev = device_find_child(dev_priv->gmbus_bridge[i],
 666                     "iicbus", -1);
 667                 if (iic_dev == NULL) {
 668                         DRM_ERROR("gmbus bridge doesn't have iicbus child\n");
 669                         goto err;
 670                 }
 671                 dev_priv->gmbus[i] = iic_dev;
 672
 673                 intel_iic_reset(dev);
 674         }
 675
 676         mtx_unlock(&Giant);
 677         return (0);
 678
 679 err:
 680         intel_teardown_gmbus_m(dev, i);
 681         mtx_unlock(&Giant);
 682         return (ret);
 683 }
 684
 685 static void
 686 intel_teardown_gmbus_m(struct drm_device *dev, int m)
 687 {
 688         struct drm_i915_private *dev_priv;
 689
 690         dev_priv = dev->dev_private;
 691
 692         free(dev_priv->gmbus, DRM_MEM_DRIVER);
 693         dev_priv->gmbus = NULL;
 694         free(dev_priv->bbbus, DRM_MEM_DRIVER);
 695         dev_priv->bbbus = NULL;
 696         free(dev_priv->gmbus_bridge, DRM_MEM_DRIVER);
 697         dev_priv->gmbus_bridge = NULL;
 698         free(dev_priv->bbbus_bridge, DRM_MEM_DRIVER);
 699         dev_priv->bbbus_bridge = NULL;
 700         sx_destroy(&dev_priv->gmbus_sx);
 701 }
 702
 703 void
 704 intel_teardown_gmbus(struct drm_device *dev)
 705 {
 706
 707         mtx_lock(&Giant);
 708         intel_teardown_gmbus_m(dev, GMBUS_NUM_PORTS);
 709         mtx_unlock(&Giant);
 710 }