sys/dev/drm2/radeon/atombios_dp.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  *          Jerome Glisse
  26  */
  27
  28 #include <sys/cdefs.h>
  29 __FBSDID("$FreeBSD$");
  30
  31 #include <dev/drm2/drmP.h>
  32 #include <dev/drm2/radeon/radeon_drm.h>
  33 #include "radeon.h"
  34
  35 #include "atom.h"
  36 #include "atom-bits.h"
  37 #include <dev/drm2/drm_dp_helper.h>
  38
  39 /* move these to drm_dp_helper.c/h */
  40 #define DP_LINK_CONFIGURATION_SIZE 9
  41 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
  42
  43 static char *voltage_names[] = {
  44         "0.4V", "0.6V", "0.8V", "1.2V"
  45 };
  46 static char *pre_emph_names[] = {
  47         "0dB", "3.5dB", "6dB", "9.5dB"
  48 };
  49
  50 /***** radeon AUX functions *****/
  51 union aux_channel_transaction {
  52         PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
  53         PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
  54 };
  55
  56 static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
  57                                  u8 *send, int send_bytes,
  58                                  u8 *recv, int recv_size,
  59                                  u8 delay, u8 *ack)
  60 {
  61         struct drm_device *dev = chan->dev;
  62         struct radeon_device *rdev = dev->dev_private;
  63         union aux_channel_transaction args;
  64         int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
  65         unsigned char *base;
  66         int recv_bytes;
  67
  68         memset(&args, 0, sizeof(args));
  69
  70         base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1);
  71
  72         memcpy(base, send, send_bytes);
  73
  74         args.v1.lpAuxRequest = 0 + 4;
  75         args.v1.lpDataOut = 16 + 4;
  76         args.v1.ucDataOutLen = 0;
  77         args.v1.ucChannelID = chan->rec.i2c_id;
  78         args.v1.ucDelay = delay / 10;
  79         if (ASIC_IS_DCE4(rdev))
  80                 args.v2.ucHPD_ID = chan->rec.hpd;
  81
  82         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  83
  84         *ack = args.v1.ucReplyStatus;
  85
  86         /* timeout */
  87         if (args.v1.ucReplyStatus == 1) {
  88                 DRM_DEBUG_KMS("dp_aux_ch timeout\n");
  89                 return -ETIMEDOUT;
  90         }
  91
  92         /* flags not zero */
  93         if (args.v1.ucReplyStatus == 2) {
  94                 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
  95                 return -EBUSY;
  96         }
  97
  98         /* error */
  99         if (args.v1.ucReplyStatus == 3) {
 100                 DRM_DEBUG_KMS("dp_aux_ch error\n");
 101                 return -EIO;
 102         }
 103
 104         recv_bytes = args.v1.ucDataOutLen;
 105         if (recv_bytes > recv_size)
 106                 recv_bytes = recv_size;
 107
 108         if (recv && recv_size)
 109                 memcpy(recv, base + 16, recv_bytes);
 110
 111         return recv_bytes;
 112 }
 113
 114 static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector,
 115                                       u16 address, u8 *send, u8 send_bytes, u8 delay)
 116 {
 117         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 118         int ret;
 119         u8 msg[20];
 120         int msg_bytes = send_bytes + 4;
 121         u8 ack;
 122         unsigned retry;
 123
 124         if (send_bytes > 16)
 125                 return -1;
 126
 127         msg[0] = address;
 128         msg[1] = address >> 8;
 129         msg[2] = AUX_NATIVE_WRITE << 4;
 130         msg[3] = (msg_bytes << 4) | (send_bytes - 1);
 131         memcpy(&msg[4], send, send_bytes);
 132
 133         for (retry = 0; retry < 4; retry++) {
 134                 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
 135                                             msg, msg_bytes, NULL, 0, delay, &ack);
 136                 if (ret == -EBUSY)
 137                         continue;
 138                 else if (ret < 0)
 139                         return ret;
 140                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 141                         return send_bytes;
 142                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 143                         DRM_UDELAY(400);
 144                 else
 145                         return -EIO;
 146         }
 147
 148         return -EIO;
 149 }
 150
 151 static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
 152                                      u16 address, u8 *recv, int recv_bytes, u8 delay)
 153 {
 154         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 155         u8 msg[4];
 156         int msg_bytes = 4;
 157         u8 ack;
 158         int ret;
 159         unsigned retry;
 160
 161         msg[0] = address;
 162         msg[1] = address >> 8;
 163         msg[2] = AUX_NATIVE_READ << 4;
 164         msg[3] = (msg_bytes << 4) | (recv_bytes - 1);
 165
 166         for (retry = 0; retry < 4; retry++) {
 167                 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
 168                                             msg, msg_bytes, recv, recv_bytes, delay, &ack);
 169                 if (ret == -EBUSY)
 170                         continue;
 171                 else if (ret < 0)
 172                         return ret;
 173                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 174                         return ret;
 175                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 176                         DRM_UDELAY(400);
 177                 else if (ret == 0)
 178                         return -EPROTO;
 179                 else
 180                         return -EIO;
 181         }
 182
 183         return -EIO;
 184 }
 185
 186 static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector,
 187                                  u16 reg, u8 val)
 188 {
 189         radeon_dp_aux_native_write(radeon_connector, reg, &val, 1, 0);
 190 }
 191
 192 static u8 radeon_read_dpcd_reg(struct radeon_connector *radeon_connector,
 193                                u16 reg)
 194 {
 195         u8 val = 0;
 196
 197         radeon_dp_aux_native_read(radeon_connector, reg, &val, 1, 0);
 198
 199         return val;
 200 }
 201
 202 int radeon_dp_i2c_aux_ch(device_t dev, int mode, u8 write_byte, u8 *read_byte)
 203 {
 204         struct iic_dp_aux_data *algo_data = device_get_softc(dev);
 205         struct radeon_i2c_chan *auxch = algo_data->priv;
 206         u16 address = algo_data->address;
 207         u8 msg[5];
 208         u8 reply[2];
 209         unsigned retry;
 210         int msg_bytes;
 211         int reply_bytes = 1;
 212         int ret;
 213         u8 ack;
 214
 215         /* Set up the command byte */
 216         if (mode & MODE_I2C_READ)
 217                 msg[2] = AUX_I2C_READ << 4;
 218         else
 219                 msg[2] = AUX_I2C_WRITE << 4;
 220
 221         if (!(mode & MODE_I2C_STOP))
 222                 msg[2] |= AUX_I2C_MOT << 4;
 223
 224         msg[0] = address;
 225         msg[1] = address >> 8;
 226
 227         switch (mode) {
 228         case MODE_I2C_WRITE:
 229                 msg_bytes = 5;
 230                 msg[3] = msg_bytes << 4;
 231                 msg[4] = write_byte;
 232                 break;
 233         case MODE_I2C_READ:
 234                 msg_bytes = 4;
 235                 msg[3] = msg_bytes << 4;
 236                 break;
 237         default:
 238                 msg_bytes = 4;
 239                 msg[3] = 3 << 4;
 240                 break;
 241         }
 242
 243         for (retry = 0; retry < 4; retry++) {
 244                 ret = radeon_process_aux_ch(auxch,
 245                                             msg, msg_bytes, reply, reply_bytes, 0, &ack);
 246                 if (ret == -EBUSY)
 247                         continue;
 248                 else if (ret < 0) {
 249                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 250                         return ret;
 251                 }
 252
 253                 switch (ack & AUX_NATIVE_REPLY_MASK) {
 254                 case AUX_NATIVE_REPLY_ACK:
 255                         /* I2C-over-AUX Reply field is only valid
 256                          * when paired with AUX ACK.
 257                          */
 258                         break;
 259                 case AUX_NATIVE_REPLY_NACK:
 260                         DRM_DEBUG_KMS("aux_ch native nack\n");
 261                         return -EREMOTEIO;
 262                 case AUX_NATIVE_REPLY_DEFER:
 263                         DRM_DEBUG_KMS("aux_ch native defer\n");
 264                         DRM_UDELAY(400);
 265                         continue;
 266                 default:
 267                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack);
 268                         return -EREMOTEIO;
 269                 }
 270
 271                 switch (ack & AUX_I2C_REPLY_MASK) {
 272                 case AUX_I2C_REPLY_ACK:
 273                         if (mode == MODE_I2C_READ)
 274                                 *read_byte = reply[0];
 275                         return ret;
 276                 case AUX_I2C_REPLY_NACK:
 277                         DRM_DEBUG_KMS("aux_i2c nack\n");
 278                         return -EREMOTEIO;
 279                 case AUX_I2C_REPLY_DEFER:
 280                         DRM_DEBUG_KMS("aux_i2c defer\n");
 281                         DRM_UDELAY(400);
 282                         break;
 283                 default:
 284                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack);
 285                         return -EREMOTEIO;
 286                 }
 287         }
 288
 289         DRM_DEBUG_KMS("aux i2c too many retries, giving up\n");
 290         return -EREMOTEIO;
 291 }
 292
 293 /***** general DP utility functions *****/
 294
 295 #define DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_1200
 296 #define DP_PRE_EMPHASIS_MAX    DP_TRAIN_PRE_EMPHASIS_9_5
 297
 298 static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
 299                                 int lane_count,
 300                                 u8 train_set[4])
 301 {
 302         u8 v = 0;
 303         u8 p = 0;
 304         int lane;
 305
 306         for (lane = 0; lane < lane_count; lane++) {
 307                 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
 308                 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
 309
 310                 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
 311                           lane,
 312                           voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
 313                           pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
 314
 315                 if (this_v > v)
 316                         v = this_v;
 317                 if (this_p > p)
 318                         p = this_p;
 319         }
 320
 321         if (v >= DP_VOLTAGE_MAX)
 322                 v |= DP_TRAIN_MAX_SWING_REACHED;
 323
 324         if (p >= DP_PRE_EMPHASIS_MAX)
 325                 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 326
 327         DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
 328                   voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
 329                   pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
 330
 331         for (lane = 0; lane < 4; lane++)
 332                 train_set[lane] = v | p;
 333 }
 334
 335 /* convert bits per color to bits per pixel */
 336 /* get bpc from the EDID */
 337 static int convert_bpc_to_bpp(int bpc)
 338 {
 339         if (bpc == 0)
 340                 return 24;
 341         else
 342                 return bpc * 3;
 343 }
 344
 345 /* get the max pix clock supported by the link rate and lane num */
 346 static int dp_get_max_dp_pix_clock(int link_rate,
 347                                    int lane_num,
 348                                    int bpp)
 349 {
 350         return (link_rate * lane_num * 8) / bpp;
 351 }
 352
 353 /***** radeon specific DP functions *****/
 354
 355 /* First get the min lane# when low rate is used according to pixel clock
 356  * (prefer low rate), second check max lane# supported by DP panel,
 357  * if the max lane# < low rate lane# then use max lane# instead.
 358  */
 359 static int radeon_dp_get_dp_lane_number(struct drm_connector *connector,
 360                                         u8 dpcd[DP_DPCD_SIZE],
 361                                         int pix_clock)
 362 {
 363         int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
 364         int max_link_rate = drm_dp_max_link_rate(dpcd);
 365         int max_lane_num = drm_dp_max_lane_count(dpcd);
 366         int lane_num;
 367         int max_dp_pix_clock;
 368
 369         for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) {
 370                 max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp);
 371                 if (pix_clock <= max_dp_pix_clock)
 372                         break;
 373         }
 374
 375         return lane_num;
 376 }
 377
 378 static int radeon_dp_get_dp_link_clock(struct drm_connector *connector,
 379                                        u8 dpcd[DP_DPCD_SIZE],
 380                                        int pix_clock)
 381 {
 382         int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
 383         int lane_num, max_pix_clock;
 384
 385         if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
 386             ENCODER_OBJECT_ID_NUTMEG)
 387                 return 270000;
 388
 389         lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock);
 390         max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp);
 391         if (pix_clock <= max_pix_clock)
 392                 return 162000;
 393         max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp);
 394         if (pix_clock <= max_pix_clock)
 395                 return 270000;
 396         if (radeon_connector_is_dp12_capable(connector)) {
 397                 max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp);
 398                 if (pix_clock <= max_pix_clock)
 399                         return 540000;
 400         }
 401
 402         return drm_dp_max_link_rate(dpcd);
 403 }
 404
 405 static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
 406                                     int action, int dp_clock,
 407                                     u8 ucconfig, u8 lane_num)
 408 {
 409         DP_ENCODER_SERVICE_PARAMETERS args;
 410         int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
 411
 412         memset(&args, 0, sizeof(args));
 413         args.ucLinkClock = dp_clock / 10;
 414         args.ucConfig = ucconfig;
 415         args.ucAction = action;
 416         args.ucLaneNum = lane_num;
 417         args.ucStatus = 0;
 418
 419         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 420         return args.ucStatus;
 421 }
 422
 423 u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
 424 {
 425         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 426         struct drm_device *dev = radeon_connector->base.dev;
 427         struct radeon_device *rdev = dev->dev_private;
 428
 429         return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
 430                                          dig_connector->dp_i2c_bus->rec.i2c_id, 0);
 431 }
 432
 433 static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector)
 434 {
 435         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 436         u8 buf[3];
 437
 438         if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
 439                 return;
 440
 441         if (radeon_dp_aux_native_read(radeon_connector, DP_SINK_OUI, buf, 3, 0))
 442                 DRM_DEBUG_KMS("Sink OUI: %02hhx%02hhx%02hhx\n",
 443                               buf[0], buf[1], buf[2]);
 444
 445         if (radeon_dp_aux_native_read(radeon_connector, DP_BRANCH_OUI, buf, 3, 0))
 446                 DRM_DEBUG_KMS("Branch OUI: %02hhx%02hhx%02hhx\n",
 447                               buf[0], buf[1], buf[2]);
 448 }
 449
 450 bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
 451 {
 452         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 453         u8 msg[DP_DPCD_SIZE];
 454         int ret, i;
 455
 456         ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, msg,
 457                                         DP_DPCD_SIZE, 0);
 458         if (ret > 0) {
 459                 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
 460                 DRM_DEBUG_KMS("DPCD: ");
 461                 for (i = 0; i < DP_DPCD_SIZE; i++)
 462                         DRM_DEBUG_KMS("%02x ", msg[i]);
 463                 DRM_DEBUG_KMS("\n");
 464
 465                 radeon_dp_probe_oui(radeon_connector);
 466
 467                 return true;
 468         }
 469         dig_connector->dpcd[0] = 0;
 470         return false;
 471 }
 472
 473 int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
 474                              struct drm_connector *connector)
 475 {
 476         struct drm_device *dev = encoder->dev;
 477         struct radeon_device *rdev = dev->dev_private;
 478         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 479         int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
 480         u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector);
 481         u8 tmp;
 482
 483         if (!ASIC_IS_DCE4(rdev))
 484                 return panel_mode;
 485
 486         if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
 487                 /* DP bridge chips */
 488                 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);
 489                 if (tmp & 1)
 490                         panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
 491                 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
 492                          (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
 493                         panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
 494                 else
 495                         panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
 496         } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
 497                 /* eDP */
 498                 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);
 499                 if (tmp & 1)
 500                         panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
 501         }
 502
 503         return panel_mode;
 504 }
 505
 506 void radeon_dp_set_link_config(struct drm_connector *connector,
 507                                const struct drm_display_mode *mode)
 508 {
 509         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 510         struct radeon_connector_atom_dig *dig_connector;
 511
 512         if (!radeon_connector->con_priv)
 513                 return;
 514         dig_connector = radeon_connector->con_priv;
 515
 516         if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 517             (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
 518                 dig_connector->dp_clock =
 519                         radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
 520                 dig_connector->dp_lane_count =
 521                         radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock);
 522         }
 523 }
 524
 525 int radeon_dp_mode_valid_helper(struct drm_connector *connector,
 526                                 struct drm_display_mode *mode)
 527 {
 528         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 529         struct radeon_connector_atom_dig *dig_connector;
 530         int dp_clock;
 531
 532         if (!radeon_connector->con_priv)
 533                 return MODE_CLOCK_HIGH;
 534         dig_connector = radeon_connector->con_priv;
 535
 536         dp_clock =
 537                 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
 538
 539         if ((dp_clock == 540000) &&
 540             (!radeon_connector_is_dp12_capable(connector)))
 541                 return MODE_CLOCK_HIGH;
 542
 543         return MODE_OK;
 544 }
 545
 546 static bool radeon_dp_get_link_status(struct radeon_connector *radeon_connector,
 547                                       u8 link_status[DP_LINK_STATUS_SIZE])
 548 {
 549         int ret;
 550         ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS,
 551                                         link_status, DP_LINK_STATUS_SIZE, 100);
 552         if (ret <= 0) {
 553                 return false;
 554         }
 555
 556         DRM_DEBUG_KMS("link status %*ph\n", 6, link_status);
 557         return true;
 558 }
 559
 560 bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
 561 {
 562         u8 link_status[DP_LINK_STATUS_SIZE];
 563         struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 564
 565         if (!radeon_dp_get_link_status(radeon_connector, link_status))
 566                 return false;
 567         if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
 568                 return false;
 569         return true;
 570 }
 571
 572 struct radeon_dp_link_train_info {
 573         struct radeon_device *rdev;
 574         struct drm_encoder *encoder;
 575         struct drm_connector *connector;
 576         struct radeon_connector *radeon_connector;
 577         int enc_id;
 578         int dp_clock;
 579         int dp_lane_count;
 580         bool tp3_supported;
 581         u8 dpcd[DP_RECEIVER_CAP_SIZE];
 582         u8 train_set[4];
 583         u8 link_status[DP_LINK_STATUS_SIZE];
 584         u8 tries;
 585         bool use_dpencoder;
 586 };
 587
 588 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)
 589 {
 590         /* set the initial vs/emph on the source */
 591         atombios_dig_transmitter_setup(dp_info->encoder,
 592                                        ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
 593                                        0, dp_info->train_set[0]); /* sets all lanes at once */
 594
 595         /* set the vs/emph on the sink */
 596         radeon_dp_aux_native_write(dp_info->radeon_connector, DP_TRAINING_LANE0_SET,
 597                                    dp_info->train_set, dp_info->dp_lane_count, 0);
 598 }
 599
 600 static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
 601 {
 602         int rtp = 0;
 603
 604         /* set training pattern on the source */
 605         if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) {
 606                 switch (tp) {
 607                 case DP_TRAINING_PATTERN_1:
 608                         rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
 609                         break;
 610                 case DP_TRAINING_PATTERN_2:
 611                         rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
 612                         break;
 613                 case DP_TRAINING_PATTERN_3:
 614                         rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
 615                         break;
 616                 }
 617                 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);
 618         } else {
 619                 switch (tp) {
 620                 case DP_TRAINING_PATTERN_1:
 621                         rtp = 0;
 622                         break;
 623                 case DP_TRAINING_PATTERN_2:
 624                         rtp = 1;
 625                         break;
 626                 }
 627                 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
 628                                           dp_info->dp_clock, dp_info->enc_id, rtp);
 629         }
 630
 631         /* enable training pattern on the sink */
 632         radeon_write_dpcd_reg(dp_info->radeon_connector, DP_TRAINING_PATTERN_SET, tp);
 633 }
 634
 635 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
 636 {
 637         struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder);
 638         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 639         u8 tmp;
 640
 641         /* power up the sink */
 642         if (dp_info->dpcd[0] >= 0x11)
 643                 radeon_write_dpcd_reg(dp_info->radeon_connector,
 644                                       DP_SET_POWER, DP_SET_POWER_D0);
 645
 646         /* possibly enable downspread on the sink */
 647         if (dp_info->dpcd[3] & 0x1)
 648                 radeon_write_dpcd_reg(dp_info->radeon_connector,
 649                                       DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
 650         else
 651                 radeon_write_dpcd_reg(dp_info->radeon_connector,
 652                                       DP_DOWNSPREAD_CTRL, 0);
 653
 654         if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) &&
 655             (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) {
 656                 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_EDP_CONFIGURATION_SET, 1);
 657         }
 658
 659         /* set the lane count on the sink */
 660         tmp = dp_info->dp_lane_count;
 661         if (dp_info->dpcd[DP_DPCD_REV] >= 0x11 &&
 662             dp_info->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)
 663                 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 664         radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LANE_COUNT_SET, tmp);
 665
 666         /* set the link rate on the sink */
 667         tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
 668         radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LINK_BW_SET, tmp);
 669
 670         /* start training on the source */
 671         if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
 672                 atombios_dig_encoder_setup(dp_info->encoder,
 673                                            ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
 674         else
 675                 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,
 676                                           dp_info->dp_clock, dp_info->enc_id, 0);
 677
 678         /* disable the training pattern on the sink */
 679         radeon_write_dpcd_reg(dp_info->radeon_connector,
 680                               DP_TRAINING_PATTERN_SET,
 681                               DP_TRAINING_PATTERN_DISABLE);
 682
 683         return 0;
 684 }
 685
 686 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)
 687 {
 688         DRM_UDELAY(400);
 689
 690         /* disable the training pattern on the sink */
 691         radeon_write_dpcd_reg(dp_info->radeon_connector,
 692                               DP_TRAINING_PATTERN_SET,
 693                               DP_TRAINING_PATTERN_DISABLE);
 694
 695         /* disable the training pattern on the source */
 696         if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
 697                 atombios_dig_encoder_setup(dp_info->encoder,
 698                                            ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
 699         else
 700                 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
 701                                           dp_info->dp_clock, dp_info->enc_id, 0);
 702
 703         return 0;
 704 }
 705
 706 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)
 707 {
 708         bool clock_recovery;
 709         u8 voltage;
 710         int i;
 711
 712         radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
 713         memset(dp_info->train_set, 0, 4);
 714         radeon_dp_update_vs_emph(dp_info);
 715
 716         DRM_UDELAY(400);
 717
 718         /* clock recovery loop */
 719         clock_recovery = false;
 720         dp_info->tries = 0;
 721         voltage = 0xff;
 722         while (1) {
 723                 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
 724
 725                 if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) {
 726                         DRM_ERROR("displayport link status failed\n");
 727                         break;
 728                 }
 729
 730                 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
 731                         clock_recovery = true;
 732                         break;
 733                 }
 734
 735                 for (i = 0; i < dp_info->dp_lane_count; i++) {
 736                         if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
 737                                 break;
 738                 }
 739                 if (i == dp_info->dp_lane_count) {
 740                         DRM_ERROR("clock recovery reached max voltage\n");
 741                         break;
 742                 }
 743
 744                 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
 745                         ++dp_info->tries;
 746                         if (dp_info->tries == 5) {
 747                                 DRM_ERROR("clock recovery tried 5 times\n");
 748                                 break;
 749                         }
 750                 } else
 751                         dp_info->tries = 0;
 752
 753                 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 754
 755                 /* Compute new train_set as requested by sink */
 756                 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
 757
 758                 radeon_dp_update_vs_emph(dp_info);
 759         }
 760         if (!clock_recovery) {
 761                 DRM_ERROR("clock recovery failed\n");
 762                 return -1;
 763         } else {
 764                 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
 765                           dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
 766                           (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
 767                           DP_TRAIN_PRE_EMPHASIS_SHIFT);
 768                 return 0;
 769         }
 770 }
 771
 772 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)
 773 {
 774         bool channel_eq;
 775
 776         if (dp_info->tp3_supported)
 777                 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
 778         else
 779                 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
 780
 781         /* channel equalization loop */
 782         dp_info->tries = 0;
 783         channel_eq = false;
 784         while (1) {
 785                 drm_dp_link_train_channel_eq_delay(dp_info->dpcd);
 786
 787                 if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) {
 788                         DRM_ERROR("displayport link status failed\n");
 789                         break;
 790                 }
 791
 792                 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
 793                         channel_eq = true;
 794                         break;
 795                 }
 796
 797                 /* Try 5 times */
 798                 if (dp_info->tries > 5) {
 799                         DRM_ERROR("channel eq failed: 5 tries\n");
 800                         break;
 801                 }
 802
 803                 /* Compute new train_set as requested by sink */
 804                 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
 805
 806                 radeon_dp_update_vs_emph(dp_info);
 807                 dp_info->tries++;
 808         }
 809
 810         if (!channel_eq) {
 811                 DRM_ERROR("channel eq failed\n");
 812                 return -1;
 813         } else {
 814                 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
 815                           dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
 816                           (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
 817                           >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
 818                 return 0;
 819         }
 820 }
 821
 822 void radeon_dp_link_train(struct drm_encoder *encoder,
 823                           struct drm_connector *connector)
 824 {
 825         struct drm_device *dev = encoder->dev;
 826         struct radeon_device *rdev = dev->dev_private;
 827         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 828         struct radeon_encoder_atom_dig *dig;
 829         struct radeon_connector *radeon_connector;
 830         struct radeon_connector_atom_dig *dig_connector;
 831         struct radeon_dp_link_train_info dp_info;
 832         int index;
 833         u8 tmp, frev, crev;
 834
 835         if (!radeon_encoder->enc_priv)
 836                 return;
 837         dig = radeon_encoder->enc_priv;
 838
 839         radeon_connector = to_radeon_connector(connector);
 840         if (!radeon_connector->con_priv)
 841                 return;
 842         dig_connector = radeon_connector->con_priv;
 843
 844         if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
 845             (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
 846                 return;
 847
 848         /* DPEncoderService newer than 1.1 can't program properly the
 849          * training pattern. When facing such version use the
 850          * DIGXEncoderControl (X== 1 | 2)
 851          */
 852         dp_info.use_dpencoder = true;
 853         index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
 854         if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) {
 855                 if (crev > 1) {
 856                         dp_info.use_dpencoder = false;
 857                 }
 858         }
 859
 860         dp_info.enc_id = 0;
 861         if (dig->dig_encoder)
 862                 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
 863         else
 864                 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
 865         if (dig->linkb)
 866                 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B;
 867         else
 868                 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
 869
 870         tmp = radeon_read_dpcd_reg(radeon_connector, DP_MAX_LANE_COUNT);
 871         if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
 872                 dp_info.tp3_supported = true;
 873         else
 874                 dp_info.tp3_supported = false;
 875
 876         memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
 877         dp_info.rdev = rdev;
 878         dp_info.encoder = encoder;
 879         dp_info.connector = connector;
 880         dp_info.radeon_connector = radeon_connector;
 881         dp_info.dp_lane_count = dig_connector->dp_lane_count;
 882         dp_info.dp_clock = dig_connector->dp_clock;
 883
 884         if (radeon_dp_link_train_init(&dp_info))
 885                 goto done;
 886         if (radeon_dp_link_train_cr(&dp_info))
 887                 goto done;
 888         if (radeon_dp_link_train_ce(&dp_info))
 889                 goto done;
 890 done:
 891         if (radeon_dp_link_train_finish(&dp_info))
 892                 return;
 893 }