sys/dev/drm2/radeon/evergreen.c

   1 /*
   2  * Copyright 2010 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24
  25 #include <sys/cdefs.h>
  26 __FBSDID("$FreeBSD$");
  27
  28 #include <dev/drm2/drmP.h>
  29 #include "radeon.h"
  30 #include "radeon_asic.h"
  31 #include <dev/drm2/radeon/radeon_drm.h>
  32 #include "evergreend.h"
  33 #include "atom.h"
  34 #include "avivod.h"
  35 #include "evergreen_reg.h"
  36 #include "evergreen_blit_shaders.h"
  37
  38 #define EVERGREEN_PFP_UCODE_SIZE 1120
  39 #define EVERGREEN_PM4_UCODE_SIZE 1376
  40
  41 static const u32 crtc_offsets[6] =
  42 {
  43         EVERGREEN_CRTC0_REGISTER_OFFSET,
  44         EVERGREEN_CRTC1_REGISTER_OFFSET,
  45         EVERGREEN_CRTC2_REGISTER_OFFSET,
  46         EVERGREEN_CRTC3_REGISTER_OFFSET,
  47         EVERGREEN_CRTC4_REGISTER_OFFSET,
  48         EVERGREEN_CRTC5_REGISTER_OFFSET
  49 };
  50
  51 static void evergreen_gpu_init(struct radeon_device *rdev);
  52 void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
  53
  54 void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
  55                              unsigned *bankh, unsigned *mtaspect,
  56                              unsigned *tile_split)
  57 {
  58         *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
  59         *bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
  60         *mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
  61         *tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
  62         switch (*bankw) {
  63         default:
  64         case 1: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_1; break;
  65         case 2: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_2; break;
  66         case 4: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_4; break;
  67         case 8: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_8; break;
  68         }
  69         switch (*bankh) {
  70         default:
  71         case 1: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_1; break;
  72         case 2: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_2; break;
  73         case 4: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_4; break;
  74         case 8: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_8; break;
  75         }
  76         switch (*mtaspect) {
  77         default:
  78         case 1: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1; break;
  79         case 2: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2; break;
  80         case 4: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4; break;
  81         case 8: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8; break;
  82         }
  83 }
  84
  85 void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
  86 {
  87         u16 ctl, v;
  88         int err, cap;
  89
  90         err = pci_find_cap(rdev->dev, PCIY_EXPRESS, &cap);
  91         if (err)
  92                 return;
  93
  94         cap += PCIER_DEVICE_CTL;
  95
  96         ctl = pci_read_config(rdev->dev, cap, 2);
  97
  98         v = (ctl & PCIEM_CTL_MAX_READ_REQUEST) >> 12;
  99
 100         /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it
 101          * to avoid hangs or perfomance issues
 102          */
 103         if ((v == 0) || (v == 6) || (v == 7)) {
 104                 ctl &= ~PCIEM_CTL_MAX_READ_REQUEST;
 105                 ctl |= (2 << 12);
 106                 pci_write_config(rdev->dev, cap, ctl, 2);
 107         }
 108 }
 109
 110 /**
 111  * dce4_wait_for_vblank - vblank wait asic callback.
 112  *
 113  * @rdev: radeon_device pointer
 114  * @crtc: crtc to wait for vblank on
 115  *
 116  * Wait for vblank on the requested crtc (evergreen+).
 117  */
 118 void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc)
 119 {
 120         int i;
 121
 122         if (crtc >= rdev->num_crtc)
 123                 return;
 124
 125         if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN) {
 126                 for (i = 0; i < rdev->usec_timeout; i++) {
 127                         if (!(RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK))
 128                                 break;
 129                         DRM_UDELAY(1);
 130                 }
 131                 for (i = 0; i < rdev->usec_timeout; i++) {
 132                         if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)
 133                                 break;
 134                         DRM_UDELAY(1);
 135                 }
 136         }
 137 }
 138
 139 /**
 140  * radeon_irq_kms_pflip_irq_get - pre-pageflip callback.
 141  *
 142  * @rdev: radeon_device pointer
 143  * @crtc: crtc to prepare for pageflip on
 144  *
 145  * Pre-pageflip callback (evergreen+).
 146  * Enables the pageflip irq (vblank irq).
 147  */
 148 void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
 149 {
 150         /* enable the pflip int */
 151         radeon_irq_kms_pflip_irq_get(rdev, crtc);
 152 }
 153
 154 /**
 155  * evergreen_post_page_flip - pos-pageflip callback.
 156  *
 157  * @rdev: radeon_device pointer
 158  * @crtc: crtc to cleanup pageflip on
 159  *
 160  * Post-pageflip callback (evergreen+).
 161  * Disables the pageflip irq (vblank irq).
 162  */
 163 void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
 164 {
 165         /* disable the pflip int */
 166         radeon_irq_kms_pflip_irq_put(rdev, crtc);
 167 }
 168
 169 /**
 170  * evergreen_page_flip - pageflip callback.
 171  *
 172  * @rdev: radeon_device pointer
 173  * @crtc_id: crtc to cleanup pageflip on
 174  * @crtc_base: new address of the crtc (GPU MC address)
 175  *
 176  * Does the actual pageflip (evergreen+).
 177  * During vblank we take the crtc lock and wait for the update_pending
 178  * bit to go high, when it does, we release the lock, and allow the
 179  * double buffered update to take place.
 180  * Returns the current update pending status.
 181  */
 182 u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
 183 {
 184         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 185         u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
 186         int i;
 187
 188         /* Lock the graphics update lock */
 189         tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
 190         WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
 191
 192         /* update the scanout addresses */
 193         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
 194                upper_32_bits(crtc_base));
 195         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 196                (u32)crtc_base);
 197
 198         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
 199                upper_32_bits(crtc_base));
 200         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 201                (u32)crtc_base);
 202
 203         /* Wait for update_pending to go high. */
 204         for (i = 0; i < rdev->usec_timeout; i++) {
 205                 if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING)
 206                         break;
 207                 DRM_UDELAY(1);
 208         }
 209         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
 210
 211         /* Unlock the lock, so double-buffering can take place inside vblank */
 212         tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
 213         WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
 214
 215         /* Return current update_pending status: */
 216         return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
 217 }
 218
 219 /* get temperature in millidegrees */
 220 int evergreen_get_temp(struct radeon_device *rdev)
 221 {
 222         u32 temp, toffset;
 223         int actual_temp = 0;
 224
 225         if (rdev->family == CHIP_JUNIPER) {
 226                 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
 227                         TOFFSET_SHIFT;
 228                 temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >>
 229                         TS0_ADC_DOUT_SHIFT;
 230
 231                 if (toffset & 0x100)
 232                         actual_temp = temp / 2 - (0x200 - toffset);
 233                 else
 234                         actual_temp = temp / 2 + toffset;
 235
 236                 actual_temp = actual_temp * 1000;
 237
 238         } else {
 239                 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
 240                         ASIC_T_SHIFT;
 241
 242                 if (temp & 0x400)
 243                         actual_temp = -256;
 244                 else if (temp & 0x200)
 245                         actual_temp = 255;
 246                 else if (temp & 0x100) {
 247                         actual_temp = temp & 0x1ff;
 248                         actual_temp |= ~0x1ff;
 249                 } else
 250                         actual_temp = temp & 0xff;
 251
 252                 actual_temp = (actual_temp * 1000) / 2;
 253         }
 254
 255         return actual_temp;
 256 }
 257
 258 int sumo_get_temp(struct radeon_device *rdev)
 259 {
 260         u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
 261         int actual_temp = temp - 49;
 262
 263         return actual_temp * 1000;
 264 }
 265
 266 /**
 267  * sumo_pm_init_profile - Initialize power profiles callback.
 268  *
 269  * @rdev: radeon_device pointer
 270  *
 271  * Initialize the power states used in profile mode
 272  * (sumo, trinity, SI).
 273  * Used for profile mode only.
 274  */
 275 void sumo_pm_init_profile(struct radeon_device *rdev)
 276 {
 277         int idx;
 278
 279         /* default */
 280         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 281         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 282         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 283         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 284
 285         /* low,mid sh/mh */
 286         if (rdev->flags & RADEON_IS_MOBILITY)
 287                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 288         else
 289                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 290
 291         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
 292         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
 293         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 294         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 295
 296         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
 297         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
 298         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 299         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 300
 301         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
 302         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
 303         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 304         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 305
 306         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
 307         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
 308         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 309         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 310
 311         /* high sh/mh */
 312         idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 313         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
 314         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
 315         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 316         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx =
 317                 rdev->pm.power_state[idx].num_clock_modes - 1;
 318
 319         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
 320         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
 321         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 322         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx =
 323                 rdev->pm.power_state[idx].num_clock_modes - 1;
 324 }
 325
 326 /**
 327  * btc_pm_init_profile - Initialize power profiles callback.
 328  *
 329  * @rdev: radeon_device pointer
 330  *
 331  * Initialize the power states used in profile mode
 332  * (BTC, cayman).
 333  * Used for profile mode only.
 334  */
 335 void btc_pm_init_profile(struct radeon_device *rdev)
 336 {
 337         int idx;
 338
 339         /* default */
 340         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 341         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 342         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 343         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 344         /* starting with BTC, there is one state that is used for both
 345          * MH and SH.  Difference is that we always use the high clock index for
 346          * mclk.
 347          */
 348         if (rdev->flags & RADEON_IS_MOBILITY)
 349                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 350         else
 351                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 352         /* low sh */
 353         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
 354         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
 355         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 356         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 357         /* mid sh */
 358         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
 359         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
 360         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 361         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 362         /* high sh */
 363         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
 364         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
 365         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 366         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 367         /* low mh */
 368         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
 369         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
 370         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 371         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 372         /* mid mh */
 373         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
 374         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
 375         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 376         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 377         /* high mh */
 378         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
 379         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
 380         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 381         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 382 }
 383
 384 /**
 385  * evergreen_pm_misc - set additional pm hw parameters callback.
 386  *
 387  * @rdev: radeon_device pointer
 388  *
 389  * Set non-clock parameters associated with a power state
 390  * (voltage, etc.) (evergreen+).
 391  */
 392 void evergreen_pm_misc(struct radeon_device *rdev)
 393 {
 394         int req_ps_idx = rdev->pm.requested_power_state_index;
 395         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 396         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 397         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 398
 399         if (voltage->type == VOLTAGE_SW) {
 400                 /* 0xff01 is a flag rather then an actual voltage */
 401                 if (voltage->voltage == 0xff01)
 402                         return;
 403                 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
 404                         radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
 405                         rdev->pm.current_vddc = voltage->voltage;
 406                         DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
 407                 }
 408                 /* 0xff01 is a flag rather then an actual voltage */
 409                 if (voltage->vddci == 0xff01)
 410                         return;
 411                 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
 412                         radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
 413                         rdev->pm.current_vddci = voltage->vddci;
 414                         DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);
 415                 }
 416         }
 417 }
 418
 419 /**
 420  * evergreen_pm_prepare - pre-power state change callback.
 421  *
 422  * @rdev: radeon_device pointer
 423  *
 424  * Prepare for a power state change (evergreen+).
 425  */
 426 void evergreen_pm_prepare(struct radeon_device *rdev)
 427 {
 428         struct drm_device *ddev = rdev->ddev;
 429         struct drm_crtc *crtc;
 430         struct radeon_crtc *radeon_crtc;
 431         u32 tmp;
 432
 433         /* disable any active CRTCs */
 434         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 435                 radeon_crtc = to_radeon_crtc(crtc);
 436                 if (radeon_crtc->enabled) {
 437                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
 438                         tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
 439                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 440                 }
 441         }
 442 }
 443
 444 /**
 445  * evergreen_pm_finish - post-power state change callback.
 446  *
 447  * @rdev: radeon_device pointer
 448  *
 449  * Clean up after a power state change (evergreen+).
 450  */
 451 void evergreen_pm_finish(struct radeon_device *rdev)
 452 {
 453         struct drm_device *ddev = rdev->ddev;
 454         struct drm_crtc *crtc;
 455         struct radeon_crtc *radeon_crtc;
 456         u32 tmp;
 457
 458         /* enable any active CRTCs */
 459         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 460                 radeon_crtc = to_radeon_crtc(crtc);
 461                 if (radeon_crtc->enabled) {
 462                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
 463                         tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
 464                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 465                 }
 466         }
 467 }
 468
 469 /**
 470  * evergreen_hpd_sense - hpd sense callback.
 471  *
 472  * @rdev: radeon_device pointer
 473  * @hpd: hpd (hotplug detect) pin
 474  *
 475  * Checks if a digital monitor is connected (evergreen+).
 476  * Returns true if connected, false if not connected.
 477  */
 478 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 479 {
 480         bool connected = false;
 481
 482         switch (hpd) {
 483         case RADEON_HPD_1:
 484                 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 485                         connected = true;
 486                 break;
 487         case RADEON_HPD_2:
 488                 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 489                         connected = true;
 490                 break;
 491         case RADEON_HPD_3:
 492                 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 493                         connected = true;
 494                 break;
 495         case RADEON_HPD_4:
 496                 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 497                         connected = true;
 498                 break;
 499         case RADEON_HPD_5:
 500                 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 501                         connected = true;
 502                 break;
 503         case RADEON_HPD_6:
 504                 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 505                         connected = true;
 506                         break;
 507         default:
 508                 break;
 509         }
 510
 511         return connected;
 512 }
 513
 514 /**
 515  * evergreen_hpd_set_polarity - hpd set polarity callback.
 516  *
 517  * @rdev: radeon_device pointer
 518  * @hpd: hpd (hotplug detect) pin
 519  *
 520  * Set the polarity of the hpd pin (evergreen+).
 521  */
 522 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
 523                                 enum radeon_hpd_id hpd)
 524 {
 525         u32 tmp;
 526         bool connected = evergreen_hpd_sense(rdev, hpd);
 527
 528         switch (hpd) {
 529         case RADEON_HPD_1:
 530                 tmp = RREG32(DC_HPD1_INT_CONTROL);
 531                 if (connected)
 532                         tmp &= ~DC_HPDx_INT_POLARITY;
 533                 else
 534                         tmp |= DC_HPDx_INT_POLARITY;
 535                 WREG32(DC_HPD1_INT_CONTROL, tmp);
 536                 break;
 537         case RADEON_HPD_2:
 538                 tmp = RREG32(DC_HPD2_INT_CONTROL);
 539                 if (connected)
 540                         tmp &= ~DC_HPDx_INT_POLARITY;
 541                 else
 542                         tmp |= DC_HPDx_INT_POLARITY;
 543                 WREG32(DC_HPD2_INT_CONTROL, tmp);
 544                 break;
 545         case RADEON_HPD_3:
 546                 tmp = RREG32(DC_HPD3_INT_CONTROL);
 547                 if (connected)
 548                         tmp &= ~DC_HPDx_INT_POLARITY;
 549                 else
 550                         tmp |= DC_HPDx_INT_POLARITY;
 551                 WREG32(DC_HPD3_INT_CONTROL, tmp);
 552                 break;
 553         case RADEON_HPD_4:
 554                 tmp = RREG32(DC_HPD4_INT_CONTROL);
 555                 if (connected)
 556                         tmp &= ~DC_HPDx_INT_POLARITY;
 557                 else
 558                         tmp |= DC_HPDx_INT_POLARITY;
 559                 WREG32(DC_HPD4_INT_CONTROL, tmp);
 560                 break;
 561         case RADEON_HPD_5:
 562                 tmp = RREG32(DC_HPD5_INT_CONTROL);
 563                 if (connected)
 564                         tmp &= ~DC_HPDx_INT_POLARITY;
 565                 else
 566                         tmp |= DC_HPDx_INT_POLARITY;
 567                 WREG32(DC_HPD5_INT_CONTROL, tmp);
 568                         break;
 569         case RADEON_HPD_6:
 570                 tmp = RREG32(DC_HPD6_INT_CONTROL);
 571                 if (connected)
 572                         tmp &= ~DC_HPDx_INT_POLARITY;
 573                 else
 574                         tmp |= DC_HPDx_INT_POLARITY;
 575                 WREG32(DC_HPD6_INT_CONTROL, tmp);
 576                 break;
 577         default:
 578                 break;
 579         }
 580 }
 581
 582 /**
 583  * evergreen_hpd_init - hpd setup callback.
 584  *
 585  * @rdev: radeon_device pointer
 586  *
 587  * Setup the hpd pins used by the card (evergreen+).
 588  * Enable the pin, set the polarity, and enable the hpd interrupts.
 589  */
 590 void evergreen_hpd_init(struct radeon_device *rdev)
 591 {
 592         struct drm_device *dev = rdev->ddev;
 593         struct drm_connector *connector;
 594         unsigned enabled = 0;
 595         u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
 596                 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
 597
 598         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 599                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 600                 switch (radeon_connector->hpd.hpd) {
 601                 case RADEON_HPD_1:
 602                         WREG32(DC_HPD1_CONTROL, tmp);
 603                         break;
 604                 case RADEON_HPD_2:
 605                         WREG32(DC_HPD2_CONTROL, tmp);
 606                         break;
 607                 case RADEON_HPD_3:
 608                         WREG32(DC_HPD3_CONTROL, tmp);
 609                         break;
 610                 case RADEON_HPD_4:
 611                         WREG32(DC_HPD4_CONTROL, tmp);
 612                         break;
 613                 case RADEON_HPD_5:
 614                         WREG32(DC_HPD5_CONTROL, tmp);
 615                         break;
 616                 case RADEON_HPD_6:
 617                         WREG32(DC_HPD6_CONTROL, tmp);
 618                         break;
 619                 default:
 620                         break;
 621                 }
 622                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 623                 enabled |= 1 << radeon_connector->hpd.hpd;
 624         }
 625         radeon_irq_kms_enable_hpd(rdev, enabled);
 626 }
 627
 628 /**
 629  * evergreen_hpd_fini - hpd tear down callback.
 630  *
 631  * @rdev: radeon_device pointer
 632  *
 633  * Tear down the hpd pins used by the card (evergreen+).
 634  * Disable the hpd interrupts.
 635  */
 636 void evergreen_hpd_fini(struct radeon_device *rdev)
 637 {
 638         struct drm_device *dev = rdev->ddev;
 639         struct drm_connector *connector;
 640         unsigned disabled = 0;
 641
 642         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 643                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 644                 switch (radeon_connector->hpd.hpd) {
 645                 case RADEON_HPD_1:
 646                         WREG32(DC_HPD1_CONTROL, 0);
 647                         break;
 648                 case RADEON_HPD_2:
 649                         WREG32(DC_HPD2_CONTROL, 0);
 650                         break;
 651                 case RADEON_HPD_3:
 652                         WREG32(DC_HPD3_CONTROL, 0);
 653                         break;
 654                 case RADEON_HPD_4:
 655                         WREG32(DC_HPD4_CONTROL, 0);
 656                         break;
 657                 case RADEON_HPD_5:
 658                         WREG32(DC_HPD5_CONTROL, 0);
 659                         break;
 660                 case RADEON_HPD_6:
 661                         WREG32(DC_HPD6_CONTROL, 0);
 662                         break;
 663                 default:
 664                         break;
 665                 }
 666                 disabled |= 1 << radeon_connector->hpd.hpd;
 667         }
 668         radeon_irq_kms_disable_hpd(rdev, disabled);
 669 }
 670
 671 /* watermark setup */
 672
 673 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
 674                                         struct radeon_crtc *radeon_crtc,
 675                                         struct drm_display_mode *mode,
 676                                         struct drm_display_mode *other_mode)
 677 {
 678         u32 tmp;
 679         /*
 680          * Line Buffer Setup
 681          * There are 3 line buffers, each one shared by 2 display controllers.
 682          * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
 683          * the display controllers.  The paritioning is done via one of four
 684          * preset allocations specified in bits 2:0:
 685          * first display controller
 686          *  0 - first half of lb (3840 * 2)
 687          *  1 - first 3/4 of lb (5760 * 2)
 688          *  2 - whole lb (7680 * 2), other crtc must be disabled
 689          *  3 - first 1/4 of lb (1920 * 2)
 690          * second display controller
 691          *  4 - second half of lb (3840 * 2)
 692          *  5 - second 3/4 of lb (5760 * 2)
 693          *  6 - whole lb (7680 * 2), other crtc must be disabled
 694          *  7 - last 1/4 of lb (1920 * 2)
 695          */
 696         /* this can get tricky if we have two large displays on a paired group
 697          * of crtcs.  Ideally for multiple large displays we'd assign them to
 698          * non-linked crtcs for maximum line buffer allocation.
 699          */
 700         if (radeon_crtc->base.enabled && mode) {
 701                 if (other_mode)
 702                         tmp = 0; /* 1/2 */
 703                 else
 704                         tmp = 2; /* whole */
 705         } else
 706                 tmp = 0;
 707
 708         /* second controller of the pair uses second half of the lb */
 709         if (radeon_crtc->crtc_id % 2)
 710                 tmp += 4;
 711         WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
 712
 713         if (radeon_crtc->base.enabled && mode) {
 714                 switch (tmp) {
 715                 case 0:
 716                 case 4:
 717                 default:
 718                         if (ASIC_IS_DCE5(rdev))
 719                                 return 4096 * 2;
 720                         else
 721                                 return 3840 * 2;
 722                 case 1:
 723                 case 5:
 724                         if (ASIC_IS_DCE5(rdev))
 725                                 return 6144 * 2;
 726                         else
 727                                 return 5760 * 2;
 728                 case 2:
 729                 case 6:
 730                         if (ASIC_IS_DCE5(rdev))
 731                                 return 8192 * 2;
 732                         else
 733                                 return 7680 * 2;
 734                 case 3:
 735                 case 7:
 736                         if (ASIC_IS_DCE5(rdev))
 737                                 return 2048 * 2;
 738                         else
 739                                 return 1920 * 2;
 740                 }
 741         }
 742
 743         /* controller not enabled, so no lb used */
 744         return 0;
 745 }
 746
 747 u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
 748 {
 749         u32 tmp = RREG32(MC_SHARED_CHMAP);
 750
 751         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
 752         case 0:
 753         default:
 754                 return 1;
 755         case 1:
 756                 return 2;
 757         case 2:
 758                 return 4;
 759         case 3:
 760                 return 8;
 761         }
 762 }
 763
 764 struct evergreen_wm_params {
 765         u32 dram_channels; /* number of dram channels */
 766         u32 yclk;          /* bandwidth per dram data pin in kHz */
 767         u32 sclk;          /* engine clock in kHz */
 768         u32 disp_clk;      /* display clock in kHz */
 769         u32 src_width;     /* viewport width */
 770         u32 active_time;   /* active display time in ns */
 771         u32 blank_time;    /* blank time in ns */
 772         bool interlaced;    /* mode is interlaced */
 773         fixed20_12 vsc;    /* vertical scale ratio */
 774         u32 num_heads;     /* number of active crtcs */
 775         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 776         u32 lb_size;       /* line buffer allocated to pipe */
 777         u32 vtaps;         /* vertical scaler taps */
 778 };
 779
 780 static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
 781 {
 782         /* Calculate DRAM Bandwidth and the part allocated to display. */
 783         fixed20_12 dram_efficiency; /* 0.7 */
 784         fixed20_12 yclk, dram_channels, bandwidth;
 785         fixed20_12 a;
 786
 787         a.full = dfixed_const(1000);
 788         yclk.full = dfixed_const(wm->yclk);
 789         yclk.full = dfixed_div(yclk, a);
 790         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 791         a.full = dfixed_const(10);
 792         dram_efficiency.full = dfixed_const(7);
 793         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 794         bandwidth.full = dfixed_mul(dram_channels, yclk);
 795         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 796
 797         return dfixed_trunc(bandwidth);
 798 }
 799
 800 static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
 801 {
 802         /* Calculate DRAM Bandwidth and the part allocated to display. */
 803         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 804         fixed20_12 yclk, dram_channels, bandwidth;
 805         fixed20_12 a;
 806
 807         a.full = dfixed_const(1000);
 808         yclk.full = dfixed_const(wm->yclk);
 809         yclk.full = dfixed_div(yclk, a);
 810         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 811         a.full = dfixed_const(10);
 812         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 813         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 814         bandwidth.full = dfixed_mul(dram_channels, yclk);
 815         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 816
 817         return dfixed_trunc(bandwidth);
 818 }
 819
 820 static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
 821 {
 822         /* Calculate the display Data return Bandwidth */
 823         fixed20_12 return_efficiency; /* 0.8 */
 824         fixed20_12 sclk, bandwidth;
 825         fixed20_12 a;
 826
 827         a.full = dfixed_const(1000);
 828         sclk.full = dfixed_const(wm->sclk);
 829         sclk.full = dfixed_div(sclk, a);
 830         a.full = dfixed_const(10);
 831         return_efficiency.full = dfixed_const(8);
 832         return_efficiency.full = dfixed_div(return_efficiency, a);
 833         a.full = dfixed_const(32);
 834         bandwidth.full = dfixed_mul(a, sclk);
 835         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 836
 837         return dfixed_trunc(bandwidth);
 838 }
 839
 840 static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
 841 {
 842         /* Calculate the DMIF Request Bandwidth */
 843         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
 844         fixed20_12 disp_clk, bandwidth;
 845         fixed20_12 a;
 846
 847         a.full = dfixed_const(1000);
 848         disp_clk.full = dfixed_const(wm->disp_clk);
 849         disp_clk.full = dfixed_div(disp_clk, a);
 850         a.full = dfixed_const(10);
 851         disp_clk_request_efficiency.full = dfixed_const(8);
 852         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
 853         a.full = dfixed_const(32);
 854         bandwidth.full = dfixed_mul(a, disp_clk);
 855         bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
 856
 857         return dfixed_trunc(bandwidth);
 858 }
 859
 860 static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
 861 {
 862         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
 863         u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
 864         u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
 865         u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
 866
 867         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
 868 }
 869
 870 static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
 871 {
 872         /* Calculate the display mode Average Bandwidth
 873          * DisplayMode should contain the source and destination dimensions,
 874          * timing, etc.
 875          */
 876         fixed20_12 bpp;
 877         fixed20_12 line_time;
 878         fixed20_12 src_width;
 879         fixed20_12 bandwidth;
 880         fixed20_12 a;
 881
 882         a.full = dfixed_const(1000);
 883         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
 884         line_time.full = dfixed_div(line_time, a);
 885         bpp.full = dfixed_const(wm->bytes_per_pixel);
 886         src_width.full = dfixed_const(wm->src_width);
 887         bandwidth.full = dfixed_mul(src_width, bpp);
 888         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
 889         bandwidth.full = dfixed_div(bandwidth, line_time);
 890
 891         return dfixed_trunc(bandwidth);
 892 }
 893
 894 static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
 895 {
 896         /* First calcualte the latency in ns */
 897         u32 mc_latency = 2000; /* 2000 ns. */
 898         u32 available_bandwidth = evergreen_available_bandwidth(wm);
 899         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
 900         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
 901         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
 902         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
 903                 (wm->num_heads * cursor_line_pair_return_time);
 904         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
 905         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
 906         fixed20_12 a, b, c;
 907
 908         if (wm->num_heads == 0)
 909                 return 0;
 910
 911         a.full = dfixed_const(2);
 912         b.full = dfixed_const(1);
 913         if ((wm->vsc.full > a.full) ||
 914             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
 915             (wm->vtaps >= 5) ||
 916             ((wm->vsc.full >= a.full) && wm->interlaced))
 917                 max_src_lines_per_dst_line = 4;
 918         else
 919                 max_src_lines_per_dst_line = 2;
 920
 921         a.full = dfixed_const(available_bandwidth);
 922         b.full = dfixed_const(wm->num_heads);
 923         a.full = dfixed_div(a, b);
 924
 925         b.full = dfixed_const(1000);
 926         c.full = dfixed_const(wm->disp_clk);
 927         b.full = dfixed_div(c, b);
 928         c.full = dfixed_const(wm->bytes_per_pixel);
 929         b.full = dfixed_mul(b, c);
 930
 931         lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
 932
 933         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
 934         b.full = dfixed_const(1000);
 935         c.full = dfixed_const(lb_fill_bw);
 936         b.full = dfixed_div(c, b);
 937         a.full = dfixed_div(a, b);
 938         line_fill_time = dfixed_trunc(a);
 939
 940         if (line_fill_time < wm->active_time)
 941                 return latency;
 942         else
 943                 return latency + (line_fill_time - wm->active_time);
 944
 945 }
 946
 947 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
 948 {
 949         if (evergreen_average_bandwidth(wm) <=
 950             (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
 951                 return true;
 952         else
 953                 return false;
 954 };
 955
 956 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
 957 {
 958         if (evergreen_average_bandwidth(wm) <=
 959             (evergreen_available_bandwidth(wm) / wm->num_heads))
 960                 return true;
 961         else
 962                 return false;
 963 };
 964
 965 static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
 966 {
 967         u32 lb_partitions = wm->lb_size / wm->src_width;
 968         u32 line_time = wm->active_time + wm->blank_time;
 969         u32 latency_tolerant_lines;
 970         u32 latency_hiding;
 971         fixed20_12 a;
 972
 973         a.full = dfixed_const(1);
 974         if (wm->vsc.full > a.full)
 975                 latency_tolerant_lines = 1;
 976         else {
 977                 if (lb_partitions <= (wm->vtaps + 1))
 978                         latency_tolerant_lines = 1;
 979                 else
 980                         latency_tolerant_lines = 2;
 981         }
 982
 983         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
 984
 985         if (evergreen_latency_watermark(wm) <= latency_hiding)
 986                 return true;
 987         else
 988                 return false;
 989 }
 990
 991 static void evergreen_program_watermarks(struct radeon_device *rdev,
 992                                          struct radeon_crtc *radeon_crtc,
 993                                          u32 lb_size, u32 num_heads)
 994 {
 995         struct drm_display_mode *mode = &radeon_crtc->base.mode;
 996         struct evergreen_wm_params wm;
 997         u32 pixel_period;
 998         u32 line_time = 0;
 999         u32 latency_watermark_a = 0, latency_watermark_b = 0;
1000         u32 priority_a_mark = 0, priority_b_mark = 0;
1001         u32 priority_a_cnt = PRIORITY_OFF;
1002         u32 priority_b_cnt = PRIORITY_OFF;
1003         u32 pipe_offset = radeon_crtc->crtc_id * 16;
1004         u32 tmp, arb_control3;
1005         fixed20_12 a, b, c;
1006
1007         if (radeon_crtc->base.enabled && num_heads && mode) {
1008                 pixel_period = 1000000 / (u32)mode->clock;
1009                 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1010                 priority_a_cnt = 0;
1011                 priority_b_cnt = 0;
1012
1013                 wm.yclk = rdev->pm.current_mclk * 10;
1014                 wm.sclk = rdev->pm.current_sclk * 10;
1015                 wm.disp_clk = mode->clock;
1016                 wm.src_width = mode->crtc_hdisplay;
1017                 wm.active_time = mode->crtc_hdisplay * pixel_period;
1018                 wm.blank_time = line_time - wm.active_time;
1019                 wm.interlaced = false;
1020                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1021                         wm.interlaced = true;
1022                 wm.vsc = radeon_crtc->vsc;
1023                 wm.vtaps = 1;
1024                 if (radeon_crtc->rmx_type != RMX_OFF)
1025                         wm.vtaps = 2;
1026                 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
1027                 wm.lb_size = lb_size;
1028                 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
1029                 wm.num_heads = num_heads;
1030
1031                 /* set for high clocks */
1032                 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
1033                 /* set for low clocks */
1034                 /* wm.yclk = low clk; wm.sclk = low clk */
1035                 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
1036
1037                 /* possibly force display priority to high */
1038                 /* should really do this at mode validation time... */
1039                 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
1040                     !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
1041                     !evergreen_check_latency_hiding(&wm) ||
1042                     (rdev->disp_priority == 2)) {
1043                         DRM_DEBUG_KMS("force priority to high\n");
1044                         priority_a_cnt |= PRIORITY_ALWAYS_ON;
1045                         priority_b_cnt |= PRIORITY_ALWAYS_ON;
1046                 }
1047
1048                 a.full = dfixed_const(1000);
1049                 b.full = dfixed_const(mode->clock);
1050                 b.full = dfixed_div(b, a);
1051                 c.full = dfixed_const(latency_watermark_a);
1052                 c.full = dfixed_mul(c, b);
1053                 c.full = dfixed_mul(c, radeon_crtc->hsc);
1054                 c.full = dfixed_div(c, a);
1055                 a.full = dfixed_const(16);
1056                 c.full = dfixed_div(c, a);
1057                 priority_a_mark = dfixed_trunc(c);
1058                 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
1059
1060                 a.full = dfixed_const(1000);
1061                 b.full = dfixed_const(mode->clock);
1062                 b.full = dfixed_div(b, a);
1063                 c.full = dfixed_const(latency_watermark_b);
1064                 c.full = dfixed_mul(c, b);
1065                 c.full = dfixed_mul(c, radeon_crtc->hsc);
1066                 c.full = dfixed_div(c, a);
1067                 a.full = dfixed_const(16);
1068                 c.full = dfixed_div(c, a);
1069                 priority_b_mark = dfixed_trunc(c);
1070                 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
1071         }
1072
1073         /* select wm A */
1074         arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
1075         tmp = arb_control3;
1076         tmp &= ~LATENCY_WATERMARK_MASK(3);
1077         tmp |= LATENCY_WATERMARK_MASK(1);
1078         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
1079         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
1080                (LATENCY_LOW_WATERMARK(latency_watermark_a) |
1081                 LATENCY_HIGH_WATERMARK(line_time)));
1082         /* select wm B */
1083         tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
1084         tmp &= ~LATENCY_WATERMARK_MASK(3);
1085         tmp |= LATENCY_WATERMARK_MASK(2);
1086         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
1087         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
1088                (LATENCY_LOW_WATERMARK(latency_watermark_b) |
1089                 LATENCY_HIGH_WATERMARK(line_time)));
1090         /* restore original selection */
1091         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
1092
1093         /* write the priority marks */
1094         WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
1095         WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
1096
1097 }
1098
1099 /**
1100  * evergreen_bandwidth_update - update display watermarks callback.
1101  *
1102  * @rdev: radeon_device pointer
1103  *
1104  * Update the display watermarks based on the requested mode(s)
1105  * (evergreen+).
1106  */
1107 void evergreen_bandwidth_update(struct radeon_device *rdev)
1108 {
1109         struct drm_display_mode *mode0 = NULL;
1110         struct drm_display_mode *mode1 = NULL;
1111         u32 num_heads = 0, lb_size;
1112         int i;
1113
1114         radeon_update_display_priority(rdev);
1115
1116         for (i = 0; i < rdev->num_crtc; i++) {
1117                 if (rdev->mode_info.crtcs[i]->base.enabled)
1118                         num_heads++;
1119         }
1120         for (i = 0; i < rdev->num_crtc; i += 2) {
1121                 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
1122                 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
1123                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
1124                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
1125                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
1126                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
1127         }
1128 }
1129
1130 /**
1131  * evergreen_mc_wait_for_idle - wait for MC idle callback.
1132  *
1133  * @rdev: radeon_device pointer
1134  *
1135  * Wait for the MC (memory controller) to be idle.
1136  * (evergreen+).
1137  * Returns 0 if the MC is idle, -1 if not.
1138  */
1139 int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
1140 {
1141         unsigned i;
1142         u32 tmp;
1143
1144         for (i = 0; i < rdev->usec_timeout; i++) {
1145                 /* read MC_STATUS */
1146                 tmp = RREG32(SRBM_STATUS) & 0x1F00;
1147                 if (!tmp)
1148                         return 0;
1149                 DRM_UDELAY(1);
1150         }
1151         return -1;
1152 }
1153
1154 /*
1155  * GART
1156  */
1157 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
1158 {
1159         unsigned i;
1160         u32 tmp;
1161
1162         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1163
1164         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
1165         for (i = 0; i < rdev->usec_timeout; i++) {
1166                 /* read MC_STATUS */
1167                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
1168                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
1169                 if (tmp == 2) {
1170                         DRM_ERROR("[drm] r600 flush TLB failed\n");
1171                         return;
1172                 }
1173                 if (tmp) {
1174                         return;
1175                 }
1176                 DRM_UDELAY(1);
1177         }
1178 }
1179
1180 static int evergreen_pcie_gart_enable(struct radeon_device *rdev)
1181 {
1182         u32 tmp;
1183         int r;
1184
1185         if (rdev->gart.robj == NULL) {
1186                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1187                 return -EINVAL;
1188         }
1189         r = radeon_gart_table_vram_pin(rdev);
1190         if (r)
1191                 return r;
1192         radeon_gart_restore(rdev);
1193         /* Setup L2 cache */
1194         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1195                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1196                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1197         WREG32(VM_L2_CNTL2, 0);
1198         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1199         /* Setup TLB control */
1200         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1201                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1202                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1203                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1204         if (rdev->flags & RADEON_IS_IGP) {
1205                 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
1206                 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
1207                 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
1208         } else {
1209                 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1210                 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1211                 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1212                 if ((rdev->family == CHIP_JUNIPER) ||
1213                     (rdev->family == CHIP_CYPRESS) ||
1214                     (rdev->family == CHIP_HEMLOCK) ||
1215                     (rdev->family == CHIP_BARTS))
1216                         WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
1217         }
1218         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1219         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1220         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1221         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1222         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1223         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1224         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1225         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1226                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1227         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1228                         (u32)(rdev->dummy_page.addr >> 12));
1229         WREG32(VM_CONTEXT1_CNTL, 0);
1230
1231         evergreen_pcie_gart_tlb_flush(rdev);
1232         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1233                  (unsigned)(rdev->mc.gtt_size >> 20),
1234                  (unsigned long long)rdev->gart.table_addr);
1235         rdev->gart.ready = true;
1236         return 0;
1237 }
1238
1239 static void evergreen_pcie_gart_disable(struct radeon_device *rdev)
1240 {
1241         u32 tmp;
1242
1243         /* Disable all tables */
1244         WREG32(VM_CONTEXT0_CNTL, 0);
1245         WREG32(VM_CONTEXT1_CNTL, 0);
1246
1247         /* Setup L2 cache */
1248         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1249                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1250         WREG32(VM_L2_CNTL2, 0);
1251         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1252         /* Setup TLB control */
1253         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1254         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1255         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1256         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1257         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1258         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1259         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1260         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1261         radeon_gart_table_vram_unpin(rdev);
1262 }
1263
1264 static void evergreen_pcie_gart_fini(struct radeon_device *rdev)
1265 {
1266         evergreen_pcie_gart_disable(rdev);
1267         radeon_gart_table_vram_free(rdev);
1268         radeon_gart_fini(rdev);
1269 }
1270
1271
1272 static void evergreen_agp_enable(struct radeon_device *rdev)
1273 {
1274         u32 tmp;
1275
1276         /* Setup L2 cache */
1277         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1278                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1279                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1280         WREG32(VM_L2_CNTL2, 0);
1281         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1282         /* Setup TLB control */
1283         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1284                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1285                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1286                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1287         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1288         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1289         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1290         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1291         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1292         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1293         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1294         WREG32(VM_CONTEXT0_CNTL, 0);
1295         WREG32(VM_CONTEXT1_CNTL, 0);
1296 }
1297
1298 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
1299 {
1300         u32 crtc_enabled, tmp, frame_count, blackout;
1301         int i, j;
1302
1303         save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
1304         save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
1305
1306         /* disable VGA render */
1307         WREG32(VGA_RENDER_CONTROL, 0);
1308         /* blank the display controllers */
1309         for (i = 0; i < rdev->num_crtc; i++) {
1310                 crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN;
1311                 if (crtc_enabled) {
1312                         save->crtc_enabled[i] = true;
1313                         if (ASIC_IS_DCE6(rdev)) {
1314                                 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
1315                                 if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
1316                                         radeon_wait_for_vblank(rdev, i);
1317                                         tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
1318                                         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
1319                                         WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
1320                                         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
1321                                 }
1322                         } else {
1323                                 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
1324                                 if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {
1325                                         radeon_wait_for_vblank(rdev, i);
1326                                         tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
1327                                         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
1328                                         WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
1329                                         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
1330                                 }
1331                         }
1332                         /* wait for the next frame */
1333                         frame_count = radeon_get_vblank_counter(rdev, i);
1334                         for (j = 0; j < rdev->usec_timeout; j++) {
1335                                 if (radeon_get_vblank_counter(rdev, i) != frame_count)
1336                                         break;
1337                                 DRM_UDELAY(1);
1338                         }
1339                 } else {
1340                         save->crtc_enabled[i] = false;
1341                 }
1342         }
1343
1344         radeon_mc_wait_for_idle(rdev);
1345
1346         blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
1347         if ((blackout & BLACKOUT_MODE_MASK) != 1) {
1348                 /* Block CPU access */
1349                 WREG32(BIF_FB_EN, 0);
1350                 /* blackout the MC */
1351                 blackout &= ~BLACKOUT_MODE_MASK;
1352                 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
1353         }
1354         /* wait for the MC to settle */
1355         DRM_UDELAY(100);
1356 }
1357
1358 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
1359 {
1360         u32 tmp, frame_count;
1361         int i, j;
1362
1363         /* update crtc base addresses */
1364         for (i = 0; i < rdev->num_crtc; i++) {
1365                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
1366                        upper_32_bits(rdev->mc.vram_start));
1367                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
1368                        upper_32_bits(rdev->mc.vram_start));
1369                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
1370                        (u32)rdev->mc.vram_start);
1371                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
1372                        (u32)rdev->mc.vram_start);
1373         }
1374         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1375         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1376
1377         /* unblackout the MC */
1378         tmp = RREG32(MC_SHARED_BLACKOUT_CNTL);
1379         tmp &= ~BLACKOUT_MODE_MASK;
1380         WREG32(MC_SHARED_BLACKOUT_CNTL, tmp);
1381         /* allow CPU access */
1382         WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
1383
1384         for (i = 0; i < rdev->num_crtc; i++) {
1385                 if (save->crtc_enabled[i]) {
1386                         if (ASIC_IS_DCE6(rdev)) {
1387                                 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
1388                                 tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
1389                                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
1390                                 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
1391                                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
1392                         } else {
1393                                 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
1394                                 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
1395                                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
1396                                 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
1397                                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
1398                         }
1399                         /* wait for the next frame */
1400                         frame_count = radeon_get_vblank_counter(rdev, i);
1401                         for (j = 0; j < rdev->usec_timeout; j++) {
1402                                 if (radeon_get_vblank_counter(rdev, i) != frame_count)
1403                                         break;
1404                                 DRM_UDELAY(1);
1405                         }
1406                 }
1407         }
1408         /* Unlock vga access */
1409         WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1410         DRM_MDELAY(1);
1411         WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1412 }
1413
1414 void evergreen_mc_program(struct radeon_device *rdev)
1415 {
1416         struct evergreen_mc_save save;
1417         u32 tmp;
1418         int i, j;
1419
1420         /* Initialize HDP */
1421         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1422                 WREG32((0x2c14 + j), 0x00000000);
1423                 WREG32((0x2c18 + j), 0x00000000);
1424                 WREG32((0x2c1c + j), 0x00000000);
1425                 WREG32((0x2c20 + j), 0x00000000);
1426                 WREG32((0x2c24 + j), 0x00000000);
1427         }
1428         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1429
1430         evergreen_mc_stop(rdev, &save);
1431         if (evergreen_mc_wait_for_idle(rdev)) {
1432                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1433         }
1434         /* Lockout access through VGA aperture*/
1435         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1436         /* Update configuration */
1437         if (rdev->flags & RADEON_IS_AGP) {
1438                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1439                         /* VRAM before AGP */
1440                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1441                                 rdev->mc.vram_start >> 12);
1442                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1443                                 rdev->mc.gtt_end >> 12);
1444                 } else {
1445                         /* VRAM after AGP */
1446                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1447                                 rdev->mc.gtt_start >> 12);
1448                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1449                                 rdev->mc.vram_end >> 12);
1450                 }
1451         } else {
1452                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1453                         rdev->mc.vram_start >> 12);
1454                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1455                         rdev->mc.vram_end >> 12);
1456         }
1457         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1458         /* llano/ontario only */
1459         if ((rdev->family == CHIP_PALM) ||
1460             (rdev->family == CHIP_SUMO) ||
1461             (rdev->family == CHIP_SUMO2)) {
1462                 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1463                 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1464                 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1465                 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1466         }
1467         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1468         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1469         WREG32(MC_VM_FB_LOCATION, tmp);
1470         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1471         WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
1472         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1473         if (rdev->flags & RADEON_IS_AGP) {
1474                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1475                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1476                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1477         } else {
1478                 WREG32(MC_VM_AGP_BASE, 0);
1479                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1480                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1481         }
1482         if (evergreen_mc_wait_for_idle(rdev)) {
1483                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1484         }
1485         evergreen_mc_resume(rdev, &save);
1486         /* we need to own VRAM, so turn off the VGA renderer here
1487          * to stop it overwriting our objects */
1488         rv515_vga_render_disable(rdev);
1489 }
1490
1491 /*
1492  * CP.
1493  */
1494 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1495 {
1496         struct radeon_ring *ring = &rdev->ring[ib->ring];
1497         u32 next_rptr;
1498
1499         /* set to DX10/11 mode */
1500         radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1501         radeon_ring_write(ring, 1);
1502
1503         if (ring->rptr_save_reg) {
1504                 next_rptr = ring->wptr + 3 + 4;
1505                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1506                 radeon_ring_write(ring, ((ring->rptr_save_reg -
1507                                           PACKET3_SET_CONFIG_REG_START) >> 2));
1508                 radeon_ring_write(ring, next_rptr);
1509         } else if (rdev->wb.enabled) {
1510                 next_rptr = ring->wptr + 5 + 4;
1511                 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
1512                 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
1513                 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
1514                 radeon_ring_write(ring, next_rptr);
1515                 radeon_ring_write(ring, 0);
1516         }
1517
1518         radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1519         radeon_ring_write(ring,
1520 #ifdef __BIG_ENDIAN
1521                           (2 << 0) |
1522 #endif
1523                           (ib->gpu_addr & 0xFFFFFFFC));
1524         radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
1525         radeon_ring_write(ring, ib->length_dw);
1526 }
1527
1528
1529 static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1530 {
1531         const __be32 *fw_data;
1532         int i;
1533
1534         if (!rdev->me_fw || !rdev->pfp_fw)
1535                 return -EINVAL;
1536
1537         r700_cp_stop(rdev);
1538         WREG32(CP_RB_CNTL,
1539 #ifdef __BIG_ENDIAN
1540                BUF_SWAP_32BIT |
1541 #endif
1542                RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1543
1544         fw_data = (const __be32 *)rdev->pfp_fw->data;
1545         WREG32(CP_PFP_UCODE_ADDR, 0);
1546         for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1547                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1548         WREG32(CP_PFP_UCODE_ADDR, 0);
1549
1550         fw_data = (const __be32 *)rdev->me_fw->data;
1551         WREG32(CP_ME_RAM_WADDR, 0);
1552         for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1553                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1554
1555         WREG32(CP_PFP_UCODE_ADDR, 0);
1556         WREG32(CP_ME_RAM_WADDR, 0);
1557         WREG32(CP_ME_RAM_RADDR, 0);
1558         return 0;
1559 }
1560
1561 static int evergreen_cp_start(struct radeon_device *rdev)
1562 {
1563         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1564         int r, i;
1565         uint32_t cp_me;
1566
1567         r = radeon_ring_lock(rdev, ring, 7);
1568         if (r) {
1569                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1570                 return r;
1571         }
1572         radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1573         radeon_ring_write(ring, 0x1);
1574         radeon_ring_write(ring, 0x0);
1575         radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1);
1576         radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1577         radeon_ring_write(ring, 0);
1578         radeon_ring_write(ring, 0);
1579         radeon_ring_unlock_commit(rdev, ring);
1580
1581         cp_me = 0xff;
1582         WREG32(CP_ME_CNTL, cp_me);
1583
1584         r = radeon_ring_lock(rdev, ring, evergreen_default_size + 19);
1585         if (r) {
1586                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1587                 return r;
1588         }
1589
1590         /* setup clear context state */
1591         radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1592         radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1593
1594         for (i = 0; i < evergreen_default_size; i++)
1595                 radeon_ring_write(ring, evergreen_default_state[i]);
1596
1597         radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1598         radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1599
1600         /* set clear context state */
1601         radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1602         radeon_ring_write(ring, 0);
1603
1604         /* SQ_VTX_BASE_VTX_LOC */
1605         radeon_ring_write(ring, 0xc0026f00);
1606         radeon_ring_write(ring, 0x00000000);
1607         radeon_ring_write(ring, 0x00000000);
1608         radeon_ring_write(ring, 0x00000000);
1609
1610         /* Clear consts */
1611         radeon_ring_write(ring, 0xc0036f00);
1612         radeon_ring_write(ring, 0x00000bc4);
1613         radeon_ring_write(ring, 0xffffffff);
1614         radeon_ring_write(ring, 0xffffffff);
1615         radeon_ring_write(ring, 0xffffffff);
1616
1617         radeon_ring_write(ring, 0xc0026900);
1618         radeon_ring_write(ring, 0x00000316);
1619         radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1620         radeon_ring_write(ring, 0x00000010); /*  */
1621
1622         radeon_ring_unlock_commit(rdev, ring);
1623
1624         return 0;
1625 }
1626
1627 static int evergreen_cp_resume(struct radeon_device *rdev)
1628 {
1629         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1630         u32 tmp;
1631         u32 rb_bufsz;
1632         int r;
1633
1634         /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1635         WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1636                                  SOFT_RESET_PA |
1637                                  SOFT_RESET_SH |
1638                                  SOFT_RESET_VGT |
1639                                  SOFT_RESET_SPI |
1640                                  SOFT_RESET_SX));
1641         RREG32(GRBM_SOFT_RESET);
1642         DRM_MDELAY(15);
1643         WREG32(GRBM_SOFT_RESET, 0);
1644         RREG32(GRBM_SOFT_RESET);
1645
1646         /* Set ring buffer size */
1647         rb_bufsz = drm_order(ring->ring_size / 8);
1648         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1649 #ifdef __BIG_ENDIAN
1650         tmp |= BUF_SWAP_32BIT;
1651 #endif
1652         WREG32(CP_RB_CNTL, tmp);
1653         WREG32(CP_SEM_WAIT_TIMER, 0x0);
1654         WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1655
1656         /* Set the write pointer delay */
1657         WREG32(CP_RB_WPTR_DELAY, 0);
1658
1659         /* Initialize the ring buffer's read and write pointers */
1660         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1661         WREG32(CP_RB_RPTR_WR, 0);
1662         ring->wptr = 0;
1663         WREG32(CP_RB_WPTR, ring->wptr);
1664
1665         /* set the wb address whether it's enabled or not */
1666         WREG32(CP_RB_RPTR_ADDR,
1667                ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
1668         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1669         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1670
1671         if (rdev->wb.enabled)
1672                 WREG32(SCRATCH_UMSK, 0xff);
1673         else {
1674                 tmp |= RB_NO_UPDATE;
1675                 WREG32(SCRATCH_UMSK, 0);
1676         }
1677
1678         DRM_MDELAY(1);
1679         WREG32(CP_RB_CNTL, tmp);
1680
1681         WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
1682         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1683
1684         ring->rptr = RREG32(CP_RB_RPTR);
1685
1686         evergreen_cp_start(rdev);
1687         ring->ready = true;
1688         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1689         if (r) {
1690                 ring->ready = false;
1691                 return r;
1692         }
1693         return 0;
1694 }
1695
1696 /*
1697  * Core functions
1698  */
1699 static void evergreen_gpu_init(struct radeon_device *rdev)
1700 {
1701         u32 gb_addr_config;
1702         u32 mc_shared_chmap, mc_arb_ramcfg;
1703         u32 sx_debug_1;
1704         u32 smx_dc_ctl0;
1705         u32 sq_config;
1706         u32 sq_lds_resource_mgmt;
1707         u32 sq_gpr_resource_mgmt_1;
1708         u32 sq_gpr_resource_mgmt_2;
1709         u32 sq_gpr_resource_mgmt_3;
1710         u32 sq_thread_resource_mgmt;
1711         u32 sq_thread_resource_mgmt_2;
1712         u32 sq_stack_resource_mgmt_1;
1713         u32 sq_stack_resource_mgmt_2;
1714         u32 sq_stack_resource_mgmt_3;
1715         u32 vgt_cache_invalidation;
1716         u32 hdp_host_path_cntl, tmp;
1717         u32 disabled_rb_mask;
1718         int i, j, num_shader_engines, ps_thread_count;
1719
1720         switch (rdev->family) {
1721         case CHIP_CYPRESS:
1722         case CHIP_HEMLOCK:
1723                 rdev->config.evergreen.num_ses = 2;
1724                 rdev->config.evergreen.max_pipes = 4;
1725                 rdev->config.evergreen.max_tile_pipes = 8;
1726                 rdev->config.evergreen.max_simds = 10;
1727                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1728                 rdev->config.evergreen.max_gprs = 256;
1729                 rdev->config.evergreen.max_threads = 248;
1730                 rdev->config.evergreen.max_gs_threads = 32;
1731                 rdev->config.evergreen.max_stack_entries = 512;
1732                 rdev->config.evergreen.sx_num_of_sets = 4;
1733                 rdev->config.evergreen.sx_max_export_size = 256;
1734                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1735                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1736                 rdev->config.evergreen.max_hw_contexts = 8;
1737                 rdev->config.evergreen.sq_num_cf_insts = 2;
1738
1739                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1740                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1741                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1742                 gb_addr_config = CYPRESS_GB_ADDR_CONFIG_GOLDEN;
1743                 break;
1744         case CHIP_JUNIPER:
1745                 rdev->config.evergreen.num_ses = 1;
1746                 rdev->config.evergreen.max_pipes = 4;
1747                 rdev->config.evergreen.max_tile_pipes = 4;
1748                 rdev->config.evergreen.max_simds = 10;
1749                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1750                 rdev->config.evergreen.max_gprs = 256;
1751                 rdev->config.evergreen.max_threads = 248;
1752                 rdev->config.evergreen.max_gs_threads = 32;
1753                 rdev->config.evergreen.max_stack_entries = 512;
1754                 rdev->config.evergreen.sx_num_of_sets = 4;
1755                 rdev->config.evergreen.sx_max_export_size = 256;
1756                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1757                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1758                 rdev->config.evergreen.max_hw_contexts = 8;
1759                 rdev->config.evergreen.sq_num_cf_insts = 2;
1760
1761                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1762                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1763                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1764                 gb_addr_config = JUNIPER_GB_ADDR_CONFIG_GOLDEN;
1765                 break;
1766         case CHIP_REDWOOD:
1767                 rdev->config.evergreen.num_ses = 1;
1768                 rdev->config.evergreen.max_pipes = 4;
1769                 rdev->config.evergreen.max_tile_pipes = 4;
1770                 rdev->config.evergreen.max_simds = 5;
1771                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1772                 rdev->config.evergreen.max_gprs = 256;
1773                 rdev->config.evergreen.max_threads = 248;
1774                 rdev->config.evergreen.max_gs_threads = 32;
1775                 rdev->config.evergreen.max_stack_entries = 256;
1776                 rdev->config.evergreen.sx_num_of_sets = 4;
1777                 rdev->config.evergreen.sx_max_export_size = 256;
1778                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1779                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1780                 rdev->config.evergreen.max_hw_contexts = 8;
1781                 rdev->config.evergreen.sq_num_cf_insts = 2;
1782
1783                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1784                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1785                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1786                 gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;
1787                 break;
1788         case CHIP_CEDAR:
1789         default:
1790                 rdev->config.evergreen.num_ses = 1;
1791                 rdev->config.evergreen.max_pipes = 2;
1792                 rdev->config.evergreen.max_tile_pipes = 2;
1793                 rdev->config.evergreen.max_simds = 2;
1794                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1795                 rdev->config.evergreen.max_gprs = 256;
1796                 rdev->config.evergreen.max_threads = 192;
1797                 rdev->config.evergreen.max_gs_threads = 16;
1798                 rdev->config.evergreen.max_stack_entries = 256;
1799                 rdev->config.evergreen.sx_num_of_sets = 4;
1800                 rdev->config.evergreen.sx_max_export_size = 128;
1801                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1802                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1803                 rdev->config.evergreen.max_hw_contexts = 4;
1804                 rdev->config.evergreen.sq_num_cf_insts = 1;
1805
1806                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1807                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1808                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1809                 gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN;
1810                 break;
1811         case CHIP_PALM:
1812                 rdev->config.evergreen.num_ses = 1;
1813                 rdev->config.evergreen.max_pipes = 2;
1814                 rdev->config.evergreen.max_tile_pipes = 2;
1815                 rdev->config.evergreen.max_simds = 2;
1816                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1817                 rdev->config.evergreen.max_gprs = 256;
1818                 rdev->config.evergreen.max_threads = 192;
1819                 rdev->config.evergreen.max_gs_threads = 16;
1820                 rdev->config.evergreen.max_stack_entries = 256;
1821                 rdev->config.evergreen.sx_num_of_sets = 4;
1822                 rdev->config.evergreen.sx_max_export_size = 128;
1823                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1824                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1825                 rdev->config.evergreen.max_hw_contexts = 4;
1826                 rdev->config.evergreen.sq_num_cf_insts = 1;
1827
1828                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1829                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1830                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1831                 gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN;
1832                 break;
1833         case CHIP_SUMO:
1834                 rdev->config.evergreen.num_ses = 1;
1835                 rdev->config.evergreen.max_pipes = 4;
1836                 rdev->config.evergreen.max_tile_pipes = 4;
1837                 if (rdev->ddev->pci_device == 0x9648)
1838                         rdev->config.evergreen.max_simds = 3;
1839                 else if ((rdev->ddev->pci_device == 0x9647) ||
1840                          (rdev->ddev->pci_device == 0x964a))
1841                         rdev->config.evergreen.max_simds = 4;
1842                 else
1843                         rdev->config.evergreen.max_simds = 5;
1844                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1845                 rdev->config.evergreen.max_gprs = 256;
1846                 rdev->config.evergreen.max_threads = 248;
1847                 rdev->config.evergreen.max_gs_threads = 32;
1848                 rdev->config.evergreen.max_stack_entries = 256;
1849                 rdev->config.evergreen.sx_num_of_sets = 4;
1850                 rdev->config.evergreen.sx_max_export_size = 256;
1851                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1852                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1853                 rdev->config.evergreen.max_hw_contexts = 8;
1854                 rdev->config.evergreen.sq_num_cf_insts = 2;
1855
1856                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1857                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1858                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1859                 gb_addr_config = SUMO_GB_ADDR_CONFIG_GOLDEN;
1860                 break;
1861         case CHIP_SUMO2:
1862                 rdev->config.evergreen.num_ses = 1;
1863                 rdev->config.evergreen.max_pipes = 4;
1864                 rdev->config.evergreen.max_tile_pipes = 4;
1865                 rdev->config.evergreen.max_simds = 2;
1866                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1867                 rdev->config.evergreen.max_gprs = 256;
1868                 rdev->config.evergreen.max_threads = 248;
1869                 rdev->config.evergreen.max_gs_threads = 32;
1870                 rdev->config.evergreen.max_stack_entries = 512;
1871                 rdev->config.evergreen.sx_num_of_sets = 4;
1872                 rdev->config.evergreen.sx_max_export_size = 256;
1873                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1874                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1875                 rdev->config.evergreen.max_hw_contexts = 8;
1876                 rdev->config.evergreen.sq_num_cf_insts = 2;
1877
1878                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1879                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1880                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1881                 gb_addr_config = SUMO2_GB_ADDR_CONFIG_GOLDEN;
1882                 break;
1883         case CHIP_BARTS:
1884                 rdev->config.evergreen.num_ses = 2;
1885                 rdev->config.evergreen.max_pipes = 4;
1886                 rdev->config.evergreen.max_tile_pipes = 8;
1887                 rdev->config.evergreen.max_simds = 7;
1888                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1889                 rdev->config.evergreen.max_gprs = 256;
1890                 rdev->config.evergreen.max_threads = 248;
1891                 rdev->config.evergreen.max_gs_threads = 32;
1892                 rdev->config.evergreen.max_stack_entries = 512;
1893                 rdev->config.evergreen.sx_num_of_sets = 4;
1894                 rdev->config.evergreen.sx_max_export_size = 256;
1895                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1896                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1897                 rdev->config.evergreen.max_hw_contexts = 8;
1898                 rdev->config.evergreen.sq_num_cf_insts = 2;
1899
1900                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1901                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1902                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1903                 gb_addr_config = BARTS_GB_ADDR_CONFIG_GOLDEN;
1904                 break;
1905         case CHIP_TURKS:
1906                 rdev->config.evergreen.num_ses = 1;
1907                 rdev->config.evergreen.max_pipes = 4;
1908                 rdev->config.evergreen.max_tile_pipes = 4;
1909                 rdev->config.evergreen.max_simds = 6;
1910                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1911                 rdev->config.evergreen.max_gprs = 256;
1912                 rdev->config.evergreen.max_threads = 248;
1913                 rdev->config.evergreen.max_gs_threads = 32;
1914                 rdev->config.evergreen.max_stack_entries = 256;
1915                 rdev->config.evergreen.sx_num_of_sets = 4;
1916                 rdev->config.evergreen.sx_max_export_size = 256;
1917                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1918                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1919                 rdev->config.evergreen.max_hw_contexts = 8;
1920                 rdev->config.evergreen.sq_num_cf_insts = 2;
1921
1922                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1923                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1924                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1925                 gb_addr_config = TURKS_GB_ADDR_CONFIG_GOLDEN;
1926                 break;
1927         case CHIP_CAICOS:
1928                 rdev->config.evergreen.num_ses = 1;
1929                 rdev->config.evergreen.max_pipes = 2;
1930                 rdev->config.evergreen.max_tile_pipes = 2;
1931                 rdev->config.evergreen.max_simds = 2;
1932                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1933                 rdev->config.evergreen.max_gprs = 256;
1934                 rdev->config.evergreen.max_threads = 192;
1935                 rdev->config.evergreen.max_gs_threads = 16;
1936                 rdev->config.evergreen.max_stack_entries = 256;
1937                 rdev->config.evergreen.sx_num_of_sets = 4;
1938                 rdev->config.evergreen.sx_max_export_size = 128;
1939                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1940                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1941                 rdev->config.evergreen.max_hw_contexts = 4;
1942                 rdev->config.evergreen.sq_num_cf_insts = 1;
1943
1944                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1945                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1946                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1947                 gb_addr_config = CAICOS_GB_ADDR_CONFIG_GOLDEN;
1948                 break;
1949         }
1950
1951         /* Initialize HDP */
1952         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1953                 WREG32((0x2c14 + j), 0x00000000);
1954                 WREG32((0x2c18 + j), 0x00000000);
1955                 WREG32((0x2c1c + j), 0x00000000);
1956                 WREG32((0x2c20 + j), 0x00000000);
1957                 WREG32((0x2c24 + j), 0x00000000);
1958         }
1959
1960         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1961
1962         evergreen_fix_pci_max_read_req_size(rdev);
1963
1964         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1965         if ((rdev->family == CHIP_PALM) ||
1966             (rdev->family == CHIP_SUMO) ||
1967             (rdev->family == CHIP_SUMO2))
1968                 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
1969         else
1970                 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1971
1972         /* setup tiling info dword.  gb_addr_config is not adequate since it does
1973          * not have bank info, so create a custom tiling dword.
1974          * bits 3:0   num_pipes
1975          * bits 7:4   num_banks
1976          * bits 11:8  group_size
1977          * bits 15:12 row_size
1978          */
1979         rdev->config.evergreen.tile_config = 0;
1980         switch (rdev->config.evergreen.max_tile_pipes) {
1981         case 1:
1982         default:
1983                 rdev->config.evergreen.tile_config |= (0 << 0);
1984                 break;
1985         case 2:
1986                 rdev->config.evergreen.tile_config |= (1 << 0);
1987                 break;
1988         case 4:
1989                 rdev->config.evergreen.tile_config |= (2 << 0);
1990                 break;
1991         case 8:
1992                 rdev->config.evergreen.tile_config |= (3 << 0);
1993                 break;
1994         }
1995         /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
1996         if (rdev->flags & RADEON_IS_IGP)
1997                 rdev->config.evergreen.tile_config |= 1 << 4;
1998         else {
1999                 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
2000                 case 0: /* four banks */
2001                         rdev->config.evergreen.tile_config |= 0 << 4;
2002                         break;
2003                 case 1: /* eight banks */
2004                         rdev->config.evergreen.tile_config |= 1 << 4;
2005                         break;
2006                 case 2: /* sixteen banks */
2007                 default:
2008                         rdev->config.evergreen.tile_config |= 2 << 4;
2009                         break;
2010                 }
2011         }
2012         rdev->config.evergreen.tile_config |= 0 << 8;
2013         rdev->config.evergreen.tile_config |=
2014                 ((gb_addr_config & 0x30000000) >> 28) << 12;
2015
2016         num_shader_engines = (gb_addr_config & NUM_SHADER_ENGINES(3) >> 12) + 1;
2017
2018         if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) {
2019                 u32 efuse_straps_4;
2020                 u32 efuse_straps_3;
2021
2022                 WREG32(RCU_IND_INDEX, 0x204);
2023                 efuse_straps_4 = RREG32(RCU_IND_DATA);
2024                 WREG32(RCU_IND_INDEX, 0x203);
2025                 efuse_straps_3 = RREG32(RCU_IND_DATA);
2026                 tmp = (((efuse_straps_4 & 0xf) << 4) |
2027                       ((efuse_straps_3 & 0xf0000000) >> 28));
2028         } else {
2029                 tmp = 0;
2030                 for (i = (rdev->config.evergreen.num_ses - 1); i >= 0; i--) {
2031                         u32 rb_disable_bitmap;
2032
2033                         WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
2034                         WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
2035                         rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
2036                         tmp <<= 4;
2037                         tmp |= rb_disable_bitmap;
2038                 }
2039         }
2040         /* enabled rb are just the one not disabled :) */
2041         disabled_rb_mask = tmp;
2042
2043         WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
2044         WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
2045
2046         WREG32(GB_ADDR_CONFIG, gb_addr_config);
2047         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
2048         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
2049         WREG32(DMA_TILING_CONFIG, gb_addr_config);
2050
2051         if ((rdev->config.evergreen.max_backends == 1) &&
2052             (rdev->flags & RADEON_IS_IGP)) {
2053                 if ((disabled_rb_mask & 3) == 1) {
2054                         /* RB0 disabled, RB1 enabled */
2055                         tmp = 0x11111111;
2056                 } else {
2057                         /* RB1 disabled, RB0 enabled */
2058                         tmp = 0x00000000;
2059                 }
2060         } else {
2061                 tmp = gb_addr_config & NUM_PIPES_MASK;
2062                 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends,
2063                                                 EVERGREEN_MAX_BACKENDS, disabled_rb_mask);
2064         }
2065         WREG32(GB_BACKEND_MAP, tmp);
2066
2067         WREG32(CGTS_SYS_TCC_DISABLE, 0);
2068         WREG32(CGTS_TCC_DISABLE, 0);
2069         WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
2070         WREG32(CGTS_USER_TCC_DISABLE, 0);
2071
2072         /* set HW defaults for 3D engine */
2073         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
2074                                      ROQ_IB2_START(0x2b)));
2075
2076         WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
2077
2078         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
2079                              SYNC_GRADIENT |
2080                              SYNC_WALKER |
2081                              SYNC_ALIGNER));
2082
2083         sx_debug_1 = RREG32(SX_DEBUG_1);
2084         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
2085         WREG32(SX_DEBUG_1, sx_debug_1);
2086
2087
2088         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
2089         smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
2090         smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
2091         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
2092
2093         if (rdev->family <= CHIP_SUMO2)
2094                 WREG32(SMX_SAR_CTL0, 0x00010000);
2095
2096         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
2097                                         POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
2098                                         SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
2099
2100         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
2101                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
2102                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
2103
2104         WREG32(VGT_NUM_INSTANCES, 1);
2105         WREG32(SPI_CONFIG_CNTL, 0);
2106         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
2107         WREG32(CP_PERFMON_CNTL, 0);
2108
2109         WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
2110                                   FETCH_FIFO_HIWATER(0x4) |
2111                                   DONE_FIFO_HIWATER(0xe0) |
2112                                   ALU_UPDATE_FIFO_HIWATER(0x8)));
2113
2114         sq_config = RREG32(SQ_CONFIG);
2115         sq_config &= ~(PS_PRIO(3) |
2116                        VS_PRIO(3) |
2117                        GS_PRIO(3) |
2118                        ES_PRIO(3));
2119         sq_config |= (VC_ENABLE |
2120                       EXPORT_SRC_C |
2121                       PS_PRIO(0) |
2122                       VS_PRIO(1) |
2123                       GS_PRIO(2) |
2124                       ES_PRIO(3));
2125
2126         switch (rdev->family) {
2127         case CHIP_CEDAR:
2128         case CHIP_PALM:
2129         case CHIP_SUMO:
2130         case CHIP_SUMO2:
2131         case CHIP_CAICOS:
2132                 /* no vertex cache */
2133                 sq_config &= ~VC_ENABLE;
2134                 break;
2135         default:
2136                 break;
2137         }
2138
2139         sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
2140
2141         sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
2142         sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
2143         sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
2144         sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2145         sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2146         sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2147         sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2148
2149         switch (rdev->family) {
2150         case CHIP_CEDAR:
2151         case CHIP_PALM:
2152         case CHIP_SUMO:
2153         case CHIP_SUMO2:
2154                 ps_thread_count = 96;
2155                 break;
2156         default:
2157                 ps_thread_count = 128;
2158                 break;
2159         }
2160
2161         sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
2162         sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2163         sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2164         sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2165         sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2166         sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2167
2168         sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2169         sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2170         sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2171         sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2172         sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2173         sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2174
2175         WREG32(SQ_CONFIG, sq_config);
2176         WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2177         WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2178         WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
2179         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2180         WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
2181         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2182         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2183         WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
2184         WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2185         WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
2186
2187         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
2188                                           FORCE_EOV_MAX_REZ_CNT(255)));
2189
2190         switch (rdev->family) {
2191         case CHIP_CEDAR:
2192         case CHIP_PALM:
2193         case CHIP_SUMO:
2194         case CHIP_SUMO2:
2195         case CHIP_CAICOS:
2196                 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
2197                 break;
2198         default:
2199                 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
2200                 break;
2201         }
2202         vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
2203         WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
2204
2205         WREG32(VGT_GS_VERTEX_REUSE, 16);
2206         WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
2207         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2208
2209         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
2210         WREG32(VGT_OUT_DEALLOC_CNTL, 16);
2211
2212         WREG32(CB_PERF_CTR0_SEL_0, 0);
2213         WREG32(CB_PERF_CTR0_SEL_1, 0);
2214         WREG32(CB_PERF_CTR1_SEL_0, 0);
2215         WREG32(CB_PERF_CTR1_SEL_1, 0);
2216         WREG32(CB_PERF_CTR2_SEL_0, 0);
2217         WREG32(CB_PERF_CTR2_SEL_1, 0);
2218         WREG32(CB_PERF_CTR3_SEL_0, 0);
2219         WREG32(CB_PERF_CTR3_SEL_1, 0);
2220
2221         /* clear render buffer base addresses */
2222         WREG32(CB_COLOR0_BASE, 0);
2223         WREG32(CB_COLOR1_BASE, 0);
2224         WREG32(CB_COLOR2_BASE, 0);
2225         WREG32(CB_COLOR3_BASE, 0);
2226         WREG32(CB_COLOR4_BASE, 0);
2227         WREG32(CB_COLOR5_BASE, 0);
2228         WREG32(CB_COLOR6_BASE, 0);
2229         WREG32(CB_COLOR7_BASE, 0);
2230         WREG32(CB_COLOR8_BASE, 0);
2231         WREG32(CB_COLOR9_BASE, 0);
2232         WREG32(CB_COLOR10_BASE, 0);
2233         WREG32(CB_COLOR11_BASE, 0);
2234
2235         /* set the shader const cache sizes to 0 */
2236         for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2237                 WREG32(i, 0);
2238         for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2239                 WREG32(i, 0);
2240
2241         tmp = RREG32(HDP_MISC_CNTL);
2242         tmp |= HDP_FLUSH_INVALIDATE_CACHE;
2243         WREG32(HDP_MISC_CNTL, tmp);
2244
2245         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2246         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2247
2248         WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2249
2250         DRM_UDELAY(50);
2251
2252 }
2253
2254 int evergreen_mc_init(struct radeon_device *rdev)
2255 {
2256         u32 tmp;
2257         int chansize, numchan;
2258
2259         /* Get VRAM informations */
2260         rdev->mc.vram_is_ddr = true;
2261         if ((rdev->family == CHIP_PALM) ||
2262             (rdev->family == CHIP_SUMO) ||
2263             (rdev->family == CHIP_SUMO2))
2264                 tmp = RREG32(FUS_MC_ARB_RAMCFG);
2265         else
2266                 tmp = RREG32(MC_ARB_RAMCFG);
2267         if (tmp & CHANSIZE_OVERRIDE) {
2268                 chansize = 16;
2269         } else if (tmp & CHANSIZE_MASK) {
2270                 chansize = 64;
2271         } else {
2272                 chansize = 32;
2273         }
2274         tmp = RREG32(MC_SHARED_CHMAP);
2275         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2276         case 0:
2277         default:
2278                 numchan = 1;
2279                 break;
2280         case 1:
2281                 numchan = 2;
2282                 break;
2283         case 2:
2284                 numchan = 4;
2285                 break;
2286         case 3:
2287                 numchan = 8;
2288                 break;
2289         }
2290         rdev->mc.vram_width = numchan * chansize;
2291         /* Could aper size report 0 ? */
2292         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
2293         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
2294         /* Setup GPU memory space */
2295         if ((rdev->family == CHIP_PALM) ||
2296             (rdev->family == CHIP_SUMO) ||
2297             (rdev->family == CHIP_SUMO2)) {
2298                 /* size in bytes on fusion */
2299                 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2300                 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2301         } else {
2302                 /* size in MB on evergreen/cayman/tn */
2303                 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2304                 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2305         }
2306         rdev->mc.visible_vram_size = rdev->mc.aper_size;
2307         r700_vram_gtt_location(rdev, &rdev->mc);
2308         radeon_update_bandwidth_info(rdev);
2309
2310         return 0;
2311 }
2312
2313 bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2314 {
2315         u32 srbm_status;
2316         u32 grbm_status;
2317         u32 grbm_status_se0, grbm_status_se1;
2318
2319         srbm_status = RREG32(SRBM_STATUS);
2320         grbm_status = RREG32(GRBM_STATUS);
2321         grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2322         grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2323         if (!(grbm_status & GUI_ACTIVE)) {
2324                 radeon_ring_lockup_update(ring);
2325                 return false;
2326         }
2327         /* force CP activities */
2328         radeon_ring_force_activity(rdev, ring);
2329         return radeon_ring_test_lockup(rdev, ring);
2330 }
2331
2332 static void evergreen_gpu_soft_reset_gfx(struct radeon_device *rdev)
2333 {
2334         u32 grbm_reset = 0;
2335
2336         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2337                 return;
2338
2339         dev_info(rdev->dev, "  GRBM_STATUS               = 0x%08X\n",
2340                 RREG32(GRBM_STATUS));
2341         dev_info(rdev->dev, "  GRBM_STATUS_SE0           = 0x%08X\n",
2342                 RREG32(GRBM_STATUS_SE0));
2343         dev_info(rdev->dev, "  GRBM_STATUS_SE1           = 0x%08X\n",
2344                 RREG32(GRBM_STATUS_SE1));
2345         dev_info(rdev->dev, "  SRBM_STATUS               = 0x%08X\n",
2346                 RREG32(SRBM_STATUS));
2347         dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
2348                 RREG32(CP_STALLED_STAT1));
2349         dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",
2350                 RREG32(CP_STALLED_STAT2));
2351         dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",
2352                 RREG32(CP_BUSY_STAT));
2353         dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
2354                 RREG32(CP_STAT));
2355
2356         /* Disable CP parsing/prefetching */
2357         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2358
2359         /* reset all the gfx blocks */
2360         grbm_reset = (SOFT_RESET_CP |
2361                       SOFT_RESET_CB |
2362                       SOFT_RESET_DB |
2363                       SOFT_RESET_PA |
2364                       SOFT_RESET_SC |
2365                       SOFT_RESET_SPI |
2366                       SOFT_RESET_SH |
2367                       SOFT_RESET_SX |
2368                       SOFT_RESET_TC |
2369                       SOFT_RESET_TA |
2370                       SOFT_RESET_VC |
2371                       SOFT_RESET_VGT);
2372
2373         dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2374         WREG32(GRBM_SOFT_RESET, grbm_reset);
2375         (void)RREG32(GRBM_SOFT_RESET);
2376         DRM_UDELAY(50);
2377         WREG32(GRBM_SOFT_RESET, 0);
2378         (void)RREG32(GRBM_SOFT_RESET);
2379
2380         dev_info(rdev->dev, "  GRBM_STATUS               = 0x%08X\n",
2381                 RREG32(GRBM_STATUS));
2382         dev_info(rdev->dev, "  GRBM_STATUS_SE0           = 0x%08X\n",
2383                 RREG32(GRBM_STATUS_SE0));
2384         dev_info(rdev->dev, "  GRBM_STATUS_SE1           = 0x%08X\n",
2385                 RREG32(GRBM_STATUS_SE1));
2386         dev_info(rdev->dev, "  SRBM_STATUS               = 0x%08X\n",
2387                 RREG32(SRBM_STATUS));
2388         dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
2389                 RREG32(CP_STALLED_STAT1));
2390         dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",
2391                 RREG32(CP_STALLED_STAT2));
2392         dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",
2393                 RREG32(CP_BUSY_STAT));
2394         dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
2395                 RREG32(CP_STAT));
2396 }
2397
2398 static void evergreen_gpu_soft_reset_dma(struct radeon_device *rdev)
2399 {
2400         u32 tmp;
2401
2402         if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
2403                 return;
2404
2405         dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",
2406                 RREG32(DMA_STATUS_REG));
2407
2408         /* Disable DMA */
2409         tmp = RREG32(DMA_RB_CNTL);
2410         tmp &= ~DMA_RB_ENABLE;
2411         WREG32(DMA_RB_CNTL, tmp);
2412
2413         /* Reset dma */
2414         WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
2415         RREG32(SRBM_SOFT_RESET);
2416         DRM_UDELAY(50);
2417         WREG32(SRBM_SOFT_RESET, 0);
2418
2419         dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",
2420                 RREG32(DMA_STATUS_REG));
2421 }
2422
2423 static int evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
2424 {
2425         struct evergreen_mc_save save;
2426
2427         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2428                 reset_mask &= ~(RADEON_RESET_GFX | RADEON_RESET_COMPUTE);
2429
2430         if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
2431                 reset_mask &= ~RADEON_RESET_DMA;
2432
2433         if (reset_mask == 0)
2434                 return 0;
2435
2436         dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
2437
2438         evergreen_mc_stop(rdev, &save);
2439         if (evergreen_mc_wait_for_idle(rdev)) {
2440                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2441         }
2442
2443         if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE))
2444                 evergreen_gpu_soft_reset_gfx(rdev);
2445
2446         if (reset_mask & RADEON_RESET_DMA)
2447                 evergreen_gpu_soft_reset_dma(rdev);
2448
2449         /* Wait a little for things to settle down */
2450         DRM_UDELAY(50);
2451
2452         evergreen_mc_resume(rdev, &save);
2453         return 0;
2454 }
2455
2456 int evergreen_asic_reset(struct radeon_device *rdev)
2457 {
2458         return evergreen_gpu_soft_reset(rdev, (RADEON_RESET_GFX |
2459                                                RADEON_RESET_COMPUTE |
2460                                                RADEON_RESET_DMA));
2461 }
2462
2463 /* Interrupts */
2464
2465 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2466 {
2467         if (crtc >= rdev->num_crtc)
2468                 return 0;
2469         else
2470                 return RREG32(CRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
2471 }
2472
2473 void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2474 {
2475         u32 tmp;
2476
2477         if (rdev->family >= CHIP_CAYMAN) {
2478                 cayman_cp_int_cntl_setup(rdev, 0,
2479                                          CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2480                 cayman_cp_int_cntl_setup(rdev, 1, 0);
2481                 cayman_cp_int_cntl_setup(rdev, 2, 0);
2482                 tmp = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE;
2483                 WREG32(CAYMAN_DMA1_CNTL, tmp);
2484         } else
2485                 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2486         tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
2487         WREG32(DMA_CNTL, tmp);
2488         WREG32(GRBM_INT_CNTL, 0);
2489         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2490         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2491         if (rdev->num_crtc >= 4) {
2492                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2493                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2494         }
2495         if (rdev->num_crtc >= 6) {
2496                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2497                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2498         }
2499
2500         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2501         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2502         if (rdev->num_crtc >= 4) {
2503                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2504                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2505         }
2506         if (rdev->num_crtc >= 6) {
2507                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2508                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2509         }
2510
2511         /* only one DAC on DCE6 */
2512         if (!ASIC_IS_DCE6(rdev))
2513                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2514         WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2515
2516         tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2517         WREG32(DC_HPD1_INT_CONTROL, tmp);
2518         tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2519         WREG32(DC_HPD2_INT_CONTROL, tmp);
2520         tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2521         WREG32(DC_HPD3_INT_CONTROL, tmp);
2522         tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2523         WREG32(DC_HPD4_INT_CONTROL, tmp);
2524         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2525         WREG32(DC_HPD5_INT_CONTROL, tmp);
2526         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2527         WREG32(DC_HPD6_INT_CONTROL, tmp);
2528
2529 }
2530
2531 int evergreen_irq_set(struct radeon_device *rdev)
2532 {
2533         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2534         u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
2535         u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2536         u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2537         u32 grbm_int_cntl = 0;
2538         u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
2539         u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0;
2540         u32 dma_cntl, dma_cntl1 = 0;
2541
2542         if (!rdev->irq.installed) {
2543                 dev_warn(rdev->dev, "Can't enable IRQ/MSI because no handler is installed\n");
2544                 return -EINVAL;
2545         }
2546         /* don't enable anything if the ih is disabled */
2547         if (!rdev->ih.enabled) {
2548                 r600_disable_interrupts(rdev);
2549                 /* force the active interrupt state to all disabled */
2550                 evergreen_disable_interrupt_state(rdev);
2551                 return 0;
2552         }
2553
2554         hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2555         hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2556         hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2557         hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2558         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2559         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2560
2561         afmt1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2562         afmt2 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2563         afmt3 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2564         afmt4 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2565         afmt5 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2566         afmt6 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2567
2568         dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
2569
2570         if (rdev->family >= CHIP_CAYMAN) {
2571                 /* enable CP interrupts on all rings */
2572                 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
2573                         DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2574                         cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2575                 }
2576                 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
2577                         DRM_DEBUG("evergreen_irq_set: sw int cp1\n");
2578                         cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
2579                 }
2580                 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
2581                         DRM_DEBUG("evergreen_irq_set: sw int cp2\n");
2582                         cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
2583                 }
2584         } else {
2585                 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
2586                         DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2587                         cp_int_cntl |= RB_INT_ENABLE;
2588                         cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2589                 }
2590         }
2591
2592         if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
2593                 DRM_DEBUG("r600_irq_set: sw int dma\n");
2594                 dma_cntl |= TRAP_ENABLE;
2595         }
2596
2597         if (rdev->family >= CHIP_CAYMAN) {
2598                 dma_cntl1 = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE;
2599                 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) {
2600                         DRM_DEBUG("r600_irq_set: sw int dma1\n");
2601                         dma_cntl1 |= TRAP_ENABLE;
2602                 }
2603         }
2604
2605         if (rdev->irq.crtc_vblank_int[0] ||
2606             atomic_read(&rdev->irq.pflip[0])) {
2607                 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2608                 crtc1 |= VBLANK_INT_MASK;
2609         }
2610         if (rdev->irq.crtc_vblank_int[1] ||
2611             atomic_read(&rdev->irq.pflip[1])) {
2612                 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2613                 crtc2 |= VBLANK_INT_MASK;
2614         }
2615         if (rdev->irq.crtc_vblank_int[2] ||
2616             atomic_read(&rdev->irq.pflip[2])) {
2617                 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2618                 crtc3 |= VBLANK_INT_MASK;
2619         }
2620         if (rdev->irq.crtc_vblank_int[3] ||
2621             atomic_read(&rdev->irq.pflip[3])) {
2622                 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2623                 crtc4 |= VBLANK_INT_MASK;
2624         }
2625         if (rdev->irq.crtc_vblank_int[4] ||
2626             atomic_read(&rdev->irq.pflip[4])) {
2627                 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2628                 crtc5 |= VBLANK_INT_MASK;
2629         }
2630         if (rdev->irq.crtc_vblank_int[5] ||
2631             atomic_read(&rdev->irq.pflip[5])) {
2632                 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2633                 crtc6 |= VBLANK_INT_MASK;
2634         }
2635         if (rdev->irq.hpd[0]) {
2636                 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2637                 hpd1 |= DC_HPDx_INT_EN;
2638         }
2639         if (rdev->irq.hpd[1]) {
2640                 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2641                 hpd2 |= DC_HPDx_INT_EN;
2642         }
2643         if (rdev->irq.hpd[2]) {
2644                 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2645                 hpd3 |= DC_HPDx_INT_EN;
2646         }
2647         if (rdev->irq.hpd[3]) {
2648                 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2649                 hpd4 |= DC_HPDx_INT_EN;
2650         }
2651         if (rdev->irq.hpd[4]) {
2652                 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2653                 hpd5 |= DC_HPDx_INT_EN;
2654         }
2655         if (rdev->irq.hpd[5]) {
2656                 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2657                 hpd6 |= DC_HPDx_INT_EN;
2658         }
2659         if (rdev->irq.afmt[0]) {
2660                 DRM_DEBUG("evergreen_irq_set: hdmi 0\n");
2661                 afmt1 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2662         }
2663         if (rdev->irq.afmt[1]) {
2664                 DRM_DEBUG("evergreen_irq_set: hdmi 1\n");
2665                 afmt2 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2666         }
2667         if (rdev->irq.afmt[2]) {
2668                 DRM_DEBUG("evergreen_irq_set: hdmi 2\n");
2669                 afmt3 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2670         }
2671         if (rdev->irq.afmt[3]) {
2672                 DRM_DEBUG("evergreen_irq_set: hdmi 3\n");
2673                 afmt4 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2674         }
2675         if (rdev->irq.afmt[4]) {
2676                 DRM_DEBUG("evergreen_irq_set: hdmi 4\n");
2677                 afmt5 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2678         }
2679         if (rdev->irq.afmt[5]) {
2680                 DRM_DEBUG("evergreen_irq_set: hdmi 5\n");
2681                 afmt6 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2682         }
2683
2684         if (rdev->family >= CHIP_CAYMAN) {
2685                 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl);
2686                 cayman_cp_int_cntl_setup(rdev, 1, cp_int_cntl1);
2687                 cayman_cp_int_cntl_setup(rdev, 2, cp_int_cntl2);
2688         } else
2689                 WREG32(CP_INT_CNTL, cp_int_cntl);
2690
2691         WREG32(DMA_CNTL, dma_cntl);
2692
2693         if (rdev->family >= CHIP_CAYMAN)
2694                 WREG32(CAYMAN_DMA1_CNTL, dma_cntl1);
2695
2696         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
2697
2698         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2699         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2700         if (rdev->num_crtc >= 4) {
2701                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2702                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2703         }
2704         if (rdev->num_crtc >= 6) {
2705                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2706                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2707         }
2708
2709         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2710         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
2711         if (rdev->num_crtc >= 4) {
2712                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2713                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2714         }
2715         if (rdev->num_crtc >= 6) {
2716                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2717                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2718         }
2719
2720         WREG32(DC_HPD1_INT_CONTROL, hpd1);
2721         WREG32(DC_HPD2_INT_CONTROL, hpd2);
2722         WREG32(DC_HPD3_INT_CONTROL, hpd3);
2723         WREG32(DC_HPD4_INT_CONTROL, hpd4);
2724         WREG32(DC_HPD5_INT_CONTROL, hpd5);
2725         WREG32(DC_HPD6_INT_CONTROL, hpd6);
2726
2727         WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, afmt1);
2728         WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, afmt2);
2729         WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, afmt3);
2730         WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, afmt4);
2731         WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, afmt5);
2732         WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, afmt6);
2733
2734         return 0;
2735 }
2736
2737 static void evergreen_irq_ack(struct radeon_device *rdev)
2738 {
2739         u32 tmp;
2740
2741         rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2742         rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2743         rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2744         rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2745         rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2746         rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2747         rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2748         rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2749         if (rdev->num_crtc >= 4) {
2750                 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2751                 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2752         }
2753         if (rdev->num_crtc >= 6) {
2754                 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2755                 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2756         }
2757
2758         rdev->irq.stat_regs.evergreen.afmt_status1 = RREG32(AFMT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2759         rdev->irq.stat_regs.evergreen.afmt_status2 = RREG32(AFMT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2760         rdev->irq.stat_regs.evergreen.afmt_status3 = RREG32(AFMT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2761         rdev->irq.stat_regs.evergreen.afmt_status4 = RREG32(AFMT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2762         rdev->irq.stat_regs.evergreen.afmt_status5 = RREG32(AFMT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2763         rdev->irq.stat_regs.evergreen.afmt_status6 = RREG32(AFMT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2764
2765         if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2766                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2767         if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2768                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2769         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
2770                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
2771         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
2772                 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2773         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
2774                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
2775         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
2776                 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2777
2778         if (rdev->num_crtc >= 4) {
2779                 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2780                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2781                 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2782                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2783                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2784                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2785                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2786                         WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2787                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2788                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2789                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2790                         WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2791         }
2792
2793         if (rdev->num_crtc >= 6) {
2794                 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2795                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2796                 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2797                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2798                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2799                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2800                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2801                         WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2802                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2803                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2804                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2805                         WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2806         }
2807
2808         if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2809                 tmp = RREG32(DC_HPD1_INT_CONTROL);
2810                 tmp |= DC_HPDx_INT_ACK;
2811                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2812         }
2813         if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2814                 tmp = RREG32(DC_HPD2_INT_CONTROL);
2815                 tmp |= DC_HPDx_INT_ACK;
2816                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2817         }
2818         if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2819                 tmp = RREG32(DC_HPD3_INT_CONTROL);
2820                 tmp |= DC_HPDx_INT_ACK;
2821                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2822         }
2823         if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2824                 tmp = RREG32(DC_HPD4_INT_CONTROL);
2825                 tmp |= DC_HPDx_INT_ACK;
2826                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2827         }
2828         if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2829                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2830                 tmp |= DC_HPDx_INT_ACK;
2831                 WREG32(DC_HPD5_INT_CONTROL, tmp);
2832         }
2833         if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2834                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2835                 tmp |= DC_HPDx_INT_ACK;
2836                 WREG32(DC_HPD6_INT_CONTROL, tmp);
2837         }
2838         if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) {
2839                 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
2840                 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2841                 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, tmp);
2842         }
2843         if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) {
2844                 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
2845                 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2846                 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, tmp);
2847         }
2848         if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) {
2849                 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
2850                 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2851                 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, tmp);
2852         }
2853         if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) {
2854                 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
2855                 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2856                 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, tmp);
2857         }
2858         if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) {
2859                 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
2860                 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2861                 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, tmp);
2862         }
2863         if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) {
2864                 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
2865                 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2866                 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp);
2867         }
2868 }
2869
2870 static void evergreen_irq_disable(struct radeon_device *rdev)
2871 {
2872         r600_disable_interrupts(rdev);
2873         /* Wait and acknowledge irq */
2874         DRM_MDELAY(1);
2875         evergreen_irq_ack(rdev);
2876         evergreen_disable_interrupt_state(rdev);
2877 }
2878
2879 void evergreen_irq_suspend(struct radeon_device *rdev)
2880 {
2881         evergreen_irq_disable(rdev);
2882         r600_rlc_stop(rdev);
2883 }
2884
2885 static u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2886 {
2887         u32 wptr, tmp;
2888
2889         if (rdev->wb.enabled)
2890                 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
2891         else
2892                 wptr = RREG32(IH_RB_WPTR);
2893
2894         if (wptr & RB_OVERFLOW) {
2895                 /* When a ring buffer overflow happen start parsing interrupt
2896                  * from the last not overwritten vector (wptr + 16). Hopefully
2897                  * this should allow us to catchup.
2898                  */
2899                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2900                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2901                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2902                 tmp = RREG32(IH_RB_CNTL);
2903                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2904                 WREG32(IH_RB_CNTL, tmp);
2905         }
2906         return (wptr & rdev->ih.ptr_mask);
2907 }
2908
2909 irqreturn_t evergreen_irq_process(struct radeon_device *rdev)
2910 {
2911         u32 wptr;
2912         u32 rptr;
2913         u32 src_id, src_data;
2914         u32 ring_index;
2915         bool queue_hotplug = false;
2916         bool queue_hdmi = false;
2917
2918         if (!rdev->ih.enabled || rdev->shutdown)
2919                 return IRQ_NONE;
2920
2921         wptr = evergreen_get_ih_wptr(rdev);
2922
2923 restart_ih:
2924         /* is somebody else already processing irqs? */
2925         if (atomic_xchg(&rdev->ih.lock, 1))
2926                 return IRQ_NONE;
2927
2928         rptr = rdev->ih.rptr;
2929         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2930
2931         /* Order reading of wptr vs. reading of IH ring data */
2932         rmb();
2933
2934         /* display interrupts */
2935         evergreen_irq_ack(rdev);
2936
2937         while (rptr != wptr) {
2938                 /* wptr/rptr are in bytes! */
2939                 ring_index = rptr / 4;
2940                 src_id =  le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
2941                 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
2942
2943                 switch (src_id) {
2944                 case 1: /* D1 vblank/vline */
2945                         switch (src_data) {
2946                         case 0: /* D1 vblank */
2947                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
2948                                         if (rdev->irq.crtc_vblank_int[0]) {
2949                                                 drm_handle_vblank(rdev->ddev, 0);
2950                                                 rdev->pm.vblank_sync = true;
2951                                                 DRM_WAKEUP(&rdev->irq.vblank_queue);
2952                                         }
2953                                         if (atomic_read(&rdev->irq.pflip[0]))
2954                                                 radeon_crtc_handle_flip(rdev, 0);
2955                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2956                                         DRM_DEBUG("IH: D1 vblank\n");
2957                                 }
2958                                 break;
2959                         case 1: /* D1 vline */
2960                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
2961                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
2962                                         DRM_DEBUG("IH: D1 vline\n");
2963                                 }
2964                                 break;
2965                         default:
2966                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2967                                 break;
2968                         }
2969                         break;
2970                 case 2: /* D2 vblank/vline */
2971                         switch (src_data) {
2972                         case 0: /* D2 vblank */
2973                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
2974                                         if (rdev->irq.crtc_vblank_int[1]) {
2975                                                 drm_handle_vblank(rdev->ddev, 1);
2976                                                 rdev->pm.vblank_sync = true;
2977                                                 DRM_WAKEUP(&rdev->irq.vblank_queue);
2978                                         }
2979                                         if (atomic_read(&rdev->irq.pflip[1]))
2980                                                 radeon_crtc_handle_flip(rdev, 1);
2981                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
2982                                         DRM_DEBUG("IH: D2 vblank\n");
2983                                 }
2984                                 break;
2985                         case 1: /* D2 vline */
2986                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2987                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
2988                                         DRM_DEBUG("IH: D2 vline\n");
2989                                 }
2990                                 break;
2991                         default:
2992                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2993                                 break;
2994                         }
2995                         break;
2996                 case 3: /* D3 vblank/vline */
2997                         switch (src_data) {
2998                         case 0: /* D3 vblank */
2999                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
3000                                         if (rdev->irq.crtc_vblank_int[2]) {
3001                                                 drm_handle_vblank(rdev->ddev, 2);
3002                                                 rdev->pm.vblank_sync = true;
3003                                                 DRM_WAKEUP(&rdev->irq.vblank_queue);
3004                                         }
3005                                         if (atomic_read(&rdev->irq.pflip[2]))
3006                                                 radeon_crtc_handle_flip(rdev, 2);
3007                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
3008                                         DRM_DEBUG("IH: D3 vblank\n");
3009                                 }
3010                                 break;
3011                         case 1: /* D3 vline */
3012                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
3013                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
3014                                         DRM_DEBUG("IH: D3 vline\n");
3015                                 }
3016                                 break;
3017                         default:
3018                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3019                                 break;
3020                         }
3021                         break;
3022                 case 4: /* D4 vblank/vline */
3023                         switch (src_data) {
3024                         case 0: /* D4 vblank */
3025                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
3026                                         if (rdev->irq.crtc_vblank_int[3]) {
3027                                                 drm_handle_vblank(rdev->ddev, 3);
3028                                                 rdev->pm.vblank_sync = true;
3029                                                 DRM_WAKEUP(&rdev->irq.vblank_queue);
3030                                         }
3031                                         if (atomic_read(&rdev->irq.pflip[3]))
3032                                                 radeon_crtc_handle_flip(rdev, 3);
3033                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
3034                                         DRM_DEBUG("IH: D4 vblank\n");
3035                                 }
3036                                 break;
3037                         case 1: /* D4 vline */
3038                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
3039                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
3040                                         DRM_DEBUG("IH: D4 vline\n");
3041                                 }
3042                                 break;
3043                         default:
3044                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3045                                 break;
3046                         }
3047                         break;
3048                 case 5: /* D5 vblank/vline */
3049                         switch (src_data) {
3050                         case 0: /* D5 vblank */
3051                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
3052                                         if (rdev->irq.crtc_vblank_int[4]) {
3053                                                 drm_handle_vblank(rdev->ddev, 4);
3054                                                 rdev->pm.vblank_sync = true;
3055                                                 DRM_WAKEUP(&rdev->irq.vblank_queue);
3056                                         }
3057                                         if (atomic_read(&rdev->irq.pflip[4]))
3058                                                 radeon_crtc_handle_flip(rdev, 4);
3059                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
3060                                         DRM_DEBUG("IH: D5 vblank\n");
3061                                 }
3062                                 break;
3063                         case 1: /* D5 vline */
3064                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
3065                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
3066                                         DRM_DEBUG("IH: D5 vline\n");
3067                                 }
3068                                 break;
3069                         default:
3070                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3071                                 break;
3072                         }
3073                         break;
3074                 case 6: /* D6 vblank/vline */
3075                         switch (src_data) {
3076                         case 0: /* D6 vblank */
3077                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
3078                                         if (rdev->irq.crtc_vblank_int[5]) {
3079                                                 drm_handle_vblank(rdev->ddev, 5);
3080                                                 rdev->pm.vblank_sync = true;
3081                                                 DRM_WAKEUP(&rdev->irq.vblank_queue);
3082                                         }
3083                                         if (atomic_read(&rdev->irq.pflip[5]))
3084                                                 radeon_crtc_handle_flip(rdev, 5);
3085                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
3086                                         DRM_DEBUG("IH: D6 vblank\n");
3087                                 }
3088                                 break;
3089                         case 1: /* D6 vline */
3090                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
3091                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
3092                                         DRM_DEBUG("IH: D6 vline\n");
3093                                 }
3094                                 break;
3095                         default:
3096                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3097                                 break;
3098                         }
3099                         break;
3100                 case 42: /* HPD hotplug */
3101                         switch (src_data) {
3102                         case 0:
3103                                 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
3104                                         rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
3105                                         queue_hotplug = true;
3106                                         DRM_DEBUG("IH: HPD1\n");
3107                                 }
3108                                 break;
3109                         case 1:
3110                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
3111                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
3112                                         queue_hotplug = true;
3113                                         DRM_DEBUG("IH: HPD2\n");
3114                                 }
3115                                 break;
3116                         case 2:
3117                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
3118                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
3119                                         queue_hotplug = true;
3120                                         DRM_DEBUG("IH: HPD3\n");
3121                                 }
3122                                 break;
3123                         case 3:
3124                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
3125                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
3126                                         queue_hotplug = true;
3127                                         DRM_DEBUG("IH: HPD4\n");
3128                                 }
3129                                 break;
3130                         case 4:
3131                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
3132                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
3133                                         queue_hotplug = true;
3134                                         DRM_DEBUG("IH: HPD5\n");
3135                                 }
3136                                 break;
3137                         case 5:
3138                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3139                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
3140                                         queue_hotplug = true;
3141                                         DRM_DEBUG("IH: HPD6\n");
3142                                 }
3143                                 break;
3144                         default:
3145                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3146                                 break;
3147                         }
3148                         break;
3149                 case 44: /* hdmi */
3150                         switch (src_data) {
3151                         case 0:
3152                                 if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) {
3153                                         rdev->irq.stat_regs.evergreen.afmt_status1 &= ~AFMT_AZ_FORMAT_WTRIG;
3154                                         queue_hdmi = true;
3155                                         DRM_DEBUG("IH: HDMI0\n");
3156                                 }
3157                                 break;
3158                         case 1:
3159                                 if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) {
3160                                         rdev->irq.stat_regs.evergreen.afmt_status2 &= ~AFMT_AZ_FORMAT_WTRIG;
3161                                         queue_hdmi = true;
3162                                         DRM_DEBUG("IH: HDMI1\n");
3163                                 }
3164                                 break;
3165                         case 2:
3166                                 if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) {
3167                                         rdev->irq.stat_regs.evergreen.afmt_status3 &= ~AFMT_AZ_FORMAT_WTRIG;
3168                                         queue_hdmi = true;
3169                                         DRM_DEBUG("IH: HDMI2\n");
3170                                 }
3171                                 break;
3172                         case 3:
3173                                 if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) {
3174                                         rdev->irq.stat_regs.evergreen.afmt_status4 &= ~AFMT_AZ_FORMAT_WTRIG;
3175                                         queue_hdmi = true;
3176                                         DRM_DEBUG("IH: HDMI3\n");
3177                                 }
3178                                 break;
3179                         case 4:
3180                                 if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) {
3181                                         rdev->irq.stat_regs.evergreen.afmt_status5 &= ~AFMT_AZ_FORMAT_WTRIG;
3182                                         queue_hdmi = true;
3183                                         DRM_DEBUG("IH: HDMI4\n");
3184                                 }
3185                                 break;
3186                         case 5:
3187                                 if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) {
3188                                         rdev->irq.stat_regs.evergreen.afmt_status6 &= ~AFMT_AZ_FORMAT_WTRIG;
3189                                         queue_hdmi = true;
3190                                         DRM_DEBUG("IH: HDMI5\n");
3191                                 }
3192                                 break;
3193                         default:
3194                                 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
3195                                 break;
3196                         }
3197                         break;
3198                 case 146:
3199                 case 147:
3200                         dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
3201                         dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
3202                                 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
3203                         dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
3204                                 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
3205                         /* reset addr and status */
3206                         WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
3207                         break;
3208                 case 176: /* CP_INT in ring buffer */
3209                 case 177: /* CP_INT in IB1 */
3210                 case 178: /* CP_INT in IB2 */
3211                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3212                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3213                         break;
3214                 case 181: /* CP EOP event */
3215                         DRM_DEBUG("IH: CP EOP\n");
3216                         if (rdev->family >= CHIP_CAYMAN) {
3217                                 switch (src_data) {
3218                                 case 0:
3219                                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3220                                         break;
3221                                 case 1:
3222                                         radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
3223                                         break;
3224                                 case 2:
3225                                         radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
3226                                         break;
3227                                 }
3228                         } else
3229                                 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3230                         break;
3231                 case 224: /* DMA trap event */
3232                         DRM_DEBUG("IH: DMA trap\n");
3233                         radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
3234                         break;
3235                 case 233: /* GUI IDLE */
3236                         DRM_DEBUG("IH: GUI idle\n");
3237                         break;
3238                 case 244: /* DMA trap event */
3239                         if (rdev->family >= CHIP_CAYMAN) {
3240                                 DRM_DEBUG("IH: DMA1 trap\n");
3241                                 radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
3242                         }
3243                         break;
3244                 default:
3245                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3246                         break;
3247                 }
3248
3249                 /* wptr/rptr are in bytes! */
3250                 rptr += 16;
3251                 rptr &= rdev->ih.ptr_mask;
3252         }
3253         if (queue_hotplug)
3254                 taskqueue_enqueue(rdev->tq, &rdev->hotplug_work);
3255         if (queue_hdmi)
3256                 taskqueue_enqueue(rdev->tq, &rdev->audio_work);
3257         rdev->ih.rptr = rptr;
3258         WREG32(IH_RB_RPTR, rdev->ih.rptr);
3259         atomic_set(&rdev->ih.lock, 0);
3260
3261         /* make sure wptr hasn't changed while processing */
3262         wptr = evergreen_get_ih_wptr(rdev);
3263         if (wptr != rptr)
3264                 goto restart_ih;
3265
3266         return IRQ_HANDLED;
3267 }
3268
3269 /**
3270  * evergreen_dma_fence_ring_emit - emit a fence on the DMA ring
3271  *
3272  * @rdev: radeon_device pointer
3273  * @fence: radeon fence object
3274  *
3275  * Add a DMA fence packet to the ring to write
3276  * the fence seq number and DMA trap packet to generate
3277  * an interrupt if needed (evergreen-SI).
3278  */
3279 void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
3280                                    struct radeon_fence *fence)
3281 {
3282         struct radeon_ring *ring = &rdev->ring[fence->ring];
3283         u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
3284         /* write the fence */
3285         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0));
3286         radeon_ring_write(ring, addr & 0xfffffffc);
3287         radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
3288         radeon_ring_write(ring, fence->seq);
3289         /* generate an interrupt */
3290         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0));
3291         /* flush HDP */
3292         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
3293         radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
3294         radeon_ring_write(ring, 1);
3295 }
3296
3297 /**
3298  * evergreen_dma_ring_ib_execute - schedule an IB on the DMA engine
3299  *
3300  * @rdev: radeon_device pointer
3301  * @ib: IB object to schedule
3302  *
3303  * Schedule an IB in the DMA ring (evergreen).
3304  */
3305 void evergreen_dma_ring_ib_execute(struct radeon_device *rdev,
3306                                    struct radeon_ib *ib)
3307 {
3308         struct radeon_ring *ring = &rdev->ring[ib->ring];
3309
3310         if (rdev->wb.enabled) {
3311                 u32 next_rptr = ring->wptr + 4;
3312                 while ((next_rptr & 7) != 5)
3313                         next_rptr++;
3314                 next_rptr += 3;
3315                 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
3316                 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3317                 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
3318                 radeon_ring_write(ring, next_rptr);
3319         }
3320
3321         /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
3322          * Pad as necessary with NOPs.
3323          */
3324         while ((ring->wptr & 7) != 5)
3325                 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
3326         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0));
3327         radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
3328         radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
3329
3330 }
3331
3332 /**
3333  * evergreen_copy_dma - copy pages using the DMA engine
3334  *
3335  * @rdev: radeon_device pointer
3336  * @src_offset: src GPU address
3337  * @dst_offset: dst GPU address
3338  * @num_gpu_pages: number of GPU pages to xfer
3339  * @fence: radeon fence object
3340  *
3341  * Copy GPU paging using the DMA engine (evergreen-cayman).
3342  * Used by the radeon ttm implementation to move pages if
3343  * registered as the asic copy callback.
3344  */
3345 int evergreen_copy_dma(struct radeon_device *rdev,
3346                        uint64_t src_offset, uint64_t dst_offset,
3347                        unsigned num_gpu_pages,
3348                        struct radeon_fence **fence)
3349 {
3350         struct radeon_semaphore *sem = NULL;
3351         int ring_index = rdev->asic->copy.dma_ring_index;
3352         struct radeon_ring *ring = &rdev->ring[ring_index];
3353         u32 size_in_dw, cur_size_in_dw;
3354         int i, num_loops;
3355         int r = 0;
3356
3357         r = radeon_semaphore_create(rdev, &sem);
3358         if (r) {
3359                 DRM_ERROR("radeon: moving bo (%d).\n", r);
3360                 return r;
3361         }
3362
3363         size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
3364         num_loops = DIV_ROUND_UP(size_in_dw, 0xfffff);
3365         r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11);
3366         if (r) {
3367                 DRM_ERROR("radeon: moving bo (%d).\n", r);
3368                 radeon_semaphore_free(rdev, &sem, NULL);
3369                 return r;
3370         }
3371
3372         if (radeon_fence_need_sync(*fence, ring->idx)) {
3373                 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
3374                                             ring->idx);
3375                 radeon_fence_note_sync(*fence, ring->idx);
3376         } else {
3377                 radeon_semaphore_free(rdev, &sem, NULL);
3378         }
3379
3380         for (i = 0; i < num_loops; i++) {
3381                 cur_size_in_dw = size_in_dw;
3382                 if (cur_size_in_dw > 0xFFFFF)
3383                         cur_size_in_dw = 0xFFFFF;
3384                 size_in_dw -= cur_size_in_dw;
3385                 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
3386                 radeon_ring_write(ring, dst_offset & 0xfffffffc);
3387                 radeon_ring_write(ring, src_offset & 0xfffffffc);
3388                 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
3389                 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
3390                 src_offset += cur_size_in_dw * 4;
3391                 dst_offset += cur_size_in_dw * 4;
3392         }
3393
3394         r = radeon_fence_emit(rdev, fence, ring->idx);
3395         if (r) {
3396                 radeon_ring_unlock_undo(rdev, ring);
3397                 return r;
3398         }
3399
3400         radeon_ring_unlock_commit(rdev, ring);
3401         radeon_semaphore_free(rdev, &sem, *fence);
3402
3403         return r;
3404 }
3405
3406 static int evergreen_startup(struct radeon_device *rdev)
3407 {
3408         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3409         int r;
3410
3411         /* enable pcie gen2 link */
3412         evergreen_pcie_gen2_enable(rdev);
3413
3414         if (ASIC_IS_DCE5(rdev)) {
3415                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
3416                         r = ni_init_microcode(rdev);
3417                         if (r) {
3418                                 DRM_ERROR("Failed to load firmware!\n");
3419                                 return r;
3420                         }
3421                 }
3422                 r = ni_mc_load_microcode(rdev);
3423                 if (r) {
3424                         DRM_ERROR("Failed to load MC firmware!\n");
3425                         return r;
3426                 }
3427         } else {
3428                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3429                         r = r600_init_microcode(rdev);
3430                         if (r) {
3431                                 DRM_ERROR("Failed to load firmware!\n");
3432                                 return r;
3433                         }
3434                 }
3435         }
3436
3437         r = r600_vram_scratch_init(rdev);
3438         if (r)
3439                 return r;
3440
3441         evergreen_mc_program(rdev);
3442         if (rdev->flags & RADEON_IS_AGP) {
3443                 evergreen_agp_enable(rdev);
3444         } else {
3445                 r = evergreen_pcie_gart_enable(rdev);
3446                 if (r)
3447                         return r;
3448         }
3449         evergreen_gpu_init(rdev);
3450
3451         r = evergreen_blit_init(rdev);
3452         if (r) {
3453                 r600_blit_fini(rdev);
3454                 rdev->asic->copy.copy = NULL;
3455                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
3456         }
3457
3458         /* allocate wb buffer */
3459         r = radeon_wb_init(rdev);
3460         if (r)
3461                 return r;
3462
3463         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3464         if (r) {
3465                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3466                 return r;
3467         }
3468
3469         r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
3470         if (r) {
3471                 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
3472                 return r;
3473         }
3474
3475         /* Enable IRQ */
3476         r = r600_irq_init(rdev);
3477         if (r) {
3478                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3479                 radeon_irq_kms_fini(rdev);
3480                 return r;
3481         }
3482         evergreen_irq_set(rdev);
3483
3484         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
3485                              R600_CP_RB_RPTR, R600_CP_RB_WPTR,
3486                              0, 0xfffff, RADEON_CP_PACKET2);
3487         if (r)
3488                 return r;
3489
3490         ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
3491         r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
3492                              DMA_RB_RPTR, DMA_RB_WPTR,
3493                              2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
3494         if (r)
3495                 return r;
3496
3497         r = evergreen_cp_load_microcode(rdev);
3498         if (r)
3499                 return r;
3500         r = evergreen_cp_resume(rdev);
3501         if (r)
3502                 return r;
3503         r = r600_dma_resume(rdev);
3504         if (r)
3505                 return r;
3506
3507         r = radeon_ib_pool_init(rdev);
3508         if (r) {
3509                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3510                 return r;
3511         }
3512
3513         r = r600_audio_init(rdev);
3514         if (r) {
3515                 DRM_ERROR("radeon: audio init failed\n");
3516                 return r;
3517         }
3518
3519         return 0;
3520 }
3521
3522 int evergreen_resume(struct radeon_device *rdev)
3523 {
3524         int r;
3525
3526         /* reset the asic, the gfx blocks are often in a bad state
3527          * after the driver is unloaded or after a resume
3528          */
3529         if (radeon_asic_reset(rdev))
3530                 dev_warn(rdev->dev, "GPU reset failed !\n");
3531         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
3532          * posting will perform necessary task to bring back GPU into good
3533          * shape.
3534          */
3535         /* post card */
3536         atom_asic_init(rdev->mode_info.atom_context);
3537
3538         rdev->accel_working = true;
3539         r = evergreen_startup(rdev);
3540         if (r) {
3541                 DRM_ERROR("evergreen startup failed on resume\n");
3542                 rdev->accel_working = false;
3543                 return r;
3544         }
3545
3546         return r;
3547
3548 }
3549
3550 int evergreen_suspend(struct radeon_device *rdev)
3551 {
3552         r600_audio_fini(rdev);
3553         r700_cp_stop(rdev);
3554         r600_dma_stop(rdev);
3555         evergreen_irq_suspend(rdev);
3556         radeon_wb_disable(rdev);
3557         evergreen_pcie_gart_disable(rdev);
3558
3559         return 0;
3560 }
3561
3562 /* Plan is to move initialization in that function and use
3563  * helper function so that radeon_device_init pretty much
3564  * do nothing more than calling asic specific function. This
3565  * should also allow to remove a bunch of callback function
3566  * like vram_info.
3567  */
3568 int evergreen_init(struct radeon_device *rdev)
3569 {
3570         int r;
3571
3572         /* Read BIOS */
3573         if (!radeon_get_bios(rdev)) {
3574                 if (ASIC_IS_AVIVO(rdev))
3575                         return -EINVAL;
3576         }
3577         /* Must be an ATOMBIOS */
3578         if (!rdev->is_atom_bios) {
3579                 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");
3580                 return -EINVAL;
3581         }
3582         r = radeon_atombios_init(rdev);
3583         if (r)
3584                 return r;
3585         /* reset the asic, the gfx blocks are often in a bad state
3586          * after the driver is unloaded or after a resume
3587          */
3588         if (radeon_asic_reset(rdev))
3589                 dev_warn(rdev->dev, "GPU reset failed !\n");
3590         /* Post card if necessary */
3591         if (!radeon_card_posted(rdev)) {
3592                 if (!rdev->bios) {
3593                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3594                         return -EINVAL;
3595                 }
3596                 DRM_INFO("GPU not posted. posting now...\n");
3597                 atom_asic_init(rdev->mode_info.atom_context);
3598         }
3599         /* Initialize scratch registers */
3600         r600_scratch_init(rdev);
3601         /* Initialize surface registers */
3602         radeon_surface_init(rdev);
3603         /* Initialize clocks */
3604         radeon_get_clock_info(rdev->ddev);
3605         /* Fence driver */
3606         r = radeon_fence_driver_init(rdev);
3607         if (r)
3608                 return r;
3609         /* initialize AGP */
3610         if (rdev->flags & RADEON_IS_AGP) {
3611                 r = radeon_agp_init(rdev);
3612                 if (r)
3613                         radeon_agp_disable(rdev);
3614         }
3615         /* initialize memory controller */
3616         r = evergreen_mc_init(rdev);
3617         if (r)
3618                 return r;
3619         /* Memory manager */
3620         r = radeon_bo_init(rdev);
3621         if (r)
3622                 return r;
3623
3624         r = radeon_irq_kms_init(rdev);
3625         if (r)
3626                 return r;
3627
3628         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
3629         r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
3630
3631         rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
3632         r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
3633
3634         rdev->ih.ring_obj = NULL;
3635         r600_ih_ring_init(rdev, 64 * 1024);
3636
3637         r = r600_pcie_gart_init(rdev);
3638         if (r)
3639                 return r;
3640
3641         rdev->accel_working = true;
3642         r = evergreen_startup(rdev);
3643         if (r) {
3644                 dev_err(rdev->dev, "disabling GPU acceleration\n");
3645                 r700_cp_fini(rdev);
3646                 r600_dma_fini(rdev);
3647                 r600_irq_fini(rdev);
3648                 radeon_wb_fini(rdev);
3649                 radeon_ib_pool_fini(rdev);
3650                 radeon_irq_kms_fini(rdev);
3651                 evergreen_pcie_gart_fini(rdev);
3652                 rdev->accel_working = false;
3653         }
3654
3655         /* Don't start up if the MC ucode is missing on BTC parts.
3656          * The default clocks and voltages before the MC ucode
3657          * is loaded are not suffient for advanced operations.
3658          */
3659         if (ASIC_IS_DCE5(rdev)) {
3660                 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
3661                         DRM_ERROR("radeon: MC ucode required for NI+.\n");
3662                         return -EINVAL;
3663                 }
3664         }
3665
3666         return 0;
3667 }
3668
3669 void evergreen_fini(struct radeon_device *rdev)
3670 {
3671         r600_audio_fini(rdev);
3672         r600_blit_fini(rdev);
3673         r700_cp_fini(rdev);
3674         r600_dma_fini(rdev);
3675         r600_irq_fini(rdev);
3676         radeon_wb_fini(rdev);
3677         radeon_ib_pool_fini(rdev);
3678         radeon_irq_kms_fini(rdev);
3679         evergreen_pcie_gart_fini(rdev);
3680         r600_vram_scratch_fini(rdev);
3681         radeon_gem_fini(rdev);
3682         radeon_fence_driver_fini(rdev);
3683         radeon_agp_fini(rdev);
3684         radeon_bo_fini(rdev);
3685         radeon_atombios_fini(rdev);
3686         if (ASIC_IS_DCE5(rdev))
3687                 ni_fini_microcode(rdev);
3688         else
3689                 r600_fini_microcode(rdev);
3690         free(rdev->bios, DRM_MEM_DRIVER);
3691         rdev->bios = NULL;
3692 }
3693
3694 void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
3695 {
3696         u32 link_width_cntl, speed_cntl, mask;
3697         int ret;
3698
3699         if (radeon_pcie_gen2 == 0)
3700                 return;
3701
3702         if (rdev->flags & RADEON_IS_IGP)
3703                 return;
3704
3705         if (!(rdev->flags & RADEON_IS_PCIE))
3706                 return;
3707
3708         /* x2 cards have a special sequence */
3709         if (ASIC_IS_X2(rdev))
3710                 return;
3711
3712         ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
3713         if (ret != 0)
3714                 return;
3715
3716         if (!(mask & DRM_PCIE_SPEED_50))
3717                 return;
3718
3719         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3720         if (speed_cntl & LC_CURRENT_DATA_RATE) {
3721                 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
3722                 return;
3723         }
3724
3725         DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
3726
3727         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3728             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3729
3730                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3731                 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3732                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3733
3734                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3735                 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3736                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3737
3738                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3739                 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3740                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3741
3742                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3743                 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3744                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3745
3746                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3747                 speed_cntl |= LC_GEN2_EN_STRAP;
3748                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3749
3750         } else {
3751                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3752                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3753                 if (1)
3754                         link_width_cntl |= LC_UPCONFIGURE_DIS;
3755                 else
3756                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3757                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3758         }
3759 }