2 * Copyright 2010 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Alex Deucher <alexander.deucher@amd.com>
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <dev/drm2/drmP.h>
33 * evergreen cards need to use the 3D engine to blit data which requires
34 * quite a bit of hw state setup. Rather than pull the whole 3D driver
35 * (which normally generates the 3D state) into the DRM, we opt to use
36 * statically generated state tables. The regsiter state and shaders
37 * were hand generated to support blitting functionality. See the 3D
38 * driver or documentation for descriptions of the registers and
39 * shader instructions.
42 const u32 evergreen_default_state[] =
46 0x00000000, /* SQ_LDS_ALLOC_PS */
50 0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
59 0x00000000, /* SQ_GS_VERT_ITEMSIZE */
66 0x00000000, /* DB_Z_INFO */
67 0x00000000, /* DB_STENCIL_INFO */
71 0x00000000, /* DB_DEPTH_CONTROL */
75 0x00000060, /* DB_RENDER_CONTROL */
76 0x00000000, /* DB_COUNT_CONTROL */
77 0x00000000, /* DB_DEPTH_VIEW */
78 0x0000002a, /* DB_RENDER_OVERRIDE */
79 0x00000000, /* DB_RENDER_OVERRIDE2 */
80 0x00000000, /* DB_HTILE_DATA_BASE */
84 0x00000000, /* DB_STENCIL_CLEAR */
85 0x00000000, /* DB_DEPTH_CLEAR */
89 0x0000aa00, /* DB_ALPHA_TO_MASK */
93 0x00000000, /* PA_SC_WINDOW_OFFSET */
97 0x0000ffff, /* PA_SC_CLIPRECT_RULE */
98 0x00000000, /* PA_SC_CLIPRECT_0_TL */
99 0x20002000, /* PA_SC_CLIPRECT_0_BR */
106 0xaaaaaaaa, /* PA_SC_EDGERULE */
107 0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */
108 0x0000000f, /* CB_TARGET_MASK */
109 0x0000000f, /* CB_SHADER_MASK */
113 0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
114 0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
145 0x00000000, /* PA_SC_VPORT_ZMIN_0 */
146 0x3f800000, /* PA_SC_VPORT_ZMAX_0 */
150 0x00000000, /* SX_MISC */
154 0x00000000, /* PA_SC_MODE_CNTL_0 */
155 0x00000000, /* PA_SC_MODE_CNTL_1 */
159 0x00000000, /* PA_SC_LINE_CNTL */
160 0x00000000, /* PA_SC_AA_CONFIG */
161 0x00000005, /* PA_SU_VTX_CNTL */
162 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
163 0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */
164 0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */
165 0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */
166 0x00000000, /* PA_SC_AA_SAMPLE_LOCS_0 */
173 0x00000000, /* PA_SC_AA_SAMPLE_LOCS_7 */
174 0xffffffff, /* PA_SC_AA_MASK */
178 0x00cc0010, /* CB_COLOR_CONTROL */
179 0x00000210, /* DB_SHADER_CONTROL */
180 0x00010000, /* PA_CL_CLIP_CNTL */
181 0x00000004, /* PA_SU_SC_MODE_CNTL */
182 0x00000100, /* PA_CL_VTE_CNTL */
183 0x00000000, /* PA_CL_VS_OUT_CNTL */
184 0x00000000, /* PA_CL_NANINF_CNTL */
185 0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */
186 0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */
187 0x00000000, /* PA_SU_PRIM_FILTER_CNTL */
190 0x00000000, /* SQ_DYN_GPR_RESOURCE_LIMIT_1 */
194 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
203 0x00000000, /* SQ_PGM_START_FS */
207 0x00000000, /* SQ_PGM_RESOURCES_FS */
211 0x00ffffff, /* VGT_MAX_VTX_INDX */
215 0x00000000, /* SX_ALPHA_TEST_CONTROL */
216 0x00000000, /* CB_BLEND_RED */
217 0x00000000, /* CB_BLEND_GREEN */
218 0x00000000, /* CB_BLEND_BLUE */
219 0x00000000, /* CB_BLEND_ALPHA */
223 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
228 0x00000000, /* VGT_REUSE_OFF */
233 0x00000000, /* PA_SU_POINT_SIZE */
234 0x00000000, /* PA_SU_POINT_MINMAX */
235 0x00000008, /* PA_SU_LINE_CNTL */
236 0x00000000, /* PA_SC_LINE_STIPPLE */
237 0x00000000, /* VGT_OUTPUT_PATH_CNTL */
238 0x00000000, /* VGT_HOS_CNTL */
249 0x00000000, /* VGT_GS_MODE */
253 0x00000000, /* VGT_PRIMITIVEID_EN */
257 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */
261 0x00000000, /* VGT_SHADER_STAGES_EN */
265 0x00000000, /* VGT_STRMOUT_CONFIG */
270 0x00000000, /* CB_BLEND0_CONTROL */
274 0x00000000, /* SPI_VS_OUT_CONFIG */
278 0x00000000, /* SPI_VS_OUT_ID_0 */
282 0x00000100, /* SPI_PS_INPUT_CNTL_0 */
286 0x20000001, /* SPI_PS_IN_CONTROL_0 */
287 0x00000000, /* SPI_PS_IN_CONTROL_1 */
288 0x00000000, /* SPI_INTERP_CONTROL_0 */
289 0x00000000, /* SPI_INPUT_Z */
290 0x00000000, /* SPI_FOG_CNTL */
291 0x00100000, /* SPI_BARYC_CNTL */
292 0x00000000, /* SPI_PS_IN_CONTROL_2 */
300 0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */
304 const u32 evergreen_vs[] =
332 const u32 evergreen_ps[] =
356 const u32 evergreen_ps_size = DRM_ARRAY_SIZE(evergreen_ps);
357 const u32 evergreen_vs_size = DRM_ARRAY_SIZE(evergreen_vs);
358 const u32 evergreen_default_size = DRM_ARRAY_SIZE(evergreen_default_state);