2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <dev/drm2/drmP.h>
33 #include <dev/drm2/radeon/radeon_drm.h>
35 #include "radeon_asic.h"
36 #include "radeon_mode.h"
41 #define PFP_UCODE_SIZE 576
42 #define PM4_UCODE_SIZE 1792
43 #define RLC_UCODE_SIZE 768
44 #define R700_PFP_UCODE_SIZE 848
45 #define R700_PM4_UCODE_SIZE 1360
46 #define R700_RLC_UCODE_SIZE 1024
47 #define EVERGREEN_PFP_UCODE_SIZE 1120
48 #define EVERGREEN_PM4_UCODE_SIZE 1376
49 #define EVERGREEN_RLC_UCODE_SIZE 768
50 #define CAYMAN_RLC_UCODE_SIZE 1024
51 #define ARUBA_RLC_UCODE_SIZE 1536
55 MODULE_FIRMWARE("radeon/R600_pfp.bin");
56 MODULE_FIRMWARE("radeon/R600_me.bin");
57 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
58 MODULE_FIRMWARE("radeon/RV610_me.bin");
59 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
60 MODULE_FIRMWARE("radeon/RV630_me.bin");
61 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
62 MODULE_FIRMWARE("radeon/RV620_me.bin");
63 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
64 MODULE_FIRMWARE("radeon/RV635_me.bin");
65 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
66 MODULE_FIRMWARE("radeon/RV670_me.bin");
67 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
68 MODULE_FIRMWARE("radeon/RS780_me.bin");
69 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
70 MODULE_FIRMWARE("radeon/RV770_me.bin");
71 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
72 MODULE_FIRMWARE("radeon/RV730_me.bin");
73 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
74 MODULE_FIRMWARE("radeon/RV710_me.bin");
75 MODULE_FIRMWARE("radeon/R600_rlc.bin");
76 MODULE_FIRMWARE("radeon/R700_rlc.bin");
77 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
78 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
79 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
80 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
81 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
82 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
83 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
84 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
85 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
86 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
87 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
88 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
89 MODULE_FIRMWARE("radeon/PALM_pfp.bin");
90 MODULE_FIRMWARE("radeon/PALM_me.bin");
91 MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
92 MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
93 MODULE_FIRMWARE("radeon/SUMO_me.bin");
94 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
95 MODULE_FIRMWARE("radeon/SUMO2_me.bin");
96 #endif /* DUMBBELL_WIP */
98 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
100 /* r600,rv610,rv630,rv620,rv635,rv670 */
101 static void r600_gpu_init(struct radeon_device *rdev);
102 void r600_irq_disable(struct radeon_device *rdev);
103 static void r600_pcie_gen2_enable(struct radeon_device *rdev);
105 /* get temperature in millidegrees */
106 int rv6xx_get_temp(struct radeon_device *rdev)
108 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
110 int actual_temp = temp & 0xff;
115 return actual_temp * 1000;
118 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
122 rdev->pm.dynpm_can_upclock = true;
123 rdev->pm.dynpm_can_downclock = true;
125 /* power state array is low to high, default is first */
126 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
127 int min_power_state_index = 0;
129 if (rdev->pm.num_power_states > 2)
130 min_power_state_index = 1;
132 switch (rdev->pm.dynpm_planned_action) {
133 case DYNPM_ACTION_MINIMUM:
134 rdev->pm.requested_power_state_index = min_power_state_index;
135 rdev->pm.requested_clock_mode_index = 0;
136 rdev->pm.dynpm_can_downclock = false;
138 case DYNPM_ACTION_DOWNCLOCK:
139 if (rdev->pm.current_power_state_index == min_power_state_index) {
140 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
141 rdev->pm.dynpm_can_downclock = false;
143 if (rdev->pm.active_crtc_count > 1) {
144 for (i = 0; i < rdev->pm.num_power_states; i++) {
145 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
147 else if (i >= rdev->pm.current_power_state_index) {
148 rdev->pm.requested_power_state_index =
149 rdev->pm.current_power_state_index;
152 rdev->pm.requested_power_state_index = i;
157 if (rdev->pm.current_power_state_index == 0)
158 rdev->pm.requested_power_state_index =
159 rdev->pm.num_power_states - 1;
161 rdev->pm.requested_power_state_index =
162 rdev->pm.current_power_state_index - 1;
165 rdev->pm.requested_clock_mode_index = 0;
166 /* don't use the power state if crtcs are active and no display flag is set */
167 if ((rdev->pm.active_crtc_count > 0) &&
168 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
169 clock_info[rdev->pm.requested_clock_mode_index].flags &
170 RADEON_PM_MODE_NO_DISPLAY)) {
171 rdev->pm.requested_power_state_index++;
174 case DYNPM_ACTION_UPCLOCK:
175 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
176 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
177 rdev->pm.dynpm_can_upclock = false;
179 if (rdev->pm.active_crtc_count > 1) {
180 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
181 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
183 else if (i <= rdev->pm.current_power_state_index) {
184 rdev->pm.requested_power_state_index =
185 rdev->pm.current_power_state_index;
188 rdev->pm.requested_power_state_index = i;
193 rdev->pm.requested_power_state_index =
194 rdev->pm.current_power_state_index + 1;
196 rdev->pm.requested_clock_mode_index = 0;
198 case DYNPM_ACTION_DEFAULT:
199 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
200 rdev->pm.requested_clock_mode_index = 0;
201 rdev->pm.dynpm_can_upclock = false;
203 case DYNPM_ACTION_NONE:
205 DRM_ERROR("Requested mode for not defined action\n");
209 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
210 /* for now just select the first power state and switch between clock modes */
211 /* power state array is low to high, default is first (0) */
212 if (rdev->pm.active_crtc_count > 1) {
213 rdev->pm.requested_power_state_index = -1;
214 /* start at 1 as we don't want the default mode */
215 for (i = 1; i < rdev->pm.num_power_states; i++) {
216 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
218 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
219 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
220 rdev->pm.requested_power_state_index = i;
224 /* if nothing selected, grab the default state. */
225 if (rdev->pm.requested_power_state_index == -1)
226 rdev->pm.requested_power_state_index = 0;
228 rdev->pm.requested_power_state_index = 1;
230 switch (rdev->pm.dynpm_planned_action) {
231 case DYNPM_ACTION_MINIMUM:
232 rdev->pm.requested_clock_mode_index = 0;
233 rdev->pm.dynpm_can_downclock = false;
235 case DYNPM_ACTION_DOWNCLOCK:
236 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
237 if (rdev->pm.current_clock_mode_index == 0) {
238 rdev->pm.requested_clock_mode_index = 0;
239 rdev->pm.dynpm_can_downclock = false;
241 rdev->pm.requested_clock_mode_index =
242 rdev->pm.current_clock_mode_index - 1;
244 rdev->pm.requested_clock_mode_index = 0;
245 rdev->pm.dynpm_can_downclock = false;
247 /* don't use the power state if crtcs are active and no display flag is set */
248 if ((rdev->pm.active_crtc_count > 0) &&
249 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
250 clock_info[rdev->pm.requested_clock_mode_index].flags &
251 RADEON_PM_MODE_NO_DISPLAY)) {
252 rdev->pm.requested_clock_mode_index++;
255 case DYNPM_ACTION_UPCLOCK:
256 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
257 if (rdev->pm.current_clock_mode_index ==
258 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
259 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
260 rdev->pm.dynpm_can_upclock = false;
262 rdev->pm.requested_clock_mode_index =
263 rdev->pm.current_clock_mode_index + 1;
265 rdev->pm.requested_clock_mode_index =
266 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
267 rdev->pm.dynpm_can_upclock = false;
270 case DYNPM_ACTION_DEFAULT:
271 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
272 rdev->pm.requested_clock_mode_index = 0;
273 rdev->pm.dynpm_can_upclock = false;
275 case DYNPM_ACTION_NONE:
277 DRM_ERROR("Requested mode for not defined action\n");
282 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
283 rdev->pm.power_state[rdev->pm.requested_power_state_index].
284 clock_info[rdev->pm.requested_clock_mode_index].sclk,
285 rdev->pm.power_state[rdev->pm.requested_power_state_index].
286 clock_info[rdev->pm.requested_clock_mode_index].mclk,
287 rdev->pm.power_state[rdev->pm.requested_power_state_index].
291 void rs780_pm_init_profile(struct radeon_device *rdev)
293 if (rdev->pm.num_power_states == 2) {
295 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
296 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
297 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
298 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
300 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
301 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
302 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
303 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
305 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
306 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
307 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
308 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
310 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
311 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
312 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
313 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
315 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
316 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
317 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
318 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
320 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
321 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
322 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
323 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
325 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
326 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
327 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
328 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
329 } else if (rdev->pm.num_power_states == 3) {
331 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
332 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
333 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
334 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
336 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
337 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
338 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
339 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
341 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
342 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
343 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
344 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
346 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
347 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
348 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
349 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
351 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
352 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
353 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
354 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
356 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
357 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
358 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
359 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
361 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
362 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
363 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
364 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
367 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
368 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
369 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
370 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
372 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
373 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
374 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
375 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
377 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
378 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
379 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
380 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
382 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
383 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
384 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
385 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
387 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
388 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
389 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
390 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
392 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
393 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
394 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
395 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
397 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
398 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
399 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
400 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
404 void r600_pm_init_profile(struct radeon_device *rdev)
408 if (rdev->family == CHIP_R600) {
411 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
412 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
413 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
414 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
416 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
417 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
418 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
419 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
421 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
422 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
423 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
424 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
426 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
427 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
428 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
429 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
431 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
432 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
433 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
434 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
436 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
437 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
438 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
439 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
441 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
442 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
443 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
444 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
446 if (rdev->pm.num_power_states < 4) {
448 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
449 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
450 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
451 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
453 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
454 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
455 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
456 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
458 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
459 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
460 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
461 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
463 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
464 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
465 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
466 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
468 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
469 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
470 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
471 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
473 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
474 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
475 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
476 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
478 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
479 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
480 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
481 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
484 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
485 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
486 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
487 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
489 if (rdev->flags & RADEON_IS_MOBILITY)
490 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
492 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
493 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
494 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
495 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
496 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
498 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
499 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
500 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
501 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
503 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
504 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
505 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
506 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
507 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
509 if (rdev->flags & RADEON_IS_MOBILITY)
510 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
512 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
513 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
514 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
515 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
516 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
518 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
519 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
520 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
521 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
523 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
524 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
525 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
526 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
527 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
532 void r600_pm_misc(struct radeon_device *rdev)
534 int req_ps_idx = rdev->pm.requested_power_state_index;
535 int req_cm_idx = rdev->pm.requested_clock_mode_index;
536 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
537 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
539 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
540 /* 0xff01 is a flag rather then an actual voltage */
541 if (voltage->voltage == 0xff01)
543 if (voltage->voltage != rdev->pm.current_vddc) {
544 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
545 rdev->pm.current_vddc = voltage->voltage;
546 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
551 bool r600_gui_idle(struct radeon_device *rdev)
553 if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
559 /* hpd for digital panel detect/disconnect */
560 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
562 bool connected = false;
564 if (ASIC_IS_DCE3(rdev)) {
567 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
571 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
575 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
579 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
584 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
588 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
597 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
601 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
605 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
615 void r600_hpd_set_polarity(struct radeon_device *rdev,
616 enum radeon_hpd_id hpd)
619 bool connected = r600_hpd_sense(rdev, hpd);
621 if (ASIC_IS_DCE3(rdev)) {
624 tmp = RREG32(DC_HPD1_INT_CONTROL);
626 tmp &= ~DC_HPDx_INT_POLARITY;
628 tmp |= DC_HPDx_INT_POLARITY;
629 WREG32(DC_HPD1_INT_CONTROL, tmp);
632 tmp = RREG32(DC_HPD2_INT_CONTROL);
634 tmp &= ~DC_HPDx_INT_POLARITY;
636 tmp |= DC_HPDx_INT_POLARITY;
637 WREG32(DC_HPD2_INT_CONTROL, tmp);
640 tmp = RREG32(DC_HPD3_INT_CONTROL);
642 tmp &= ~DC_HPDx_INT_POLARITY;
644 tmp |= DC_HPDx_INT_POLARITY;
645 WREG32(DC_HPD3_INT_CONTROL, tmp);
648 tmp = RREG32(DC_HPD4_INT_CONTROL);
650 tmp &= ~DC_HPDx_INT_POLARITY;
652 tmp |= DC_HPDx_INT_POLARITY;
653 WREG32(DC_HPD4_INT_CONTROL, tmp);
656 tmp = RREG32(DC_HPD5_INT_CONTROL);
658 tmp &= ~DC_HPDx_INT_POLARITY;
660 tmp |= DC_HPDx_INT_POLARITY;
661 WREG32(DC_HPD5_INT_CONTROL, tmp);
665 tmp = RREG32(DC_HPD6_INT_CONTROL);
667 tmp &= ~DC_HPDx_INT_POLARITY;
669 tmp |= DC_HPDx_INT_POLARITY;
670 WREG32(DC_HPD6_INT_CONTROL, tmp);
678 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
680 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
682 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
683 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
686 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
688 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
690 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
691 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
694 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
696 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
698 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
699 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
707 void r600_hpd_init(struct radeon_device *rdev)
709 struct drm_device *dev = rdev->ddev;
710 struct drm_connector *connector;
713 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
714 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
716 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
717 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
718 /* don't try to enable hpd on eDP or LVDS avoid breaking the
719 * aux dp channel on imac and help (but not completely fix)
720 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
724 if (ASIC_IS_DCE3(rdev)) {
725 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
726 if (ASIC_IS_DCE32(rdev))
729 switch (radeon_connector->hpd.hpd) {
731 WREG32(DC_HPD1_CONTROL, tmp);
734 WREG32(DC_HPD2_CONTROL, tmp);
737 WREG32(DC_HPD3_CONTROL, tmp);
740 WREG32(DC_HPD4_CONTROL, tmp);
744 WREG32(DC_HPD5_CONTROL, tmp);
747 WREG32(DC_HPD6_CONTROL, tmp);
753 switch (radeon_connector->hpd.hpd) {
755 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
758 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
761 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
767 enable |= 1 << radeon_connector->hpd.hpd;
768 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
770 radeon_irq_kms_enable_hpd(rdev, enable);
773 void r600_hpd_fini(struct radeon_device *rdev)
775 struct drm_device *dev = rdev->ddev;
776 struct drm_connector *connector;
777 unsigned disable = 0;
779 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
780 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
781 if (ASIC_IS_DCE3(rdev)) {
782 switch (radeon_connector->hpd.hpd) {
784 WREG32(DC_HPD1_CONTROL, 0);
787 WREG32(DC_HPD2_CONTROL, 0);
790 WREG32(DC_HPD3_CONTROL, 0);
793 WREG32(DC_HPD4_CONTROL, 0);
797 WREG32(DC_HPD5_CONTROL, 0);
800 WREG32(DC_HPD6_CONTROL, 0);
806 switch (radeon_connector->hpd.hpd) {
808 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
811 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
814 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
820 disable |= 1 << radeon_connector->hpd.hpd;
822 radeon_irq_kms_disable_hpd(rdev, disable);
828 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
833 /* flush hdp cache so updates hit vram */
834 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
835 !(rdev->flags & RADEON_IS_AGP)) {
836 volatile uint32_t *ptr = rdev->gart.ptr;
839 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
840 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
841 * This seems to cause problems on some AGP cards. Just use the old
844 WREG32(HDP_DEBUG1, 0);
847 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
849 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
850 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
851 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
852 for (i = 0; i < rdev->usec_timeout; i++) {
854 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
855 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
857 DRM_ERROR("[drm] r600 flush TLB failed\n");
867 int r600_pcie_gart_init(struct radeon_device *rdev)
871 if (rdev->gart.robj) {
872 DRM_ERROR("R600 PCIE GART already initialized\n");
875 /* Initialize common gart structure */
876 r = radeon_gart_init(rdev);
879 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
880 return radeon_gart_table_vram_alloc(rdev);
883 static int r600_pcie_gart_enable(struct radeon_device *rdev)
888 if (rdev->gart.robj == NULL) {
889 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
892 r = radeon_gart_table_vram_pin(rdev);
895 radeon_gart_restore(rdev);
898 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
899 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
900 EFFECTIVE_L2_QUEUE_SIZE(7));
901 WREG32(VM_L2_CNTL2, 0);
902 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
903 /* Setup TLB control */
904 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
905 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
906 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
907 ENABLE_WAIT_L2_QUERY;
908 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
909 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
910 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
911 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
912 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
913 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
914 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
915 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
916 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
917 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
918 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
919 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
920 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
921 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
922 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
923 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
924 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
925 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
926 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
927 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
928 (u32)(rdev->dummy_page.addr >> 12));
929 for (i = 1; i < 7; i++)
930 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
932 r600_pcie_gart_tlb_flush(rdev);
933 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
934 (unsigned)(rdev->mc.gtt_size >> 20),
935 (unsigned long long)rdev->gart.table_addr);
936 rdev->gart.ready = true;
940 static void r600_pcie_gart_disable(struct radeon_device *rdev)
945 /* Disable all tables */
946 for (i = 0; i < 7; i++)
947 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
949 /* Disable L2 cache */
950 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
951 EFFECTIVE_L2_QUEUE_SIZE(7));
952 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
953 /* Setup L1 TLB control */
954 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
955 ENABLE_WAIT_L2_QUERY;
956 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
957 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
958 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
959 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
960 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
961 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
962 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
963 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
964 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
965 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
966 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
967 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
968 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
969 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
970 radeon_gart_table_vram_unpin(rdev);
973 static void r600_pcie_gart_fini(struct radeon_device *rdev)
975 radeon_gart_fini(rdev);
976 r600_pcie_gart_disable(rdev);
977 radeon_gart_table_vram_free(rdev);
980 static void r600_agp_enable(struct radeon_device *rdev)
986 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
987 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
988 EFFECTIVE_L2_QUEUE_SIZE(7));
989 WREG32(VM_L2_CNTL2, 0);
990 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
991 /* Setup TLB control */
992 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
993 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
994 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
995 ENABLE_WAIT_L2_QUERY;
996 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
997 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
998 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
999 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1000 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1001 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1002 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1003 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1004 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1005 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1006 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1007 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1008 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1009 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1010 for (i = 0; i < 7; i++)
1011 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1014 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1019 for (i = 0; i < rdev->usec_timeout; i++) {
1020 /* read MC_STATUS */
1021 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1029 static void r600_mc_program(struct radeon_device *rdev)
1031 struct rv515_mc_save save;
1035 /* Initialize HDP */
1036 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1037 WREG32((0x2c14 + j), 0x00000000);
1038 WREG32((0x2c18 + j), 0x00000000);
1039 WREG32((0x2c1c + j), 0x00000000);
1040 WREG32((0x2c20 + j), 0x00000000);
1041 WREG32((0x2c24 + j), 0x00000000);
1043 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1045 rv515_mc_stop(rdev, &save);
1046 if (r600_mc_wait_for_idle(rdev)) {
1047 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1049 /* Lockout access through VGA aperture (doesn't exist before R600) */
1050 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1051 /* Update configuration */
1052 if (rdev->flags & RADEON_IS_AGP) {
1053 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1054 /* VRAM before AGP */
1055 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1056 rdev->mc.vram_start >> 12);
1057 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1058 rdev->mc.gtt_end >> 12);
1060 /* VRAM after AGP */
1061 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1062 rdev->mc.gtt_start >> 12);
1063 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1064 rdev->mc.vram_end >> 12);
1067 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1068 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1070 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1071 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1072 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1073 WREG32(MC_VM_FB_LOCATION, tmp);
1074 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1075 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1076 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1077 if (rdev->flags & RADEON_IS_AGP) {
1078 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1079 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1080 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1082 WREG32(MC_VM_AGP_BASE, 0);
1083 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1084 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1086 if (r600_mc_wait_for_idle(rdev)) {
1087 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1089 rv515_mc_resume(rdev, &save);
1090 /* we need to own VRAM, so turn off the VGA renderer here
1091 * to stop it overwriting our objects */
1092 rv515_vga_render_disable(rdev);
1096 * r600_vram_gtt_location - try to find VRAM & GTT location
1097 * @rdev: radeon device structure holding all necessary informations
1098 * @mc: memory controller structure holding memory informations
1100 * Function will place try to place VRAM at same place as in CPU (PCI)
1101 * address space as some GPU seems to have issue when we reprogram at
1102 * different address space.
1104 * If there is not enough space to fit the unvisible VRAM after the
1105 * aperture then we limit the VRAM size to the aperture.
1107 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1108 * them to be in one from GPU point of view so that we can program GPU to
1109 * catch access outside them (weird GPU policy see ??).
1111 * This function will never fails, worst case are limiting VRAM or GTT.
1113 * Note: GTT start, end, size should be initialized before calling this
1114 * function on AGP platform.
1116 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1118 u64 size_bf, size_af;
1120 if (mc->mc_vram_size > 0xE0000000) {
1121 /* leave room for at least 512M GTT */
1122 dev_warn(rdev->dev, "limiting VRAM\n");
1123 mc->real_vram_size = 0xE0000000;
1124 mc->mc_vram_size = 0xE0000000;
1126 if (rdev->flags & RADEON_IS_AGP) {
1127 size_bf = mc->gtt_start;
1128 size_af = 0xFFFFFFFF - mc->gtt_end;
1129 if (size_bf > size_af) {
1130 if (mc->mc_vram_size > size_bf) {
1131 dev_warn(rdev->dev, "limiting VRAM\n");
1132 mc->real_vram_size = size_bf;
1133 mc->mc_vram_size = size_bf;
1135 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1137 if (mc->mc_vram_size > size_af) {
1138 dev_warn(rdev->dev, "limiting VRAM\n");
1139 mc->real_vram_size = size_af;
1140 mc->mc_vram_size = size_af;
1142 mc->vram_start = mc->gtt_end + 1;
1144 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1145 dev_info(rdev->dev, "VRAM: %juM 0x%08jX - 0x%08jX (%juM used)\n",
1146 (uintmax_t)mc->mc_vram_size >> 20, (uintmax_t)mc->vram_start,
1147 (uintmax_t)mc->vram_end, (uintmax_t)mc->real_vram_size >> 20);
1150 if (rdev->flags & RADEON_IS_IGP) {
1151 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1154 radeon_vram_location(rdev, &rdev->mc, base);
1155 rdev->mc.gtt_base_align = 0;
1156 radeon_gtt_location(rdev, mc);
1160 static int r600_mc_init(struct radeon_device *rdev)
1163 int chansize, numchan;
1165 /* Get VRAM informations */
1166 rdev->mc.vram_is_ddr = true;
1167 tmp = RREG32(RAMCFG);
1168 if (tmp & CHANSIZE_OVERRIDE) {
1170 } else if (tmp & CHANSIZE_MASK) {
1175 tmp = RREG32(CHMAP);
1176 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1191 rdev->mc.vram_width = numchan * chansize;
1192 /* Could aper size report 0 ? */
1193 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1194 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1195 /* Setup GPU memory space */
1196 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1197 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1198 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1199 r600_vram_gtt_location(rdev, &rdev->mc);
1201 if (rdev->flags & RADEON_IS_IGP) {
1202 rs690_pm_info(rdev);
1203 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1205 radeon_update_bandwidth_info(rdev);
1209 int r600_vram_scratch_init(struct radeon_device *rdev)
1212 void *vram_scratch_ptr_ptr;
1214 if (rdev->vram_scratch.robj == NULL) {
1215 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
1216 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
1217 NULL, &rdev->vram_scratch.robj);
1223 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1224 if (unlikely(r != 0)) {
1225 radeon_bo_unref(&rdev->vram_scratch.robj);
1228 r = radeon_bo_pin(rdev->vram_scratch.robj,
1229 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
1231 radeon_bo_unreserve(rdev->vram_scratch.robj);
1232 radeon_bo_unref(&rdev->vram_scratch.robj);
1235 vram_scratch_ptr_ptr = &rdev->vram_scratch.ptr;
1236 r = radeon_bo_kmap(rdev->vram_scratch.robj,
1237 vram_scratch_ptr_ptr);
1239 radeon_bo_unpin(rdev->vram_scratch.robj);
1240 radeon_bo_unreserve(rdev->vram_scratch.robj);
1242 radeon_bo_unref(&rdev->vram_scratch.robj);
1247 void r600_vram_scratch_fini(struct radeon_device *rdev)
1251 if (rdev->vram_scratch.robj == NULL) {
1254 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1255 if (likely(r == 0)) {
1256 radeon_bo_kunmap(rdev->vram_scratch.robj);
1257 radeon_bo_unpin(rdev->vram_scratch.robj);
1258 radeon_bo_unreserve(rdev->vram_scratch.robj);
1260 radeon_bo_unref(&rdev->vram_scratch.robj);
1263 /* We doesn't check that the GPU really needs a reset we simply do the
1264 * reset, it's up to the caller to determine if the GPU needs one. We
1265 * might add an helper function to check that.
1267 static void r600_gpu_soft_reset_gfx(struct radeon_device *rdev)
1269 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1270 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1271 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1272 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1273 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1274 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1275 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1276 S_008010_GUI_ACTIVE(1);
1277 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1278 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1279 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1280 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1281 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1282 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1283 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1284 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
1287 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1290 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n",
1291 RREG32(R_008010_GRBM_STATUS));
1292 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n",
1293 RREG32(R_008014_GRBM_STATUS2));
1294 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n",
1295 RREG32(R_000E50_SRBM_STATUS));
1296 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1297 RREG32(CP_STALLED_STAT1));
1298 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1299 RREG32(CP_STALLED_STAT2));
1300 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
1301 RREG32(CP_BUSY_STAT));
1302 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
1305 /* Disable CP parsing/prefetching */
1306 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1308 /* Check if any of the rendering block is busy and reset it */
1309 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1310 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
1311 tmp = S_008020_SOFT_RESET_CR(1) |
1312 S_008020_SOFT_RESET_DB(1) |
1313 S_008020_SOFT_RESET_CB(1) |
1314 S_008020_SOFT_RESET_PA(1) |
1315 S_008020_SOFT_RESET_SC(1) |
1316 S_008020_SOFT_RESET_SMX(1) |
1317 S_008020_SOFT_RESET_SPI(1) |
1318 S_008020_SOFT_RESET_SX(1) |
1319 S_008020_SOFT_RESET_SH(1) |
1320 S_008020_SOFT_RESET_TC(1) |
1321 S_008020_SOFT_RESET_TA(1) |
1322 S_008020_SOFT_RESET_VC(1) |
1323 S_008020_SOFT_RESET_VGT(1);
1324 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1325 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1326 RREG32(R_008020_GRBM_SOFT_RESET);
1328 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1330 /* Reset CP (we always reset CP) */
1331 tmp = S_008020_SOFT_RESET_CP(1);
1332 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1333 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1334 RREG32(R_008020_GRBM_SOFT_RESET);
1336 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1338 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n",
1339 RREG32(R_008010_GRBM_STATUS));
1340 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n",
1341 RREG32(R_008014_GRBM_STATUS2));
1342 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n",
1343 RREG32(R_000E50_SRBM_STATUS));
1344 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1345 RREG32(CP_STALLED_STAT1));
1346 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1347 RREG32(CP_STALLED_STAT2));
1348 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
1349 RREG32(CP_BUSY_STAT));
1350 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
1355 static void r600_gpu_soft_reset_dma(struct radeon_device *rdev)
1359 if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
1362 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
1363 RREG32(DMA_STATUS_REG));
1366 tmp = RREG32(DMA_RB_CNTL);
1367 tmp &= ~DMA_RB_ENABLE;
1368 WREG32(DMA_RB_CNTL, tmp);
1371 if (rdev->family >= CHIP_RV770)
1372 WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA);
1374 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
1375 RREG32(SRBM_SOFT_RESET);
1377 WREG32(SRBM_SOFT_RESET, 0);
1379 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
1380 RREG32(DMA_STATUS_REG));
1383 static int r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1385 struct rv515_mc_save save;
1387 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1388 reset_mask &= ~(RADEON_RESET_GFX | RADEON_RESET_COMPUTE);
1390 if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
1391 reset_mask &= ~RADEON_RESET_DMA;
1393 if (reset_mask == 0)
1396 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1398 rv515_mc_stop(rdev, &save);
1399 if (r600_mc_wait_for_idle(rdev)) {
1400 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1403 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE))
1404 r600_gpu_soft_reset_gfx(rdev);
1406 if (reset_mask & RADEON_RESET_DMA)
1407 r600_gpu_soft_reset_dma(rdev);
1409 /* Wait a little for things to settle down */
1412 rv515_mc_resume(rdev, &save);
1416 bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1422 srbm_status = RREG32(R_000E50_SRBM_STATUS);
1423 grbm_status = RREG32(R_008010_GRBM_STATUS);
1424 grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1425 if (!G_008010_GUI_ACTIVE(grbm_status)) {
1426 radeon_ring_lockup_update(ring);
1429 /* force CP activities */
1430 radeon_ring_force_activity(rdev, ring);
1431 return radeon_ring_test_lockup(rdev, ring);
1435 * r600_dma_is_lockup - Check if the DMA engine is locked up
1437 * @rdev: radeon_device pointer
1438 * @ring: radeon_ring structure holding ring information
1440 * Check if the async DMA engine is locked up (r6xx-evergreen).
1441 * Returns true if the engine appears to be locked up, false if not.
1443 bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1447 dma_status_reg = RREG32(DMA_STATUS_REG);
1448 if (dma_status_reg & DMA_IDLE) {
1449 radeon_ring_lockup_update(ring);
1452 /* force ring activities */
1453 radeon_ring_force_activity(rdev, ring);
1454 return radeon_ring_test_lockup(rdev, ring);
1457 int r600_asic_reset(struct radeon_device *rdev)
1459 return r600_gpu_soft_reset(rdev, (RADEON_RESET_GFX |
1460 RADEON_RESET_COMPUTE |
1464 u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1465 u32 tiling_pipe_num,
1467 u32 total_max_rb_num,
1468 u32 disabled_rb_mask)
1470 u32 rendering_pipe_num, rb_num_width, req_rb_num;
1471 u32 pipe_rb_ratio, pipe_rb_remain, tmp;
1472 u32 data = 0, mask = 1 << (max_rb_num - 1);
1475 /* mask out the RBs that don't exist on that asic */
1476 tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff);
1477 /* make sure at least one RB is available */
1478 if ((tmp & 0xff) != 0xff)
1479 disabled_rb_mask = tmp;
1481 rendering_pipe_num = 1 << tiling_pipe_num;
1482 req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask);
1483 KASSERT(rendering_pipe_num >= req_rb_num, ("rendering_pipe_num < req_rb_num"));
1485 pipe_rb_ratio = rendering_pipe_num / req_rb_num;
1486 pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num;
1488 if (rdev->family <= CHIP_RV740) {
1496 for (i = 0; i < max_rb_num; i++) {
1497 if (!(mask & disabled_rb_mask)) {
1498 for (j = 0; j < pipe_rb_ratio; j++) {
1499 data <<= rb_num_width;
1500 data |= max_rb_num - i - 1;
1502 if (pipe_rb_remain) {
1503 data <<= rb_num_width;
1504 data |= max_rb_num - i - 1;
1514 int r600_count_pipe_bits(uint32_t val)
1516 return hweight32(val);
1519 static void r600_gpu_init(struct radeon_device *rdev)
1523 u32 cc_rb_backend_disable;
1524 u32 cc_gc_shader_pipe_config;
1528 u32 sq_gpr_resource_mgmt_1 = 0;
1529 u32 sq_gpr_resource_mgmt_2 = 0;
1530 u32 sq_thread_resource_mgmt = 0;
1531 u32 sq_stack_resource_mgmt_1 = 0;
1532 u32 sq_stack_resource_mgmt_2 = 0;
1533 u32 disabled_rb_mask;
1535 rdev->config.r600.tiling_group_size = 256;
1536 switch (rdev->family) {
1538 rdev->config.r600.max_pipes = 4;
1539 rdev->config.r600.max_tile_pipes = 8;
1540 rdev->config.r600.max_simds = 4;
1541 rdev->config.r600.max_backends = 4;
1542 rdev->config.r600.max_gprs = 256;
1543 rdev->config.r600.max_threads = 192;
1544 rdev->config.r600.max_stack_entries = 256;
1545 rdev->config.r600.max_hw_contexts = 8;
1546 rdev->config.r600.max_gs_threads = 16;
1547 rdev->config.r600.sx_max_export_size = 128;
1548 rdev->config.r600.sx_max_export_pos_size = 16;
1549 rdev->config.r600.sx_max_export_smx_size = 128;
1550 rdev->config.r600.sq_num_cf_insts = 2;
1554 rdev->config.r600.max_pipes = 2;
1555 rdev->config.r600.max_tile_pipes = 2;
1556 rdev->config.r600.max_simds = 3;
1557 rdev->config.r600.max_backends = 1;
1558 rdev->config.r600.max_gprs = 128;
1559 rdev->config.r600.max_threads = 192;
1560 rdev->config.r600.max_stack_entries = 128;
1561 rdev->config.r600.max_hw_contexts = 8;
1562 rdev->config.r600.max_gs_threads = 4;
1563 rdev->config.r600.sx_max_export_size = 128;
1564 rdev->config.r600.sx_max_export_pos_size = 16;
1565 rdev->config.r600.sx_max_export_smx_size = 128;
1566 rdev->config.r600.sq_num_cf_insts = 2;
1572 rdev->config.r600.max_pipes = 1;
1573 rdev->config.r600.max_tile_pipes = 1;
1574 rdev->config.r600.max_simds = 2;
1575 rdev->config.r600.max_backends = 1;
1576 rdev->config.r600.max_gprs = 128;
1577 rdev->config.r600.max_threads = 192;
1578 rdev->config.r600.max_stack_entries = 128;
1579 rdev->config.r600.max_hw_contexts = 4;
1580 rdev->config.r600.max_gs_threads = 4;
1581 rdev->config.r600.sx_max_export_size = 128;
1582 rdev->config.r600.sx_max_export_pos_size = 16;
1583 rdev->config.r600.sx_max_export_smx_size = 128;
1584 rdev->config.r600.sq_num_cf_insts = 1;
1587 rdev->config.r600.max_pipes = 4;
1588 rdev->config.r600.max_tile_pipes = 4;
1589 rdev->config.r600.max_simds = 4;
1590 rdev->config.r600.max_backends = 4;
1591 rdev->config.r600.max_gprs = 192;
1592 rdev->config.r600.max_threads = 192;
1593 rdev->config.r600.max_stack_entries = 256;
1594 rdev->config.r600.max_hw_contexts = 8;
1595 rdev->config.r600.max_gs_threads = 16;
1596 rdev->config.r600.sx_max_export_size = 128;
1597 rdev->config.r600.sx_max_export_pos_size = 16;
1598 rdev->config.r600.sx_max_export_smx_size = 128;
1599 rdev->config.r600.sq_num_cf_insts = 2;
1605 /* Initialize HDP */
1606 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1607 WREG32((0x2c14 + j), 0x00000000);
1608 WREG32((0x2c18 + j), 0x00000000);
1609 WREG32((0x2c1c + j), 0x00000000);
1610 WREG32((0x2c20 + j), 0x00000000);
1611 WREG32((0x2c24 + j), 0x00000000);
1614 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1618 ramcfg = RREG32(RAMCFG);
1619 switch (rdev->config.r600.max_tile_pipes) {
1621 tiling_config |= PIPE_TILING(0);
1624 tiling_config |= PIPE_TILING(1);
1627 tiling_config |= PIPE_TILING(2);
1630 tiling_config |= PIPE_TILING(3);
1635 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1636 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1637 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1638 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1640 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1642 tiling_config |= ROW_TILING(3);
1643 tiling_config |= SAMPLE_SPLIT(3);
1645 tiling_config |= ROW_TILING(tmp);
1646 tiling_config |= SAMPLE_SPLIT(tmp);
1648 tiling_config |= BANK_SWAPS(1);
1650 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1651 tmp = R6XX_MAX_BACKENDS -
1652 r600_count_pipe_bits((cc_rb_backend_disable >> 16) & R6XX_MAX_BACKENDS_MASK);
1653 if (tmp < rdev->config.r600.max_backends) {
1654 rdev->config.r600.max_backends = tmp;
1657 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00;
1658 tmp = R6XX_MAX_PIPES -
1659 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R6XX_MAX_PIPES_MASK);
1660 if (tmp < rdev->config.r600.max_pipes) {
1661 rdev->config.r600.max_pipes = tmp;
1663 tmp = R6XX_MAX_SIMDS -
1664 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK);
1665 if (tmp < rdev->config.r600.max_simds) {
1666 rdev->config.r600.max_simds = tmp;
1669 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK;
1670 tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
1671 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,
1672 R6XX_MAX_BACKENDS, disabled_rb_mask);
1673 tiling_config |= tmp << 16;
1674 rdev->config.r600.backend_map = tmp;
1676 rdev->config.r600.tile_config = tiling_config;
1677 WREG32(GB_TILING_CONFIG, tiling_config);
1678 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1679 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1680 WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff);
1682 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1683 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1684 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1686 /* Setup some CP states */
1687 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1688 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1690 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1691 SYNC_WALKER | SYNC_ALIGNER));
1692 /* Setup various GPU states */
1693 if (rdev->family == CHIP_RV670)
1694 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1696 tmp = RREG32(SX_DEBUG_1);
1697 tmp |= SMX_EVENT_RELEASE;
1698 if ((rdev->family > CHIP_R600))
1699 tmp |= ENABLE_NEW_SMX_ADDRESS;
1700 WREG32(SX_DEBUG_1, tmp);
1702 if (((rdev->family) == CHIP_R600) ||
1703 ((rdev->family) == CHIP_RV630) ||
1704 ((rdev->family) == CHIP_RV610) ||
1705 ((rdev->family) == CHIP_RV620) ||
1706 ((rdev->family) == CHIP_RS780) ||
1707 ((rdev->family) == CHIP_RS880)) {
1708 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1710 WREG32(DB_DEBUG, 0);
1712 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1713 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1715 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1716 WREG32(VGT_NUM_INSTANCES, 0);
1718 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1719 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1721 tmp = RREG32(SQ_MS_FIFO_SIZES);
1722 if (((rdev->family) == CHIP_RV610) ||
1723 ((rdev->family) == CHIP_RV620) ||
1724 ((rdev->family) == CHIP_RS780) ||
1725 ((rdev->family) == CHIP_RS880)) {
1726 tmp = (CACHE_FIFO_SIZE(0xa) |
1727 FETCH_FIFO_HIWATER(0xa) |
1728 DONE_FIFO_HIWATER(0xe0) |
1729 ALU_UPDATE_FIFO_HIWATER(0x8));
1730 } else if (((rdev->family) == CHIP_R600) ||
1731 ((rdev->family) == CHIP_RV630)) {
1732 tmp &= ~DONE_FIFO_HIWATER(0xff);
1733 tmp |= DONE_FIFO_HIWATER(0x4);
1735 WREG32(SQ_MS_FIFO_SIZES, tmp);
1737 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1738 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1740 sq_config = RREG32(SQ_CONFIG);
1741 sq_config &= ~(PS_PRIO(3) |
1745 sq_config |= (DX9_CONSTS |
1752 if ((rdev->family) == CHIP_R600) {
1753 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1755 NUM_CLAUSE_TEMP_GPRS(4));
1756 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1758 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1759 NUM_VS_THREADS(48) |
1762 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1763 NUM_VS_STACK_ENTRIES(128));
1764 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1765 NUM_ES_STACK_ENTRIES(0));
1766 } else if (((rdev->family) == CHIP_RV610) ||
1767 ((rdev->family) == CHIP_RV620) ||
1768 ((rdev->family) == CHIP_RS780) ||
1769 ((rdev->family) == CHIP_RS880)) {
1770 /* no vertex cache */
1771 sq_config &= ~VC_ENABLE;
1773 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1775 NUM_CLAUSE_TEMP_GPRS(2));
1776 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1778 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1779 NUM_VS_THREADS(78) |
1781 NUM_ES_THREADS(31));
1782 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1783 NUM_VS_STACK_ENTRIES(40));
1784 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1785 NUM_ES_STACK_ENTRIES(16));
1786 } else if (((rdev->family) == CHIP_RV630) ||
1787 ((rdev->family) == CHIP_RV635)) {
1788 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1790 NUM_CLAUSE_TEMP_GPRS(2));
1791 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1793 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1794 NUM_VS_THREADS(78) |
1796 NUM_ES_THREADS(31));
1797 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1798 NUM_VS_STACK_ENTRIES(40));
1799 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1800 NUM_ES_STACK_ENTRIES(16));
1801 } else if ((rdev->family) == CHIP_RV670) {
1802 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1804 NUM_CLAUSE_TEMP_GPRS(2));
1805 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1807 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1808 NUM_VS_THREADS(78) |
1810 NUM_ES_THREADS(31));
1811 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1812 NUM_VS_STACK_ENTRIES(64));
1813 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1814 NUM_ES_STACK_ENTRIES(64));
1817 WREG32(SQ_CONFIG, sq_config);
1818 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1819 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1820 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1821 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1822 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1824 if (((rdev->family) == CHIP_RV610) ||
1825 ((rdev->family) == CHIP_RV620) ||
1826 ((rdev->family) == CHIP_RS780) ||
1827 ((rdev->family) == CHIP_RS880)) {
1828 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1830 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1833 /* More default values. 2D/3D driver should adjust as needed */
1834 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1835 S1_X(0x4) | S1_Y(0xc)));
1836 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1837 S1_X(0x2) | S1_Y(0x2) |
1838 S2_X(0xa) | S2_Y(0x6) |
1839 S3_X(0x6) | S3_Y(0xa)));
1840 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1841 S1_X(0x4) | S1_Y(0xc) |
1842 S2_X(0x1) | S2_Y(0x6) |
1843 S3_X(0xa) | S3_Y(0xe)));
1844 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1845 S5_X(0x0) | S5_Y(0x0) |
1846 S6_X(0xb) | S6_Y(0x4) |
1847 S7_X(0x7) | S7_Y(0x8)));
1849 WREG32(VGT_STRMOUT_EN, 0);
1850 tmp = rdev->config.r600.max_pipes * 16;
1851 switch (rdev->family) {
1867 WREG32(VGT_ES_PER_GS, 128);
1868 WREG32(VGT_GS_PER_ES, tmp);
1869 WREG32(VGT_GS_PER_VS, 2);
1870 WREG32(VGT_GS_VERTEX_REUSE, 16);
1872 /* more default values. 2D/3D driver should adjust as needed */
1873 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1874 WREG32(VGT_STRMOUT_EN, 0);
1876 WREG32(PA_SC_MODE_CNTL, 0);
1877 WREG32(PA_SC_AA_CONFIG, 0);
1878 WREG32(PA_SC_LINE_STIPPLE, 0);
1879 WREG32(SPI_INPUT_Z, 0);
1880 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1881 WREG32(CB_COLOR7_FRAG, 0);
1883 /* Clear render buffer base addresses */
1884 WREG32(CB_COLOR0_BASE, 0);
1885 WREG32(CB_COLOR1_BASE, 0);
1886 WREG32(CB_COLOR2_BASE, 0);
1887 WREG32(CB_COLOR3_BASE, 0);
1888 WREG32(CB_COLOR4_BASE, 0);
1889 WREG32(CB_COLOR5_BASE, 0);
1890 WREG32(CB_COLOR6_BASE, 0);
1891 WREG32(CB_COLOR7_BASE, 0);
1892 WREG32(CB_COLOR7_FRAG, 0);
1894 switch (rdev->family) {
1899 tmp = TC_L2_SIZE(8);
1903 tmp = TC_L2_SIZE(4);
1906 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1909 tmp = TC_L2_SIZE(0);
1912 WREG32(TC_CNTL, tmp);
1914 tmp = RREG32(HDP_HOST_PATH_CNTL);
1915 WREG32(HDP_HOST_PATH_CNTL, tmp);
1917 tmp = RREG32(ARB_POP);
1918 tmp |= ENABLE_TC128;
1919 WREG32(ARB_POP, tmp);
1921 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1922 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1924 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1925 WREG32(VC_ENHANCE, 0);
1930 * Indirect registers accessor
1932 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1936 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1937 (void)RREG32(PCIE_PORT_INDEX);
1938 r = RREG32(PCIE_PORT_DATA);
1942 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1944 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1945 (void)RREG32(PCIE_PORT_INDEX);
1946 WREG32(PCIE_PORT_DATA, (v));
1947 (void)RREG32(PCIE_PORT_DATA);
1953 void r600_cp_stop(struct radeon_device *rdev)
1955 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1956 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1957 WREG32(SCRATCH_UMSK, 0);
1958 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1961 int r600_init_microcode(struct radeon_device *rdev)
1963 const char *chip_name;
1964 const char *rlc_chip_name;
1965 size_t pfp_req_size, me_req_size, rlc_req_size;
1971 switch (rdev->family) {
1974 rlc_chip_name = "R600";
1977 chip_name = "RV610";
1978 rlc_chip_name = "R600";
1981 chip_name = "RV630";
1982 rlc_chip_name = "R600";
1985 chip_name = "RV620";
1986 rlc_chip_name = "R600";
1989 chip_name = "RV635";
1990 rlc_chip_name = "R600";
1993 chip_name = "RV670";
1994 rlc_chip_name = "R600";
1998 chip_name = "RS780";
1999 rlc_chip_name = "R600";
2002 chip_name = "RV770";
2003 rlc_chip_name = "R700";
2007 chip_name = "RV730";
2008 rlc_chip_name = "R700";
2011 chip_name = "RV710";
2012 rlc_chip_name = "R700";
2015 chip_name = "CEDAR";
2016 rlc_chip_name = "CEDAR";
2019 chip_name = "REDWOOD";
2020 rlc_chip_name = "REDWOOD";
2023 chip_name = "JUNIPER";
2024 rlc_chip_name = "JUNIPER";
2028 chip_name = "CYPRESS";
2029 rlc_chip_name = "CYPRESS";
2033 rlc_chip_name = "SUMO";
2037 rlc_chip_name = "SUMO";
2040 chip_name = "SUMO2";
2041 rlc_chip_name = "SUMO";
2043 default: panic("%s: Unsupported family %d", __func__, rdev->family);
2046 if (rdev->family >= CHIP_CEDAR) {
2047 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2048 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
2049 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
2050 } else if (rdev->family >= CHIP_RV770) {
2051 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2052 me_req_size = R700_PM4_UCODE_SIZE * 4;
2053 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
2055 pfp_req_size = PFP_UCODE_SIZE * 4;
2056 me_req_size = PM4_UCODE_SIZE * 12;
2057 rlc_req_size = RLC_UCODE_SIZE * 4;
2060 DRM_INFO("Loading %s Microcode\n", chip_name);
2063 snprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_pfp", chip_name);
2064 rdev->pfp_fw = firmware_get(fw_name);
2065 if (rdev->pfp_fw == NULL) {
2069 if (rdev->pfp_fw->datasize != pfp_req_size) {
2071 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2072 rdev->pfp_fw->datasize, fw_name);
2077 snprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_me", chip_name);
2078 rdev->me_fw = firmware_get(fw_name);
2079 if (rdev->me_fw == NULL) {
2083 if (rdev->me_fw->datasize != me_req_size) {
2085 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2086 rdev->me_fw->datasize, fw_name);
2090 snprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_rlc", rlc_chip_name);
2091 rdev->rlc_fw = firmware_get(fw_name);
2092 if (rdev->rlc_fw == NULL) {
2096 if (rdev->rlc_fw->datasize != rlc_req_size) {
2098 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2099 rdev->rlc_fw->datasize, fw_name);
2107 "r600_cp: Failed to load firmware \"%s\"\n",
2109 if (rdev->pfp_fw != NULL) {
2110 firmware_put(rdev->pfp_fw, FIRMWARE_UNLOAD);
2111 rdev->pfp_fw = NULL;
2113 if (rdev->me_fw != NULL) {
2114 firmware_put(rdev->me_fw, FIRMWARE_UNLOAD);
2117 if (rdev->rlc_fw != NULL) {
2118 firmware_put(rdev->rlc_fw, FIRMWARE_UNLOAD);
2119 rdev->rlc_fw = NULL;
2126 * r600_fini_microcode - drop the firmwares image references
2128 * @rdev: radeon_device pointer
2130 * Drop the pfp, me and rlc firmwares image references.
2131 * Called at driver shutdown.
2133 void r600_fini_microcode(struct radeon_device *rdev)
2136 if (rdev->pfp_fw != NULL) {
2137 firmware_put(rdev->pfp_fw, FIRMWARE_UNLOAD);
2138 rdev->pfp_fw = NULL;
2141 if (rdev->me_fw != NULL) {
2142 firmware_put(rdev->me_fw, FIRMWARE_UNLOAD);
2146 if (rdev->rlc_fw != NULL) {
2147 firmware_put(rdev->rlc_fw, FIRMWARE_UNLOAD);
2148 rdev->rlc_fw = NULL;
2152 static int r600_cp_load_microcode(struct radeon_device *rdev)
2154 const __be32 *fw_data;
2157 if (!rdev->me_fw || !rdev->pfp_fw)
2166 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2169 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2170 RREG32(GRBM_SOFT_RESET);
2172 WREG32(GRBM_SOFT_RESET, 0);
2174 WREG32(CP_ME_RAM_WADDR, 0);
2176 fw_data = (const __be32 *)rdev->me_fw->data;
2177 WREG32(CP_ME_RAM_WADDR, 0);
2178 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2179 WREG32(CP_ME_RAM_DATA,
2180 be32_to_cpup(fw_data++));
2182 fw_data = (const __be32 *)rdev->pfp_fw->data;
2183 WREG32(CP_PFP_UCODE_ADDR, 0);
2184 for (i = 0; i < PFP_UCODE_SIZE; i++)
2185 WREG32(CP_PFP_UCODE_DATA,
2186 be32_to_cpup(fw_data++));
2188 WREG32(CP_PFP_UCODE_ADDR, 0);
2189 WREG32(CP_ME_RAM_WADDR, 0);
2190 WREG32(CP_ME_RAM_RADDR, 0);
2194 int r600_cp_start(struct radeon_device *rdev)
2196 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2200 r = radeon_ring_lock(rdev, ring, 7);
2202 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2205 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2206 radeon_ring_write(ring, 0x1);
2207 if (rdev->family >= CHIP_RV770) {
2208 radeon_ring_write(ring, 0x0);
2209 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
2211 radeon_ring_write(ring, 0x3);
2212 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
2214 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2215 radeon_ring_write(ring, 0);
2216 radeon_ring_write(ring, 0);
2217 radeon_ring_unlock_commit(rdev, ring);
2220 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2224 int r600_cp_resume(struct radeon_device *rdev)
2226 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2232 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2233 RREG32(GRBM_SOFT_RESET);
2235 WREG32(GRBM_SOFT_RESET, 0);
2237 /* Set ring buffer size */
2238 rb_bufsz = drm_order(ring->ring_size / 8);
2239 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2241 tmp |= BUF_SWAP_32BIT;
2243 WREG32(CP_RB_CNTL, tmp);
2244 WREG32(CP_SEM_WAIT_TIMER, 0x0);
2246 /* Set the write pointer delay */
2247 WREG32(CP_RB_WPTR_DELAY, 0);
2249 /* Initialize the ring buffer's read and write pointers */
2250 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2251 WREG32(CP_RB_RPTR_WR, 0);
2253 WREG32(CP_RB_WPTR, ring->wptr);
2255 /* set the wb address whether it's enabled or not */
2256 WREG32(CP_RB_RPTR_ADDR,
2257 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
2258 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2259 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2261 if (rdev->wb.enabled)
2262 WREG32(SCRATCH_UMSK, 0xff);
2264 tmp |= RB_NO_UPDATE;
2265 WREG32(SCRATCH_UMSK, 0);
2269 WREG32(CP_RB_CNTL, tmp);
2271 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
2272 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2274 ring->rptr = RREG32(CP_RB_RPTR);
2276 r600_cp_start(rdev);
2278 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
2280 ring->ready = false;
2286 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size)
2291 /* Align ring size */
2292 rb_bufsz = drm_order(ring_size / 8);
2293 ring_size = (1 << (rb_bufsz + 1)) * 4;
2294 ring->ring_size = ring_size;
2295 ring->align_mask = 16 - 1;
2297 if (radeon_ring_supports_scratch_reg(rdev, ring)) {
2298 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
2300 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
2301 ring->rptr_save_reg = 0;
2306 void r600_cp_fini(struct radeon_device *rdev)
2308 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2310 radeon_ring_fini(rdev, ring);
2311 radeon_scratch_free(rdev, ring->rptr_save_reg);
2316 * Starting with R600, the GPU has an asynchronous
2317 * DMA engine. The programming model is very similar
2318 * to the 3D engine (ring buffer, IBs, etc.), but the
2319 * DMA controller has it's own packet format that is
2320 * different form the PM4 format used by the 3D engine.
2321 * It supports copying data, writing embedded data,
2322 * solid fills, and a number of other things. It also
2323 * has support for tiling/detiling of buffers.
2326 * r600_dma_stop - stop the async dma engine
2328 * @rdev: radeon_device pointer
2330 * Stop the async dma engine (r6xx-evergreen).
2332 void r600_dma_stop(struct radeon_device *rdev)
2334 u32 rb_cntl = RREG32(DMA_RB_CNTL);
2336 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
2338 rb_cntl &= ~DMA_RB_ENABLE;
2339 WREG32(DMA_RB_CNTL, rb_cntl);
2341 rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
2345 * r600_dma_resume - setup and start the async dma engine
2347 * @rdev: radeon_device pointer
2349 * Set up the DMA ring buffer and enable it. (r6xx-evergreen).
2350 * Returns 0 for success, error for failure.
2352 int r600_dma_resume(struct radeon_device *rdev)
2354 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2355 u32 rb_cntl, dma_cntl, ib_cntl;
2360 if (rdev->family >= CHIP_RV770)
2361 WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA);
2363 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
2364 RREG32(SRBM_SOFT_RESET);
2366 WREG32(SRBM_SOFT_RESET, 0);
2368 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0);
2369 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0);
2371 /* Set ring buffer size in dwords */
2372 rb_bufsz = drm_order(ring->ring_size / 4);
2373 rb_cntl = rb_bufsz << 1;
2375 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE;
2377 WREG32(DMA_RB_CNTL, rb_cntl);
2379 /* Initialize the ring buffer's read and write pointers */
2380 WREG32(DMA_RB_RPTR, 0);
2381 WREG32(DMA_RB_WPTR, 0);
2383 /* set the wb address whether it's enabled or not */
2384 WREG32(DMA_RB_RPTR_ADDR_HI,
2385 upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF);
2386 WREG32(DMA_RB_RPTR_ADDR_LO,
2387 ((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC));
2389 if (rdev->wb.enabled)
2390 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE;
2392 WREG32(DMA_RB_BASE, ring->gpu_addr >> 8);
2394 /* enable DMA IBs */
2395 ib_cntl = DMA_IB_ENABLE;
2397 ib_cntl |= DMA_IB_SWAP_ENABLE;
2399 WREG32(DMA_IB_CNTL, ib_cntl);
2401 dma_cntl = RREG32(DMA_CNTL);
2402 dma_cntl &= ~CTXEMPTY_INT_ENABLE;
2403 WREG32(DMA_CNTL, dma_cntl);
2405 if (rdev->family >= CHIP_RV770)
2406 WREG32(DMA_MODE, 1);
2409 WREG32(DMA_RB_WPTR, ring->wptr << 2);
2411 ring->rptr = RREG32(DMA_RB_RPTR) >> 2;
2413 WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE);
2417 r = radeon_ring_test(rdev, R600_RING_TYPE_DMA_INDEX, ring);
2419 ring->ready = false;
2423 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
2429 * r600_dma_fini - tear down the async dma engine
2431 * @rdev: radeon_device pointer
2433 * Stop the async dma engine and free the ring (r6xx-evergreen).
2435 void r600_dma_fini(struct radeon_device *rdev)
2437 r600_dma_stop(rdev);
2438 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
2442 * GPU scratch registers helpers function.
2444 void r600_scratch_init(struct radeon_device *rdev)
2448 rdev->scratch.num_reg = 7;
2449 rdev->scratch.reg_base = SCRATCH_REG0;
2450 for (i = 0; i < rdev->scratch.num_reg; i++) {
2451 rdev->scratch.free[i] = true;
2452 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
2456 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
2463 r = radeon_scratch_get(rdev, &scratch);
2465 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2468 WREG32(scratch, 0xCAFEDEAD);
2469 r = radeon_ring_lock(rdev, ring, 3);
2471 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r);
2472 radeon_scratch_free(rdev, scratch);
2475 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2476 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2477 radeon_ring_write(ring, 0xDEADBEEF);
2478 radeon_ring_unlock_commit(rdev, ring);
2479 for (i = 0; i < rdev->usec_timeout; i++) {
2480 tmp = RREG32(scratch);
2481 if (tmp == 0xDEADBEEF)
2485 if (i < rdev->usec_timeout) {
2486 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2488 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2489 ring->idx, scratch, tmp);
2492 radeon_scratch_free(rdev, scratch);
2497 * r600_dma_ring_test - simple async dma engine test
2499 * @rdev: radeon_device pointer
2500 * @ring: radeon_ring structure holding ring information
2502 * Test the DMA engine by writing using it to write an
2503 * value to memory. (r6xx-SI).
2504 * Returns 0 for success, error for failure.
2506 int r600_dma_ring_test(struct radeon_device *rdev,
2507 struct radeon_ring *ring)
2511 volatile uint32_t *ptr = rdev->vram_scratch.ptr;
2515 DRM_ERROR("invalid vram scratch pointer\n");
2522 r = radeon_ring_lock(rdev, ring, 4);
2524 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r);
2527 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
2528 radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc);
2529 radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff);
2530 radeon_ring_write(ring, 0xDEADBEEF);
2531 radeon_ring_unlock_commit(rdev, ring);
2533 for (i = 0; i < rdev->usec_timeout; i++) {
2535 if (tmp == 0xDEADBEEF)
2540 if (i < rdev->usec_timeout) {
2541 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2543 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
2551 * CP fences/semaphores
2554 void r600_fence_ring_emit(struct radeon_device *rdev,
2555 struct radeon_fence *fence)
2557 struct radeon_ring *ring = &rdev->ring[fence->ring];
2559 if (rdev->wb.use_event) {
2560 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2561 /* flush read cache over gart */
2562 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2563 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2564 PACKET3_VC_ACTION_ENA |
2565 PACKET3_SH_ACTION_ENA);
2566 radeon_ring_write(ring, 0xFFFFFFFF);
2567 radeon_ring_write(ring, 0);
2568 radeon_ring_write(ring, 10); /* poll interval */
2569 /* EVENT_WRITE_EOP - flush caches, send int */
2570 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2571 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2572 radeon_ring_write(ring, addr & 0xffffffff);
2573 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2574 radeon_ring_write(ring, fence->seq);
2575 radeon_ring_write(ring, 0);
2577 /* flush read cache over gart */
2578 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2579 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2580 PACKET3_VC_ACTION_ENA |
2581 PACKET3_SH_ACTION_ENA);
2582 radeon_ring_write(ring, 0xFFFFFFFF);
2583 radeon_ring_write(ring, 0);
2584 radeon_ring_write(ring, 10); /* poll interval */
2585 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2586 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
2587 /* wait for 3D idle clean */
2588 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2589 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2590 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2591 /* Emit fence sequence & fire IRQ */
2592 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2593 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2594 radeon_ring_write(ring, fence->seq);
2595 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2596 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0));
2597 radeon_ring_write(ring, RB_INT_STAT);
2601 void r600_semaphore_ring_emit(struct radeon_device *rdev,
2602 struct radeon_ring *ring,
2603 struct radeon_semaphore *semaphore,
2606 uint64_t addr = semaphore->gpu_addr;
2607 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
2609 if (rdev->family < CHIP_CAYMAN)
2610 sel |= PACKET3_SEM_WAIT_ON_SIGNAL;
2612 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
2613 radeon_ring_write(ring, addr & 0xffffffff);
2614 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
2618 * DMA fences/semaphores
2622 * r600_dma_fence_ring_emit - emit a fence on the DMA ring
2624 * @rdev: radeon_device pointer
2625 * @fence: radeon fence object
2627 * Add a DMA fence packet to the ring to write
2628 * the fence seq number and DMA trap packet to generate
2629 * an interrupt if needed (r6xx-r7xx).
2631 void r600_dma_fence_ring_emit(struct radeon_device *rdev,
2632 struct radeon_fence *fence)
2634 struct radeon_ring *ring = &rdev->ring[fence->ring];
2635 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2637 /* write the fence */
2638 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0));
2639 radeon_ring_write(ring, addr & 0xfffffffc);
2640 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
2641 radeon_ring_write(ring, lower_32_bits(fence->seq));
2642 /* generate an interrupt */
2643 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0));
2647 * r600_dma_semaphore_ring_emit - emit a semaphore on the dma ring
2649 * @rdev: radeon_device pointer
2650 * @ring: radeon_ring structure holding ring information
2651 * @semaphore: radeon semaphore object
2652 * @emit_wait: wait or signal semaphore
2654 * Add a DMA semaphore packet to the ring wait on or signal
2655 * other rings (r6xx-SI).
2657 void r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
2658 struct radeon_ring *ring,
2659 struct radeon_semaphore *semaphore,
2662 u64 addr = semaphore->gpu_addr;
2663 u32 s = emit_wait ? 0 : 1;
2665 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SEMAPHORE, 0, s, 0));
2666 radeon_ring_write(ring, addr & 0xfffffffc);
2667 radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
2670 int r600_copy_blit(struct radeon_device *rdev,
2671 uint64_t src_offset,
2672 uint64_t dst_offset,
2673 unsigned num_gpu_pages,
2674 struct radeon_fence **fence)
2676 struct radeon_semaphore *sem = NULL;
2677 struct radeon_sa_bo *vb = NULL;
2680 r = r600_blit_prepare_copy(rdev, num_gpu_pages, fence, &vb, &sem);
2684 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages, vb);
2685 r600_blit_done_copy(rdev, fence, vb, sem);
2690 * r600_copy_dma - copy pages using the DMA engine
2692 * @rdev: radeon_device pointer
2693 * @src_offset: src GPU address
2694 * @dst_offset: dst GPU address
2695 * @num_gpu_pages: number of GPU pages to xfer
2696 * @fence: radeon fence object
2698 * Copy GPU paging using the DMA engine (r6xx).
2699 * Used by the radeon ttm implementation to move pages if
2700 * registered as the asic copy callback.
2702 int r600_copy_dma(struct radeon_device *rdev,
2703 uint64_t src_offset, uint64_t dst_offset,
2704 unsigned num_gpu_pages,
2705 struct radeon_fence **fence)
2707 struct radeon_semaphore *sem = NULL;
2708 int ring_index = rdev->asic->copy.dma_ring_index;
2709 struct radeon_ring *ring = &rdev->ring[ring_index];
2710 u32 size_in_dw, cur_size_in_dw;
2714 r = radeon_semaphore_create(rdev, &sem);
2716 DRM_ERROR("radeon: moving bo (%d).\n", r);
2720 size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
2721 num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFE);
2722 r = radeon_ring_lock(rdev, ring, num_loops * 4 + 8);
2724 DRM_ERROR("radeon: moving bo (%d).\n", r);
2725 radeon_semaphore_free(rdev, &sem, NULL);
2729 if (radeon_fence_need_sync(*fence, ring->idx)) {
2730 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
2732 radeon_fence_note_sync(*fence, ring->idx);
2734 radeon_semaphore_free(rdev, &sem, NULL);
2737 for (i = 0; i < num_loops; i++) {
2738 cur_size_in_dw = size_in_dw;
2739 if (cur_size_in_dw > 0xFFFE)
2740 cur_size_in_dw = 0xFFFE;
2741 size_in_dw -= cur_size_in_dw;
2742 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
2743 radeon_ring_write(ring, dst_offset & 0xfffffffc);
2744 radeon_ring_write(ring, src_offset & 0xfffffffc);
2745 radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) |
2746 (upper_32_bits(src_offset) & 0xff)));
2747 src_offset += cur_size_in_dw * 4;
2748 dst_offset += cur_size_in_dw * 4;
2751 r = radeon_fence_emit(rdev, fence, ring->idx);
2753 radeon_ring_unlock_undo(rdev, ring);
2757 radeon_ring_unlock_commit(rdev, ring);
2758 radeon_semaphore_free(rdev, &sem, *fence);
2763 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2764 uint32_t tiling_flags, uint32_t pitch,
2765 uint32_t offset, uint32_t obj_size)
2767 /* FIXME: implement */
2771 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2773 /* FIXME: implement */
2776 static int r600_startup(struct radeon_device *rdev)
2778 struct radeon_ring *ring;
2781 /* enable pcie gen2 link */
2782 r600_pcie_gen2_enable(rdev);
2784 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2785 r = r600_init_microcode(rdev);
2787 DRM_ERROR("Failed to load firmware!\n");
2792 r = r600_vram_scratch_init(rdev);
2796 r600_mc_program(rdev);
2797 if (rdev->flags & RADEON_IS_AGP) {
2798 r600_agp_enable(rdev);
2800 r = r600_pcie_gart_enable(rdev);
2804 r600_gpu_init(rdev);
2805 r = r600_blit_init(rdev);
2807 r600_blit_fini(rdev);
2808 rdev->asic->copy.copy = NULL;
2809 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2812 /* allocate wb buffer */
2813 r = radeon_wb_init(rdev);
2817 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
2819 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2823 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
2825 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
2830 r = r600_irq_init(rdev);
2832 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2833 radeon_irq_kms_fini(rdev);
2838 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2839 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
2840 R600_CP_RB_RPTR, R600_CP_RB_WPTR,
2841 0, 0xfffff, RADEON_CP_PACKET2);
2845 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2846 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
2847 DMA_RB_RPTR, DMA_RB_WPTR,
2848 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
2852 r = r600_cp_load_microcode(rdev);
2855 r = r600_cp_resume(rdev);
2859 r = r600_dma_resume(rdev);
2863 r = radeon_ib_pool_init(rdev);
2865 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2869 r = r600_audio_init(rdev);
2871 DRM_ERROR("radeon: audio init failed\n");
2878 void r600_vga_set_state(struct radeon_device *rdev, bool state)
2882 temp = RREG32(CONFIG_CNTL);
2883 if (state == false) {
2889 WREG32(CONFIG_CNTL, temp);
2892 int r600_resume(struct radeon_device *rdev)
2896 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2897 * posting will perform necessary task to bring back GPU into good
2901 atom_asic_init(rdev->mode_info.atom_context);
2903 rdev->accel_working = true;
2904 r = r600_startup(rdev);
2906 DRM_ERROR("r600 startup failed on resume\n");
2907 rdev->accel_working = false;
2914 int r600_suspend(struct radeon_device *rdev)
2916 r600_audio_fini(rdev);
2918 r600_dma_stop(rdev);
2919 r600_irq_suspend(rdev);
2920 radeon_wb_disable(rdev);
2921 r600_pcie_gart_disable(rdev);
2926 /* Plan is to move initialization in that function and use
2927 * helper function so that radeon_device_init pretty much
2928 * do nothing more than calling asic specific function. This
2929 * should also allow to remove a bunch of callback function
2932 int r600_init(struct radeon_device *rdev)
2936 if (r600_debugfs_mc_info_init(rdev)) {
2937 DRM_ERROR("Failed to register debugfs file for mc !\n");
2940 if (!radeon_get_bios(rdev)) {
2941 if (ASIC_IS_AVIVO(rdev))
2944 /* Must be an ATOMBIOS */
2945 if (!rdev->is_atom_bios) {
2946 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2949 r = radeon_atombios_init(rdev);
2952 /* Post card if necessary */
2953 if (!radeon_card_posted(rdev)) {
2955 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2958 DRM_INFO("GPU not posted. posting now...\n");
2959 atom_asic_init(rdev->mode_info.atom_context);
2961 /* Initialize scratch registers */
2962 r600_scratch_init(rdev);
2963 /* Initialize surface registers */
2964 radeon_surface_init(rdev);
2965 /* Initialize clocks */
2966 radeon_get_clock_info(rdev->ddev);
2968 r = radeon_fence_driver_init(rdev);
2971 if (rdev->flags & RADEON_IS_AGP) {
2972 r = radeon_agp_init(rdev);
2974 radeon_agp_disable(rdev);
2976 r = r600_mc_init(rdev);
2979 /* Memory manager */
2980 r = radeon_bo_init(rdev);
2984 r = radeon_irq_kms_init(rdev);
2988 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
2989 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
2991 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
2992 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
2994 rdev->ih.ring_obj = NULL;
2995 r600_ih_ring_init(rdev, 64 * 1024);
2997 r = r600_pcie_gart_init(rdev);
3001 rdev->accel_working = true;
3002 r = r600_startup(rdev);
3004 dev_err(rdev->dev, "disabling GPU acceleration\n");
3006 r600_dma_fini(rdev);
3007 r600_irq_fini(rdev);
3008 radeon_wb_fini(rdev);
3009 radeon_ib_pool_fini(rdev);
3010 radeon_irq_kms_fini(rdev);
3011 r600_pcie_gart_fini(rdev);
3012 rdev->accel_working = false;
3018 void r600_fini(struct radeon_device *rdev)
3020 r600_audio_fini(rdev);
3021 r600_blit_fini(rdev);
3023 r600_dma_fini(rdev);
3024 r600_irq_fini(rdev);
3025 radeon_wb_fini(rdev);
3026 radeon_ib_pool_fini(rdev);
3027 radeon_irq_kms_fini(rdev);
3028 r600_pcie_gart_fini(rdev);
3029 r600_vram_scratch_fini(rdev);
3030 radeon_agp_fini(rdev);
3031 radeon_gem_fini(rdev);
3032 radeon_fence_driver_fini(rdev);
3033 radeon_bo_fini(rdev);
3034 radeon_atombios_fini(rdev);
3035 r600_fini_microcode(rdev);
3036 free(rdev->bios, DRM_MEM_DRIVER);
3044 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3046 struct radeon_ring *ring = &rdev->ring[ib->ring];
3049 if (ring->rptr_save_reg) {
3050 next_rptr = ring->wptr + 3 + 4;
3051 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3052 radeon_ring_write(ring, ((ring->rptr_save_reg -
3053 PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
3054 radeon_ring_write(ring, next_rptr);
3055 } else if (rdev->wb.enabled) {
3056 next_rptr = ring->wptr + 5 + 4;
3057 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
3058 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3059 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
3060 radeon_ring_write(ring, next_rptr);
3061 radeon_ring_write(ring, 0);
3064 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3065 radeon_ring_write(ring,
3069 (ib->gpu_addr & 0xFFFFFFFC));
3070 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
3071 radeon_ring_write(ring, ib->length_dw);
3074 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3076 struct radeon_ib ib;
3082 r = radeon_scratch_get(rdev, &scratch);
3084 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3087 WREG32(scratch, 0xCAFEDEAD);
3088 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3090 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3093 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
3094 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
3095 ib.ptr[2] = 0xDEADBEEF;
3097 r = radeon_ib_schedule(rdev, &ib, NULL);
3099 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3102 r = radeon_fence_wait(ib.fence, false);
3104 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3107 for (i = 0; i < rdev->usec_timeout; i++) {
3108 tmp = RREG32(scratch);
3109 if (tmp == 0xDEADBEEF)
3113 if (i < rdev->usec_timeout) {
3114 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3116 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3121 radeon_ib_free(rdev, &ib);
3123 radeon_scratch_free(rdev, scratch);
3128 * r600_dma_ib_test - test an IB on the DMA engine
3130 * @rdev: radeon_device pointer
3131 * @ring: radeon_ring structure holding ring information
3133 * Test a simple IB in the DMA ring (r6xx-SI).
3134 * Returns 0 on success, error on failure.
3136 int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3138 struct radeon_ib ib;
3141 volatile uint32_t *ptr = rdev->vram_scratch.ptr;
3145 DRM_ERROR("invalid vram scratch pointer\n");
3152 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3154 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3158 ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1);
3159 ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc;
3160 ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff;
3161 ib.ptr[3] = 0xDEADBEEF;
3164 r = radeon_ib_schedule(rdev, &ib, NULL);
3166 radeon_ib_free(rdev, &ib);
3167 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3170 r = radeon_fence_wait(ib.fence, false);
3172 radeon_ib_free(rdev, &ib);
3173 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3176 for (i = 0; i < rdev->usec_timeout; i++) {
3178 if (tmp == 0xDEADBEEF)
3182 if (i < rdev->usec_timeout) {
3183 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3185 DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp);
3188 radeon_ib_free(rdev, &ib);
3193 * r600_dma_ring_ib_execute - Schedule an IB on the DMA engine
3195 * @rdev: radeon_device pointer
3196 * @ib: IB object to schedule
3198 * Schedule an IB in the DMA ring (r6xx-r7xx).
3200 void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3202 struct radeon_ring *ring = &rdev->ring[ib->ring];
3204 if (rdev->wb.enabled) {
3205 u32 next_rptr = ring->wptr + 4;
3206 while ((next_rptr & 7) != 5)
3209 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
3210 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3211 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
3212 radeon_ring_write(ring, next_rptr);
3215 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
3216 * Pad as necessary with NOPs.
3218 while ((ring->wptr & 7) != 5)
3219 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
3220 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0));
3221 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
3222 radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF));
3229 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
3230 * the same as the CP ring buffer, but in reverse. Rather than the CPU
3231 * writing to the ring and the GPU consuming, the GPU writes to the ring
3232 * and host consumes. As the host irq handler processes interrupts, it
3233 * increments the rptr. When the rptr catches up with the wptr, all the
3234 * current interrupts have been processed.
3237 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
3241 /* Align ring size */
3242 rb_bufsz = drm_order(ring_size / 4);
3243 ring_size = (1 << rb_bufsz) * 4;
3244 rdev->ih.ring_size = ring_size;
3245 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
3249 int r600_ih_ring_alloc(struct radeon_device *rdev)
3254 /* Allocate ring buffer */
3255 if (rdev->ih.ring_obj == NULL) {
3256 r = radeon_bo_create(rdev, rdev->ih.ring_size,
3258 RADEON_GEM_DOMAIN_GTT,
3259 NULL, &rdev->ih.ring_obj);
3261 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
3264 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3265 if (unlikely(r != 0)) {
3266 radeon_bo_unref(&rdev->ih.ring_obj);
3269 r = radeon_bo_pin(rdev->ih.ring_obj,
3270 RADEON_GEM_DOMAIN_GTT,
3271 &rdev->ih.gpu_addr);
3273 radeon_bo_unreserve(rdev->ih.ring_obj);
3274 radeon_bo_unref(&rdev->ih.ring_obj);
3275 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
3278 ring_ptr = &rdev->ih.ring;
3279 r = radeon_bo_kmap(rdev->ih.ring_obj,
3282 radeon_bo_unpin(rdev->ih.ring_obj);
3283 radeon_bo_unreserve(rdev->ih.ring_obj);
3285 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
3286 radeon_bo_unref(&rdev->ih.ring_obj);
3293 void r600_ih_ring_fini(struct radeon_device *rdev)
3296 if (rdev->ih.ring_obj) {
3297 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3298 if (likely(r == 0)) {
3299 radeon_bo_kunmap(rdev->ih.ring_obj);
3300 radeon_bo_unpin(rdev->ih.ring_obj);
3301 radeon_bo_unreserve(rdev->ih.ring_obj);
3303 radeon_bo_unref(&rdev->ih.ring_obj);
3304 rdev->ih.ring = NULL;
3305 rdev->ih.ring_obj = NULL;
3309 void r600_rlc_stop(struct radeon_device *rdev)
3312 if ((rdev->family >= CHIP_RV770) &&
3313 (rdev->family <= CHIP_RV740)) {
3314 /* r7xx asics need to soft reset RLC before halting */
3315 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
3316 RREG32(SRBM_SOFT_RESET);
3318 WREG32(SRBM_SOFT_RESET, 0);
3319 RREG32(SRBM_SOFT_RESET);
3322 WREG32(RLC_CNTL, 0);
3325 static void r600_rlc_start(struct radeon_device *rdev)
3327 WREG32(RLC_CNTL, RLC_ENABLE);
3330 static int r600_rlc_init(struct radeon_device *rdev)
3333 const __be32 *fw_data;
3338 r600_rlc_stop(rdev);
3340 WREG32(RLC_HB_CNTL, 0);
3342 if (rdev->family == CHIP_ARUBA) {
3343 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
3344 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
3346 if (rdev->family <= CHIP_CAYMAN) {
3347 WREG32(RLC_HB_BASE, 0);
3348 WREG32(RLC_HB_RPTR, 0);
3349 WREG32(RLC_HB_WPTR, 0);
3351 if (rdev->family <= CHIP_CAICOS) {
3352 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
3353 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
3355 WREG32(RLC_MC_CNTL, 0);
3356 WREG32(RLC_UCODE_CNTL, 0);
3358 fw_data = (const __be32 *)rdev->rlc_fw->data;
3359 if (rdev->family >= CHIP_ARUBA) {
3360 for (i = 0; i < ARUBA_RLC_UCODE_SIZE; i++) {
3361 WREG32(RLC_UCODE_ADDR, i);
3362 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3364 } else if (rdev->family >= CHIP_CAYMAN) {
3365 for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) {
3366 WREG32(RLC_UCODE_ADDR, i);
3367 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3369 } else if (rdev->family >= CHIP_CEDAR) {
3370 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
3371 WREG32(RLC_UCODE_ADDR, i);
3372 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3374 } else if (rdev->family >= CHIP_RV770) {
3375 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
3376 WREG32(RLC_UCODE_ADDR, i);
3377 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3380 for (i = 0; i < RLC_UCODE_SIZE; i++) {
3381 WREG32(RLC_UCODE_ADDR, i);
3382 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3385 WREG32(RLC_UCODE_ADDR, 0);
3387 r600_rlc_start(rdev);
3392 static void r600_enable_interrupts(struct radeon_device *rdev)
3394 u32 ih_cntl = RREG32(IH_CNTL);
3395 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3397 ih_cntl |= ENABLE_INTR;
3398 ih_rb_cntl |= IH_RB_ENABLE;
3399 WREG32(IH_CNTL, ih_cntl);
3400 WREG32(IH_RB_CNTL, ih_rb_cntl);
3401 rdev->ih.enabled = true;
3404 void r600_disable_interrupts(struct radeon_device *rdev)
3406 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3407 u32 ih_cntl = RREG32(IH_CNTL);
3409 ih_rb_cntl &= ~IH_RB_ENABLE;
3410 ih_cntl &= ~ENABLE_INTR;
3411 WREG32(IH_RB_CNTL, ih_rb_cntl);
3412 WREG32(IH_CNTL, ih_cntl);
3413 /* set rptr, wptr to 0 */
3414 WREG32(IH_RB_RPTR, 0);
3415 WREG32(IH_RB_WPTR, 0);
3416 rdev->ih.enabled = false;
3420 static void r600_disable_interrupt_state(struct radeon_device *rdev)
3424 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
3425 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3426 WREG32(DMA_CNTL, tmp);
3427 WREG32(GRBM_INT_CNTL, 0);
3428 WREG32(DxMODE_INT_MASK, 0);
3429 WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
3430 WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
3431 if (ASIC_IS_DCE3(rdev)) {
3432 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
3433 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
3434 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3435 WREG32(DC_HPD1_INT_CONTROL, tmp);
3436 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3437 WREG32(DC_HPD2_INT_CONTROL, tmp);
3438 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3439 WREG32(DC_HPD3_INT_CONTROL, tmp);
3440 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3441 WREG32(DC_HPD4_INT_CONTROL, tmp);
3442 if (ASIC_IS_DCE32(rdev)) {
3443 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3444 WREG32(DC_HPD5_INT_CONTROL, tmp);
3445 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3446 WREG32(DC_HPD6_INT_CONTROL, tmp);
3447 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3448 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3449 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3450 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
3452 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3453 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3454 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3455 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3458 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
3459 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
3460 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3461 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3462 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3463 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3464 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3465 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3466 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3467 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3468 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3469 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3473 int r600_irq_init(struct radeon_device *rdev)
3477 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
3480 ret = r600_ih_ring_alloc(rdev);
3485 r600_disable_interrupts(rdev);
3488 ret = r600_rlc_init(rdev);
3490 r600_ih_ring_fini(rdev);
3494 /* setup interrupt control */
3495 /* set dummy read address to ring address */
3496 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
3497 interrupt_cntl = RREG32(INTERRUPT_CNTL);
3498 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3499 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3501 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3502 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3503 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3504 WREG32(INTERRUPT_CNTL, interrupt_cntl);
3506 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3507 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
3509 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3510 IH_WPTR_OVERFLOW_CLEAR |
3513 if (rdev->wb.enabled)
3514 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3516 /* set the writeback address whether it's enabled or not */
3517 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3518 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
3520 WREG32(IH_RB_CNTL, ih_rb_cntl);
3522 /* set rptr, wptr to 0 */
3523 WREG32(IH_RB_RPTR, 0);
3524 WREG32(IH_RB_WPTR, 0);
3526 /* Default settings for IH_CNTL (disabled at first) */
3527 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
3528 /* RPTR_REARM only works if msi's are enabled */
3529 if (rdev->msi_enabled)
3530 ih_cntl |= RPTR_REARM;
3531 WREG32(IH_CNTL, ih_cntl);
3533 /* force the active interrupt state to all disabled */
3534 if (rdev->family >= CHIP_CEDAR)
3535 evergreen_disable_interrupt_state(rdev);
3537 r600_disable_interrupt_state(rdev);
3539 /* at this point everything should be setup correctly to enable master */
3540 pci_enable_busmaster(rdev->dev);
3543 r600_enable_interrupts(rdev);
3548 void r600_irq_suspend(struct radeon_device *rdev)
3550 r600_irq_disable(rdev);
3551 r600_rlc_stop(rdev);
3554 void r600_irq_fini(struct radeon_device *rdev)
3556 r600_irq_suspend(rdev);
3557 r600_ih_ring_fini(rdev);
3560 int r600_irq_set(struct radeon_device *rdev)
3562 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3564 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
3565 u32 grbm_int_cntl = 0;
3567 u32 d1grph = 0, d2grph = 0;
3570 if (!rdev->irq.installed) {
3571 DRM_ERROR("Can't enable IRQ/MSI because no handler is installed\n");
3574 /* don't enable anything if the ih is disabled */
3575 if (!rdev->ih.enabled) {
3576 r600_disable_interrupts(rdev);
3577 /* force the active interrupt state to all disabled */
3578 r600_disable_interrupt_state(rdev);
3582 if (ASIC_IS_DCE3(rdev)) {
3583 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3584 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3585 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3586 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3587 if (ASIC_IS_DCE32(rdev)) {
3588 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3589 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3590 hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3591 hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3593 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3594 hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3597 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3598 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3599 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3600 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3601 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3603 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3605 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
3606 DRM_DEBUG("r600_irq_set: sw int\n");
3607 cp_int_cntl |= RB_INT_ENABLE;
3608 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3611 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
3612 DRM_DEBUG("r600_irq_set: sw int dma\n");
3613 dma_cntl |= TRAP_ENABLE;
3616 if (rdev->irq.crtc_vblank_int[0] ||
3617 atomic_read(&rdev->irq.pflip[0])) {
3618 DRM_DEBUG("r600_irq_set: vblank 0\n");
3619 mode_int |= D1MODE_VBLANK_INT_MASK;
3621 if (rdev->irq.crtc_vblank_int[1] ||
3622 atomic_read(&rdev->irq.pflip[1])) {
3623 DRM_DEBUG("r600_irq_set: vblank 1\n");
3624 mode_int |= D2MODE_VBLANK_INT_MASK;
3626 if (rdev->irq.hpd[0]) {
3627 DRM_DEBUG("r600_irq_set: hpd 1\n");
3628 hpd1 |= DC_HPDx_INT_EN;
3630 if (rdev->irq.hpd[1]) {
3631 DRM_DEBUG("r600_irq_set: hpd 2\n");
3632 hpd2 |= DC_HPDx_INT_EN;
3634 if (rdev->irq.hpd[2]) {
3635 DRM_DEBUG("r600_irq_set: hpd 3\n");
3636 hpd3 |= DC_HPDx_INT_EN;
3638 if (rdev->irq.hpd[3]) {
3639 DRM_DEBUG("r600_irq_set: hpd 4\n");
3640 hpd4 |= DC_HPDx_INT_EN;
3642 if (rdev->irq.hpd[4]) {
3643 DRM_DEBUG("r600_irq_set: hpd 5\n");
3644 hpd5 |= DC_HPDx_INT_EN;
3646 if (rdev->irq.hpd[5]) {
3647 DRM_DEBUG("r600_irq_set: hpd 6\n");
3648 hpd6 |= DC_HPDx_INT_EN;
3650 if (rdev->irq.afmt[0]) {
3651 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3652 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
3654 if (rdev->irq.afmt[1]) {
3655 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3656 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
3659 WREG32(CP_INT_CNTL, cp_int_cntl);
3660 WREG32(DMA_CNTL, dma_cntl);
3661 WREG32(DxMODE_INT_MASK, mode_int);
3662 WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
3663 WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
3664 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3665 if (ASIC_IS_DCE3(rdev)) {
3666 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3667 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3668 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3669 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3670 if (ASIC_IS_DCE32(rdev)) {
3671 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3672 WREG32(DC_HPD6_INT_CONTROL, hpd6);
3673 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0);
3674 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1);
3676 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3677 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3680 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3681 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3682 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3683 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3684 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3690 static void r600_irq_ack(struct radeon_device *rdev)
3694 if (ASIC_IS_DCE3(rdev)) {
3695 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3696 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3697 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3698 if (ASIC_IS_DCE32(rdev)) {
3699 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0);
3700 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1);
3702 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3703 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS);
3706 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3707 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3708 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
3709 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3710 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS);
3712 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3713 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3715 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3716 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3717 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3718 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3719 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
3720 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3721 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
3722 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3723 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
3724 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3725 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
3726 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3727 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3728 if (ASIC_IS_DCE3(rdev)) {
3729 tmp = RREG32(DC_HPD1_INT_CONTROL);
3730 tmp |= DC_HPDx_INT_ACK;
3731 WREG32(DC_HPD1_INT_CONTROL, tmp);
3733 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3734 tmp |= DC_HPDx_INT_ACK;
3735 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3738 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3739 if (ASIC_IS_DCE3(rdev)) {
3740 tmp = RREG32(DC_HPD2_INT_CONTROL);
3741 tmp |= DC_HPDx_INT_ACK;
3742 WREG32(DC_HPD2_INT_CONTROL, tmp);
3744 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3745 tmp |= DC_HPDx_INT_ACK;
3746 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3749 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3750 if (ASIC_IS_DCE3(rdev)) {
3751 tmp = RREG32(DC_HPD3_INT_CONTROL);
3752 tmp |= DC_HPDx_INT_ACK;
3753 WREG32(DC_HPD3_INT_CONTROL, tmp);
3755 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3756 tmp |= DC_HPDx_INT_ACK;
3757 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3760 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3761 tmp = RREG32(DC_HPD4_INT_CONTROL);
3762 tmp |= DC_HPDx_INT_ACK;
3763 WREG32(DC_HPD4_INT_CONTROL, tmp);
3765 if (ASIC_IS_DCE32(rdev)) {
3766 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3767 tmp = RREG32(DC_HPD5_INT_CONTROL);
3768 tmp |= DC_HPDx_INT_ACK;
3769 WREG32(DC_HPD5_INT_CONTROL, tmp);
3771 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3772 tmp = RREG32(DC_HPD5_INT_CONTROL);
3773 tmp |= DC_HPDx_INT_ACK;
3774 WREG32(DC_HPD6_INT_CONTROL, tmp);
3776 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) {
3777 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0);
3778 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3779 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3781 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) {
3782 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1);
3783 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3784 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
3787 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
3788 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL);
3789 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3790 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3792 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
3793 if (ASIC_IS_DCE3(rdev)) {
3794 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL);
3795 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3796 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3798 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL);
3799 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3800 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3806 void r600_irq_disable(struct radeon_device *rdev)
3808 r600_disable_interrupts(rdev);
3809 /* Wait and acknowledge irq */
3812 r600_disable_interrupt_state(rdev);
3815 static u32 r600_get_ih_wptr(struct radeon_device *rdev)
3819 if (rdev->wb.enabled)
3820 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
3822 wptr = RREG32(IH_RB_WPTR);
3824 if (wptr & RB_OVERFLOW) {
3825 /* When a ring buffer overflow happen start parsing interrupt
3826 * from the last not overwritten vector (wptr + 16). Hopefully
3827 * this should allow us to catchup.
3829 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3830 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3831 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3832 tmp = RREG32(IH_RB_CNTL);
3833 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3834 WREG32(IH_RB_CNTL, tmp);
3836 return (wptr & rdev->ih.ptr_mask);
3840 * Each IV ring entry is 128 bits:
3841 * [7:0] - interrupt source id
3843 * [59:32] - interrupt source data
3844 * [127:60] - reserved
3846 * The basic interrupt vector entries
3847 * are decoded as follows:
3848 * src_id src_data description
3853 * 19 0 FP Hot plug detection A
3854 * 19 1 FP Hot plug detection B
3855 * 19 2 DAC A auto-detection
3856 * 19 3 DAC B auto-detection
3862 * 181 - EOP Interrupt
3865 * Note, these are based on r600 and may need to be
3866 * adjusted or added to on newer asics
3869 irqreturn_t r600_irq_process(struct radeon_device *rdev)
3873 u32 src_id, src_data;
3875 bool queue_hotplug = false;
3876 bool queue_hdmi = false;
3878 if (!rdev->ih.enabled || rdev->shutdown)
3881 /* No MSIs, need a dummy read to flush PCI DMAs */
3882 if (!rdev->msi_enabled)
3885 wptr = r600_get_ih_wptr(rdev);
3888 /* is somebody else already processing irqs? */
3889 if (atomic_xchg(&rdev->ih.lock, 1))
3892 rptr = rdev->ih.rptr;
3893 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3895 /* Order reading of wptr vs. reading of IH ring data */
3898 /* display interrupts */
3901 while (rptr != wptr) {
3902 /* wptr/rptr are in bytes! */
3903 ring_index = rptr / 4;
3904 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3905 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
3908 case 1: /* D1 vblank/vline */
3910 case 0: /* D1 vblank */
3911 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) {
3912 if (rdev->irq.crtc_vblank_int[0]) {
3913 drm_handle_vblank(rdev->ddev, 0);
3914 rdev->pm.vblank_sync = true;
3915 DRM_WAKEUP(&rdev->irq.vblank_queue);
3917 if (atomic_read(&rdev->irq.pflip[0]))
3918 radeon_crtc_handle_flip(rdev, 0);
3919 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3920 DRM_DEBUG("IH: D1 vblank\n");
3923 case 1: /* D1 vline */
3924 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) {
3925 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
3926 DRM_DEBUG("IH: D1 vline\n");
3930 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3934 case 5: /* D2 vblank/vline */
3936 case 0: /* D2 vblank */
3937 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) {
3938 if (rdev->irq.crtc_vblank_int[1]) {
3939 drm_handle_vblank(rdev->ddev, 1);
3940 rdev->pm.vblank_sync = true;
3941 DRM_WAKEUP(&rdev->irq.vblank_queue);
3943 if (atomic_read(&rdev->irq.pflip[1]))
3944 radeon_crtc_handle_flip(rdev, 1);
3945 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
3946 DRM_DEBUG("IH: D2 vblank\n");
3949 case 1: /* D1 vline */
3950 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) {
3951 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
3952 DRM_DEBUG("IH: D2 vline\n");
3956 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3960 case 19: /* HPD/DAC hotplug */
3963 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3964 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
3965 queue_hotplug = true;
3966 DRM_DEBUG("IH: HPD1\n");
3970 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3971 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
3972 queue_hotplug = true;
3973 DRM_DEBUG("IH: HPD2\n");
3977 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3978 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
3979 queue_hotplug = true;
3980 DRM_DEBUG("IH: HPD3\n");
3984 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3985 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
3986 queue_hotplug = true;
3987 DRM_DEBUG("IH: HPD4\n");
3991 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3992 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
3993 queue_hotplug = true;
3994 DRM_DEBUG("IH: HPD5\n");
3998 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3999 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
4000 queue_hotplug = true;
4001 DRM_DEBUG("IH: HPD6\n");
4005 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4012 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
4013 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG;
4015 DRM_DEBUG("IH: HDMI0\n");
4019 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
4020 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG;
4022 DRM_DEBUG("IH: HDMI1\n");
4026 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
4030 case 176: /* CP_INT in ring buffer */
4031 case 177: /* CP_INT in IB1 */
4032 case 178: /* CP_INT in IB2 */
4033 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
4034 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4036 case 181: /* CP EOP event */
4037 DRM_DEBUG("IH: CP EOP\n");
4038 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4040 case 224: /* DMA trap event */
4041 DRM_DEBUG("IH: DMA trap\n");
4042 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
4044 case 233: /* GUI IDLE */
4045 DRM_DEBUG("IH: GUI idle\n");
4048 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4052 /* wptr/rptr are in bytes! */
4054 rptr &= rdev->ih.ptr_mask;
4057 taskqueue_enqueue(rdev->tq, &rdev->hotplug_work);
4059 taskqueue_enqueue(rdev->tq, &rdev->audio_work);
4060 rdev->ih.rptr = rptr;
4061 WREG32(IH_RB_RPTR, rdev->ih.rptr);
4062 atomic_set(&rdev->ih.lock, 0);
4064 /* make sure wptr hasn't changed while processing */
4065 wptr = r600_get_ih_wptr(rdev);
4075 #if defined(CONFIG_DEBUG_FS)
4077 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
4079 struct drm_info_node *node = (struct drm_info_node *) m->private;
4080 struct drm_device *dev = node->minor->dev;
4081 struct radeon_device *rdev = dev->dev_private;
4083 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
4084 DREG32_SYS(m, rdev, VM_L2_STATUS);
4088 static struct drm_info_list r600_mc_info_list[] = {
4089 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
4093 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
4095 #if defined(CONFIG_DEBUG_FS)
4096 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
4103 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
4104 * rdev: radeon device structure
4105 * bo: buffer object struct which userspace is waiting for idle
4107 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
4108 * through ring buffer, this leads to corruption in rendering, see
4109 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
4110 * directly perform HDP flush by writing register through MMIO.
4112 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
4114 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
4115 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
4116 * This seems to cause problems on some AGP cards. Just use the old
4119 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
4120 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
4121 volatile uint32_t *ptr = rdev->vram_scratch.ptr;
4124 WREG32(HDP_DEBUG1, 0);
4127 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
4130 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
4132 u32 link_width_cntl, mask, target_reg;
4134 if (rdev->flags & RADEON_IS_IGP)
4137 if (!(rdev->flags & RADEON_IS_PCIE))
4140 /* x2 cards have a special sequence */
4141 if (ASIC_IS_X2(rdev))
4144 /* FIXME wait for idle */
4148 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
4151 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
4154 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
4157 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
4160 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
4163 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
4167 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
4171 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4173 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
4174 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
4177 if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS)
4180 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
4181 RADEON_PCIE_LC_RECONFIG_NOW |
4182 R600_PCIE_LC_RENEGOTIATE_EN |
4183 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
4184 link_width_cntl |= mask;
4186 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4188 /* some northbridges can renegotiate the link rather than requiring
4189 * a complete re-config.
4190 * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.)
4192 if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT)
4193 link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT;
4195 link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE;
4197 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
4198 RADEON_PCIE_LC_RECONFIG_NOW));
4200 if (rdev->family >= CHIP_RV770)
4201 target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX;
4203 target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX;
4205 /* wait for lane set to complete */
4206 link_width_cntl = RREG32(target_reg);
4207 while (link_width_cntl == 0xffffffff)
4208 link_width_cntl = RREG32(target_reg);
4212 int r600_get_pcie_lanes(struct radeon_device *rdev)
4214 u32 link_width_cntl;
4216 if (rdev->flags & RADEON_IS_IGP)
4219 if (!(rdev->flags & RADEON_IS_PCIE))
4222 /* x2 cards have a special sequence */
4223 if (ASIC_IS_X2(rdev))
4226 /* FIXME wait for idle */
4228 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4230 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
4231 case RADEON_PCIE_LC_LINK_WIDTH_X0:
4233 case RADEON_PCIE_LC_LINK_WIDTH_X1:
4235 case RADEON_PCIE_LC_LINK_WIDTH_X2:
4237 case RADEON_PCIE_LC_LINK_WIDTH_X4:
4239 case RADEON_PCIE_LC_LINK_WIDTH_X8:
4241 case RADEON_PCIE_LC_LINK_WIDTH_X16:
4247 static void r600_pcie_gen2_enable(struct radeon_device *rdev)
4249 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
4254 if (radeon_pcie_gen2 == 0)
4257 if (rdev->flags & RADEON_IS_IGP)
4260 if (!(rdev->flags & RADEON_IS_PCIE))
4263 /* x2 cards have a special sequence */
4264 if (ASIC_IS_X2(rdev))
4267 /* only RV6xx+ chips are supported */
4268 if (rdev->family <= CHIP_R600)
4271 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
4275 if (!(mask & DRM_PCIE_SPEED_50))
4278 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
4279 if (speed_cntl & LC_CURRENT_DATA_RATE) {
4280 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
4284 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
4286 /* 55 nm r6xx asics */
4287 if ((rdev->family == CHIP_RV670) ||
4288 (rdev->family == CHIP_RV620) ||
4289 (rdev->family == CHIP_RV635)) {
4290 /* advertise upconfig capability */
4291 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
4292 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4293 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4294 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
4295 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
4296 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
4297 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
4298 LC_RECONFIG_ARC_MISSING_ESCAPE);
4299 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
4300 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4302 link_width_cntl |= LC_UPCONFIGURE_DIS;
4303 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4307 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
4308 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
4309 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
4311 /* 55 nm r6xx asics */
4312 if ((rdev->family == CHIP_RV670) ||
4313 (rdev->family == CHIP_RV620) ||
4314 (rdev->family == CHIP_RV635)) {
4315 WREG32(MM_CFGREGS_CNTL, 0x8);
4316 link_cntl2 = RREG32(0x4088);
4317 WREG32(MM_CFGREGS_CNTL, 0);
4318 /* not supported yet */
4319 if (link_cntl2 & SELECTABLE_DEEMPHASIS)
4323 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
4324 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
4325 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
4326 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
4327 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
4328 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
4330 tmp = RREG32(0x541c);
4331 WREG32(0x541c, tmp | 0x8);
4332 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
4333 link_cntl2 = RREG16(0x4088);
4334 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
4336 WREG16(0x4088, link_cntl2);
4337 WREG32(MM_CFGREGS_CNTL, 0);
4339 if ((rdev->family == CHIP_RV670) ||
4340 (rdev->family == CHIP_RV620) ||
4341 (rdev->family == CHIP_RV635)) {
4342 training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL);
4343 training_cntl &= ~LC_POINT_7_PLUS_EN;
4344 WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl);
4346 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
4347 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
4348 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
4351 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
4352 speed_cntl |= LC_GEN2_EN_STRAP;
4353 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
4356 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
4357 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
4359 link_width_cntl |= LC_UPCONFIGURE_DIS;
4361 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4362 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4367 * r600_get_gpu_clock - return GPU clock counter snapshot
4369 * @rdev: radeon_device pointer
4371 * Fetches a GPU clock counter snapshot (R6xx-cayman).
4372 * Returns the 64 bit clock counter snapshot.
4374 uint64_t r600_get_gpu_clock(struct radeon_device *rdev)
4378 sx_xlock(&rdev->gpu_clock_mutex);
4379 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4380 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
4381 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4382 sx_xunlock(&rdev->gpu_clock_mutex);