sys/dev/drm2/radeon/radeon_cp.c

   1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
   2 /*
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * Copyright 2007 Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  *
  27  * Authors:
  28  *    Kevin E. Martin <martin@valinux.com>
  29  *    Gareth Hughes <gareth@valinux.com>
  30  */
  31
  32 #include <sys/cdefs.h>
  33 __FBSDID("$FreeBSD$");
  34
  35 #include <sys/param.h>
  36 #include <sys/systm.h>
  37 #include <sys/linker.h>
  38 #include <sys/firmware.h>
  39
  40 #include <dev/drm2/drmP.h>
  41 #include <dev/drm2/radeon/radeon_drm.h>
  42 #include "radeon_drv.h"
  43 #include "r300_reg.h"
  44
  45 #define RADEON_FIFO_DEBUG       0
  46
  47 /* Firmware Names */
  48 #define FIRMWARE_R100           "radeonkmsfw_R100_cp"
  49 #define FIRMWARE_R200           "radeonkmsfw_R200_cp"
  50 #define FIRMWARE_R300           "radeonkmsfw_R300_cp"
  51 #define FIRMWARE_R420           "radeonkmsfw_R420_cp"
  52 #define FIRMWARE_RS690          "radeonkmsfw_RS690_cp"
  53 #define FIRMWARE_RS600          "radeonkmsfw_RS600_cp"
  54 #define FIRMWARE_R520           "radeonkmsfw_R520_cp"
  55
  56 static int radeon_do_cleanup_cp(struct drm_device * dev);
  57 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
  58
  59 u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off)
  60 {
  61         u32 val;
  62
  63         if (dev_priv->flags & RADEON_IS_AGP) {
  64                 val = DRM_READ32(dev_priv->ring_rptr, off);
  65         } else {
  66                 val = *(((volatile u32 *)
  67                          dev_priv->ring_rptr->handle) +
  68                         (off / sizeof(u32)));
  69                 val = le32_to_cpu(val);
  70         }
  71         return val;
  72 }
  73
  74 u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv)
  75 {
  76         if (dev_priv->writeback_works)
  77                 return radeon_read_ring_rptr(dev_priv, 0);
  78         else {
  79                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
  80                         return RADEON_READ(R600_CP_RB_RPTR);
  81                 else
  82                         return RADEON_READ(RADEON_CP_RB_RPTR);
  83         }
  84 }
  85
  86 void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val)
  87 {
  88         if (dev_priv->flags & RADEON_IS_AGP)
  89                 DRM_WRITE32(dev_priv->ring_rptr, off, val);
  90         else
  91                 *(((volatile u32 *) dev_priv->ring_rptr->handle) +
  92                   (off / sizeof(u32))) = cpu_to_le32(val);
  93 }
  94
  95 void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val)
  96 {
  97         radeon_write_ring_rptr(dev_priv, 0, val);
  98 }
  99
 100 u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index)
 101 {
 102         if (dev_priv->writeback_works) {
 103                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 104                         return radeon_read_ring_rptr(dev_priv,
 105                                                      R600_SCRATCHOFF(index));
 106                 else
 107                         return radeon_read_ring_rptr(dev_priv,
 108                                                      RADEON_SCRATCHOFF(index));
 109         } else {
 110                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 111                         return RADEON_READ(R600_SCRATCH_REG0 + 4*index);
 112                 else
 113                         return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index);
 114         }
 115 }
 116
 117 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 118 {
 119         u32 ret;
 120         RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
 121         ret = RADEON_READ(R520_MC_IND_DATA);
 122         RADEON_WRITE(R520_MC_IND_INDEX, 0);
 123         return ret;
 124 }
 125
 126 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 127 {
 128         u32 ret;
 129         RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
 130         ret = RADEON_READ(RS480_NB_MC_DATA);
 131         RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
 132         return ret;
 133 }
 134
 135 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 136 {
 137         u32 ret;
 138         RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
 139         ret = RADEON_READ(RS690_MC_DATA);
 140         RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
 141         return ret;
 142 }
 143
 144 static u32 RS600_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 145 {
 146         u32 ret;
 147         RADEON_WRITE(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) |
 148                                       RS600_MC_IND_CITF_ARB0));
 149         ret = RADEON_READ(RS600_MC_DATA);
 150         return ret;
 151 }
 152
 153 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 154 {
 155         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 156             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 157                 return RS690_READ_MCIND(dev_priv, addr);
 158         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 159                 return RS600_READ_MCIND(dev_priv, addr);
 160         else
 161                 return RS480_READ_MCIND(dev_priv, addr);
 162 }
 163
 164 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
 165 {
 166
 167         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 168                 return RADEON_READ(R700_MC_VM_FB_LOCATION);
 169         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 170                 return RADEON_READ(R600_MC_VM_FB_LOCATION);
 171         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 172                 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
 173         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 174                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 175                 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
 176         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 177                 return RS600_READ_MCIND(dev_priv, RS600_MC_FB_LOCATION);
 178         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 179                 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
 180         else
 181                 return RADEON_READ(RADEON_MC_FB_LOCATION);
 182 }
 183
 184 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
 185 {
 186         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 187                 RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc);
 188         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 189                 RADEON_WRITE(R600_MC_VM_FB_LOCATION, fb_loc);
 190         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 191                 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
 192         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 193                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 194                 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
 195         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 196                 RS600_WRITE_MCIND(RS600_MC_FB_LOCATION, fb_loc);
 197         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 198                 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
 199         else
 200                 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
 201 }
 202
 203 void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
 204 {
 205         /*R6xx/R7xx: AGP_TOP and BOT are actually 18 bits each */
 206         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
 207                 RADEON_WRITE(R700_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
 208                 RADEON_WRITE(R700_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
 209         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
 210                 RADEON_WRITE(R600_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
 211                 RADEON_WRITE(R600_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
 212         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 213                 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
 214         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 215                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 216                 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
 217         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 218                 RS600_WRITE_MCIND(RS600_MC_AGP_LOCATION, agp_loc);
 219         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 220                 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
 221         else
 222                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
 223 }
 224
 225 void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
 226 {
 227         u32 agp_base_hi = upper_32_bits(agp_base);
 228         u32 agp_base_lo = agp_base & 0xffffffff;
 229         u32 r6xx_agp_base = (agp_base >> 22) & 0x3ffff;
 230
 231         /* R6xx/R7xx must be aligned to a 4MB boundary */
 232         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 233                 RADEON_WRITE(R700_MC_VM_AGP_BASE, r6xx_agp_base);
 234         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 235                 RADEON_WRITE(R600_MC_VM_AGP_BASE, r6xx_agp_base);
 236         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
 237                 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
 238                 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
 239         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 240                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 241                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
 242                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
 243         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
 244                 RS600_WRITE_MCIND(RS600_AGP_BASE, agp_base_lo);
 245                 RS600_WRITE_MCIND(RS600_AGP_BASE_2, agp_base_hi);
 246         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
 247                 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
 248                 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
 249         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 250                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 251                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
 252                 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
 253         } else {
 254                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
 255                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
 256                         RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
 257         }
 258 }
 259
 260 void radeon_enable_bm(struct drm_radeon_private *dev_priv)
 261 {
 262         u32 tmp;
 263         /* Turn on bus mastering */
 264         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 265             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 266                 /* rs600/rs690/rs740 */
 267                 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
 268                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 269         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
 270                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
 271                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 272                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 273                 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
 274                 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 275                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 276         } /* PCIE cards appears to not need this */
 277 }
 278
 279 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
 280 {
 281         drm_radeon_private_t *dev_priv = dev->dev_private;
 282
 283         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
 284         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 285 }
 286
 287 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
 288 {
 289         RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
 290         return RADEON_READ(RADEON_PCIE_DATA);
 291 }
 292
 293 #if RADEON_FIFO_DEBUG
 294 static void radeon_status(drm_radeon_private_t * dev_priv)
 295 {
 296         printk("%s:\n", __func__);
 297         printk("RBBM_STATUS = 0x%08x\n",
 298                (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
 299         printk("CP_RB_RTPR = 0x%08x\n",
 300                (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
 301         printk("CP_RB_WTPR = 0x%08x\n",
 302                (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
 303         printk("AIC_CNTL = 0x%08x\n",
 304                (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
 305         printk("AIC_STAT = 0x%08x\n",
 306                (unsigned int)RADEON_READ(RADEON_AIC_STAT));
 307         printk("AIC_PT_BASE = 0x%08x\n",
 308                (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
 309         printk("TLB_ADDR = 0x%08x\n",
 310                (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
 311         printk("TLB_DATA = 0x%08x\n",
 312                (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
 313 }
 314 #endif
 315
 316 /* ================================================================
 317  * Engine, FIFO control
 318  */
 319
 320 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
 321 {
 322         u32 tmp;
 323         int i;
 324
 325         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 326
 327         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
 328                 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
 329                 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
 330                 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
 331
 332                 for (i = 0; i < dev_priv->usec_timeout; i++) {
 333                         if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
 334                               & RADEON_RB3D_DC_BUSY)) {
 335                                 return 0;
 336                         }
 337                         DRM_UDELAY(1);
 338                 }
 339         } else {
 340                 /* don't flush or purge cache here or lockup */
 341                 return 0;
 342         }
 343
 344 #if RADEON_FIFO_DEBUG
 345         DRM_ERROR("failed!\n");
 346         radeon_status(dev_priv);
 347 #endif
 348         return -EBUSY;
 349 }
 350
 351 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
 352 {
 353         int i;
 354
 355         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 356
 357         for (i = 0; i < dev_priv->usec_timeout; i++) {
 358                 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
 359                              & RADEON_RBBM_FIFOCNT_MASK);
 360                 if (slots >= entries)
 361                         return 0;
 362                 DRM_UDELAY(1);
 363         }
 364         DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
 365                  RADEON_READ(RADEON_RBBM_STATUS),
 366                  RADEON_READ(R300_VAP_CNTL_STATUS));
 367
 368 #if RADEON_FIFO_DEBUG
 369         DRM_ERROR("failed!\n");
 370         radeon_status(dev_priv);
 371 #endif
 372         return -EBUSY;
 373 }
 374
 375 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
 376 {
 377         int i, ret;
 378
 379         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 380
 381         ret = radeon_do_wait_for_fifo(dev_priv, 64);
 382         if (ret)
 383                 return ret;
 384
 385         for (i = 0; i < dev_priv->usec_timeout; i++) {
 386                 if (!(RADEON_READ(RADEON_RBBM_STATUS)
 387                       & RADEON_RBBM_ACTIVE)) {
 388                         radeon_do_pixcache_flush(dev_priv);
 389                         return 0;
 390                 }
 391                 DRM_UDELAY(1);
 392         }
 393         DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
 394                  RADEON_READ(RADEON_RBBM_STATUS),
 395                  RADEON_READ(R300_VAP_CNTL_STATUS));
 396
 397 #if RADEON_FIFO_DEBUG
 398         DRM_ERROR("failed!\n");
 399         radeon_status(dev_priv);
 400 #endif
 401         return -EBUSY;
 402 }
 403
 404 static void radeon_init_pipes(struct drm_device *dev)
 405 {
 406         drm_radeon_private_t *dev_priv = dev->dev_private;
 407         uint32_t gb_tile_config, gb_pipe_sel = 0;
 408
 409         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) {
 410                 uint32_t z_pipe_sel = RADEON_READ(RV530_GB_PIPE_SELECT2);
 411                 if ((z_pipe_sel & 3) == 3)
 412                         dev_priv->num_z_pipes = 2;
 413                 else
 414                         dev_priv->num_z_pipes = 1;
 415         } else
 416                 dev_priv->num_z_pipes = 1;
 417
 418         /* RS4xx/RS6xx/R4xx/R5xx */
 419         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
 420                 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
 421                 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
 422                 /* SE cards have 1 pipe */
 423                 if ((dev->pci_device == 0x5e4c) ||
 424                     (dev->pci_device == 0x5e4f))
 425                         dev_priv->num_gb_pipes = 1;
 426         } else {
 427                 /* R3xx */
 428                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300 &&
 429                      dev->pci_device != 0x4144) ||
 430                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350 &&
 431                      dev->pci_device != 0x4148)) {
 432                         dev_priv->num_gb_pipes = 2;
 433                 } else {
 434                         /* RV3xx/R300 AD/R350 AH */
 435                         dev_priv->num_gb_pipes = 1;
 436                 }
 437         }
 438         DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
 439
 440         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
 441
 442         switch (dev_priv->num_gb_pipes) {
 443         case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
 444         case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
 445         case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
 446         default:
 447         case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
 448         }
 449
 450         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
 451                 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
 452                 RADEON_WRITE(R300_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
 453         }
 454         RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
 455         radeon_do_wait_for_idle(dev_priv);
 456         RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
 457         RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
 458                                                R300_DC_AUTOFLUSH_ENABLE |
 459                                                R300_DC_DC_DISABLE_IGNORE_PE));
 460
 461
 462 }
 463
 464 /* ================================================================
 465  * CP control, initialization
 466  */
 467
 468 /* Load the microcode for the CP */
 469 static int radeon_cp_init_microcode(drm_radeon_private_t *dev_priv)
 470 {
 471         const char *fw_name = NULL;
 472         int err;
 473
 474         DRM_DEBUG("\n");
 475
 476         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
 477             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
 478             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
 479             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
 480             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
 481                 DRM_INFO("Loading R100 Microcode\n");
 482                 fw_name = FIRMWARE_R100;
 483         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
 484                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
 485                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
 486                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
 487                 DRM_INFO("Loading R200 Microcode\n");
 488                 fw_name = FIRMWARE_R200;
 489         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
 490                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
 491                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
 492                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
 493                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 494                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 495                 DRM_INFO("Loading R300 Microcode\n");
 496                 fw_name = FIRMWARE_R300;
 497         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
 498                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
 499                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
 500                 DRM_INFO("Loading R400 Microcode\n");
 501                 fw_name = FIRMWARE_R420;
 502         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 503                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 504                 DRM_INFO("Loading RS690/RS740 Microcode\n");
 505                 fw_name = FIRMWARE_RS690;
 506         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
 507                 DRM_INFO("Loading RS600 Microcode\n");
 508                 fw_name = FIRMWARE_RS600;
 509         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
 510                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
 511                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
 512                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
 513                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
 514                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
 515                 DRM_INFO("Loading R500 Microcode\n");
 516                 fw_name = FIRMWARE_R520;
 517         }
 518
 519         err = 0;
 520
 521         dev_priv->me_fw = firmware_get(fw_name);
 522         if (dev_priv->me_fw == NULL) {
 523                 err = -ENOENT;
 524                 DRM_ERROR("radeon_cp: Failed to load firmware \"%s\"\n",
 525                        fw_name);
 526         } else if (dev_priv->me_fw->datasize % 8) {
 527                 DRM_ERROR(
 528                        "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
 529                        dev_priv->me_fw->datasize, fw_name);
 530                 err = -EINVAL;
 531                 firmware_put(dev_priv->me_fw, FIRMWARE_UNLOAD);
 532                 dev_priv->me_fw = NULL;
 533         }
 534         return err;
 535 }
 536
 537 static void radeon_cp_load_microcode(drm_radeon_private_t *dev_priv)
 538 {
 539         const __be32 *fw_data;
 540         int i, size;
 541
 542         radeon_do_wait_for_idle(dev_priv);
 543
 544         if (dev_priv->me_fw) {
 545                 size = dev_priv->me_fw->datasize / 4;
 546                 fw_data = (const __be32 *)dev_priv->me_fw->data;
 547                 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
 548                 for (i = 0; i < size; i += 2) {
 549                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 550                                      be32_to_cpup(&fw_data[i]));
 551                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 552                                      be32_to_cpup(&fw_data[i + 1]));
 553                 }
 554         }
 555 }
 556
 557 /* Flush any pending commands to the CP.  This should only be used just
 558  * prior to a wait for idle, as it informs the engine that the command
 559  * stream is ending.
 560  */
 561 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
 562 {
 563         DRM_DEBUG("\n");
 564 #if 0
 565         u32 tmp;
 566
 567         tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
 568         RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
 569 #endif
 570 }
 571
 572 /* Wait for the CP to go idle.
 573  */
 574 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
 575 {
 576         RING_LOCALS;
 577         DRM_DEBUG("\n");
 578
 579         BEGIN_RING(6);
 580
 581         RADEON_PURGE_CACHE();
 582         RADEON_PURGE_ZCACHE();
 583         RADEON_WAIT_UNTIL_IDLE();
 584
 585         ADVANCE_RING();
 586         COMMIT_RING();
 587
 588         return radeon_do_wait_for_idle(dev_priv);
 589 }
 590
 591 /* Start the Command Processor.
 592  */
 593 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
 594 {
 595         RING_LOCALS;
 596         DRM_DEBUG("\n");
 597
 598         radeon_do_wait_for_idle(dev_priv);
 599
 600         RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
 601
 602         dev_priv->cp_running = 1;
 603
 604         /* on r420, any DMA from CP to system memory while 2D is active
 605          * can cause a hang.  workaround is to queue a CP RESYNC token
 606          */
 607         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) {
 608                 BEGIN_RING(3);
 609                 OUT_RING(CP_PACKET0(R300_CP_RESYNC_ADDR, 1));
 610                 OUT_RING(5); /* scratch reg 5 */
 611                 OUT_RING(0xdeadbeef);
 612                 ADVANCE_RING();
 613                 COMMIT_RING();
 614         }
 615
 616         BEGIN_RING(8);
 617         /* isync can only be written through cp on r5xx write it here */
 618         OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
 619         OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
 620                  RADEON_ISYNC_ANY3D_IDLE2D |
 621                  RADEON_ISYNC_WAIT_IDLEGUI |
 622                  RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 623         RADEON_PURGE_CACHE();
 624         RADEON_PURGE_ZCACHE();
 625         RADEON_WAIT_UNTIL_IDLE();
 626         ADVANCE_RING();
 627         COMMIT_RING();
 628
 629         dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
 630 }
 631
 632 /* Reset the Command Processor.  This will not flush any pending
 633  * commands, so you must wait for the CP command stream to complete
 634  * before calling this routine.
 635  */
 636 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
 637 {
 638         u32 cur_read_ptr;
 639         DRM_DEBUG("\n");
 640
 641         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 642         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 643         SET_RING_HEAD(dev_priv, cur_read_ptr);
 644         dev_priv->ring.tail = cur_read_ptr;
 645 }
 646
 647 /* Stop the Command Processor.  This will not flush any pending
 648  * commands, so you must flush the command stream and wait for the CP
 649  * to go idle before calling this routine.
 650  */
 651 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
 652 {
 653         RING_LOCALS;
 654         DRM_DEBUG("\n");
 655
 656         /* finish the pending CP_RESYNC token */
 657         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) {
 658                 BEGIN_RING(2);
 659                 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 660                 OUT_RING(R300_RB3D_DC_FINISH);
 661                 ADVANCE_RING();
 662                 COMMIT_RING();
 663                 radeon_do_wait_for_idle(dev_priv);
 664         }
 665
 666         RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
 667
 668         dev_priv->cp_running = 0;
 669 }
 670
 671 /* Reset the engine.  This will stop the CP if it is running.
 672  */
 673 static int radeon_do_engine_reset(struct drm_device * dev)
 674 {
 675         drm_radeon_private_t *dev_priv = dev->dev_private;
 676         u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
 677         DRM_DEBUG("\n");
 678
 679         radeon_do_pixcache_flush(dev_priv);
 680
 681         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 682                 /* may need something similar for newer chips */
 683                 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
 684                 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
 685
 686                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
 687                                                     RADEON_FORCEON_MCLKA |
 688                                                     RADEON_FORCEON_MCLKB |
 689                                                     RADEON_FORCEON_YCLKA |
 690                                                     RADEON_FORCEON_YCLKB |
 691                                                     RADEON_FORCEON_MC |
 692                                                     RADEON_FORCEON_AIC));
 693         }
 694
 695         rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
 696
 697         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
 698                                               RADEON_SOFT_RESET_CP |
 699                                               RADEON_SOFT_RESET_HI |
 700                                               RADEON_SOFT_RESET_SE |
 701                                               RADEON_SOFT_RESET_RE |
 702                                               RADEON_SOFT_RESET_PP |
 703                                               RADEON_SOFT_RESET_E2 |
 704                                               RADEON_SOFT_RESET_RB));
 705         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 706         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
 707                                               ~(RADEON_SOFT_RESET_CP |
 708                                                 RADEON_SOFT_RESET_HI |
 709                                                 RADEON_SOFT_RESET_SE |
 710                                                 RADEON_SOFT_RESET_RE |
 711                                                 RADEON_SOFT_RESET_PP |
 712                                                 RADEON_SOFT_RESET_E2 |
 713                                                 RADEON_SOFT_RESET_RB)));
 714         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 715
 716         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 717                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
 718                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
 719                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
 720         }
 721
 722         /* setup the raster pipes */
 723         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
 724             radeon_init_pipes(dev);
 725
 726         /* Reset the CP ring */
 727         radeon_do_cp_reset(dev_priv);
 728
 729         /* The CP is no longer running after an engine reset */
 730         dev_priv->cp_running = 0;
 731
 732         /* Reset any pending vertex, indirect buffers */
 733         radeon_freelist_reset(dev);
 734
 735         return 0;
 736 }
 737
 738 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
 739                                        drm_radeon_private_t *dev_priv,
 740                                        struct drm_file *file_priv)
 741 {
 742         struct drm_radeon_master_private *master_priv;
 743         u32 ring_start, cur_read_ptr;
 744
 745         /* Initialize the memory controller. With new memory map, the fb location
 746          * is not changed, it should have been properly initialized already. Part
 747          * of the problem is that the code below is bogus, assuming the GART is
 748          * always appended to the fb which is not necessarily the case
 749          */
 750         if (!dev_priv->new_memmap)
 751                 radeon_write_fb_location(dev_priv,
 752                              ((dev_priv->gart_vm_start - 1) & 0xffff0000)
 753                              | (dev_priv->fb_location >> 16));
 754
 755 #if __OS_HAS_AGP
 756         if (dev_priv->flags & RADEON_IS_AGP) {
 757                 radeon_write_agp_base(dev_priv, dev->agp->base);
 758
 759                 radeon_write_agp_location(dev_priv,
 760                              (((dev_priv->gart_vm_start - 1 +
 761                                 dev_priv->gart_size) & 0xffff0000) |
 762                               (dev_priv->gart_vm_start >> 16)));
 763
 764                 ring_start = (dev_priv->cp_ring->offset
 765                               - dev->agp->base
 766                               + dev_priv->gart_vm_start);
 767         } else
 768 #endif
 769                 ring_start = (dev_priv->cp_ring->offset
 770                               - (unsigned long)dev->sg->vaddr
 771                               + dev_priv->gart_vm_start);
 772
 773         RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
 774
 775         /* Set the write pointer delay */
 776         RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
 777
 778         /* Initialize the ring buffer's read and write pointers */
 779         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 780         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 781         SET_RING_HEAD(dev_priv, cur_read_ptr);
 782         dev_priv->ring.tail = cur_read_ptr;
 783
 784 #if __OS_HAS_AGP
 785         if (dev_priv->flags & RADEON_IS_AGP) {
 786                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 787                              dev_priv->ring_rptr->offset
 788                              - dev->agp->base + dev_priv->gart_vm_start);
 789         } else
 790 #endif
 791         {
 792                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 793                              dev_priv->ring_rptr->offset
 794                              - ((unsigned long) dev->sg->vaddr)
 795                              + dev_priv->gart_vm_start);
 796         }
 797
 798         /* Set ring buffer size */
 799 #ifdef __BIG_ENDIAN
 800         RADEON_WRITE(RADEON_CP_RB_CNTL,
 801                      RADEON_BUF_SWAP_32BIT |
 802                      (dev_priv->ring.fetch_size_l2ow << 18) |
 803                      (dev_priv->ring.rptr_update_l2qw << 8) |
 804                      dev_priv->ring.size_l2qw);
 805 #else
 806         RADEON_WRITE(RADEON_CP_RB_CNTL,
 807                      (dev_priv->ring.fetch_size_l2ow << 18) |
 808                      (dev_priv->ring.rptr_update_l2qw << 8) |
 809                      dev_priv->ring.size_l2qw);
 810 #endif
 811
 812
 813         /* Initialize the scratch register pointer.  This will cause
 814          * the scratch register values to be written out to memory
 815          * whenever they are updated.
 816          *
 817          * We simply put this behind the ring read pointer, this works
 818          * with PCI GART as well as (whatever kind of) AGP GART
 819          */
 820         RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
 821                      + RADEON_SCRATCH_REG_OFFSET);
 822
 823         RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
 824
 825         radeon_enable_bm(dev_priv);
 826
 827         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0);
 828         RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
 829
 830         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
 831         RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
 832
 833         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0);
 834         RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
 835
 836         /* reset sarea copies of these */
 837         master_priv = file_priv->masterp->driver_priv;
 838         if (master_priv->sarea_priv) {
 839                 master_priv->sarea_priv->last_frame = 0;
 840                 master_priv->sarea_priv->last_dispatch = 0;
 841                 master_priv->sarea_priv->last_clear = 0;
 842         }
 843
 844         radeon_do_wait_for_idle(dev_priv);
 845
 846         /* Sync everything up */
 847         RADEON_WRITE(RADEON_ISYNC_CNTL,
 848                      (RADEON_ISYNC_ANY2D_IDLE3D |
 849                       RADEON_ISYNC_ANY3D_IDLE2D |
 850                       RADEON_ISYNC_WAIT_IDLEGUI |
 851                       RADEON_ISYNC_CPSCRATCH_IDLEGUI));
 852
 853 }
 854
 855 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
 856 {
 857         u32 tmp;
 858
 859         /* Start with assuming that writeback doesn't work */
 860         dev_priv->writeback_works = 0;
 861
 862         /* Writeback doesn't seem to work everywhere, test it here and possibly
 863          * enable it if it appears to work
 864          */
 865         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
 866
 867         RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
 868
 869         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
 870                 u32 val;
 871
 872                 val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
 873                 if (val == 0xdeadbeef)
 874                         break;
 875                 DRM_UDELAY(1);
 876         }
 877
 878         if (tmp < dev_priv->usec_timeout) {
 879                 dev_priv->writeback_works = 1;
 880                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
 881         } else {
 882                 dev_priv->writeback_works = 0;
 883                 DRM_INFO("writeback test failed\n");
 884         }
 885         if (radeon_no_wb == 1) {
 886                 dev_priv->writeback_works = 0;
 887                 DRM_INFO("writeback forced off\n");
 888         }
 889
 890         if (!dev_priv->writeback_works) {
 891                 /* Disable writeback to avoid unnecessary bus master transfer */
 892                 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
 893                              RADEON_RB_NO_UPDATE);
 894                 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
 895         }
 896 }
 897
 898 /* Enable or disable IGP GART on the chip */
 899 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
 900 {
 901         u32 temp;
 902
 903         if (on) {
 904                 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
 905                           dev_priv->gart_vm_start,
 906                           (long)dev_priv->gart_info.bus_addr,
 907                           dev_priv->gart_size);
 908
 909                 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
 910                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 911                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 912                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
 913                                                              RS690_BLOCK_GFX_D3_EN));
 914                 else
 915                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
 916
 917                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 918                                                                RS480_VA_SIZE_32MB));
 919
 920                 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
 921                 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
 922                                                         RS480_TLB_ENABLE |
 923                                                         RS480_GTW_LAC_EN |
 924                                                         RS480_1LEVEL_GART));
 925
 926                 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
 927                 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
 928                 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
 929
 930                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
 931                 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
 932                                                       RS480_REQ_TYPE_SNOOP_DIS));
 933
 934                 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
 935
 936                 dev_priv->gart_size = 32*1024*1024;
 937                 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
 938                          0xffff0000) | (dev_priv->gart_vm_start >> 16));
 939
 940                 radeon_write_agp_location(dev_priv, temp);
 941
 942                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
 943                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 944                                                                RS480_VA_SIZE_32MB));
 945
 946                 do {
 947                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 948                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 949                                 break;
 950                         DRM_UDELAY(1);
 951                 } while (1);
 952
 953                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
 954                                 RS480_GART_CACHE_INVALIDATE);
 955
 956                 do {
 957                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 958                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 959                                 break;
 960                         DRM_UDELAY(1);
 961                 } while (1);
 962
 963                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
 964         } else {
 965                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
 966         }
 967 }
 968
 969 /* Enable or disable IGP GART on the chip */
 970 static void rs600_set_igpgart(drm_radeon_private_t *dev_priv, int on)
 971 {
 972         u32 temp;
 973         int i;
 974
 975         if (on) {
 976                 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
 977                          dev_priv->gart_vm_start,
 978                          (long)dev_priv->gart_info.bus_addr,
 979                          dev_priv->gart_size);
 980
 981                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (RS600_EFFECTIVE_L2_CACHE_SIZE(6) |
 982                                                     RS600_EFFECTIVE_L2_QUEUE_SIZE(6)));
 983
 984                 for (i = 0; i < 19; i++)
 985                         IGP_WRITE_MCIND(RS600_MC_PT0_CLIENT0_CNTL + i,
 986                                         (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE |
 987                                          RS600_SYSTEM_ACCESS_MODE_IN_SYS |
 988                                          RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH |
 989                                          RS600_EFFECTIVE_L1_CACHE_SIZE(3) |
 990                                          RS600_ENABLE_FRAGMENT_PROCESSING |
 991                                          RS600_EFFECTIVE_L1_QUEUE_SIZE(3)));
 992
 993                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL, (RS600_ENABLE_PAGE_TABLE |
 994                                                              RS600_PAGE_TABLE_TYPE_FLAT));
 995
 996                 /* disable all other contexts */
 997                 for (i = 1; i < 8; i++)
 998                         IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL + i, 0);
 999
1000                 /* setup the page table aperture */
1001                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
1002                                 dev_priv->gart_info.bus_addr);
1003                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR,
1004                                 dev_priv->gart_vm_start);
1005                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR,
1006                                 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
1007                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
1008
1009                 /* setup the system aperture */
1010                 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR,
1011                                 dev_priv->gart_vm_start);
1012                 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR,
1013                                 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
1014
1015                 /* enable page tables */
1016                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1017                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (temp | RS600_ENABLE_PT));
1018
1019                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
1020                 IGP_WRITE_MCIND(RS600_MC_CNTL1, (temp | RS600_ENABLE_PAGE_TABLES));
1021
1022                 /* invalidate the cache */
1023                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1024
1025                 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
1026                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1027                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1028
1029                 temp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE;
1030                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1031                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1032
1033                 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
1034                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1035                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1036
1037         } else {
1038                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, 0);
1039                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
1040                 temp &= ~RS600_ENABLE_PAGE_TABLES;
1041                 IGP_WRITE_MCIND(RS600_MC_CNTL1, temp);
1042         }
1043 }
1044
1045 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
1046 {
1047         u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
1048         if (on) {
1049
1050                 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
1051                           dev_priv->gart_vm_start,
1052                           (long)dev_priv->gart_info.bus_addr,
1053                           dev_priv->gart_size);
1054                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
1055                                   dev_priv->gart_vm_start);
1056                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
1057                                   dev_priv->gart_info.bus_addr);
1058                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
1059                                   dev_priv->gart_vm_start);
1060                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
1061                                   dev_priv->gart_vm_start +
1062                                   dev_priv->gart_size - 1);
1063
1064                 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
1065
1066                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1067                                   RADEON_PCIE_TX_GART_EN);
1068         } else {
1069                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1070                                   tmp & ~RADEON_PCIE_TX_GART_EN);
1071         }
1072 }
1073
1074 /* Enable or disable PCI GART on the chip */
1075 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1076 {
1077         u32 tmp;
1078
1079         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
1080             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
1081             (dev_priv->flags & RADEON_IS_IGPGART)) {
1082                 radeon_set_igpgart(dev_priv, on);
1083                 return;
1084         }
1085
1086         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
1087                 rs600_set_igpgart(dev_priv, on);
1088                 return;
1089         }
1090
1091         if (dev_priv->flags & RADEON_IS_PCIE) {
1092                 radeon_set_pciegart(dev_priv, on);
1093                 return;
1094         }
1095
1096         tmp = RADEON_READ(RADEON_AIC_CNTL);
1097
1098         if (on) {
1099                 RADEON_WRITE(RADEON_AIC_CNTL,
1100                              tmp | RADEON_PCIGART_TRANSLATE_EN);
1101
1102                 /* set PCI GART page-table base address
1103                  */
1104                 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1105
1106                 /* set address range for PCI address translate
1107                  */
1108                 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1109                 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1110                              + dev_priv->gart_size - 1);
1111
1112                 /* Turn off AGP aperture -- is this required for PCI GART?
1113                  */
1114                 radeon_write_agp_location(dev_priv, 0xffffffc0);
1115                 RADEON_WRITE(RADEON_AGP_COMMAND, 0);    /* clear AGP_COMMAND */
1116         } else {
1117                 RADEON_WRITE(RADEON_AIC_CNTL,
1118                              tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1119         }
1120 }
1121
1122 static int radeon_setup_pcigart_surface(drm_radeon_private_t *dev_priv)
1123 {
1124         struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
1125         struct radeon_virt_surface *vp;
1126         int i;
1127
1128         for (i = 0; i < RADEON_MAX_SURFACES * 2; i++) {
1129                 if (!dev_priv->virt_surfaces[i].file_priv ||
1130                     dev_priv->virt_surfaces[i].file_priv == PCIGART_FILE_PRIV)
1131                         break;
1132         }
1133         if (i >= 2 * RADEON_MAX_SURFACES)
1134                 return -ENOMEM;
1135         vp = &dev_priv->virt_surfaces[i];
1136
1137         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1138                 struct radeon_surface *sp = &dev_priv->surfaces[i];
1139                 if (sp->refcount)
1140                         continue;
1141
1142                 vp->surface_index = i;
1143                 vp->lower = gart_info->bus_addr;
1144                 vp->upper = vp->lower + gart_info->table_size;
1145                 vp->flags = 0;
1146                 vp->file_priv = PCIGART_FILE_PRIV;
1147
1148                 sp->refcount = 1;
1149                 sp->lower = vp->lower;
1150                 sp->upper = vp->upper;
1151                 sp->flags = 0;
1152
1153                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, sp->flags);
1154                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * i, sp->lower);
1155                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * i, sp->upper);
1156                 return 0;
1157         }
1158
1159         return -ENOMEM;
1160 }
1161
1162 static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1163                              struct drm_file *file_priv)
1164 {
1165         drm_radeon_private_t *dev_priv = dev->dev_private;
1166         struct drm_radeon_master_private *master_priv = file_priv->masterp->driver_priv;
1167
1168         DRM_DEBUG("\n");
1169
1170         /* if we require new memory map but we don't have it fail */
1171         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1172                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1173                 radeon_do_cleanup_cp(dev);
1174                 return -EINVAL;
1175         }
1176
1177         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1178                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1179                 dev_priv->flags &= ~RADEON_IS_AGP;
1180         } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1181                    && !init->is_pci) {
1182                 DRM_DEBUG("Restoring AGP flag\n");
1183                 dev_priv->flags |= RADEON_IS_AGP;
1184         }
1185
1186         if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
1187                 DRM_ERROR("PCI GART memory not allocated!\n");
1188                 radeon_do_cleanup_cp(dev);
1189                 return -EINVAL;
1190         }
1191
1192         dev_priv->usec_timeout = init->usec_timeout;
1193         if (dev_priv->usec_timeout < 1 ||
1194             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1195                 DRM_DEBUG("TIMEOUT problem!\n");
1196                 radeon_do_cleanup_cp(dev);
1197                 return -EINVAL;
1198         }
1199
1200         /* Enable vblank on CRTC1 for older X servers
1201          */
1202         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1203
1204         switch(init->func) {
1205         case RADEON_INIT_R200_CP:
1206                 dev_priv->microcode_version = UCODE_R200;
1207                 break;
1208         case RADEON_INIT_R300_CP:
1209                 dev_priv->microcode_version = UCODE_R300;
1210                 break;
1211         default:
1212                 dev_priv->microcode_version = UCODE_R100;
1213         }
1214
1215         dev_priv->do_boxes = 0;
1216         dev_priv->cp_mode = init->cp_mode;
1217
1218         /* We don't support anything other than bus-mastering ring mode,
1219          * but the ring can be in either AGP or PCI space for the ring
1220          * read pointer.
1221          */
1222         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1223             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1224                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1225                 radeon_do_cleanup_cp(dev);
1226                 return -EINVAL;
1227         }
1228
1229         switch (init->fb_bpp) {
1230         case 16:
1231                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1232                 break;
1233         case 32:
1234         default:
1235                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1236                 break;
1237         }
1238         dev_priv->front_offset = init->front_offset;
1239         dev_priv->front_pitch = init->front_pitch;
1240         dev_priv->back_offset = init->back_offset;
1241         dev_priv->back_pitch = init->back_pitch;
1242
1243         switch (init->depth_bpp) {
1244         case 16:
1245                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1246                 break;
1247         case 32:
1248         default:
1249                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1250                 break;
1251         }
1252         dev_priv->depth_offset = init->depth_offset;
1253         dev_priv->depth_pitch = init->depth_pitch;
1254
1255         /* Hardware state for depth clears.  Remove this if/when we no
1256          * longer clear the depth buffer with a 3D rectangle.  Hard-code
1257          * all values to prevent unwanted 3D state from slipping through
1258          * and screwing with the clear operation.
1259          */
1260         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1261                                            (dev_priv->color_fmt << 10) |
1262                                            (dev_priv->microcode_version ==
1263                                             UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1264
1265         dev_priv->depth_clear.rb3d_zstencilcntl =
1266             (dev_priv->depth_fmt |
1267              RADEON_Z_TEST_ALWAYS |
1268              RADEON_STENCIL_TEST_ALWAYS |
1269              RADEON_STENCIL_S_FAIL_REPLACE |
1270              RADEON_STENCIL_ZPASS_REPLACE |
1271              RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1272
1273         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1274                                          RADEON_BFACE_SOLID |
1275                                          RADEON_FFACE_SOLID |
1276                                          RADEON_FLAT_SHADE_VTX_LAST |
1277                                          RADEON_DIFFUSE_SHADE_FLAT |
1278                                          RADEON_ALPHA_SHADE_FLAT |
1279                                          RADEON_SPECULAR_SHADE_FLAT |
1280                                          RADEON_FOG_SHADE_FLAT |
1281                                          RADEON_VTX_PIX_CENTER_OGL |
1282                                          RADEON_ROUND_MODE_TRUNC |
1283                                          RADEON_ROUND_PREC_8TH_PIX);
1284
1285
1286         dev_priv->ring_offset = init->ring_offset;
1287         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1288         dev_priv->buffers_offset = init->buffers_offset;
1289         dev_priv->gart_textures_offset = init->gart_textures_offset;
1290
1291         master_priv->sarea = drm_getsarea(dev);
1292         if (!master_priv->sarea) {
1293                 DRM_ERROR("could not find sarea!\n");
1294                 radeon_do_cleanup_cp(dev);
1295                 return -EINVAL;
1296         }
1297
1298         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1299         if (!dev_priv->cp_ring) {
1300                 DRM_ERROR("could not find cp ring region!\n");
1301                 radeon_do_cleanup_cp(dev);
1302                 return -EINVAL;
1303         }
1304         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1305         if (!dev_priv->ring_rptr) {
1306                 DRM_ERROR("could not find ring read pointer!\n");
1307                 radeon_do_cleanup_cp(dev);
1308                 return -EINVAL;
1309         }
1310         dev->agp_buffer_token = init->buffers_offset;
1311         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1312         if (!dev->agp_buffer_map) {
1313                 DRM_ERROR("could not find dma buffer region!\n");
1314                 radeon_do_cleanup_cp(dev);
1315                 return -EINVAL;
1316         }
1317
1318         if (init->gart_textures_offset) {
1319                 dev_priv->gart_textures =
1320                     drm_core_findmap(dev, init->gart_textures_offset);
1321                 if (!dev_priv->gart_textures) {
1322                         DRM_ERROR("could not find GART texture region!\n");
1323                         radeon_do_cleanup_cp(dev);
1324                         return -EINVAL;
1325                 }
1326         }
1327
1328 #if __OS_HAS_AGP
1329         if (dev_priv->flags & RADEON_IS_AGP) {
1330                 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1331                 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1332                 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
1333                 if (!dev_priv->cp_ring->handle ||
1334                     !dev_priv->ring_rptr->handle ||
1335                     !dev->agp_buffer_map->handle) {
1336                         DRM_ERROR("could not find ioremap agp regions!\n");
1337                         radeon_do_cleanup_cp(dev);
1338                         return -EINVAL;
1339                 }
1340         } else
1341 #endif
1342         {
1343                 dev_priv->cp_ring->handle =
1344                         (void *)(unsigned long)dev_priv->cp_ring->offset;
1345                 dev_priv->ring_rptr->handle =
1346                         (void *)(unsigned long)dev_priv->ring_rptr->offset;
1347                 dev->agp_buffer_map->handle =
1348                         (void *)(unsigned long)dev->agp_buffer_map->offset;
1349
1350                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1351                           dev_priv->cp_ring->handle);
1352                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1353                           dev_priv->ring_rptr->handle);
1354                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1355                           dev->agp_buffer_map->handle);
1356         }
1357
1358         dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1359         dev_priv->fb_size =
1360                 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1361                 - dev_priv->fb_location;
1362
1363         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1364                                         ((dev_priv->front_offset
1365                                           + dev_priv->fb_location) >> 10));
1366
1367         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1368                                        ((dev_priv->back_offset
1369                                          + dev_priv->fb_location) >> 10));
1370
1371         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1372                                         ((dev_priv->depth_offset
1373                                           + dev_priv->fb_location) >> 10));
1374
1375         dev_priv->gart_size = init->gart_size;
1376
1377         /* New let's set the memory map ... */
1378         if (dev_priv->new_memmap) {
1379                 u32 base = 0;
1380
1381                 DRM_INFO("Setting GART location based on new memory map\n");
1382
1383                 /* If using AGP, try to locate the AGP aperture at the same
1384                  * location in the card and on the bus, though we have to
1385                  * align it down.
1386                  */
1387 #if __OS_HAS_AGP
1388                 if (dev_priv->flags & RADEON_IS_AGP) {
1389                         base = dev->agp->base;
1390                         /* Check if valid */
1391                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1392                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1393                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1394                                          dev->agp->base);
1395                                 base = 0;
1396                         }
1397                 }
1398 #endif
1399                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1400                 if (base == 0) {
1401                         base = dev_priv->fb_location + dev_priv->fb_size;
1402                         if (base < dev_priv->fb_location ||
1403                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1404                                 base = dev_priv->fb_location
1405                                         - dev_priv->gart_size;
1406                 }
1407                 dev_priv->gart_vm_start = base & 0xffc00000u;
1408                 if (dev_priv->gart_vm_start != base)
1409                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1410                                  base, dev_priv->gart_vm_start);
1411         } else {
1412                 DRM_INFO("Setting GART location based on old memory map\n");
1413                 dev_priv->gart_vm_start = dev_priv->fb_location +
1414                         RADEON_READ(RADEON_CONFIG_APER_SIZE);
1415         }
1416
1417 #if __OS_HAS_AGP
1418         if (dev_priv->flags & RADEON_IS_AGP)
1419                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1420                                                  - dev->agp->base
1421                                                  + dev_priv->gart_vm_start);
1422         else
1423 #endif
1424                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1425                                         - (unsigned long)dev->sg->vaddr
1426                                         + dev_priv->gart_vm_start);
1427
1428         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1429         DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1430         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1431                   dev_priv->gart_buffers_offset);
1432
1433         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1434         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1435                               + init->ring_size / sizeof(u32));
1436         dev_priv->ring.size = init->ring_size;
1437         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1438
1439         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1440         dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1441
1442         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1443         dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1444         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1445
1446         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1447
1448 #if __OS_HAS_AGP
1449         if (dev_priv->flags & RADEON_IS_AGP) {
1450                 /* Turn off PCI GART */
1451                 radeon_set_pcigart(dev_priv, 0);
1452         } else
1453 #endif
1454         {
1455                 u32 sctrl;
1456                 int ret;
1457
1458                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1459                 /* if we have an offset set from userspace */
1460                 if (dev_priv->pcigart_offset_set) {
1461                         dev_priv->gart_info.bus_addr =
1462                                 (resource_size_t)dev_priv->pcigart_offset + dev_priv->fb_location;
1463                         dev_priv->gart_info.mapping.offset =
1464                             dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1465                         dev_priv->gart_info.mapping.size =
1466                             dev_priv->gart_info.table_size;
1467
1468                         drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1469                         dev_priv->gart_info.addr =
1470                             dev_priv->gart_info.mapping.handle;
1471
1472                         if (dev_priv->flags & RADEON_IS_PCIE)
1473                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1474                         else
1475                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1476                         dev_priv->gart_info.gart_table_location =
1477                             DRM_ATI_GART_FB;
1478
1479                         DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1480                                   dev_priv->gart_info.addr,
1481                                   dev_priv->pcigart_offset);
1482                 } else {
1483                         if (dev_priv->flags & RADEON_IS_IGPGART)
1484                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1485                         else
1486                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1487                         dev_priv->gart_info.gart_table_location =
1488                             DRM_ATI_GART_MAIN;
1489                         dev_priv->gart_info.addr = NULL;
1490                         dev_priv->gart_info.bus_addr = 0;
1491                         if (dev_priv->flags & RADEON_IS_PCIE) {
1492                                 DRM_ERROR
1493                                     ("Cannot use PCI Express without GART in FB memory\n");
1494                                 radeon_do_cleanup_cp(dev);
1495                                 return -EINVAL;
1496                         }
1497                 }
1498
1499                 sctrl = RADEON_READ(RADEON_SURFACE_CNTL);
1500                 RADEON_WRITE(RADEON_SURFACE_CNTL, 0);
1501                 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1502                         ret = r600_page_table_init(dev);
1503                 else
1504                         ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info);
1505                 RADEON_WRITE(RADEON_SURFACE_CNTL, sctrl);
1506
1507                 if (!ret) {
1508                         DRM_ERROR("failed to init PCI GART!\n");
1509                         radeon_do_cleanup_cp(dev);
1510                         return -ENOMEM;
1511                 }
1512
1513                 ret = radeon_setup_pcigart_surface(dev_priv);
1514                 if (ret) {
1515                         DRM_ERROR("failed to setup GART surface!\n");
1516                         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1517                                 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1518                         else
1519                                 drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info);
1520                         radeon_do_cleanup_cp(dev);
1521                         return ret;
1522                 }
1523
1524                 /* Turn on PCI GART */
1525                 radeon_set_pcigart(dev_priv, 1);
1526         }
1527
1528         if (!dev_priv->me_fw) {
1529                 int err = radeon_cp_init_microcode(dev_priv);
1530                 if (err) {
1531                         DRM_ERROR("Failed to load firmware!\n");
1532                         radeon_do_cleanup_cp(dev);
1533                         return err;
1534                 }
1535         }
1536         radeon_cp_load_microcode(dev_priv);
1537         radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1538
1539         dev_priv->last_buf = 0;
1540
1541         radeon_do_engine_reset(dev);
1542         radeon_test_writeback(dev_priv);
1543
1544         return 0;
1545 }
1546
1547 static int radeon_do_cleanup_cp(struct drm_device * dev)
1548 {
1549         drm_radeon_private_t *dev_priv = dev->dev_private;
1550         DRM_DEBUG("\n");
1551
1552         /* Make sure interrupts are disabled here because the uninstall ioctl
1553          * may not have been called from userspace and after dev_private
1554          * is freed, it's too late.
1555          */
1556         if (dev->irq_enabled)
1557                 drm_irq_uninstall(dev);
1558
1559 #if __OS_HAS_AGP
1560         if (dev_priv->flags & RADEON_IS_AGP) {
1561                 if (dev_priv->cp_ring != NULL) {
1562                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1563                         dev_priv->cp_ring = NULL;
1564                 }
1565                 if (dev_priv->ring_rptr != NULL) {
1566                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1567                         dev_priv->ring_rptr = NULL;
1568                 }
1569                 if (dev->agp_buffer_map != NULL) {
1570                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1571                         dev->agp_buffer_map = NULL;
1572                 }
1573         } else
1574 #endif
1575         {
1576
1577                 if (dev_priv->gart_info.bus_addr) {
1578                         /* Turn off PCI GART */
1579                         radeon_set_pcigart(dev_priv, 0);
1580                         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1581                                 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1582                         else {
1583                                 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1584                                         DRM_ERROR("failed to cleanup PCI GART!\n");
1585                         }
1586                 }
1587
1588                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1589                 {
1590                         drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1591                         dev_priv->gart_info.addr = NULL;
1592                 }
1593         }
1594         /* only clear to the start of flags */
1595         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1596
1597         return 0;
1598 }
1599
1600 /* This code will reinit the Radeon CP hardware after a resume from disc.
1601  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1602  * here we make sure that all Radeon hardware initialisation is re-done without
1603  * affecting running applications.
1604  *
1605  * Charl P. Botha <http://cpbotha.net>
1606  */
1607 static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
1608 {
1609         drm_radeon_private_t *dev_priv = dev->dev_private;
1610
1611         if (!dev_priv) {
1612                 DRM_ERROR("Called with no initialization\n");
1613                 return -EINVAL;
1614         }
1615
1616         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1617
1618 #if __OS_HAS_AGP
1619         if (dev_priv->flags & RADEON_IS_AGP) {
1620                 /* Turn off PCI GART */
1621                 radeon_set_pcigart(dev_priv, 0);
1622         } else
1623 #endif
1624         {
1625                 /* Turn on PCI GART */
1626                 radeon_set_pcigart(dev_priv, 1);
1627         }
1628
1629         radeon_cp_load_microcode(dev_priv);
1630         radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1631
1632         dev_priv->have_z_offset = 0;
1633         radeon_do_engine_reset(dev);
1634         radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1635
1636         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1637
1638         return 0;
1639 }
1640
1641 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1642 {
1643         drm_radeon_private_t *dev_priv = dev->dev_private;
1644         drm_radeon_init_t *init = data;
1645
1646         LOCK_TEST_WITH_RETURN(dev, file_priv);
1647
1648         if (init->func == RADEON_INIT_R300_CP)
1649                 r300_init_reg_flags(dev);
1650
1651         switch (init->func) {
1652         case RADEON_INIT_CP:
1653         case RADEON_INIT_R200_CP:
1654         case RADEON_INIT_R300_CP:
1655                 return radeon_do_init_cp(dev, init, file_priv);
1656         case RADEON_INIT_R600_CP:
1657                 return r600_do_init_cp(dev, init, file_priv);
1658                 break;
1659         case RADEON_CLEANUP_CP:
1660                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1661                         return r600_do_cleanup_cp(dev);
1662                 else
1663                         return radeon_do_cleanup_cp(dev);
1664         }
1665
1666         return -EINVAL;
1667 }
1668
1669 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1670 {
1671         drm_radeon_private_t *dev_priv = dev->dev_private;
1672         DRM_DEBUG("\n");
1673
1674         LOCK_TEST_WITH_RETURN(dev, file_priv);
1675
1676         if (dev_priv->cp_running) {
1677                 DRM_DEBUG("while CP running\n");
1678                 return 0;
1679         }
1680         if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1681                 DRM_DEBUG("called with bogus CP mode (%d)\n",
1682                           dev_priv->cp_mode);
1683                 return 0;
1684         }
1685
1686         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1687                 r600_do_cp_start(dev_priv);
1688         else
1689                 radeon_do_cp_start(dev_priv);
1690
1691         return 0;
1692 }
1693
1694 /* Stop the CP.  The engine must have been idled before calling this
1695  * routine.
1696  */
1697 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1698 {
1699         drm_radeon_private_t *dev_priv = dev->dev_private;
1700         drm_radeon_cp_stop_t *stop = data;
1701         int ret;
1702         DRM_DEBUG("\n");
1703
1704         LOCK_TEST_WITH_RETURN(dev, file_priv);
1705
1706         if (!dev_priv->cp_running)
1707                 return 0;
1708
1709         /* Flush any pending CP commands.  This ensures any outstanding
1710          * commands are exectuted by the engine before we turn it off.
1711          */
1712         if (stop->flush) {
1713                 radeon_do_cp_flush(dev_priv);
1714         }
1715
1716         /* If we fail to make the engine go idle, we return an error
1717          * code so that the DRM ioctl wrapper can try again.
1718          */
1719         if (stop->idle) {
1720                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1721                         ret = r600_do_cp_idle(dev_priv);
1722                 else
1723                         ret = radeon_do_cp_idle(dev_priv);
1724                 if (ret)
1725                         return ret;
1726         }
1727
1728         /* Finally, we can turn off the CP.  If the engine isn't idle,
1729          * we will get some dropped triangles as they won't be fully
1730          * rendered before the CP is shut down.
1731          */
1732         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1733                 r600_do_cp_stop(dev_priv);
1734         else
1735                 radeon_do_cp_stop(dev_priv);
1736
1737         /* Reset the engine */
1738         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1739                 r600_do_engine_reset(dev);
1740         else
1741                 radeon_do_engine_reset(dev);
1742
1743         return 0;
1744 }
1745
1746 void radeon_do_release(struct drm_device * dev)
1747 {
1748         drm_radeon_private_t *dev_priv = dev->dev_private;
1749         int i, ret;
1750
1751         if (dev_priv) {
1752                 if (dev_priv->cp_running) {
1753                         /* Stop the cp */
1754                         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1755                                 while ((ret = r600_do_cp_idle(dev_priv)) != 0) {
1756                                         DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1757 #ifdef __linux__
1758                                         schedule();
1759 #else
1760                                         tsleep(&ret, PZERO, "rdnrel", 1);
1761 #endif
1762                                 }
1763                         } else {
1764                                 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1765                                         DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1766 #ifdef __linux__
1767                                         schedule();
1768 #else
1769                                         tsleep(&ret, PZERO, "rdnrel", 1);
1770 #endif
1771                                 }
1772                         }
1773                         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1774                                 r600_do_cp_stop(dev_priv);
1775                                 r600_do_engine_reset(dev);
1776                         } else {
1777                                 radeon_do_cp_stop(dev_priv);
1778                                 radeon_do_engine_reset(dev);
1779                         }
1780                 }
1781
1782                 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) {
1783                         /* Disable *all* interrupts */
1784                         if (dev_priv->mmio)     /* remove this after permanent addmaps */
1785                                 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1786
1787                         if (dev_priv->mmio) {   /* remove all surfaces */
1788                                 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1789                                         RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1790                                         RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1791                                                      16 * i, 0);
1792                                         RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1793                                                      16 * i, 0);
1794                                 }
1795                         }
1796                 }
1797
1798                 /* Free memory heap structures */
1799                 radeon_mem_takedown(&(dev_priv->gart_heap));
1800                 radeon_mem_takedown(&(dev_priv->fb_heap));
1801
1802                 /* deallocate kernel resources */
1803                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1804                         r600_do_cleanup_cp(dev);
1805                 else
1806                         radeon_do_cleanup_cp(dev);
1807                 if (dev_priv->me_fw != NULL) {
1808                         firmware_put(dev_priv->me_fw, FIRMWARE_UNLOAD);
1809                         dev_priv->me_fw = NULL;
1810                 }
1811                 if (dev_priv->pfp_fw != NULL) {
1812                         firmware_put(dev_priv->pfp_fw, FIRMWARE_UNLOAD);
1813                         dev_priv->pfp_fw = NULL;
1814                 }
1815         }
1816 }
1817
1818 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1819  */
1820 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1821 {
1822         drm_radeon_private_t *dev_priv = dev->dev_private;
1823         DRM_DEBUG("\n");
1824
1825         LOCK_TEST_WITH_RETURN(dev, file_priv);
1826
1827         if (!dev_priv) {
1828                 DRM_DEBUG("called before init done\n");
1829                 return -EINVAL;
1830         }
1831
1832         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1833                 r600_do_cp_reset(dev_priv);
1834         else
1835                 radeon_do_cp_reset(dev_priv);
1836
1837         /* The CP is no longer running after an engine reset */
1838         dev_priv->cp_running = 0;
1839
1840         return 0;
1841 }
1842
1843 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1844 {
1845         drm_radeon_private_t *dev_priv = dev->dev_private;
1846         DRM_DEBUG("\n");
1847
1848         LOCK_TEST_WITH_RETURN(dev, file_priv);
1849
1850         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1851                 return r600_do_cp_idle(dev_priv);
1852         else
1853                 return radeon_do_cp_idle(dev_priv);
1854 }
1855
1856 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1857  */
1858 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1859 {
1860         drm_radeon_private_t *dev_priv = dev->dev_private;
1861         DRM_DEBUG("\n");
1862
1863         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1864                 return r600_do_resume_cp(dev, file_priv);
1865         else
1866                 return radeon_do_resume_cp(dev, file_priv);
1867 }
1868
1869 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1870 {
1871         drm_radeon_private_t *dev_priv = dev->dev_private;
1872         DRM_DEBUG("\n");
1873
1874         LOCK_TEST_WITH_RETURN(dev, file_priv);
1875
1876         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1877                 return r600_do_engine_reset(dev);
1878         else
1879                 return radeon_do_engine_reset(dev);
1880 }
1881
1882 /* ================================================================
1883  * Fullscreen mode
1884  */
1885
1886 /* KW: Deprecated to say the least:
1887  */
1888 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1889 {
1890         return 0;
1891 }
1892
1893 /* ================================================================
1894  * Freelist management
1895  */
1896
1897 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1898  *   bufs until freelist code is used.  Note this hides a problem with
1899  *   the scratch register * (used to keep track of last buffer
1900  *   completed) being written to before * the last buffer has actually
1901  *   completed rendering.
1902  *
1903  * KW:  It's also a good way to find free buffers quickly.
1904  *
1905  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1906  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1907  * we essentially have to do this, else old clients will break.
1908  *
1909  * However, it does leave open a potential deadlock where all the
1910  * buffers are held by other clients, which can't release them because
1911  * they can't get the lock.
1912  */
1913
1914 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1915 {
1916         struct drm_device_dma *dma = dev->dma;
1917         drm_radeon_private_t *dev_priv = dev->dev_private;
1918         drm_radeon_buf_priv_t *buf_priv;
1919         struct drm_buf *buf;
1920         int i, t;
1921         int start;
1922
1923         if (++dev_priv->last_buf >= dma->buf_count)
1924                 dev_priv->last_buf = 0;
1925
1926         start = dev_priv->last_buf;
1927
1928         for (t = 0; t < dev_priv->usec_timeout; t++) {
1929                 u32 done_age = GET_SCRATCH(dev_priv, 1);
1930                 DRM_DEBUG("done_age = %d\n", done_age);
1931                 for (i = 0; i < dma->buf_count; i++) {
1932                         buf = dma->buflist[start];
1933                         buf_priv = buf->dev_private;
1934                         if (buf->file_priv == NULL || (buf->pending &&
1935                                                        buf_priv->age <=
1936                                                        done_age)) {
1937                                 dev_priv->stats.requested_bufs++;
1938                                 buf->pending = 0;
1939                                 return buf;
1940                         }
1941                         if (++start >= dma->buf_count)
1942                                 start = 0;
1943                 }
1944
1945                 if (t) {
1946                         DRM_UDELAY(1);
1947                         dev_priv->stats.freelist_loops++;
1948                 }
1949         }
1950
1951         return NULL;
1952 }
1953
1954 void radeon_freelist_reset(struct drm_device * dev)
1955 {
1956         struct drm_device_dma *dma = dev->dma;
1957         drm_radeon_private_t *dev_priv = dev->dev_private;
1958         int i;
1959
1960         dev_priv->last_buf = 0;
1961         for (i = 0; i < dma->buf_count; i++) {
1962                 struct drm_buf *buf = dma->buflist[i];
1963                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1964                 buf_priv->age = 0;
1965         }
1966 }
1967
1968 /* ================================================================
1969  * CP command submission
1970  */
1971
1972 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1973 {
1974         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1975         int i;
1976         u32 last_head = GET_RING_HEAD(dev_priv);
1977
1978         for (i = 0; i < dev_priv->usec_timeout; i++) {
1979                 u32 head = GET_RING_HEAD(dev_priv);
1980
1981                 ring->space = (head - ring->tail) * sizeof(u32);
1982                 if (ring->space <= 0)
1983                         ring->space += ring->size;
1984                 if (ring->space > n)
1985                         return 0;
1986
1987                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1988
1989                 if (head != last_head)
1990                         i = 0;
1991                 last_head = head;
1992
1993                 DRM_UDELAY(1);
1994         }
1995
1996         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1997 #if RADEON_FIFO_DEBUG
1998         radeon_status(dev_priv);
1999         DRM_ERROR("failed!\n");
2000 #endif
2001         return -EBUSY;
2002 }
2003
2004 static int radeon_cp_get_buffers(struct drm_device *dev,
2005                                  struct drm_file *file_priv,
2006                                  struct drm_dma * d)
2007 {
2008         int i;
2009         struct drm_buf *buf;
2010
2011         for (i = d->granted_count; i < d->request_count; i++) {
2012                 buf = radeon_freelist_get(dev);
2013                 if (!buf)
2014                         return -EBUSY;  /* NOTE: broken client */
2015
2016                 buf->file_priv = file_priv;
2017
2018                 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
2019                                      sizeof(buf->idx)))
2020                         return -EFAULT;
2021                 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
2022                                      sizeof(buf->total)))
2023                         return -EFAULT;
2024
2025                 d->granted_count++;
2026         }
2027         return 0;
2028 }
2029
2030 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
2031 {
2032         struct drm_device_dma *dma = dev->dma;
2033         int ret = 0;
2034         struct drm_dma *d = data;
2035
2036         LOCK_TEST_WITH_RETURN(dev, file_priv);
2037
2038         /* Please don't send us buffers.
2039          */
2040         if (d->send_count != 0) {
2041                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
2042                           DRM_CURRENTPID, d->send_count);
2043                 return -EINVAL;
2044         }
2045
2046         /* We'll send you buffers.
2047          */
2048         if (d->request_count < 0 || d->request_count > dma->buf_count) {
2049                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
2050                           DRM_CURRENTPID, d->request_count, dma->buf_count);
2051                 return -EINVAL;
2052         }
2053
2054         d->granted_count = 0;
2055
2056         if (d->request_count) {
2057                 ret = radeon_cp_get_buffers(dev, file_priv, d);
2058         }
2059
2060         return ret;
2061 }
2062
2063 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
2064 {
2065         drm_radeon_private_t *dev_priv;
2066         int ret = 0;
2067
2068         dev_priv = malloc(sizeof(drm_radeon_private_t),
2069             DRM_MEM_DRIVER, M_ZERO | M_WAITOK);
2070         if (dev_priv == NULL)
2071                 return -ENOMEM;
2072
2073         dev->dev_private = (void *)dev_priv;
2074         dev_priv->flags = flags;
2075
2076         switch (flags & RADEON_FAMILY_MASK) {
2077         case CHIP_R100:
2078         case CHIP_RV200:
2079         case CHIP_R200:
2080         case CHIP_R300:
2081         case CHIP_R350:
2082         case CHIP_R420:
2083         case CHIP_R423:
2084         case CHIP_RV410:
2085         case CHIP_RV515:
2086         case CHIP_R520:
2087         case CHIP_RV570:
2088         case CHIP_R580:
2089                 dev_priv->flags |= RADEON_HAS_HIERZ;
2090                 break;
2091         default:
2092                 /* all other chips have no hierarchical z buffer */
2093                 break;
2094         }
2095
2096         pci_enable_busmaster(dev->device);
2097
2098         if (drm_device_is_agp(dev))
2099                 dev_priv->flags |= RADEON_IS_AGP;
2100         else if (drm_device_is_pcie(dev))
2101                 dev_priv->flags |= RADEON_IS_PCIE;
2102         else
2103                 dev_priv->flags |= RADEON_IS_PCI;
2104
2105         ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
2106                          drm_get_resource_len(dev, 2), _DRM_REGISTERS,
2107                          _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
2108         if (ret != 0)
2109                 return ret;
2110
2111         ret = drm_vblank_init(dev, 2);
2112         if (ret) {
2113                 radeon_driver_unload(dev);
2114                 return ret;
2115         }
2116
2117         DRM_DEBUG("%s card detected\n",
2118                   ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
2119         return ret;
2120 }
2121
2122 int radeon_master_create(struct drm_device *dev, struct drm_master *master)
2123 {
2124         struct drm_radeon_master_private *master_priv;
2125         unsigned long sareapage;
2126         int ret;
2127
2128         master_priv = malloc(sizeof(*master_priv),
2129             DRM_MEM_DRIVER, M_ZERO | M_WAITOK);
2130         if (!master_priv)
2131                 return -ENOMEM;
2132
2133         /* prebuild the SAREA */
2134         sareapage = max_t(unsigned long, SAREA_MAX, PAGE_SIZE);
2135         ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK,
2136                          &master_priv->sarea);
2137         if (ret) {
2138                 DRM_ERROR("SAREA setup failed\n");
2139                 free(master_priv, DRM_MEM_DRIVER);
2140                 return ret;
2141         }
2142         master_priv->sarea_priv = (drm_radeon_sarea_t *)((char *)master_priv->sarea->handle) +
2143             sizeof(struct drm_sarea);
2144         master_priv->sarea_priv->pfCurrentPage = 0;
2145
2146         master->driver_priv = master_priv;
2147         return 0;
2148 }
2149
2150 void radeon_master_destroy(struct drm_device *dev, struct drm_master *master)
2151 {
2152         struct drm_radeon_master_private *master_priv = master->driver_priv;
2153
2154         if (!master_priv)
2155                 return;
2156
2157         if (master_priv->sarea_priv &&
2158             master_priv->sarea_priv->pfCurrentPage != 0)
2159                 radeon_cp_dispatch_flip(dev, master);
2160
2161         master_priv->sarea_priv = NULL;
2162         if (master_priv->sarea)
2163 #ifdef __linux__
2164                 drm_rmmap_locked(dev, master_priv->sarea);
2165 #else
2166                 drm_rmmap(dev, master_priv->sarea);
2167 #endif
2168
2169         free(master_priv, DRM_MEM_DRIVER);
2170
2171         master->driver_priv = NULL;
2172 }
2173
2174 /* Create mappings for registers and framebuffer so userland doesn't necessarily
2175  * have to find them.
2176  */
2177 int radeon_driver_firstopen(struct drm_device *dev)
2178 {
2179         int ret;
2180         drm_local_map_t *map;
2181         drm_radeon_private_t *dev_priv = dev->dev_private;
2182
2183         dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2184
2185         dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
2186         ret = drm_addmap(dev, dev_priv->fb_aper_offset,
2187                          drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
2188                          _DRM_WRITE_COMBINING, &map);
2189         if (ret != 0)
2190                 return ret;
2191
2192         return 0;
2193 }
2194
2195 int radeon_driver_unload(struct drm_device *dev)
2196 {
2197         drm_radeon_private_t *dev_priv = dev->dev_private;
2198
2199         DRM_DEBUG("\n");
2200
2201         drm_rmmap(dev, dev_priv->mmio);
2202
2203         free(dev_priv, DRM_MEM_DRIVER);
2204
2205         dev->dev_private = NULL;
2206         return 0;
2207 }
2208
2209 void radeon_commit_ring(drm_radeon_private_t *dev_priv)
2210 {
2211         int i;
2212         u32 *ring;
2213         int tail_aligned;
2214
2215         /* check if the ring is padded out to 16-dword alignment */
2216
2217         tail_aligned = dev_priv->ring.tail & (RADEON_RING_ALIGN-1);
2218         if (tail_aligned) {
2219                 int num_p2 = RADEON_RING_ALIGN - tail_aligned;
2220
2221                 ring = dev_priv->ring.start;
2222                 /* pad with some CP_PACKET2 */
2223                 for (i = 0; i < num_p2; i++)
2224                         ring[dev_priv->ring.tail + i] = CP_PACKET2();
2225
2226                 dev_priv->ring.tail += i;
2227
2228                 dev_priv->ring.space -= num_p2 * sizeof(u32);
2229         }
2230
2231         dev_priv->ring.tail &= dev_priv->ring.tail_mask;
2232
2233         DRM_MEMORYBARRIER();
2234         GET_RING_HEAD( dev_priv );
2235
2236         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
2237                 RADEON_WRITE(R600_CP_RB_WPTR, dev_priv->ring.tail);
2238                 /* read from PCI bus to ensure correct posting */
2239                 RADEON_READ(R600_CP_RB_RPTR);
2240         } else {
2241                 RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail);
2242                 /* read from PCI bus to ensure correct posting */
2243                 RADEON_READ(RADEON_CP_RB_RPTR);
2244         }
2245 }