sys/dev/drm2/radeon/radeon_object.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32
  33 #include <sys/cdefs.h>
  34 __FBSDID("$FreeBSD$");
  35
  36 #include <dev/drm2/drmP.h>
  37 #include <dev/drm2/radeon/radeon_drm.h>
  38 #include "radeon.h"
  39 #ifdef DUMBBELL_WIP
  40 #include "radeon_trace.h"
  41 #endif /* DUMBBELL_WIP */
  42
  43
  44 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
  45
  46 /*
  47  * To exclude mutual BO access we rely on bo_reserve exclusion, as all
  48  * function are calling it.
  49  */
  50
  51 static void radeon_bo_clear_va(struct radeon_bo *bo)
  52 {
  53         struct radeon_bo_va *bo_va, *tmp;
  54
  55         list_for_each_entry_safe(bo_va, tmp, &bo->va, bo_list) {
  56                 /* remove from all vm address space */
  57                 radeon_vm_bo_rmv(bo->rdev, bo_va);
  58         }
  59 }
  60
  61 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  62 {
  63         struct radeon_bo *bo;
  64
  65         bo = container_of(tbo, struct radeon_bo, tbo);
  66         sx_xlock(&bo->rdev->gem.mutex);
  67         list_del_init(&bo->list);
  68         sx_xunlock(&bo->rdev->gem.mutex);
  69         radeon_bo_clear_surface_reg(bo);
  70         radeon_bo_clear_va(bo);
  71         drm_gem_object_release(&bo->gem_base);
  72         free(bo, DRM_MEM_DRIVER);
  73 }
  74
  75 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
  76 {
  77         if (bo->destroy == &radeon_ttm_bo_destroy)
  78                 return true;
  79         return false;
  80 }
  81
  82 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
  83 {
  84         u32 c = 0;
  85
  86         rbo->placement.fpfn = 0;
  87         rbo->placement.lpfn = 0;
  88         rbo->placement.placement = rbo->placements;
  89         rbo->placement.busy_placement = rbo->placements;
  90         if (domain & RADEON_GEM_DOMAIN_VRAM)
  91                 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
  92                                         TTM_PL_FLAG_VRAM;
  93         if (domain & RADEON_GEM_DOMAIN_GTT) {
  94                 if (rbo->rdev->flags & RADEON_IS_AGP) {
  95                         rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT;
  96                 } else {
  97                         rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
  98                 }
  99         }
 100         if (domain & RADEON_GEM_DOMAIN_CPU) {
 101                 if (rbo->rdev->flags & RADEON_IS_AGP) {
 102                         rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_SYSTEM;
 103                 } else {
 104                         rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM;
 105                 }
 106         }
 107         if (!c)
 108                 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
 109         rbo->placement.num_placement = c;
 110         rbo->placement.num_busy_placement = c;
 111 }
 112
 113 int radeon_bo_create(struct radeon_device *rdev,
 114                      unsigned long size, int byte_align, bool kernel, u32 domain,
 115                      struct sg_table *sg, struct radeon_bo **bo_ptr)
 116 {
 117         struct radeon_bo *bo;
 118         enum ttm_bo_type type;
 119         unsigned long page_align = roundup2(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
 120         size_t acc_size;
 121         int r;
 122
 123         size = roundup2(size, PAGE_SIZE);
 124
 125         if (kernel) {
 126                 type = ttm_bo_type_kernel;
 127         } else if (sg) {
 128                 type = ttm_bo_type_sg;
 129         } else {
 130                 type = ttm_bo_type_device;
 131         }
 132         *bo_ptr = NULL;
 133
 134         acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
 135                                        sizeof(struct radeon_bo));
 136
 137         bo = malloc(sizeof(struct radeon_bo),
 138             DRM_MEM_DRIVER, M_ZERO | M_WAITOK);
 139         if (bo == NULL)
 140                 return -ENOMEM;
 141         r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
 142         if (unlikely(r)) {
 143                 free(bo, DRM_MEM_DRIVER);
 144                 return r;
 145         }
 146         bo->rdev = rdev;
 147         bo->gem_base.driver_private = NULL;
 148         bo->surface_reg = -1;
 149         INIT_LIST_HEAD(&bo->list);
 150         INIT_LIST_HEAD(&bo->va);
 151         radeon_ttm_placement_from_domain(bo, domain);
 152         /* Kernel allocation are uninterruptible */
 153         sx_slock(&rdev->pm.mclk_lock);
 154         r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
 155                         &bo->placement, page_align, !kernel, NULL,
 156                         acc_size, sg, &radeon_ttm_bo_destroy);
 157         sx_sunlock(&rdev->pm.mclk_lock);
 158         if (unlikely(r != 0)) {
 159                 return r;
 160         }
 161         *bo_ptr = bo;
 162
 163 #ifdef DUMBBELL_WIP
 164         trace_radeon_bo_create(bo);
 165 #endif /* DUMBBELL_WIP */
 166
 167         return 0;
 168 }
 169
 170 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
 171 {
 172         bool is_iomem;
 173         int r;
 174
 175         if (bo->kptr) {
 176                 if (ptr) {
 177                         *ptr = bo->kptr;
 178                 }
 179                 return 0;
 180         }
 181         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
 182         if (r) {
 183                 return r;
 184         }
 185         bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
 186         if (ptr) {
 187                 *ptr = bo->kptr;
 188         }
 189         radeon_bo_check_tiling(bo, 0, 0);
 190         return 0;
 191 }
 192
 193 void radeon_bo_kunmap(struct radeon_bo *bo)
 194 {
 195         if (bo->kptr == NULL)
 196                 return;
 197         bo->kptr = NULL;
 198         radeon_bo_check_tiling(bo, 0, 0);
 199         ttm_bo_kunmap(&bo->kmap);
 200 }
 201
 202 void radeon_bo_unref(struct radeon_bo **bo)
 203 {
 204         struct ttm_buffer_object *tbo;
 205         struct radeon_device *rdev;
 206
 207         if ((*bo) == NULL)
 208                 return;
 209         rdev = (*bo)->rdev;
 210         tbo = &((*bo)->tbo);
 211         sx_slock(&rdev->pm.mclk_lock);
 212         ttm_bo_unref(&tbo);
 213         sx_sunlock(&rdev->pm.mclk_lock);
 214         if (tbo == NULL)
 215                 *bo = NULL;
 216 }
 217
 218 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
 219                              u64 *gpu_addr)
 220 {
 221         int r, i;
 222
 223         if (bo->pin_count) {
 224                 bo->pin_count++;
 225                 if (gpu_addr)
 226                         *gpu_addr = radeon_bo_gpu_offset(bo);
 227
 228                 if (max_offset != 0) {
 229                         u64 domain_start;
 230
 231                         if (domain == RADEON_GEM_DOMAIN_VRAM)
 232                                 domain_start = bo->rdev->mc.vram_start;
 233                         else
 234                                 domain_start = bo->rdev->mc.gtt_start;
 235                         if (max_offset < (radeon_bo_gpu_offset(bo) - domain_start)) {
 236                                 DRM_ERROR("radeon_bo_pin_restricted: "
 237                                     "max_offset(%ju) < "
 238                                     "(radeon_bo_gpu_offset(%ju) - "
 239                                     "domain_start(%ju)",
 240                                     (uintmax_t)max_offset, (uintmax_t)radeon_bo_gpu_offset(bo),
 241                                     (uintmax_t)domain_start);
 242                         }
 243                 }
 244
 245                 return 0;
 246         }
 247         radeon_ttm_placement_from_domain(bo, domain);
 248         if (domain == RADEON_GEM_DOMAIN_VRAM) {
 249                 /* force to pin into visible video ram */
 250                 bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 251         }
 252         if (max_offset) {
 253                 u64 lpfn = max_offset >> PAGE_SHIFT;
 254
 255                 if (!bo->placement.lpfn)
 256                         bo->placement.lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT;
 257
 258                 if (lpfn < bo->placement.lpfn)
 259                         bo->placement.lpfn = lpfn;
 260         }
 261         for (i = 0; i < bo->placement.num_placement; i++)
 262                 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
 263         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 264         if (likely(r == 0)) {
 265                 bo->pin_count = 1;
 266                 if (gpu_addr != NULL)
 267                         *gpu_addr = radeon_bo_gpu_offset(bo);
 268         }
 269         if (unlikely(r != 0))
 270                 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
 271         return r;
 272 }
 273
 274 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
 275 {
 276         return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
 277 }
 278
 279 int radeon_bo_unpin(struct radeon_bo *bo)
 280 {
 281         int r, i;
 282
 283         if (!bo->pin_count) {
 284                 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
 285                 return 0;
 286         }
 287         bo->pin_count--;
 288         if (bo->pin_count)
 289                 return 0;
 290         for (i = 0; i < bo->placement.num_placement; i++)
 291                 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
 292         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 293         if (unlikely(r != 0))
 294                 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
 295         return r;
 296 }
 297
 298 int radeon_bo_evict_vram(struct radeon_device *rdev)
 299 {
 300         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
 301         if (0 && (rdev->flags & RADEON_IS_IGP)) {
 302                 if (rdev->mc.igp_sideport_enabled == false)
 303                         /* Useless to evict on IGP chips */
 304                         return 0;
 305         }
 306         return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
 307 }
 308
 309 void radeon_bo_force_delete(struct radeon_device *rdev)
 310 {
 311         struct radeon_bo *bo, *n;
 312
 313         if (list_empty(&rdev->gem.objects)) {
 314                 return;
 315         }
 316         dev_err(rdev->dev, "Userspace still has active objects !\n");
 317         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
 318                 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
 319                         &bo->gem_base, bo, (unsigned long)bo->gem_base.size,
 320                         *((unsigned long *)&bo->gem_base.refcount));
 321                 sx_xlock(&bo->rdev->gem.mutex);
 322                 list_del_init(&bo->list);
 323                 sx_xunlock(&bo->rdev->gem.mutex);
 324                 /* this should unref the ttm bo */
 325                 drm_gem_object_unreference(&bo->gem_base);
 326         }
 327 }
 328
 329 int radeon_bo_init(struct radeon_device *rdev)
 330 {
 331         /* Add an MTRR for the VRAM */
 332         rdev->mc.vram_mtrr = drm_mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
 333                         DRM_MTRR_WC);
 334         DRM_INFO("Detected VRAM RAM=%juM, BAR=%juM\n",
 335                 (uintmax_t)rdev->mc.mc_vram_size >> 20,
 336                 (uintmax_t)rdev->mc.aper_size >> 20);
 337         DRM_INFO("RAM width %dbits %cDR\n",
 338                         rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
 339         return radeon_ttm_init(rdev);
 340 }
 341
 342 void radeon_bo_fini(struct radeon_device *rdev)
 343 {
 344         radeon_ttm_fini(rdev);
 345 }
 346
 347 void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
 348                                 struct list_head *head)
 349 {
 350         if (lobj->wdomain) {
 351                 list_add(&lobj->tv.head, head);
 352         } else {
 353                 list_add_tail(&lobj->tv.head, head);
 354         }
 355 }
 356
 357 int radeon_bo_list_validate(struct list_head *head)
 358 {
 359         struct radeon_bo_list *lobj;
 360         struct radeon_bo *bo;
 361         u32 domain;
 362         int r;
 363
 364         r = ttm_eu_reserve_buffers(head);
 365         if (unlikely(r != 0)) {
 366                 return r;
 367         }
 368         list_for_each_entry(lobj, head, tv.head) {
 369                 bo = lobj->bo;
 370                 if (!bo->pin_count) {
 371                         domain = lobj->wdomain ? lobj->wdomain : lobj->rdomain;
 372
 373                 retry:
 374                         radeon_ttm_placement_from_domain(bo, domain);
 375                         r = ttm_bo_validate(&bo->tbo, &bo->placement,
 376                                                 true, false);
 377                         if (unlikely(r)) {
 378                                 if (r != -ERESTARTSYS && domain == RADEON_GEM_DOMAIN_VRAM) {
 379                                         domain |= RADEON_GEM_DOMAIN_GTT;
 380                                         goto retry;
 381                                 }
 382                                 return r;
 383                         }
 384                 }
 385                 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
 386                 lobj->tiling_flags = bo->tiling_flags;
 387         }
 388         return 0;
 389 }
 390
 391 #ifdef DUMBBELL_WIP
 392 int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
 393                              struct vm_area_struct *vma)
 394 {
 395         return ttm_fbdev_mmap(vma, &bo->tbo);
 396 }
 397 #endif /* DUMBBELL_WIP */
 398
 399 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
 400 {
 401         struct radeon_device *rdev = bo->rdev;
 402         struct radeon_surface_reg *reg;
 403         struct radeon_bo *old_object;
 404         int steal;
 405         int i;
 406
 407         KASSERT(radeon_bo_is_reserved(bo),
 408             ("radeon_bo_get_surface_reg: radeon_bo is not reserved"));
 409
 410         if (!bo->tiling_flags)
 411                 return 0;
 412
 413         if (bo->surface_reg >= 0) {
 414                 reg = &rdev->surface_regs[bo->surface_reg];
 415                 i = bo->surface_reg;
 416                 goto out;
 417         }
 418
 419         steal = -1;
 420         for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
 421
 422                 reg = &rdev->surface_regs[i];
 423                 if (!reg->bo)
 424                         break;
 425
 426                 old_object = reg->bo;
 427                 if (old_object->pin_count == 0)
 428                         steal = i;
 429         }
 430
 431         /* if we are all out */
 432         if (i == RADEON_GEM_MAX_SURFACES) {
 433                 if (steal == -1)
 434                         return -ENOMEM;
 435                 /* find someone with a surface reg and nuke their BO */
 436                 reg = &rdev->surface_regs[steal];
 437                 old_object = reg->bo;
 438                 /* blow away the mapping */
 439                 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
 440                 ttm_bo_unmap_virtual(&old_object->tbo);
 441                 old_object->surface_reg = -1;
 442                 i = steal;
 443         }
 444
 445         bo->surface_reg = i;
 446         reg->bo = bo;
 447
 448 out:
 449         radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
 450                                bo->tbo.mem.start << PAGE_SHIFT,
 451                                bo->tbo.num_pages << PAGE_SHIFT);
 452         return 0;
 453 }
 454
 455 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
 456 {
 457         struct radeon_device *rdev = bo->rdev;
 458         struct radeon_surface_reg *reg;
 459
 460         if (bo->surface_reg == -1)
 461                 return;
 462
 463         reg = &rdev->surface_regs[bo->surface_reg];
 464         radeon_clear_surface_reg(rdev, bo->surface_reg);
 465
 466         reg->bo = NULL;
 467         bo->surface_reg = -1;
 468 }
 469
 470 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
 471                                 uint32_t tiling_flags, uint32_t pitch)
 472 {
 473         struct radeon_device *rdev = bo->rdev;
 474         int r;
 475
 476         if (rdev->family >= CHIP_CEDAR) {
 477                 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
 478
 479                 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
 480                 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
 481                 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
 482                 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
 483                 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
 484                 switch (bankw) {
 485                 case 0:
 486                 case 1:
 487                 case 2:
 488                 case 4:
 489                 case 8:
 490                         break;
 491                 default:
 492                         return -EINVAL;
 493                 }
 494                 switch (bankh) {
 495                 case 0:
 496                 case 1:
 497                 case 2:
 498                 case 4:
 499                 case 8:
 500                         break;
 501                 default:
 502                         return -EINVAL;
 503                 }
 504                 switch (mtaspect) {
 505                 case 0:
 506                 case 1:
 507                 case 2:
 508                 case 4:
 509                 case 8:
 510                         break;
 511                 default:
 512                         return -EINVAL;
 513                 }
 514                 if (tilesplit > 6) {
 515                         return -EINVAL;
 516                 }
 517                 if (stilesplit > 6) {
 518                         return -EINVAL;
 519                 }
 520         }
 521         r = radeon_bo_reserve(bo, false);
 522         if (unlikely(r != 0))
 523                 return r;
 524         bo->tiling_flags = tiling_flags;
 525         bo->pitch = pitch;
 526         radeon_bo_unreserve(bo);
 527         return 0;
 528 }
 529
 530 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
 531                                 uint32_t *tiling_flags,
 532                                 uint32_t *pitch)
 533 {
 534         KASSERT(radeon_bo_is_reserved(bo),
 535             ("radeon_bo_get_tiling_flags: radeon_bo is not reserved"));
 536         if (tiling_flags)
 537                 *tiling_flags = bo->tiling_flags;
 538         if (pitch)
 539                 *pitch = bo->pitch;
 540 }
 541
 542 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
 543                                 bool force_drop)
 544 {
 545         KASSERT((radeon_bo_is_reserved(bo) || force_drop),
 546             ("radeon_bo_check_tiling: radeon_bo is not reserved && !force_drop"));
 547
 548         if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
 549                 return 0;
 550
 551         if (force_drop) {
 552                 radeon_bo_clear_surface_reg(bo);
 553                 return 0;
 554         }
 555
 556         if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
 557                 if (!has_moved)
 558                         return 0;
 559
 560                 if (bo->surface_reg >= 0)
 561                         radeon_bo_clear_surface_reg(bo);
 562                 return 0;
 563         }
 564
 565         if ((bo->surface_reg >= 0) && !has_moved)
 566                 return 0;
 567
 568         return radeon_bo_get_surface_reg(bo);
 569 }
 570
 571 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
 572                            struct ttm_mem_reg *mem)
 573 {
 574         struct radeon_bo *rbo;
 575         if (!radeon_ttm_bo_is_radeon_bo(bo))
 576                 return;
 577         rbo = container_of(bo, struct radeon_bo, tbo);
 578         radeon_bo_check_tiling(rbo, 0, 1);
 579         radeon_vm_bo_invalidate(rbo->rdev, rbo);
 580 }
 581
 582 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 583 {
 584         struct radeon_device *rdev;
 585         struct radeon_bo *rbo;
 586         unsigned long offset, size;
 587         int r;
 588
 589         if (!radeon_ttm_bo_is_radeon_bo(bo))
 590                 return 0;
 591         rbo = container_of(bo, struct radeon_bo, tbo);
 592         radeon_bo_check_tiling(rbo, 0, 0);
 593         rdev = rbo->rdev;
 594         if (bo->mem.mem_type == TTM_PL_VRAM) {
 595                 size = bo->mem.num_pages << PAGE_SHIFT;
 596                 offset = bo->mem.start << PAGE_SHIFT;
 597                 if ((offset + size) > rdev->mc.visible_vram_size) {
 598                         /* hurrah the memory is not visible ! */
 599                         radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
 600                         rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
 601                         r = ttm_bo_validate(bo, &rbo->placement, false, false);
 602                         if (unlikely(r != 0))
 603                                 return r;
 604                         offset = bo->mem.start << PAGE_SHIFT;
 605                         /* this should not happen */
 606                         if ((offset + size) > rdev->mc.visible_vram_size)
 607                                 return -EINVAL;
 608                 }
 609         }
 610         return 0;
 611 }
 612
 613 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
 614 {
 615         int r;
 616
 617         r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
 618         if (unlikely(r != 0))
 619                 return r;
 620         mtx_lock(&bo->tbo.bdev->fence_lock);
 621         if (mem_type)
 622                 *mem_type = bo->tbo.mem.mem_type;
 623         if (bo->tbo.sync_obj)
 624                 r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
 625         mtx_unlock(&bo->tbo.bdev->fence_lock);
 626         ttm_bo_unreserve(&bo->tbo);
 627         return r;
 628 }
 629
 630
 631 /**
 632  * radeon_bo_reserve - reserve bo
 633  * @bo:         bo structure
 634  * @no_intr:    don't return -ERESTARTSYS on pending signal
 635  *
 636  * Returns:
 637  * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
 638  * a signal. Release all buffer reservations and return to user-space.
 639  */
 640 int radeon_bo_reserve(struct radeon_bo *bo, bool no_intr)
 641 {
 642         int r;
 643
 644         r = ttm_bo_reserve(&bo->tbo, !no_intr, false, false, 0);
 645         if (unlikely(r != 0)) {
 646                 if (r != -ERESTARTSYS)
 647                         dev_err(bo->rdev->dev, "%p reserve failed\n", bo);
 648                 return r;
 649         }
 650         return 0;
 651 }