sys/dev/drm2/radeon/radeon_pm.c

   1 /*
   2  * Permission is hereby granted, free of charge, to any person obtaining a
   3  * copy of this software and associated documentation files (the "Software"),
   4  * to deal in the Software without restriction, including without limitation
   5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   6  * and/or sell copies of the Software, and to permit persons to whom the
   7  * Software is furnished to do so, subject to the following conditions:
   8  *
   9  * The above copyright notice and this permission notice shall be included in
  10  * all copies or substantial portions of the Software.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18  * OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * Authors: Rafał Miłecki <zajec5@gmail.com>
  21  *          Alex Deucher <alexdeucher@gmail.com>
  22  */
  23
  24 #include <sys/cdefs.h>
  25 __FBSDID("$FreeBSD$");
  26
  27 #include <dev/drm2/drmP.h>
  28 #include "radeon.h"
  29 #include "avivod.h"
  30 #include "atom.h"
  31
  32 #define RADEON_IDLE_LOOP_MS 100
  33 #define RADEON_RECLOCK_DELAY_MS 200
  34 #define RADEON_WAIT_VBLANK_TIMEOUT 200
  35
  36 static const char *radeon_pm_state_type_name[5] = {
  37         "",
  38         "Powersave",
  39         "Battery",
  40         "Balanced",
  41         "Performance",
  42 };
  43
  44 #ifdef DUMBBELL_WIP
  45 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
  46 #endif /* DUMBBELL_WIP */
  47 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
  48 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
  49 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
  50 static void radeon_pm_update_profile(struct radeon_device *rdev);
  51 static void radeon_pm_set_clocks(struct radeon_device *rdev);
  52
  53 int radeon_pm_get_type_index(struct radeon_device *rdev,
  54                              enum radeon_pm_state_type ps_type,
  55                              int instance)
  56 {
  57         int i;
  58         int found_instance = -1;
  59
  60         for (i = 0; i < rdev->pm.num_power_states; i++) {
  61                 if (rdev->pm.power_state[i].type == ps_type) {
  62                         found_instance++;
  63                         if (found_instance == instance)
  64                                 return i;
  65                 }
  66         }
  67         /* return default if no match */
  68         return rdev->pm.default_power_state_index;
  69 }
  70
  71 void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
  72 {
  73         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
  74                 if (rdev->pm.profile == PM_PROFILE_AUTO) {
  75                         sx_xlock(&rdev->pm.mutex);
  76                         radeon_pm_update_profile(rdev);
  77                         radeon_pm_set_clocks(rdev);
  78                         sx_xunlock(&rdev->pm.mutex);
  79                 }
  80         }
  81 }
  82
  83 static void radeon_pm_update_profile(struct radeon_device *rdev)
  84 {
  85         switch (rdev->pm.profile) {
  86         case PM_PROFILE_DEFAULT:
  87                 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
  88                 break;
  89         case PM_PROFILE_AUTO:
  90 #ifdef DUMBBELL_WIP
  91                 if (power_supply_is_system_supplied() > 0) {
  92                         if (rdev->pm.active_crtc_count > 1)
  93                                 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
  94                         else
  95                                 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
  96                 } else {
  97                         if (rdev->pm.active_crtc_count > 1)
  98                                 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
  99                         else
 100                                 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
 101                 }
 102 #endif /* DUMBBELL_WIP */
 103                 break;
 104         case PM_PROFILE_LOW:
 105                 if (rdev->pm.active_crtc_count > 1)
 106                         rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
 107                 else
 108                         rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
 109                 break;
 110         case PM_PROFILE_MID:
 111                 if (rdev->pm.active_crtc_count > 1)
 112                         rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
 113                 else
 114                         rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
 115                 break;
 116         case PM_PROFILE_HIGH:
 117                 if (rdev->pm.active_crtc_count > 1)
 118                         rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
 119                 else
 120                         rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
 121                 break;
 122         }
 123
 124         if (rdev->pm.active_crtc_count == 0) {
 125                 rdev->pm.requested_power_state_index =
 126                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
 127                 rdev->pm.requested_clock_mode_index =
 128                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
 129         } else {
 130                 rdev->pm.requested_power_state_index =
 131                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
 132                 rdev->pm.requested_clock_mode_index =
 133                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
 134         }
 135 }
 136
 137 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
 138 {
 139         struct radeon_bo *bo, *n;
 140
 141         if (list_empty(&rdev->gem.objects))
 142                 return;
 143
 144         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
 145                 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
 146                         ttm_bo_unmap_virtual(&bo->tbo);
 147         }
 148 }
 149
 150 static void radeon_sync_with_vblank(struct radeon_device *rdev)
 151 {
 152         if (rdev->pm.active_crtcs) {
 153                 rdev->pm.vblank_sync = false;
 154 #ifdef DUMBBELL_WIP
 155                 wait_event_timeout(
 156                         rdev->irq.vblank_queue, rdev->pm.vblank_sync,
 157                         msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
 158 #endif /* DUMBBELL_WIP */
 159         }
 160 }
 161
 162 static void radeon_set_power_state(struct radeon_device *rdev)
 163 {
 164         u32 sclk, mclk;
 165         bool misc_after = false;
 166
 167         if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
 168             (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
 169                 return;
 170
 171         if (radeon_gui_idle(rdev)) {
 172                 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 173                         clock_info[rdev->pm.requested_clock_mode_index].sclk;
 174                 if (sclk > rdev->pm.default_sclk)
 175                         sclk = rdev->pm.default_sclk;
 176
 177                 /* starting with BTC, there is one state that is used for both
 178                  * MH and SH.  Difference is that we always use the high clock index for
 179                  * mclk.
 180                  */
 181                 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
 182                     (rdev->family >= CHIP_BARTS) &&
 183                     rdev->pm.active_crtc_count &&
 184                     ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
 185                      (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
 186                         mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 187                                 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
 188                 else
 189                         mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 190                                 clock_info[rdev->pm.requested_clock_mode_index].mclk;
 191
 192                 if (mclk > rdev->pm.default_mclk)
 193                         mclk = rdev->pm.default_mclk;
 194
 195                 /* upvolt before raising clocks, downvolt after lowering clocks */
 196                 if (sclk < rdev->pm.current_sclk)
 197                         misc_after = true;
 198
 199                 radeon_sync_with_vblank(rdev);
 200
 201                 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 202                         if (!radeon_pm_in_vbl(rdev))
 203                                 return;
 204                 }
 205
 206                 radeon_pm_prepare(rdev);
 207
 208                 if (!misc_after)
 209                         /* voltage, pcie lanes, etc.*/
 210                         radeon_pm_misc(rdev);
 211
 212                 /* set engine clock */
 213                 if (sclk != rdev->pm.current_sclk) {
 214                         radeon_pm_debug_check_in_vbl(rdev, false);
 215                         radeon_set_engine_clock(rdev, sclk);
 216                         radeon_pm_debug_check_in_vbl(rdev, true);
 217                         rdev->pm.current_sclk = sclk;
 218                         DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
 219                 }
 220
 221                 /* set memory clock */
 222                 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
 223                         radeon_pm_debug_check_in_vbl(rdev, false);
 224                         radeon_set_memory_clock(rdev, mclk);
 225                         radeon_pm_debug_check_in_vbl(rdev, true);
 226                         rdev->pm.current_mclk = mclk;
 227                         DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
 228                 }
 229
 230                 if (misc_after)
 231                         /* voltage, pcie lanes, etc.*/
 232                         radeon_pm_misc(rdev);
 233
 234                 radeon_pm_finish(rdev);
 235
 236                 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
 237                 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
 238         } else
 239                 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
 240 }
 241
 242 static void radeon_pm_set_clocks(struct radeon_device *rdev)
 243 {
 244         int i, r;
 245
 246         /* no need to take locks, etc. if nothing's going to change */
 247         if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
 248             (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
 249                 return;
 250
 251         DRM_LOCK(rdev->ddev);
 252         sx_xlock(&rdev->pm.mclk_lock);
 253         sx_xlock(&rdev->ring_lock);
 254
 255         /* wait for the rings to drain */
 256         for (i = 0; i < RADEON_NUM_RINGS; i++) {
 257                 struct radeon_ring *ring = &rdev->ring[i];
 258                 if (!ring->ready) {
 259                         continue;
 260                 }
 261                 r = radeon_fence_wait_empty_locked(rdev, i);
 262                 if (r) {
 263                         /* needs a GPU reset dont reset here */
 264                         sx_xunlock(&rdev->ring_lock);
 265                         sx_xunlock(&rdev->pm.mclk_lock);
 266                         DRM_UNLOCK(rdev->ddev);
 267                         return;
 268                 }
 269         }
 270
 271         radeon_unmap_vram_bos(rdev);
 272
 273         if (rdev->irq.installed) {
 274                 for (i = 0; i < rdev->num_crtc; i++) {
 275                         if (rdev->pm.active_crtcs & (1 << i)) {
 276                                 rdev->pm.req_vblank |= (1 << i);
 277                                 drm_vblank_get(rdev->ddev, i);
 278                         }
 279                 }
 280         }
 281
 282         radeon_set_power_state(rdev);
 283
 284         if (rdev->irq.installed) {
 285                 for (i = 0; i < rdev->num_crtc; i++) {
 286                         if (rdev->pm.req_vblank & (1 << i)) {
 287                                 rdev->pm.req_vblank &= ~(1 << i);
 288                                 drm_vblank_put(rdev->ddev, i);
 289                         }
 290                 }
 291         }
 292
 293         /* update display watermarks based on new power state */
 294         radeon_update_bandwidth_info(rdev);
 295         if (rdev->pm.active_crtc_count)
 296                 radeon_bandwidth_update(rdev);
 297
 298         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 299
 300         sx_xunlock(&rdev->ring_lock);
 301         sx_xunlock(&rdev->pm.mclk_lock);
 302         DRM_UNLOCK(rdev->ddev);
 303 }
 304
 305 static void radeon_pm_print_states(struct radeon_device *rdev)
 306 {
 307         int i, j;
 308         struct radeon_power_state *power_state;
 309         struct radeon_pm_clock_info *clock_info;
 310
 311         DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
 312         for (i = 0; i < rdev->pm.num_power_states; i++) {
 313                 power_state = &rdev->pm.power_state[i];
 314                 DRM_DEBUG_DRIVER("State %d: %s\n", i,
 315                         radeon_pm_state_type_name[power_state->type]);
 316                 if (i == rdev->pm.default_power_state_index)
 317                         DRM_DEBUG_DRIVER("\tDefault");
 318                 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
 319                         DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
 320                 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 321                         DRM_DEBUG_DRIVER("\tSingle display only\n");
 322                 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
 323                 for (j = 0; j < power_state->num_clock_modes; j++) {
 324                         clock_info = &(power_state->clock_info[j]);
 325                         if (rdev->flags & RADEON_IS_IGP)
 326                                 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
 327                                                  j,
 328                                                  clock_info->sclk * 10);
 329                         else
 330                                 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
 331                                                  j,
 332                                                  clock_info->sclk * 10,
 333                                                  clock_info->mclk * 10,
 334                                                  clock_info->voltage.voltage);
 335                 }
 336         }
 337 }
 338
 339 #ifdef DUMBBELL_WIP
 340 static ssize_t radeon_get_pm_profile(struct device *dev,
 341                                      struct device_attribute *attr,
 342                                      char *buf)
 343 {
 344         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 345         struct radeon_device *rdev = ddev->dev_private;
 346         int cp = rdev->pm.profile;
 347
 348         return snprintf(buf, PAGE_SIZE, "%s\n",
 349                         (cp == PM_PROFILE_AUTO) ? "auto" :
 350                         (cp == PM_PROFILE_LOW) ? "low" :
 351                         (cp == PM_PROFILE_MID) ? "mid" :
 352                         (cp == PM_PROFILE_HIGH) ? "high" : "default");
 353 }
 354
 355 static ssize_t radeon_set_pm_profile(struct device *dev,
 356                                      struct device_attribute *attr,
 357                                      const char *buf,
 358                                      size_t count)
 359 {
 360         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 361         struct radeon_device *rdev = ddev->dev_private;
 362
 363         sx_xlock(&rdev->pm.mutex);
 364         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 365                 if (strncmp("default", buf, strlen("default")) == 0)
 366                         rdev->pm.profile = PM_PROFILE_DEFAULT;
 367                 else if (strncmp("auto", buf, strlen("auto")) == 0)
 368                         rdev->pm.profile = PM_PROFILE_AUTO;
 369                 else if (strncmp("low", buf, strlen("low")) == 0)
 370                         rdev->pm.profile = PM_PROFILE_LOW;
 371                 else if (strncmp("mid", buf, strlen("mid")) == 0)
 372                         rdev->pm.profile = PM_PROFILE_MID;
 373                 else if (strncmp("high", buf, strlen("high")) == 0)
 374                         rdev->pm.profile = PM_PROFILE_HIGH;
 375                 else {
 376                         count = -EINVAL;
 377                         goto fail;
 378                 }
 379                 radeon_pm_update_profile(rdev);
 380                 radeon_pm_set_clocks(rdev);
 381         } else
 382                 count = -EINVAL;
 383
 384 fail:
 385         sx_xunlock(&rdev->pm.mutex);
 386
 387         return count;
 388 }
 389
 390 static ssize_t radeon_get_pm_method(struct device *dev,
 391                                     struct device_attribute *attr,
 392                                     char *buf)
 393 {
 394         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 395         struct radeon_device *rdev = ddev->dev_private;
 396         int pm = rdev->pm.pm_method;
 397
 398         return snprintf(buf, PAGE_SIZE, "%s\n",
 399                         (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile");
 400 }
 401
 402 static ssize_t radeon_set_pm_method(struct device *dev,
 403                                     struct device_attribute *attr,
 404                                     const char *buf,
 405                                     size_t count)
 406 {
 407         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 408         struct radeon_device *rdev = ddev->dev_private;
 409
 410
 411         if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
 412                 sx_xlock(&rdev->pm.mutex);
 413                 rdev->pm.pm_method = PM_METHOD_DYNPM;
 414                 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
 415                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 416                 sx_xunlock(&rdev->pm.mutex);
 417         } else if (strncmp("profile", buf, strlen("profile")) == 0) {
 418                 sx_xlock(&rdev->pm.mutex);
 419                 /* disable dynpm */
 420                 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 421                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 422                 rdev->pm.pm_method = PM_METHOD_PROFILE;
 423                 sx_xunlock(&rdev->pm.mutex);
 424 #ifdef DUMBBELL_WIP
 425                 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
 426 #endif /* DUMBBELL_WIP */
 427         } else {
 428                 count = -EINVAL;
 429                 goto fail;
 430         }
 431         radeon_pm_compute_clocks(rdev);
 432 fail:
 433         return count;
 434 }
 435
 436 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
 437 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
 438
 439 static ssize_t radeon_hwmon_show_temp(struct device *dev,
 440                                       struct device_attribute *attr,
 441                                       char *buf)
 442 {
 443         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 444         struct radeon_device *rdev = ddev->dev_private;
 445         int temp;
 446
 447         switch (rdev->pm.int_thermal_type) {
 448         case THERMAL_TYPE_RV6XX:
 449                 temp = rv6xx_get_temp(rdev);
 450                 break;
 451         case THERMAL_TYPE_RV770:
 452                 temp = rv770_get_temp(rdev);
 453                 break;
 454         case THERMAL_TYPE_EVERGREEN:
 455         case THERMAL_TYPE_NI:
 456                 temp = evergreen_get_temp(rdev);
 457                 break;
 458         case THERMAL_TYPE_SUMO:
 459                 temp = sumo_get_temp(rdev);
 460                 break;
 461         case THERMAL_TYPE_SI:
 462                 temp = si_get_temp(rdev);
 463                 break;
 464         default:
 465                 temp = 0;
 466                 break;
 467         }
 468
 469         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 470 }
 471
 472 static ssize_t radeon_hwmon_show_name(struct device *dev,
 473                                       struct device_attribute *attr,
 474                                       char *buf)
 475 {
 476         return sprintf(buf, "radeon\n");
 477 }
 478
 479 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
 480 static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
 481
 482 static struct attribute *hwmon_attributes[] = {
 483         &sensor_dev_attr_temp1_input.dev_attr.attr,
 484         &sensor_dev_attr_name.dev_attr.attr,
 485         NULL
 486 };
 487
 488 static const struct attribute_group hwmon_attrgroup = {
 489         .attrs = hwmon_attributes,
 490 };
 491 #endif /* DUMBBELL_WIP */
 492
 493 static int radeon_hwmon_init(struct radeon_device *rdev)
 494 {
 495         int err = 0;
 496
 497 #ifdef DUMBBELL_WIP
 498         rdev->pm.int_hwmon_dev = NULL;
 499 #endif /* DUMBBELL_WIP */
 500
 501         switch (rdev->pm.int_thermal_type) {
 502         case THERMAL_TYPE_RV6XX:
 503         case THERMAL_TYPE_RV770:
 504         case THERMAL_TYPE_EVERGREEN:
 505         case THERMAL_TYPE_NI:
 506         case THERMAL_TYPE_SUMO:
 507         case THERMAL_TYPE_SI:
 508                 /* No support for TN yet */
 509                 if (rdev->family == CHIP_ARUBA)
 510                         return err;
 511 #ifdef DUMBBELL_WIP
 512                 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
 513                 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
 514                         err = PTR_ERR(rdev->pm.int_hwmon_dev);
 515                         dev_err(rdev->dev,
 516                                 "Unable to register hwmon device: %d\n", err);
 517                         break;
 518                 }
 519                 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
 520                 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
 521                                          &hwmon_attrgroup);
 522                 if (err) {
 523                         dev_err(rdev->dev,
 524                                 "Unable to create hwmon sysfs file: %d\n", err);
 525                         hwmon_device_unregister(rdev->dev);
 526                 }
 527 #endif /* DUMBBELL_WIP */
 528                 break;
 529         default:
 530                 break;
 531         }
 532
 533         return err;
 534 }
 535
 536 static void radeon_hwmon_fini(struct radeon_device *rdev)
 537 {
 538 #ifdef DUMBBELL_WIP
 539         if (rdev->pm.int_hwmon_dev) {
 540                 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup);
 541                 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
 542         }
 543 #endif /* DUMBBELL_WIP */
 544 }
 545
 546 void radeon_pm_suspend(struct radeon_device *rdev)
 547 {
 548         sx_xlock(&rdev->pm.mutex);
 549         if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 550                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
 551                         rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
 552         }
 553         sx_xunlock(&rdev->pm.mutex);
 554
 555 #ifdef DUMBBELL_WIP
 556         cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
 557 #endif /* DUMBBELL_WIP */
 558 }
 559
 560 void radeon_pm_resume(struct radeon_device *rdev)
 561 {
 562         /* set up the default clocks if the MC ucode is loaded */
 563         if ((rdev->family >= CHIP_BARTS) &&
 564             (rdev->family <= CHIP_CAYMAN) &&
 565             rdev->mc_fw) {
 566                 if (rdev->pm.default_vddc)
 567                         radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
 568                                                 SET_VOLTAGE_TYPE_ASIC_VDDC);
 569                 if (rdev->pm.default_vddci)
 570                         radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
 571                                                 SET_VOLTAGE_TYPE_ASIC_VDDCI);
 572                 if (rdev->pm.default_sclk)
 573                         radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
 574                 if (rdev->pm.default_mclk)
 575                         radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
 576         }
 577         /* asic init will reset the default power state */
 578         sx_xlock(&rdev->pm.mutex);
 579         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
 580         rdev->pm.current_clock_mode_index = 0;
 581         rdev->pm.current_sclk = rdev->pm.default_sclk;
 582         rdev->pm.current_mclk = rdev->pm.default_mclk;
 583         rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
 584         rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
 585         if (rdev->pm.pm_method == PM_METHOD_DYNPM
 586             && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
 587                 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 588 #ifdef DUMBBELL_WIP
 589                 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
 590                                       msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 591 #endif /* DUMBBELL_WIP */
 592         }
 593         sx_xunlock(&rdev->pm.mutex);
 594         radeon_pm_compute_clocks(rdev);
 595 }
 596
 597 int radeon_pm_init(struct radeon_device *rdev)
 598 {
 599         int ret;
 600
 601         /* default to profile method */
 602         rdev->pm.pm_method = PM_METHOD_PROFILE;
 603         rdev->pm.profile = PM_PROFILE_DEFAULT;
 604         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 605         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 606         rdev->pm.dynpm_can_upclock = true;
 607         rdev->pm.dynpm_can_downclock = true;
 608         rdev->pm.default_sclk = rdev->clock.default_sclk;
 609         rdev->pm.default_mclk = rdev->clock.default_mclk;
 610         rdev->pm.current_sclk = rdev->clock.default_sclk;
 611         rdev->pm.current_mclk = rdev->clock.default_mclk;
 612         rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
 613
 614         if (rdev->bios) {
 615                 if (rdev->is_atom_bios)
 616                         radeon_atombios_get_power_modes(rdev);
 617                 else
 618                         radeon_combios_get_power_modes(rdev);
 619                 radeon_pm_print_states(rdev);
 620                 radeon_pm_init_profile(rdev);
 621                 /* set up the default clocks if the MC ucode is loaded */
 622                 if ((rdev->family >= CHIP_BARTS) &&
 623                     (rdev->family <= CHIP_CAYMAN) &&
 624                     rdev->mc_fw) {
 625                         if (rdev->pm.default_vddc)
 626                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
 627                                                         SET_VOLTAGE_TYPE_ASIC_VDDC);
 628                         if (rdev->pm.default_vddci)
 629                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
 630                                                         SET_VOLTAGE_TYPE_ASIC_VDDCI);
 631                         if (rdev->pm.default_sclk)
 632                                 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
 633                         if (rdev->pm.default_mclk)
 634                                 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
 635                 }
 636         }
 637
 638         /* set up the internal thermal sensor if applicable */
 639         ret = radeon_hwmon_init(rdev);
 640         if (ret)
 641                 return ret;
 642
 643 #ifdef DUMBBELL_WIP
 644         INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
 645 #endif /* DUMBBELL_WIP */
 646
 647         if (rdev->pm.num_power_states > 1) {
 648                 /* where's the best place to put these? */
 649 #ifdef DUMBBELL_WIP
 650                 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
 651 #endif /* DUMBBELL_WIP */
 652                 if (ret)
 653                         DRM_ERROR("failed to create device file for power profile\n");
 654 #ifdef DUMBBELL_WIP
 655                 ret = device_create_file(rdev->dev, &dev_attr_power_method);
 656 #endif /* DUMBBELL_WIP */
 657                 if (ret)
 658                         DRM_ERROR("failed to create device file for power method\n");
 659
 660                 if (radeon_debugfs_pm_init(rdev)) {
 661                         DRM_ERROR("Failed to register debugfs file for PM!\n");
 662                 }
 663
 664                 DRM_INFO("radeon: power management initialized\n");
 665         }
 666
 667         return 0;
 668 }
 669
 670 void radeon_pm_fini(struct radeon_device *rdev)
 671 {
 672         if (rdev->pm.num_power_states > 1) {
 673                 DRM_UNLOCK(rdev->ddev); /* Work around LOR. */
 674                 sx_xlock(&rdev->pm.mutex);
 675                 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 676                         rdev->pm.profile = PM_PROFILE_DEFAULT;
 677                         radeon_pm_update_profile(rdev);
 678                         radeon_pm_set_clocks(rdev);
 679                 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 680                         /* reset default clocks */
 681                         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 682                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 683                         radeon_pm_set_clocks(rdev);
 684                 }
 685                 sx_xunlock(&rdev->pm.mutex);
 686                 DRM_LOCK(rdev->ddev);
 687
 688 #ifdef DUMBBELL_WIP
 689                 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
 690
 691                 device_remove_file(rdev->dev, &dev_attr_power_profile);
 692                 device_remove_file(rdev->dev, &dev_attr_power_method);
 693 #endif /* DUMBBELL_WIP */
 694         }
 695
 696         if (rdev->pm.power_state) {
 697                 int i;
 698                 for (i = 0; i < rdev->pm.num_power_states; ++i) {
 699                         free(rdev->pm.power_state[i].clock_info, DRM_MEM_DRIVER);
 700                 }
 701                 free(rdev->pm.power_state, DRM_MEM_DRIVER);
 702                 rdev->pm.power_state = NULL;
 703                 rdev->pm.num_power_states = 0;
 704         }
 705
 706         radeon_hwmon_fini(rdev);
 707 }
 708
 709 void radeon_pm_compute_clocks(struct radeon_device *rdev)
 710 {
 711         struct drm_device *ddev = rdev->ddev;
 712         struct drm_crtc *crtc;
 713         struct radeon_crtc *radeon_crtc;
 714
 715         if (rdev->pm.num_power_states < 2)
 716                 return;
 717
 718         sx_xlock(&rdev->pm.mutex);
 719
 720         rdev->pm.active_crtcs = 0;
 721         rdev->pm.active_crtc_count = 0;
 722         list_for_each_entry(crtc,
 723                 &ddev->mode_config.crtc_list, head) {
 724                 radeon_crtc = to_radeon_crtc(crtc);
 725                 if (radeon_crtc->enabled) {
 726                         rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
 727                         rdev->pm.active_crtc_count++;
 728                 }
 729         }
 730
 731         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 732                 radeon_pm_update_profile(rdev);
 733                 radeon_pm_set_clocks(rdev);
 734         } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 735                 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
 736                         if (rdev->pm.active_crtc_count > 1) {
 737                                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
 738 #ifdef DUMBBELL_WIP
 739                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 740 #endif /* DUMBBELL_WIP */
 741
 742                                         rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
 743                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 744                                         radeon_pm_get_dynpm_state(rdev);
 745                                         radeon_pm_set_clocks(rdev);
 746
 747                                         DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
 748                                 }
 749                         } else if (rdev->pm.active_crtc_count == 1) {
 750                                 /* TODO: Increase clocks if needed for current mode */
 751
 752                                 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
 753                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 754                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
 755                                         radeon_pm_get_dynpm_state(rdev);
 756                                         radeon_pm_set_clocks(rdev);
 757
 758 #ifdef DUMBBELL_WIP
 759                                         schedule_delayed_work(&rdev->pm.dynpm_idle_work,
 760                                                               msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 761 #endif /* DUMBBELL_WIP */
 762                                 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
 763                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 764 #ifdef DUMBBELL_WIP
 765                                         schedule_delayed_work(&rdev->pm.dynpm_idle_work,
 766                                                               msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 767 #endif /* DUMBBELL_WIP */
 768                                         DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
 769                                 }
 770                         } else { /* count == 0 */
 771                                 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
 772 #ifdef DUMBBELL_WIP
 773                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 774 #endif /* DUMBBELL_WIP */
 775
 776                                         rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
 777                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
 778                                         radeon_pm_get_dynpm_state(rdev);
 779                                         radeon_pm_set_clocks(rdev);
 780                                 }
 781                         }
 782                 }
 783         }
 784
 785         sx_xunlock(&rdev->pm.mutex);
 786 }
 787
 788 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
 789 {
 790         int  crtc, vpos, hpos, vbl_status;
 791         bool in_vbl = true;
 792
 793         /* Iterate over all active crtc's. All crtc's must be in vblank,
 794          * otherwise return in_vbl == false.
 795          */
 796         for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
 797                 if (rdev->pm.active_crtcs & (1 << crtc)) {
 798                         vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos);
 799                         if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
 800                             !(vbl_status & DRM_SCANOUTPOS_INVBL))
 801                                 in_vbl = false;
 802                 }
 803         }
 804
 805         return in_vbl;
 806 }
 807
 808 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
 809 {
 810         u32 stat_crtc = 0;
 811         bool in_vbl = radeon_pm_in_vbl(rdev);
 812
 813         if (in_vbl == false)
 814                 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
 815                          finish ? "exit" : "entry");
 816         return in_vbl;
 817 }
 818
 819 #ifdef DUMBBELL_WIP
 820 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
 821 {
 822         struct radeon_device *rdev;
 823         int resched;
 824         rdev = container_of(work, struct radeon_device,
 825                                 pm.dynpm_idle_work.work);
 826
 827         resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
 828         sx_xlock(&rdev->pm.mutex);
 829         if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
 830                 int not_processed = 0;
 831                 int i;
 832
 833                 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 834                         struct radeon_ring *ring = &rdev->ring[i];
 835
 836                         if (ring->ready) {
 837                                 not_processed += radeon_fence_count_emitted(rdev, i);
 838                                 if (not_processed >= 3)
 839                                         break;
 840                         }
 841                 }
 842
 843                 if (not_processed >= 3) { /* should upclock */
 844                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
 845                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 846                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
 847                                    rdev->pm.dynpm_can_upclock) {
 848                                 rdev->pm.dynpm_planned_action =
 849                                         DYNPM_ACTION_UPCLOCK;
 850                                 rdev->pm.dynpm_action_timeout = jiffies +
 851                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 852                         }
 853                 } else if (not_processed == 0) { /* should downclock */
 854                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
 855                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 856                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
 857                                    rdev->pm.dynpm_can_downclock) {
 858                                 rdev->pm.dynpm_planned_action =
 859                                         DYNPM_ACTION_DOWNCLOCK;
 860                                 rdev->pm.dynpm_action_timeout = jiffies +
 861                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 862                         }
 863                 }
 864
 865                 /* Note, radeon_pm_set_clocks is called with static_switch set
 866                  * to false since we want to wait for vbl to avoid flicker.
 867                  */
 868                 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
 869                     jiffies > rdev->pm.dynpm_action_timeout) {
 870                         radeon_pm_get_dynpm_state(rdev);
 871                         radeon_pm_set_clocks(rdev);
 872                 }
 873
 874                 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
 875                                       msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 876         }
 877         sx_xunlock(&rdev->pm.mutex);
 878         ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
 879 }
 880 #endif /* DUMBBELL_WIP */
 881
 882 /*
 883  * Debugfs info
 884  */
 885 #if defined(CONFIG_DEBUG_FS)
 886
 887 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
 888 {
 889         struct drm_info_node *node = (struct drm_info_node *) m->private;
 890         struct drm_device *dev = node->minor->dev;
 891         struct radeon_device *rdev = dev->dev_private;
 892
 893         seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
 894         seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
 895         seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
 896         if (rdev->asic->pm.get_memory_clock)
 897                 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
 898         if (rdev->pm.current_vddc)
 899                 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
 900         if (rdev->asic->pm.get_pcie_lanes)
 901                 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
 902
 903         return 0;
 904 }
 905
 906 static struct drm_info_list radeon_pm_info_list[] = {
 907         {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
 908 };
 909 #endif
 910
 911 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
 912 {
 913 #if defined(CONFIG_DEBUG_FS)
 914         return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
 915 #else
 916         return 0;
 917 #endif
 918 }