2 * Copyright (c) 2011 Aleksandr Rybalko.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #ifndef __AR8X16_SWITCHREG_H__
30 #define __AR8X16_SWITCHREG_H__
32 /* XXX doesn't belong here; stolen shamelessly from ath_hal/ah_internal.h */
34 * Register manipulation macros that expect bit field defines
35 * to follow the convention that an _S suffix is appended for
36 * a shift count, while the field mask has no suffix.
38 #define SM(_v, _f) (((_v) << _f##_S) & (_f))
39 #define MS(_v, _f) (((_v) & (_f)) >> _f##_S)
41 /* Atheros specific MII registers */
42 #define MII_ATH_DBG_ADDR 0x1d
43 #define MII_ATH_DBG_DATA 0x1e
45 #define AR8X16_REG_MASK_CTRL 0x0000
46 #define AR8X16_MASK_CTRL_REV_MASK 0x000000ff
47 #define AR8X16_MASK_CTRL_VER_MASK 0x0000ff00
48 #define AR8X16_MASK_CTRL_VER_SHIFT 8
49 #define AR8X16_MASK_CTRL_SOFT_RESET (1 << 31)
51 #define AR8X16_REG_MODE 0x0008
52 /* DIR-615 E4 U-Boot */
53 #define AR8X16_MODE_DIR_615_UBOOT 0x8d1003e0
54 /* From Ubiquiti RSPRO */
55 #define AR8X16_MODE_RGMII_PORT4_ISO 0x81461bea
56 #define AR8X16_MODE_RGMII_PORT4_SWITCH 0x01261be2
57 /* AVM Fritz!Box 7390 */
58 #define AR8X16_MODE_GMII 0x010e5b71
59 /* from avm_cpmac/linux_ar_reg.h */
60 #define AR8X16_MODE_RESERVED 0x000e1b20
61 #define AR8X16_MODE_MAC0_GMII_EN (1u << 0)
62 #define AR8X16_MODE_MAC0_RGMII_EN (1u << 1)
63 #define AR8X16_MODE_PHY4_GMII_EN (1u << 2)
64 #define AR8X16_MODE_PHY4_RGMII_EN (1u << 3)
65 #define AR8X16_MODE_MAC0_MAC_MODE (1u << 4)
66 #define AR8X16_MODE_RGMII_RXCLK_DELAY_EN (1u << 6)
67 #define AR8X16_MODE_RGMII_TXCLK_DELAY_EN (1u << 7)
68 #define AR8X16_MODE_MAC5_MAC_MODE (1u << 14)
69 #define AR8X16_MODE_MAC5_PHY_MODE (1u << 15)
70 #define AR8X16_MODE_TXDELAY_S0 (1u << 21)
71 #define AR8X16_MODE_TXDELAY_S1 (1u << 22)
72 #define AR8X16_MODE_RXDELAY_S0 (1u << 23)
73 #define AR8X16_MODE_LED_OPEN_EN (1u << 24)
74 #define AR8X16_MODE_SPI_EN (1u << 25)
75 #define AR8X16_MODE_RXDELAY_S1 (1u << 26)
76 #define AR8X16_MODE_POWER_ON_SEL (1u << 31)
78 #define AR8X16_REG_ISR 0x0010
79 #define AR8X16_REG_IMR 0x0014
81 #define AR8X16_REG_SW_MAC_ADDR0 0x0020
82 #define AR8X16_REG_SW_MAC_ADDR1 0x0024
84 #define AR8X16_REG_FLOOD_MASK 0x002c
85 #define AR8X16_FLOOD_MASK_BCAST_TO_CPU (1 << 26)
87 #define AR8X16_REG_GLOBAL_CTRL 0x0030
88 #define AR8216_GLOBAL_CTRL_MTU_MASK 0x00000fff
89 #define AR8216_GLOBAL_CTRL_MTU_MASK_S 0
90 #define AR8316_GLOBAL_CTRL_MTU_MASK 0x00007fff
91 #define AR8316_GLOBAL_CTRL_MTU_MASK_S 0
92 #define AR8236_GLOBAL_CTRL_MTU_MASK 0x00007fff
93 #define AR8236_GLOBAL_CTRL_MTU_MASK_S 0
94 #define AR7240_GLOBAL_CTRL_MTU_MASK 0x00003fff
95 #define AR7240_GLOBAL_CTRL_MTU_MASK_S 0
97 #define AR8X16_REG_VLAN_CTRL 0x0040
98 #define AR8X16_VLAN_OP 0x00000007
99 #define AR8X16_VLAN_OP_NOOP 0x0
100 #define AR8X16_VLAN_OP_FLUSH 0x1
101 #define AR8X16_VLAN_OP_LOAD 0x2
102 #define AR8X16_VLAN_OP_PURGE 0x3
103 #define AR8X16_VLAN_OP_REMOVE_PORT 0x4
104 #define AR8X16_VLAN_OP_GET_NEXT 0x5
105 #define AR8X16_VLAN_OP_GET 0x6
106 #define AR8X16_VLAN_ACTIVE (1 << 3)
107 #define AR8X16_VLAN_FULL (1 << 4)
108 #define AR8X16_VLAN_PORT 0x00000f00
109 #define AR8X16_VLAN_PORT_SHIFT 8
110 #define AR8X16_VLAN_VID 0x0fff0000
111 #define AR8X16_VLAN_VID_SHIFT 16
112 #define AR8X16_VLAN_PRIO 0x70000000
113 #define AR8X16_VLAN_PRIO_SHIFT 28
114 #define AR8X16_VLAN_PRIO_EN (1 << 31)
116 #define AR8X16_REG_VLAN_DATA 0x0044
117 #define AR8X16_VLAN_MEMBER 0x0000003f
118 #define AR8X16_VLAN_VALID (1 << 11)
120 #define AR8X16_REG_ARL_CTRL0 0x0050
121 #define AR8X16_REG_ARL_CTRL1 0x0054
122 #define AR8X16_REG_ARL_CTRL2 0x0058
124 #define AR8X16_REG_AT_CTRL 0x005c
125 #define AR8X16_AT_CTRL_ARP_EN (1 << 20)
127 #define AR8X16_REG_IP_PRIORITY_1 0x0060
128 #define AR8X16_REG_IP_PRIORITY_2 0x0064
129 #define AR8X16_REG_IP_PRIORITY_3 0x0068
130 #define AR8X16_REG_IP_PRIORITY_4 0x006C
132 #define AR8X16_REG_TAG_PRIO 0x0070
134 #define AR8X16_REG_SERVICE_TAG 0x0074
135 #define AR8X16_SERVICE_TAG_MASK 0x0000ffff
137 #define AR8X16_REG_CPU_PORT 0x0078
138 #define AR8X16_MIRROR_PORT_SHIFT 4
139 #define AR8X16_MIRROR_PORT_MASK (0xf << AR8X16_MIRROR_PORT_SHIFT)
140 #define AR8X16_CPU_MIRROR_PORT(_p) ((_p) << AR8X16_MIRROR_PORT_SHIFT)
141 #define AR8X16_CPU_MIRROR_DIS AR8X16_CPU_MIRROR_PORT(0xf)
142 #define AR8X16_CPU_PORT_EN (1 << 8)
144 #define AR8X16_REG_MIB_FUNC0 0x0080
145 #define AR8X16_MIB_TIMER_MASK 0x0000ffff
146 #define AR8X16_MIB_AT_HALF_EN (1 << 16)
147 #define AR8X16_MIB_BUSY (1 << 17)
148 #define AR8X16_MIB_FUNC_SHIFT 24
149 #define AR8X16_MIB_FUNC_NO_OP 0x0
150 #define AR8X16_MIB_FUNC_FLUSH 0x1
151 #define AR8X16_MIB_FUNC_CAPTURE 0x3
152 #define AR8X16_MIB_FUNC_XXX (1 << 30) /* 0x40000000 */
154 #define AR8X16_REG_MDIO_HIGH_ADDR 0x0094
156 #define AR8X16_REG_MDIO_CTRL 0x0098
157 #define AR8X16_MDIO_CTRL_DATA_MASK 0x0000ffff
158 #define AR8X16_MDIO_CTRL_REG_ADDR_SHIFT 16
159 #define AR8X16_MDIO_CTRL_PHY_ADDR_SHIFT 21
160 #define AR8X16_MDIO_CTRL_CMD_WRITE 0
161 #define AR8X16_MDIO_CTRL_CMD_READ (1 << 27)
162 #define AR8X16_MDIO_CTRL_MASTER_EN (1 << 30)
163 #define AR8X16_MDIO_CTRL_BUSY (1 << 31)
165 #define AR8X16_REG_PORT_BASE(_p) (0x0100 + (_p) * 0x0100)
167 #define AR8X16_REG_PORT_STS(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0000)
168 #define AR8X16_PORT_STS_SPEED_MASK 0x00000003
169 #define AR8X16_PORT_STS_SPEED_10 0
170 #define AR8X16_PORT_STS_SPEED_100 1
171 #define AR8X16_PORT_STS_SPEED_1000 2
172 #define AR8X16_PORT_STS_TXMAC (1 << 2)
173 #define AR8X16_PORT_STS_RXMAC (1 << 3)
174 #define AR8X16_PORT_STS_TXFLOW (1 << 4)
175 #define AR8X16_PORT_STS_RXFLOW (1 << 5)
176 #define AR8X16_PORT_STS_DUPLEX (1 << 6)
177 #define AR8X16_PORT_STS_LINK_UP (1 << 8)
178 #define AR8X16_PORT_STS_LINK_AUTO (1 << 9)
179 #define AR8X16_PORT_STS_LINK_PAUSE (1 << 10)
181 #define AR8X16_REG_PORT_CTRL(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0004)
182 #define AR8X16_PORT_CTRL_STATE_MASK 0x00000007
183 #define AR8X16_PORT_CTRL_STATE_DISABLED 0
184 #define AR8X16_PORT_CTRL_STATE_BLOCK 1
185 #define AR8X16_PORT_CTRL_STATE_LISTEN 2
186 #define AR8X16_PORT_CTRL_STATE_LEARN 3
187 #define AR8X16_PORT_CTRL_STATE_FORWARD 4
188 #define AR8X16_PORT_CTRL_LEARN_LOCK (1 << 7)
189 #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_SHIFT 8
190 #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_KEEP 0
191 #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_STRIP 1
192 #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_ADD 2
193 #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_DOUBLE_TAG 3
194 #define AR8X16_PORT_CTRL_IGMP_SNOOP (1 << 10)
195 #define AR8X16_PORT_CTRL_HEADER (1 << 11)
196 #define AR8X16_PORT_CTRL_MAC_LOOP (1 << 12)
197 #define AR8X16_PORT_CTRL_SINGLE_VLAN (1 << 13)
198 #define AR8X16_PORT_CTRL_LEARN (1 << 14)
199 #define AR8X16_PORT_CTRL_DOUBLE_TAG (1 << 15)
200 #define AR8X16_PORT_CTRL_MIRROR_TX (1 << 16)
201 #define AR8X16_PORT_CTRL_MIRROR_RX (1 << 17)
203 #define AR8X16_REG_PORT_VLAN(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0008)
205 #define AR8X16_PORT_VLAN_DEFAULT_ID_SHIFT 0
206 #define AR8X16_PORT_VLAN_DEST_PORTS_SHIFT 16
207 #define AR8X16_PORT_VLAN_MODE_MASK 0xc0000000
208 #define AR8X16_PORT_VLAN_MODE_SHIFT 30
209 #define AR8X16_PORT_VLAN_MODE_PORT_ONLY 0
210 #define AR8X16_PORT_VLAN_MODE_PORT_FALLBACK 1
211 #define AR8X16_PORT_VLAN_MODE_VLAN_ONLY 2
212 #define AR8X16_PORT_VLAN_MODE_SECURE 3
214 #define AR8X16_REG_PORT_RATE_LIM(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x000c)
215 #define AR8X16_PORT_RATE_LIM_128KB 0
216 #define AR8X16_PORT_RATE_LIM_256KB 1
217 #define AR8X16_PORT_RATE_LIM_512KB 2
218 #define AR8X16_PORT_RATE_LIM_1MB 3
219 #define AR8X16_PORT_RATE_LIM_2MB 4
220 #define AR8X16_PORT_RATE_LIM_4MB 5
221 #define AR8X16_PORT_RATE_LIM_8MB 6
222 #define AR8X16_PORT_RATE_LIM_16MB 7
223 #define AR8X16_PORT_RATE_LIM_32MB 8
224 #define AR8X16_PORT_RATE_LIM_64MB 9
225 #define AR8X16_PORT_RATE_LIM_IN_EN (1 << 24)
226 #define AR8X16_PORT_RATE_LIM_OUT_EN (1 << 23)
227 #define AR8X16_PORT_RATE_LIM_IN_MASK 0x000f0000
228 #define AR8X16_PORT_RATE_LIM_IN_SHIFT 16
229 #define AR8X16_PORT_RATE_LIM_OUT_MASK 0x0000000f
230 #define AR8X16_PORT_RATE_LIM_OUT_SHIFT 0
232 #define AR8X16_REG_PORT_PRIORITY(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0010)
234 #define AR8X16_REG_STATS_BASE(_p) (0x20000 + (_p) * 0x100)
236 #define AR8X16_STATS_RXBROAD 0x0000
237 #define AR8X16_STATS_RXPAUSE 0x0004
238 #define AR8X16_STATS_RXMULTI 0x0008
239 #define AR8X16_STATS_RXFCSERR 0x000c
240 #define AR8X16_STATS_RXALIGNERR 0x0010
241 #define AR8X16_STATS_RXRUNT 0x0014
242 #define AR8X16_STATS_RXFRAGMENT 0x0018
243 #define AR8X16_STATS_RX64BYTE 0x001c
244 #define AR8X16_STATS_RX128BYTE 0x0020
245 #define AR8X16_STATS_RX256BYTE 0x0024
246 #define AR8X16_STATS_RX512BYTE 0x0028
247 #define AR8X16_STATS_RX1024BYTE 0x002c
248 #define AR8X16_STATS_RX1518BYTE 0x0030
249 #define AR8X16_STATS_RXMAXBYTE 0x0034
250 #define AR8X16_STATS_RXTOOLONG 0x0038
251 #define AR8X16_STATS_RXGOODBYTE 0x003c
252 #define AR8X16_STATS_RXBADBYTE 0x0044
253 #define AR8X16_STATS_RXOVERFLOW 0x004c
254 #define AR8X16_STATS_FILTERED 0x0050
255 #define AR8X16_STATS_TXBROAD 0x0054
256 #define AR8X16_STATS_TXPAUSE 0x0058
257 #define AR8X16_STATS_TXMULTI 0x005c
258 #define AR8X16_STATS_TXUNDERRUN 0x0060
259 #define AR8X16_STATS_TX64BYTE 0x0064
260 #define AR8X16_STATS_TX128BYTE 0x0068
261 #define AR8X16_STATS_TX256BYTE 0x006c
262 #define AR8X16_STATS_TX512BYTE 0x0070
263 #define AR8X16_STATS_TX1024BYTE 0x0074
264 #define AR8X16_STATS_TX1518BYTE 0x0078
265 #define AR8X16_STATS_TXMAXBYTE 0x007c
266 #define AR8X16_STATS_TXOVERSIZE 0x0080
267 #define AR8X16_STATS_TXBYTE 0x0084
268 #define AR8X16_STATS_TXCOLLISION 0x008c
269 #define AR8X16_STATS_TXABORTCOL 0x0090
270 #define AR8X16_STATS_TXMULTICOL 0x0094
271 #define AR8X16_STATS_TXSINGLECOL 0x0098
272 #define AR8X16_STATS_TXEXCDEFER 0x009c
273 #define AR8X16_STATS_TXDEFER 0x00a0
274 #define AR8X16_STATS_TXLATECOL 0x00a4
276 #define AR8X16_PORT_CPU 0
277 #define AR8X16_NUM_PORTS 6
278 #define AR8X16_NUM_PHYS 5
279 #define AR8X16_MAGIC 0xc000050e
281 #define AR8X16_PHY_ID1 0x004d
282 #define AR8X16_PHY_ID2 0xd041
284 #define AR8X16_PORT_MASK(_port) (1 << (_port))
285 #define AR8X16_PORT_MASK_ALL ((1<<AR8X16_NUM_PORTS)-1)
286 #define AR8X16_PORT_MASK_BUT(_port) (AR8X16_PORT_MASK_ALL & ~(1 << (_port)))
288 #define AR8X16_MAX_VLANS 16
290 #endif /* __AR8X16_SWITCHREG_H__ */