sys/dev/hifn/hifn7751.c

   1 /*      $OpenBSD: hifn7751.c,v 1.120 2002/05/17 00:33:34 deraadt Exp $  */
   2
   3 /*-
   4  * Invertex AEON / Hifn 7751 driver
   5  * Copyright (c) 1999 Invertex Inc. All rights reserved.
   6  * Copyright (c) 1999 Theo de Raadt
   7  * Copyright (c) 2000-2001 Network Security Technologies, Inc.
   8  *                      http://www.netsec.net
   9  * Copyright (c) 2003 Hifn Inc.
  10  *
  11  * This driver is based on a previous driver by Invertex, for which they
  12  * requested:  Please send any comments, feedback, bug-fixes, or feature
  13  * requests to software@invertex.com.
  14  *
  15  * Redistribution and use in source and binary forms, with or without
  16  * modification, are permitted provided that the following conditions
  17  * are met:
  18  *
  19  * 1. Redistributions of source code must retain the above copyright
  20  *   notice, this list of conditions and the following disclaimer.
  21  * 2. Redistributions in binary form must reproduce the above copyright
  22  *   notice, this list of conditions and the following disclaimer in the
  23  *   documentation and/or other materials provided with the distribution.
  24  * 3. The name of the author may not be used to endorse or promote products
  25  *   derived from this software without specific prior written permission.
  26  *
  27  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  28  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  29  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  30  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  31  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  32  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  33  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  34  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  35  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  36  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  *
  38  * Effort sponsored in part by the Defense Advanced Research Projects
  39  * Agency (DARPA) and Air Force Research Laboratory, Air Force
  40  * Materiel Command, USAF, under agreement number F30602-01-2-0537.
  41  */
  42
  43 #include <sys/cdefs.h>
  44 __FBSDID("$FreeBSD$");
  45
  46 /*
  47  * Driver for various Hifn encryption processors.
  48  */
  49 #include "opt_hifn.h"
  50
  51 #include <sys/param.h>
  52 #include <sys/systm.h>
  53 #include <sys/proc.h>
  54 #include <sys/errno.h>
  55 #include <sys/malloc.h>
  56 #include <sys/kernel.h>
  57 #include <sys/module.h>
  58 #include <sys/mbuf.h>
  59 #include <sys/lock.h>
  60 #include <sys/mutex.h>
  61 #include <sys/sysctl.h>
  62
  63 #include <vm/vm.h>
  64 #include <vm/pmap.h>
  65
  66 #include <machine/bus.h>
  67 #include <machine/resource.h>
  68 #include <sys/bus.h>
  69 #include <sys/rman.h>
  70
  71 #include <opencrypto/cryptodev.h>
  72 #include <sys/random.h>
  73 #include <sys/kobj.h>
  74
  75 #include "cryptodev_if.h"
  76
  77 #include <dev/pci/pcivar.h>
  78 #include <dev/pci/pcireg.h>
  79
  80 #ifdef HIFN_RNDTEST
  81 #include <dev/rndtest/rndtest.h>
  82 #endif
  83 #include <dev/hifn/hifn7751reg.h>
  84 #include <dev/hifn/hifn7751var.h>
  85
  86 #ifdef HIFN_VULCANDEV
  87 #include <sys/conf.h>
  88 #include <sys/uio.h>
  89
  90 static struct cdevsw vulcanpk_cdevsw; /* forward declaration */
  91 #endif
  92
  93 /*
  94  * Prototypes and count for the pci_device structure
  95  */
  96 static  int hifn_probe(device_t);
  97 static  int hifn_attach(device_t);
  98 static  int hifn_detach(device_t);
  99 static  int hifn_suspend(device_t);
 100 static  int hifn_resume(device_t);
 101 static  int hifn_shutdown(device_t);
 102
 103 static  int hifn_newsession(device_t, u_int32_t *, struct cryptoini *);
 104 static  int hifn_freesession(device_t, u_int64_t);
 105 static  int hifn_process(device_t, struct cryptop *, int);
 106
 107 static device_method_t hifn_methods[] = {
 108         /* Device interface */
 109         DEVMETHOD(device_probe,         hifn_probe),
 110         DEVMETHOD(device_attach,        hifn_attach),
 111         DEVMETHOD(device_detach,        hifn_detach),
 112         DEVMETHOD(device_suspend,       hifn_suspend),
 113         DEVMETHOD(device_resume,        hifn_resume),
 114         DEVMETHOD(device_shutdown,      hifn_shutdown),
 115
 116         /* crypto device methods */
 117         DEVMETHOD(cryptodev_newsession, hifn_newsession),
 118         DEVMETHOD(cryptodev_freesession,hifn_freesession),
 119         DEVMETHOD(cryptodev_process,    hifn_process),
 120
 121         DEVMETHOD_END
 122 };
 123 static driver_t hifn_driver = {
 124         "hifn",
 125         hifn_methods,
 126         sizeof (struct hifn_softc)
 127 };
 128 static devclass_t hifn_devclass;
 129
 130 DRIVER_MODULE(hifn, pci, hifn_driver, hifn_devclass, 0, 0);
 131 MODULE_DEPEND(hifn, crypto, 1, 1, 1);
 132 #ifdef HIFN_RNDTEST
 133 MODULE_DEPEND(hifn, rndtest, 1, 1, 1);
 134 #endif
 135
 136 static  void hifn_reset_board(struct hifn_softc *, int);
 137 static  void hifn_reset_puc(struct hifn_softc *);
 138 static  void hifn_puc_wait(struct hifn_softc *);
 139 static  int hifn_enable_crypto(struct hifn_softc *);
 140 static  void hifn_set_retry(struct hifn_softc *sc);
 141 static  void hifn_init_dma(struct hifn_softc *);
 142 static  void hifn_init_pci_registers(struct hifn_softc *);
 143 static  int hifn_sramsize(struct hifn_softc *);
 144 static  int hifn_dramsize(struct hifn_softc *);
 145 static  int hifn_ramtype(struct hifn_softc *);
 146 static  void hifn_sessions(struct hifn_softc *);
 147 static  void hifn_intr(void *);
 148 static  u_int hifn_write_command(struct hifn_command *, u_int8_t *);
 149 static  u_int32_t hifn_next_signature(u_int32_t a, u_int cnt);
 150 static  void hifn_callback(struct hifn_softc *, struct hifn_command *, u_int8_t *);
 151 static  int hifn_crypto(struct hifn_softc *, struct hifn_command *, struct cryptop *, int);
 152 static  int hifn_readramaddr(struct hifn_softc *, int, u_int8_t *);
 153 static  int hifn_writeramaddr(struct hifn_softc *, int, u_int8_t *);
 154 static  int hifn_dmamap_load_src(struct hifn_softc *, struct hifn_command *);
 155 static  int hifn_dmamap_load_dst(struct hifn_softc *, struct hifn_command *);
 156 static  int hifn_init_pubrng(struct hifn_softc *);
 157 static  void hifn_rng(void *);
 158 static  void hifn_tick(void *);
 159 static  void hifn_abort(struct hifn_softc *);
 160 static  void hifn_alloc_slot(struct hifn_softc *, int *, int *, int *, int *);
 161
 162 static  void hifn_write_reg_0(struct hifn_softc *, bus_size_t, u_int32_t);
 163 static  void hifn_write_reg_1(struct hifn_softc *, bus_size_t, u_int32_t);
 164
 165 static __inline u_int32_t
 166 READ_REG_0(struct hifn_softc *sc, bus_size_t reg)
 167 {
 168     u_int32_t v = bus_space_read_4(sc->sc_st0, sc->sc_sh0, reg);
 169     sc->sc_bar0_lastreg = (bus_size_t) -1;
 170     return (v);
 171 }
 172 #define WRITE_REG_0(sc, reg, val)       hifn_write_reg_0(sc, reg, val)
 173
 174 static __inline u_int32_t
 175 READ_REG_1(struct hifn_softc *sc, bus_size_t reg)
 176 {
 177     u_int32_t v = bus_space_read_4(sc->sc_st1, sc->sc_sh1, reg);
 178     sc->sc_bar1_lastreg = (bus_size_t) -1;
 179     return (v);
 180 }
 181 #define WRITE_REG_1(sc, reg, val)       hifn_write_reg_1(sc, reg, val)
 182
 183 static SYSCTL_NODE(_hw, OID_AUTO, hifn, CTLFLAG_RD, 0,
 184             "Hifn driver parameters");
 185
 186 #ifdef HIFN_DEBUG
 187 static  int hifn_debug = 0;
 188 SYSCTL_INT(_hw_hifn, OID_AUTO, debug, CTLFLAG_RW, &hifn_debug,
 189             0, "control debugging msgs");
 190 #endif
 191
 192 static  struct hifn_stats hifnstats;
 193 SYSCTL_STRUCT(_hw_hifn, OID_AUTO, stats, CTLFLAG_RD, &hifnstats,
 194             hifn_stats, "driver statistics");
 195 static  int hifn_maxbatch = 1;
 196 SYSCTL_INT(_hw_hifn, OID_AUTO, maxbatch, CTLFLAG_RW, &hifn_maxbatch,
 197             0, "max ops to batch w/o interrupt");
 198
 199 /*
 200  * Probe for a supported device.  The PCI vendor and device
 201  * IDs are used to detect devices we know how to handle.
 202  */
 203 static int
 204 hifn_probe(device_t dev)
 205 {
 206         if (pci_get_vendor(dev) == PCI_VENDOR_INVERTEX &&
 207             pci_get_device(dev) == PCI_PRODUCT_INVERTEX_AEON)
 208                 return (BUS_PROBE_DEFAULT);
 209         if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
 210             (pci_get_device(dev) == PCI_PRODUCT_HIFN_7751 ||
 211              pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 ||
 212              pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 ||
 213              pci_get_device(dev) == PCI_PRODUCT_HIFN_7956 ||
 214              pci_get_device(dev) == PCI_PRODUCT_HIFN_7811))
 215                 return (BUS_PROBE_DEFAULT);
 216         if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC &&
 217             pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751)
 218                 return (BUS_PROBE_DEFAULT);
 219         return (ENXIO);
 220 }
 221
 222 static void
 223 hifn_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 224 {
 225         bus_addr_t *paddr = (bus_addr_t*) arg;
 226         *paddr = segs->ds_addr;
 227 }
 228
 229 static const char*
 230 hifn_partname(struct hifn_softc *sc)
 231 {
 232         /* XXX sprintf numbers when not decoded */
 233         switch (pci_get_vendor(sc->sc_dev)) {
 234         case PCI_VENDOR_HIFN:
 235                 switch (pci_get_device(sc->sc_dev)) {
 236                 case PCI_PRODUCT_HIFN_6500:     return "Hifn 6500";
 237                 case PCI_PRODUCT_HIFN_7751:     return "Hifn 7751";
 238                 case PCI_PRODUCT_HIFN_7811:     return "Hifn 7811";
 239                 case PCI_PRODUCT_HIFN_7951:     return "Hifn 7951";
 240                 case PCI_PRODUCT_HIFN_7955:     return "Hifn 7955";
 241                 case PCI_PRODUCT_HIFN_7956:     return "Hifn 7956";
 242                 }
 243                 return "Hifn unknown-part";
 244         case PCI_VENDOR_INVERTEX:
 245                 switch (pci_get_device(sc->sc_dev)) {
 246                 case PCI_PRODUCT_INVERTEX_AEON: return "Invertex AEON";
 247                 }
 248                 return "Invertex unknown-part";
 249         case PCI_VENDOR_NETSEC:
 250                 switch (pci_get_device(sc->sc_dev)) {
 251                 case PCI_PRODUCT_NETSEC_7751:   return "NetSec 7751";
 252                 }
 253                 return "NetSec unknown-part";
 254         }
 255         return "Unknown-vendor unknown-part";
 256 }
 257
 258 static void
 259 default_harvest(struct rndtest_state *rsp, void *buf, u_int count)
 260 {
 261         random_harvest(buf, count, count*NBBY/2, RANDOM_PURE_HIFN);
 262 }
 263
 264 static u_int
 265 checkmaxmin(device_t dev, const char *what, u_int v, u_int min, u_int max)
 266 {
 267         if (v > max) {
 268                 device_printf(dev, "Warning, %s %u out of range, "
 269                         "using max %u\n", what, v, max);
 270                 v = max;
 271         } else if (v < min) {
 272                 device_printf(dev, "Warning, %s %u out of range, "
 273                         "using min %u\n", what, v, min);
 274                 v = min;
 275         }
 276         return v;
 277 }
 278
 279 /*
 280  * Select PLL configuration for 795x parts.  This is complicated in
 281  * that we cannot determine the optimal parameters without user input.
 282  * The reference clock is derived from an external clock through a
 283  * multiplier.  The external clock is either the host bus (i.e. PCI)
 284  * or an external clock generator.  When using the PCI bus we assume
 285  * the clock is either 33 or 66 MHz; for an external source we cannot
 286  * tell the speed.
 287  *
 288  * PLL configuration is done with a string: "pci" for PCI bus, or "ext"
 289  * for an external source, followed by the frequency.  We calculate
 290  * the appropriate multiplier and PLL register contents accordingly.
 291  * When no configuration is given we default to "pci66" since that
 292  * always will allow the card to work.  If a card is using the PCI
 293  * bus clock and in a 33MHz slot then it will be operating at half
 294  * speed until the correct information is provided.
 295  *
 296  * We use a default setting of "ext66" because according to Mike Ham
 297  * of HiFn, almost every board in existence has an external crystal
 298  * populated at 66Mhz. Using PCI can be a problem on modern motherboards,
 299  * because PCI33 can have clocks from 0 to 33Mhz, and some have
 300  * non-PCI-compliant spread-spectrum clocks, which can confuse the pll.
 301  */
 302 static void
 303 hifn_getpllconfig(device_t dev, u_int *pll)
 304 {
 305         const char *pllspec;
 306         u_int freq, mul, fl, fh;
 307         u_int32_t pllconfig;
 308         char *nxt;
 309
 310         if (resource_string_value("hifn", device_get_unit(dev),
 311             "pllconfig", &pllspec))
 312                 pllspec = "ext66";
 313         fl = 33, fh = 66;
 314         pllconfig = 0;
 315         if (strncmp(pllspec, "ext", 3) == 0) {
 316                 pllspec += 3;
 317                 pllconfig |= HIFN_PLL_REF_SEL;
 318                 switch (pci_get_device(dev)) {
 319                 case PCI_PRODUCT_HIFN_7955:
 320                 case PCI_PRODUCT_HIFN_7956:
 321                         fl = 20, fh = 100;
 322                         break;
 323 #ifdef notyet
 324                 case PCI_PRODUCT_HIFN_7954:
 325                         fl = 20, fh = 66;
 326                         break;
 327 #endif
 328                 }
 329         } else if (strncmp(pllspec, "pci", 3) == 0)
 330                 pllspec += 3;
 331         freq = strtoul(pllspec, &nxt, 10);
 332         if (nxt == pllspec)
 333                 freq = 66;
 334         else
 335                 freq = checkmaxmin(dev, "frequency", freq, fl, fh);
 336         /*
 337          * Calculate multiplier.  We target a Fck of 266 MHz,
 338          * allowing only even values, possibly rounded down.
 339          * Multipliers > 8 must set the charge pump current.
 340          */
 341         mul = checkmaxmin(dev, "PLL divisor", (266 / freq) &~ 1, 2, 12);
 342         pllconfig |= (mul / 2 - 1) << HIFN_PLL_ND_SHIFT;
 343         if (mul > 8)
 344                 pllconfig |= HIFN_PLL_IS;
 345         *pll = pllconfig;
 346 }
 347
 348 /*
 349  * Attach an interface that successfully probed.
 350  */
 351 static int
 352 hifn_attach(device_t dev)
 353 {
 354         struct hifn_softc *sc = device_get_softc(dev);
 355         caddr_t kva;
 356         int rseg, rid;
 357         char rbase;
 358         u_int16_t ena, rev;
 359
 360         sc->sc_dev = dev;
 361
 362         mtx_init(&sc->sc_mtx, device_get_nameunit(dev), "hifn driver", MTX_DEF);
 363
 364         /* XXX handle power management */
 365
 366         /*
 367          * The 7951 and 795x have a random number generator and
 368          * public key support; note this.
 369          */
 370         if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
 371             (pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 ||
 372              pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 ||
 373              pci_get_device(dev) == PCI_PRODUCT_HIFN_7956))
 374                 sc->sc_flags = HIFN_HAS_RNG | HIFN_HAS_PUBLIC;
 375         /*
 376          * The 7811 has a random number generator and
 377          * we also note it's identity 'cuz of some quirks.
 378          */
 379         if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
 380             pci_get_device(dev) == PCI_PRODUCT_HIFN_7811)
 381                 sc->sc_flags |= HIFN_IS_7811 | HIFN_HAS_RNG;
 382
 383         /*
 384          * The 795x parts support AES.
 385          */
 386         if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
 387             (pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 ||
 388              pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) {
 389                 sc->sc_flags |= HIFN_IS_7956 | HIFN_HAS_AES;
 390                 /*
 391                  * Select PLL configuration.  This depends on the
 392                  * bus and board design and must be manually configured
 393                  * if the default setting is unacceptable.
 394                  */
 395                 hifn_getpllconfig(dev, &sc->sc_pllconfig);
 396         }
 397
 398         /*
 399          * Setup PCI resources. Note that we record the bus
 400          * tag and handle for each register mapping, this is
 401          * used by the READ_REG_0, WRITE_REG_0, READ_REG_1,
 402          * and WRITE_REG_1 macros throughout the driver.
 403          */
 404         pci_enable_busmaster(dev);
 405
 406         rid = HIFN_BAR0;
 407         sc->sc_bar0res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 408                                                 RF_ACTIVE);
 409         if (sc->sc_bar0res == NULL) {
 410                 device_printf(dev, "cannot map bar%d register space\n", 0);
 411                 goto fail_pci;
 412         }
 413         sc->sc_st0 = rman_get_bustag(sc->sc_bar0res);
 414         sc->sc_sh0 = rman_get_bushandle(sc->sc_bar0res);
 415         sc->sc_bar0_lastreg = (bus_size_t) -1;
 416
 417         rid = HIFN_BAR1;
 418         sc->sc_bar1res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 419                                                 RF_ACTIVE);
 420         if (sc->sc_bar1res == NULL) {
 421                 device_printf(dev, "cannot map bar%d register space\n", 1);
 422                 goto fail_io0;
 423         }
 424         sc->sc_st1 = rman_get_bustag(sc->sc_bar1res);
 425         sc->sc_sh1 = rman_get_bushandle(sc->sc_bar1res);
 426         sc->sc_bar1_lastreg = (bus_size_t) -1;
 427
 428         hifn_set_retry(sc);
 429
 430         /*
 431          * Setup the area where the Hifn DMA's descriptors
 432          * and associated data structures.
 433          */
 434         if (bus_dma_tag_create(bus_get_dma_tag(dev),    /* PCI parent */
 435                                1, 0,                    /* alignment,boundary */
 436                                BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
 437                                BUS_SPACE_MAXADDR,       /* highaddr */
 438                                NULL, NULL,              /* filter, filterarg */
 439                                HIFN_MAX_DMALEN,         /* maxsize */
 440                                MAX_SCATTER,             /* nsegments */
 441                                HIFN_MAX_SEGLEN,         /* maxsegsize */
 442                                BUS_DMA_ALLOCNOW,        /* flags */
 443                                NULL,                    /* lockfunc */
 444                                NULL,                    /* lockarg */
 445                                &sc->sc_dmat)) {
 446                 device_printf(dev, "cannot allocate DMA tag\n");
 447                 goto fail_io1;
 448         }
 449         if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &sc->sc_dmamap)) {
 450                 device_printf(dev, "cannot create dma map\n");
 451                 bus_dma_tag_destroy(sc->sc_dmat);
 452                 goto fail_io1;
 453         }
 454         if (bus_dmamem_alloc(sc->sc_dmat, (void**) &kva, BUS_DMA_NOWAIT, &sc->sc_dmamap)) {
 455                 device_printf(dev, "cannot alloc dma buffer\n");
 456                 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap);
 457                 bus_dma_tag_destroy(sc->sc_dmat);
 458                 goto fail_io1;
 459         }
 460         if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, kva,
 461                              sizeof (*sc->sc_dma),
 462                              hifn_dmamap_cb, &sc->sc_dma_physaddr,
 463                              BUS_DMA_NOWAIT)) {
 464                 device_printf(dev, "cannot load dma map\n");
 465                 bus_dmamem_free(sc->sc_dmat, kva, sc->sc_dmamap);
 466                 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap);
 467                 bus_dma_tag_destroy(sc->sc_dmat);
 468                 goto fail_io1;
 469         }
 470         sc->sc_dma = (struct hifn_dma *)kva;
 471         bzero(sc->sc_dma, sizeof(*sc->sc_dma));
 472
 473         KASSERT(sc->sc_st0 != 0, ("hifn_attach: null bar0 tag!"));
 474         KASSERT(sc->sc_sh0 != 0, ("hifn_attach: null bar0 handle!"));
 475         KASSERT(sc->sc_st1 != 0, ("hifn_attach: null bar1 tag!"));
 476         KASSERT(sc->sc_sh1 != 0, ("hifn_attach: null bar1 handle!"));
 477
 478         /*
 479          * Reset the board and do the ``secret handshake''
 480          * to enable the crypto support.  Then complete the
 481          * initialization procedure by setting up the interrupt
 482          * and hooking in to the system crypto support so we'll
 483          * get used for system services like the crypto device,
 484          * IPsec, RNG device, etc.
 485          */
 486         hifn_reset_board(sc, 0);
 487
 488         if (hifn_enable_crypto(sc) != 0) {
 489                 device_printf(dev, "crypto enabling failed\n");
 490                 goto fail_mem;
 491         }
 492         hifn_reset_puc(sc);
 493
 494         hifn_init_dma(sc);
 495         hifn_init_pci_registers(sc);
 496
 497         /* XXX can't dynamically determine ram type for 795x; force dram */
 498         if (sc->sc_flags & HIFN_IS_7956)
 499                 sc->sc_drammodel = 1;
 500         else if (hifn_ramtype(sc))
 501                 goto fail_mem;
 502
 503         if (sc->sc_drammodel == 0)
 504                 hifn_sramsize(sc);
 505         else
 506                 hifn_dramsize(sc);
 507
 508         /*
 509          * Workaround for NetSec 7751 rev A: half ram size because two
 510          * of the address lines were left floating
 511          */
 512         if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC &&
 513             pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751 &&
 514             pci_get_revid(dev) == 0x61) /*XXX???*/
 515                 sc->sc_ramsize >>= 1;
 516
 517         /*
 518          * Arrange the interrupt line.
 519          */
 520         rid = 0;
 521         sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 522                                             RF_SHAREABLE|RF_ACTIVE);
 523         if (sc->sc_irq == NULL) {
 524                 device_printf(dev, "could not map interrupt\n");
 525                 goto fail_mem;
 526         }
 527         /*
 528          * NB: Network code assumes we are blocked with splimp()
 529          *     so make sure the IRQ is marked appropriately.
 530          */
 531         if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE,
 532                            NULL, hifn_intr, sc, &sc->sc_intrhand)) {
 533                 device_printf(dev, "could not setup interrupt\n");
 534                 goto fail_intr2;
 535         }
 536
 537         hifn_sessions(sc);
 538
 539         /*
 540          * NB: Keep only the low 16 bits; this masks the chip id
 541          *     from the 7951.
 542          */
 543         rev = READ_REG_1(sc, HIFN_1_REVID) & 0xffff;
 544
 545         rseg = sc->sc_ramsize / 1024;
 546         rbase = 'K';
 547         if (sc->sc_ramsize >= (1024 * 1024)) {
 548                 rbase = 'M';
 549                 rseg /= 1024;
 550         }
 551         device_printf(sc->sc_dev, "%s, rev %u, %d%cB %cram",
 552                 hifn_partname(sc), rev,
 553                 rseg, rbase, sc->sc_drammodel ? 'd' : 's');
 554         if (sc->sc_flags & HIFN_IS_7956)
 555                 printf(", pll=0x%x<%s clk, %ux mult>",
 556                         sc->sc_pllconfig,
 557                         sc->sc_pllconfig & HIFN_PLL_REF_SEL ? "ext" : "pci",
 558                         2 + 2*((sc->sc_pllconfig & HIFN_PLL_ND) >> 11));
 559         printf("\n");
 560
 561         sc->sc_cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE);
 562         if (sc->sc_cid < 0) {
 563                 device_printf(dev, "could not get crypto driver id\n");
 564                 goto fail_intr;
 565         }
 566
 567         WRITE_REG_0(sc, HIFN_0_PUCNFG,
 568             READ_REG_0(sc, HIFN_0_PUCNFG) | HIFN_PUCNFG_CHIPID);
 569         ena = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA;
 570
 571         switch (ena) {
 572         case HIFN_PUSTAT_ENA_2:
 573                 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0);
 574                 crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0);
 575                 if (sc->sc_flags & HIFN_HAS_AES)
 576                         crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0);
 577                 /*FALLTHROUGH*/
 578         case HIFN_PUSTAT_ENA_1:
 579                 crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0);
 580                 crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0);
 581                 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0);
 582                 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0);
 583                 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0);
 584                 break;
 585         }
 586
 587         bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
 588             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 589
 590         if (sc->sc_flags & (HIFN_HAS_PUBLIC | HIFN_HAS_RNG))
 591                 hifn_init_pubrng(sc);
 592
 593         callout_init(&sc->sc_tickto, CALLOUT_MPSAFE);
 594         callout_reset(&sc->sc_tickto, hz, hifn_tick, sc);
 595
 596         return (0);
 597
 598 fail_intr:
 599         bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand);
 600 fail_intr2:
 601         /* XXX don't store rid */
 602         bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
 603 fail_mem:
 604         bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap);
 605         bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap);
 606         bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap);
 607         bus_dma_tag_destroy(sc->sc_dmat);
 608
 609         /* Turn off DMA polling */
 610         WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
 611             HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
 612 fail_io1:
 613         bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res);
 614 fail_io0:
 615         bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res);
 616 fail_pci:
 617         mtx_destroy(&sc->sc_mtx);
 618         return (ENXIO);
 619 }
 620
 621 /*
 622  * Detach an interface that successfully probed.
 623  */
 624 static int
 625 hifn_detach(device_t dev)
 626 {
 627         struct hifn_softc *sc = device_get_softc(dev);
 628
 629         KASSERT(sc != NULL, ("hifn_detach: null software carrier!"));
 630
 631         /* disable interrupts */
 632         WRITE_REG_1(sc, HIFN_1_DMA_IER, 0);
 633
 634         /*XXX other resources */
 635         callout_stop(&sc->sc_tickto);
 636         callout_stop(&sc->sc_rngto);
 637 #ifdef HIFN_RNDTEST
 638         if (sc->sc_rndtest)
 639                 rndtest_detach(sc->sc_rndtest);
 640 #endif
 641
 642         /* Turn off DMA polling */
 643         WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
 644             HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
 645
 646         crypto_unregister_all(sc->sc_cid);
 647
 648         bus_generic_detach(dev);        /*XXX should be no children, right? */
 649
 650         bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand);
 651         /* XXX don't store rid */
 652         bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
 653
 654         bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap);
 655         bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap);
 656         bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap);
 657         bus_dma_tag_destroy(sc->sc_dmat);
 658
 659         bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res);
 660         bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res);
 661
 662         mtx_destroy(&sc->sc_mtx);
 663
 664         return (0);
 665 }
 666
 667 /*
 668  * Stop all chip I/O so that the kernel's probe routines don't
 669  * get confused by errant DMAs when rebooting.
 670  */
 671 static int
 672 hifn_shutdown(device_t dev)
 673 {
 674 #ifdef notyet
 675         hifn_stop(device_get_softc(dev));
 676 #endif
 677         return (0);
 678 }
 679
 680 /*
 681  * Device suspend routine.  Stop the interface and save some PCI
 682  * settings in case the BIOS doesn't restore them properly on
 683  * resume.
 684  */
 685 static int
 686 hifn_suspend(device_t dev)
 687 {
 688         struct hifn_softc *sc = device_get_softc(dev);
 689 #ifdef notyet
 690         hifn_stop(sc);
 691 #endif
 692         sc->sc_suspended = 1;
 693
 694         return (0);
 695 }
 696
 697 /*
 698  * Device resume routine.  Restore some PCI settings in case the BIOS
 699  * doesn't, re-enable busmastering, and restart the interface if
 700  * appropriate.
 701  */
 702 static int
 703 hifn_resume(device_t dev)
 704 {
 705         struct hifn_softc *sc = device_get_softc(dev);
 706 #ifdef notyet
 707         /* reinitialize interface if necessary */
 708         if (ifp->if_flags & IFF_UP)
 709                 rl_init(sc);
 710 #endif
 711         sc->sc_suspended = 0;
 712
 713         return (0);
 714 }
 715
 716 static int
 717 hifn_init_pubrng(struct hifn_softc *sc)
 718 {
 719         u_int32_t r;
 720         int i;
 721
 722 #ifdef HIFN_RNDTEST
 723         sc->sc_rndtest = rndtest_attach(sc->sc_dev);
 724         if (sc->sc_rndtest)
 725                 sc->sc_harvest = rndtest_harvest;
 726         else
 727                 sc->sc_harvest = default_harvest;
 728 #else
 729         sc->sc_harvest = default_harvest;
 730 #endif
 731         if ((sc->sc_flags & HIFN_IS_7811) == 0) {
 732                 /* Reset 7951 public key/rng engine */
 733                 WRITE_REG_1(sc, HIFN_1_PUB_RESET,
 734                     READ_REG_1(sc, HIFN_1_PUB_RESET) | HIFN_PUBRST_RESET);
 735
 736                 for (i = 0; i < 100; i++) {
 737                         DELAY(1000);
 738                         if ((READ_REG_1(sc, HIFN_1_PUB_RESET) &
 739                             HIFN_PUBRST_RESET) == 0)
 740                                 break;
 741                 }
 742
 743                 if (i == 100) {
 744                         device_printf(sc->sc_dev, "public key init failed\n");
 745                         return (1);
 746                 }
 747         }
 748
 749         /* Enable the rng, if available */
 750         if (sc->sc_flags & HIFN_HAS_RNG) {
 751                 if (sc->sc_flags & HIFN_IS_7811) {
 752                         r = READ_REG_1(sc, HIFN_1_7811_RNGENA);
 753                         if (r & HIFN_7811_RNGENA_ENA) {
 754                                 r &= ~HIFN_7811_RNGENA_ENA;
 755                                 WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r);
 756                         }
 757                         WRITE_REG_1(sc, HIFN_1_7811_RNGCFG,
 758                             HIFN_7811_RNGCFG_DEFL);
 759                         r |= HIFN_7811_RNGENA_ENA;
 760                         WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r);
 761                 } else
 762                         WRITE_REG_1(sc, HIFN_1_RNG_CONFIG,
 763                             READ_REG_1(sc, HIFN_1_RNG_CONFIG) |
 764                             HIFN_RNGCFG_ENA);
 765
 766                 sc->sc_rngfirst = 1;
 767                 if (hz >= 100)
 768                         sc->sc_rnghz = hz / 100;
 769                 else
 770                         sc->sc_rnghz = 1;
 771                 callout_init(&sc->sc_rngto, CALLOUT_MPSAFE);
 772                 callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc);
 773         }
 774
 775         /* Enable public key engine, if available */
 776         if (sc->sc_flags & HIFN_HAS_PUBLIC) {
 777                 WRITE_REG_1(sc, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE);
 778                 sc->sc_dmaier |= HIFN_DMAIER_PUBDONE;
 779                 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
 780 #ifdef HIFN_VULCANDEV
 781                 sc->sc_pkdev = make_dev(&vulcanpk_cdevsw, 0,
 782                                         UID_ROOT, GID_WHEEL, 0666,
 783                                         "vulcanpk");
 784                 sc->sc_pkdev->si_drv1 = sc;
 785 #endif
 786         }
 787
 788         return (0);
 789 }
 790
 791 static void
 792 hifn_rng(void *vsc)
 793 {
 794 #define RANDOM_BITS(n)  (n)*sizeof (u_int32_t), (n)*sizeof (u_int32_t)*NBBY, 0
 795         struct hifn_softc *sc = vsc;
 796         u_int32_t sts, num[2];
 797         int i;
 798
 799         if (sc->sc_flags & HIFN_IS_7811) {
 800                 /* ONLY VALID ON 7811!!!! */
 801                 for (i = 0; i < 5; i++) {
 802                         sts = READ_REG_1(sc, HIFN_1_7811_RNGSTS);
 803                         if (sts & HIFN_7811_RNGSTS_UFL) {
 804                                 device_printf(sc->sc_dev,
 805                                               "RNG underflow: disabling\n");
 806                                 return;
 807                         }
 808                         if ((sts & HIFN_7811_RNGSTS_RDY) == 0)
 809                                 break;
 810
 811                         /*
 812                          * There are at least two words in the RNG FIFO
 813                          * at this point.
 814                          */
 815                         num[0] = READ_REG_1(sc, HIFN_1_7811_RNGDAT);
 816                         num[1] = READ_REG_1(sc, HIFN_1_7811_RNGDAT);
 817                         /* NB: discard first data read */
 818                         if (sc->sc_rngfirst)
 819                                 sc->sc_rngfirst = 0;
 820                         else
 821                                 (*sc->sc_harvest)(sc->sc_rndtest,
 822                                         num, sizeof (num));
 823                 }
 824         } else {
 825                 num[0] = READ_REG_1(sc, HIFN_1_RNG_DATA);
 826
 827                 /* NB: discard first data read */
 828                 if (sc->sc_rngfirst)
 829                         sc->sc_rngfirst = 0;
 830                 else
 831                         (*sc->sc_harvest)(sc->sc_rndtest,
 832                                 num, sizeof (num[0]));
 833         }
 834
 835         callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc);
 836 #undef RANDOM_BITS
 837 }
 838
 839 static void
 840 hifn_puc_wait(struct hifn_softc *sc)
 841 {
 842         int i;
 843         int reg = HIFN_0_PUCTRL;
 844
 845         if (sc->sc_flags & HIFN_IS_7956) {
 846                 reg = HIFN_0_PUCTRL2;
 847         }
 848
 849         for (i = 5000; i > 0; i--) {
 850                 DELAY(1);
 851                 if (!(READ_REG_0(sc, reg) & HIFN_PUCTRL_RESET))
 852                         break;
 853         }
 854         if (!i)
 855                 device_printf(sc->sc_dev, "proc unit did not reset\n");
 856 }
 857
 858 /*
 859  * Reset the processing unit.
 860  */
 861 static void
 862 hifn_reset_puc(struct hifn_softc *sc)
 863 {
 864         /* Reset processing unit */
 865         int reg = HIFN_0_PUCTRL;
 866
 867         if (sc->sc_flags & HIFN_IS_7956) {
 868                 reg = HIFN_0_PUCTRL2;
 869         }
 870         WRITE_REG_0(sc, reg, HIFN_PUCTRL_DMAENA);
 871
 872         hifn_puc_wait(sc);
 873 }
 874
 875 /*
 876  * Set the Retry and TRDY registers; note that we set them to
 877  * zero because the 7811 locks up when forced to retry (section
 878  * 3.6 of "Specification Update SU-0014-04".  Not clear if we
 879  * should do this for all Hifn parts, but it doesn't seem to hurt.
 880  */
 881 static void
 882 hifn_set_retry(struct hifn_softc *sc)
 883 {
 884         /* NB: RETRY only responds to 8-bit reads/writes */
 885         pci_write_config(sc->sc_dev, HIFN_RETRY_TIMEOUT, 0, 1);
 886         pci_write_config(sc->sc_dev, HIFN_TRDY_TIMEOUT, 0, 1);
 887 }
 888
 889 /*
 890  * Resets the board.  Values in the regesters are left as is
 891  * from the reset (i.e. initial values are assigned elsewhere).
 892  */
 893 static void
 894 hifn_reset_board(struct hifn_softc *sc, int full)
 895 {
 896         u_int32_t reg;
 897
 898         /*
 899          * Set polling in the DMA configuration register to zero.  0x7 avoids
 900          * resetting the board and zeros out the other fields.
 901          */
 902         WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
 903             HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
 904
 905         /*
 906          * Now that polling has been disabled, we have to wait 1 ms
 907          * before resetting the board.
 908          */
 909         DELAY(1000);
 910
 911         /* Reset the DMA unit */
 912         if (full) {
 913                 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE);
 914                 DELAY(1000);
 915         } else {
 916                 WRITE_REG_1(sc, HIFN_1_DMA_CNFG,
 917                     HIFN_DMACNFG_MODE | HIFN_DMACNFG_MSTRESET);
 918                 hifn_reset_puc(sc);
 919         }
 920
 921         KASSERT(sc->sc_dma != NULL, ("hifn_reset_board: null DMA tag!"));
 922         bzero(sc->sc_dma, sizeof(*sc->sc_dma));
 923
 924         /* Bring dma unit out of reset */
 925         WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
 926             HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
 927
 928         hifn_puc_wait(sc);
 929         hifn_set_retry(sc);
 930
 931         if (sc->sc_flags & HIFN_IS_7811) {
 932                 for (reg = 0; reg < 1000; reg++) {
 933                         if (READ_REG_1(sc, HIFN_1_7811_MIPSRST) &
 934                             HIFN_MIPSRST_CRAMINIT)
 935                                 break;
 936                         DELAY(1000);
 937                 }
 938                 if (reg == 1000)
 939                         printf(": cram init timeout\n");
 940         } else {
 941           /* set up DMA configuration register #2 */
 942           /* turn off all PK and BAR0 swaps */
 943           WRITE_REG_1(sc, HIFN_1_DMA_CNFG2,
 944                       (3 << HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT)|
 945                       (3 << HIFN_DMACNFG2_INIT_READ_BURST_SHIFT)|
 946                       (2 << HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT)|
 947                       (2 << HIFN_DMACNFG2_TGT_READ_BURST_SHIFT));
 948         }
 949
 950 }
 951
 952 static u_int32_t
 953 hifn_next_signature(u_int32_t a, u_int cnt)
 954 {
 955         int i;
 956         u_int32_t v;
 957
 958         for (i = 0; i < cnt; i++) {
 959
 960                 /* get the parity */
 961                 v = a & 0x80080125;
 962                 v ^= v >> 16;
 963                 v ^= v >> 8;
 964                 v ^= v >> 4;
 965                 v ^= v >> 2;
 966                 v ^= v >> 1;
 967
 968                 a = (v & 1) ^ (a << 1);
 969         }
 970
 971         return a;
 972 }
 973
 974 struct pci2id {
 975         u_short         pci_vendor;
 976         u_short         pci_prod;
 977         char            card_id[13];
 978 };
 979 static struct pci2id pci2id[] = {
 980         {
 981                 PCI_VENDOR_HIFN,
 982                 PCI_PRODUCT_HIFN_7951,
 983                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 984                   0x00, 0x00, 0x00, 0x00, 0x00 }
 985         }, {
 986                 PCI_VENDOR_HIFN,
 987                 PCI_PRODUCT_HIFN_7955,
 988                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 989                   0x00, 0x00, 0x00, 0x00, 0x00 }
 990         }, {
 991                 PCI_VENDOR_HIFN,
 992                 PCI_PRODUCT_HIFN_7956,
 993                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 994                   0x00, 0x00, 0x00, 0x00, 0x00 }
 995         }, {
 996                 PCI_VENDOR_NETSEC,
 997                 PCI_PRODUCT_NETSEC_7751,
 998                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 999                   0x00, 0x00, 0x00, 0x00, 0x00 }
1000         }, {
1001                 PCI_VENDOR_INVERTEX,
1002                 PCI_PRODUCT_INVERTEX_AEON,
1003                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1004                   0x00, 0x00, 0x00, 0x00, 0x00 }
1005         }, {
1006                 PCI_VENDOR_HIFN,
1007                 PCI_PRODUCT_HIFN_7811,
1008                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1009                   0x00, 0x00, 0x00, 0x00, 0x00 }
1010         }, {
1011                 /*
1012                  * Other vendors share this PCI ID as well, such as
1013                  * http://www.powercrypt.com, and obviously they also
1014                  * use the same key.
1015                  */
1016                 PCI_VENDOR_HIFN,
1017                 PCI_PRODUCT_HIFN_7751,
1018                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1019                   0x00, 0x00, 0x00, 0x00, 0x00 }
1020         },
1021 };
1022
1023 /*
1024  * Checks to see if crypto is already enabled.  If crypto isn't enable,
1025  * "hifn_enable_crypto" is called to enable it.  The check is important,
1026  * as enabling crypto twice will lock the board.
1027  */
1028 static int
1029 hifn_enable_crypto(struct hifn_softc *sc)
1030 {
1031         u_int32_t dmacfg, ramcfg, encl, addr, i;
1032         char *offtbl = NULL;
1033
1034         for (i = 0; i < sizeof(pci2id)/sizeof(pci2id[0]); i++) {
1035                 if (pci2id[i].pci_vendor == pci_get_vendor(sc->sc_dev) &&
1036                     pci2id[i].pci_prod == pci_get_device(sc->sc_dev)) {
1037                         offtbl = pci2id[i].card_id;
1038                         break;
1039                 }
1040         }
1041         if (offtbl == NULL) {
1042                 device_printf(sc->sc_dev, "Unknown card!\n");
1043                 return (1);
1044         }
1045
1046         ramcfg = READ_REG_0(sc, HIFN_0_PUCNFG);
1047         dmacfg = READ_REG_1(sc, HIFN_1_DMA_CNFG);
1048
1049         /*
1050          * The RAM config register's encrypt level bit needs to be set before
1051          * every read performed on the encryption level register.
1052          */
1053         WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID);
1054
1055         encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA;
1056
1057         /*
1058          * Make sure we don't re-unlock.  Two unlocks kills chip until the
1059          * next reboot.
1060          */
1061         if (encl == HIFN_PUSTAT_ENA_1 || encl == HIFN_PUSTAT_ENA_2) {
1062 #ifdef HIFN_DEBUG
1063                 if (hifn_debug)
1064                         device_printf(sc->sc_dev,
1065                             "Strong crypto already enabled!\n");
1066 #endif
1067                 goto report;
1068         }
1069
1070         if (encl != 0 && encl != HIFN_PUSTAT_ENA_0) {
1071 #ifdef HIFN_DEBUG
1072                 if (hifn_debug)
1073                         device_printf(sc->sc_dev,
1074                               "Unknown encryption level 0x%x\n", encl);
1075 #endif
1076                 return 1;
1077         }
1078
1079         WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_UNLOCK |
1080             HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
1081         DELAY(1000);
1082         addr = READ_REG_1(sc, HIFN_UNLOCK_SECRET1);
1083         DELAY(1000);
1084         WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, 0);
1085         DELAY(1000);
1086
1087         for (i = 0; i <= 12; i++) {
1088                 addr = hifn_next_signature(addr, offtbl[i] + 0x101);
1089                 WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, addr);
1090
1091                 DELAY(1000);
1092         }
1093
1094         WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID);
1095         encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA;
1096
1097 #ifdef HIFN_DEBUG
1098         if (hifn_debug) {
1099                 if (encl != HIFN_PUSTAT_ENA_1 && encl != HIFN_PUSTAT_ENA_2)
1100                         device_printf(sc->sc_dev, "Engine is permanently "
1101                                 "locked until next system reset!\n");
1102                 else
1103                         device_printf(sc->sc_dev, "Engine enabled "
1104                                 "successfully!\n");
1105         }
1106 #endif
1107
1108 report:
1109         WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg);
1110         WRITE_REG_1(sc, HIFN_1_DMA_CNFG, dmacfg);
1111
1112         switch (encl) {
1113         case HIFN_PUSTAT_ENA_1:
1114         case HIFN_PUSTAT_ENA_2:
1115                 break;
1116         case HIFN_PUSTAT_ENA_0:
1117         default:
1118                 device_printf(sc->sc_dev, "disabled");
1119                 break;
1120         }
1121
1122         return 0;
1123 }
1124
1125 /*
1126  * Give initial values to the registers listed in the "Register Space"
1127  * section of the HIFN Software Development reference manual.
1128  */
1129 static void
1130 hifn_init_pci_registers(struct hifn_softc *sc)
1131 {
1132         /* write fixed values needed by the Initialization registers */
1133         WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA);
1134         WRITE_REG_0(sc, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD);
1135         WRITE_REG_0(sc, HIFN_0_PUIER, HIFN_PUIER_DSTOVER);
1136
1137         /* write all 4 ring address registers */
1138         WRITE_REG_1(sc, HIFN_1_DMA_CRAR, sc->sc_dma_physaddr +
1139             offsetof(struct hifn_dma, cmdr[0]));
1140         WRITE_REG_1(sc, HIFN_1_DMA_SRAR, sc->sc_dma_physaddr +
1141             offsetof(struct hifn_dma, srcr[0]));
1142         WRITE_REG_1(sc, HIFN_1_DMA_DRAR, sc->sc_dma_physaddr +
1143             offsetof(struct hifn_dma, dstr[0]));
1144         WRITE_REG_1(sc, HIFN_1_DMA_RRAR, sc->sc_dma_physaddr +
1145             offsetof(struct hifn_dma, resr[0]));
1146
1147         DELAY(2000);
1148
1149         /* write status register */
1150         WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1151             HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS |
1152             HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS |
1153             HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST |
1154             HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER |
1155             HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST |
1156             HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER |
1157             HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST |
1158             HIFN_DMACSR_S_WAIT |
1159             HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST |
1160             HIFN_DMACSR_C_WAIT |
1161             HIFN_DMACSR_ENGINE |
1162             ((sc->sc_flags & HIFN_HAS_PUBLIC) ?
1163                 HIFN_DMACSR_PUBDONE : 0) |
1164             ((sc->sc_flags & HIFN_IS_7811) ?
1165                 HIFN_DMACSR_ILLW | HIFN_DMACSR_ILLR : 0));
1166
1167         sc->sc_d_busy = sc->sc_r_busy = sc->sc_s_busy = sc->sc_c_busy = 0;
1168         sc->sc_dmaier |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT |
1169             HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER |
1170             HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT |
1171             ((sc->sc_flags & HIFN_IS_7811) ?
1172                 HIFN_DMAIER_ILLW | HIFN_DMAIER_ILLR : 0);
1173         sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT;
1174         WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
1175
1176
1177         if (sc->sc_flags & HIFN_IS_7956) {
1178                 u_int32_t pll;
1179
1180                 WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING |
1181                     HIFN_PUCNFG_TCALLPHASES |
1182                     HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32);
1183
1184                 /* turn off the clocks and insure bypass is set */
1185                 pll = READ_REG_1(sc, HIFN_1_PLL);
1186                 pll = (pll &~ (HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL))
1187                   | HIFN_PLL_BP | HIFN_PLL_MBSET;
1188                 WRITE_REG_1(sc, HIFN_1_PLL, pll);
1189                 DELAY(10*1000);         /* 10ms */
1190
1191                 /* change configuration */
1192                 pll = (pll &~ HIFN_PLL_CONFIG) | sc->sc_pllconfig;
1193                 WRITE_REG_1(sc, HIFN_1_PLL, pll);
1194                 DELAY(10*1000);         /* 10ms */
1195
1196                 /* disable bypass */
1197                 pll &= ~HIFN_PLL_BP;
1198                 WRITE_REG_1(sc, HIFN_1_PLL, pll);
1199                 /* enable clocks with new configuration */
1200                 pll |= HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL;
1201                 WRITE_REG_1(sc, HIFN_1_PLL, pll);
1202         } else {
1203                 WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING |
1204                     HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES |
1205                     HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 |
1206                     (sc->sc_drammodel ? HIFN_PUCNFG_DRAM : HIFN_PUCNFG_SRAM));
1207         }
1208
1209         WRITE_REG_0(sc, HIFN_0_PUISR, HIFN_PUISR_DSTOVER);
1210         WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
1211             HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST |
1212             ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) |
1213             ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL));
1214 }
1215
1216 /*
1217  * The maximum number of sessions supported by the card
1218  * is dependent on the amount of context ram, which
1219  * encryption algorithms are enabled, and how compression
1220  * is configured.  This should be configured before this
1221  * routine is called.
1222  */
1223 static void
1224 hifn_sessions(struct hifn_softc *sc)
1225 {
1226         u_int32_t pucnfg;
1227         int ctxsize;
1228
1229         pucnfg = READ_REG_0(sc, HIFN_0_PUCNFG);
1230
1231         if (pucnfg & HIFN_PUCNFG_COMPSING) {
1232                 if (pucnfg & HIFN_PUCNFG_ENCCNFG)
1233                         ctxsize = 128;
1234                 else
1235                         ctxsize = 512;
1236                 /*
1237                  * 7955/7956 has internal context memory of 32K
1238                  */
1239                 if (sc->sc_flags & HIFN_IS_7956)
1240                         sc->sc_maxses = 32768 / ctxsize;
1241                 else
1242                         sc->sc_maxses = 1 +
1243                             ((sc->sc_ramsize - 32768) / ctxsize);
1244         } else
1245                 sc->sc_maxses = sc->sc_ramsize / 16384;
1246
1247         if (sc->sc_maxses > 2048)
1248                 sc->sc_maxses = 2048;
1249 }
1250
1251 /*
1252  * Determine ram type (sram or dram).  Board should be just out of a reset
1253  * state when this is called.
1254  */
1255 static int
1256 hifn_ramtype(struct hifn_softc *sc)
1257 {
1258         u_int8_t data[8], dataexpect[8];
1259         int i;
1260
1261         for (i = 0; i < sizeof(data); i++)
1262                 data[i] = dataexpect[i] = 0x55;
1263         if (hifn_writeramaddr(sc, 0, data))
1264                 return (-1);
1265         if (hifn_readramaddr(sc, 0, data))
1266                 return (-1);
1267         if (bcmp(data, dataexpect, sizeof(data)) != 0) {
1268                 sc->sc_drammodel = 1;
1269                 return (0);
1270         }
1271
1272         for (i = 0; i < sizeof(data); i++)
1273                 data[i] = dataexpect[i] = 0xaa;
1274         if (hifn_writeramaddr(sc, 0, data))
1275                 return (-1);
1276         if (hifn_readramaddr(sc, 0, data))
1277                 return (-1);
1278         if (bcmp(data, dataexpect, sizeof(data)) != 0) {
1279                 sc->sc_drammodel = 1;
1280                 return (0);
1281         }
1282
1283         return (0);
1284 }
1285
1286 #define HIFN_SRAM_MAX           (32 << 20)
1287 #define HIFN_SRAM_STEP_SIZE     16384
1288 #define HIFN_SRAM_GRANULARITY   (HIFN_SRAM_MAX / HIFN_SRAM_STEP_SIZE)
1289
1290 static int
1291 hifn_sramsize(struct hifn_softc *sc)
1292 {
1293         u_int32_t a;
1294         u_int8_t data[8];
1295         u_int8_t dataexpect[sizeof(data)];
1296         int32_t i;
1297
1298         for (i = 0; i < sizeof(data); i++)
1299                 data[i] = dataexpect[i] = i ^ 0x5a;
1300
1301         for (i = HIFN_SRAM_GRANULARITY - 1; i >= 0; i--) {
1302                 a = i * HIFN_SRAM_STEP_SIZE;
1303                 bcopy(&i, data, sizeof(i));
1304                 hifn_writeramaddr(sc, a, data);
1305         }
1306
1307         for (i = 0; i < HIFN_SRAM_GRANULARITY; i++) {
1308                 a = i * HIFN_SRAM_STEP_SIZE;
1309                 bcopy(&i, dataexpect, sizeof(i));
1310                 if (hifn_readramaddr(sc, a, data) < 0)
1311                         return (0);
1312                 if (bcmp(data, dataexpect, sizeof(data)) != 0)
1313                         return (0);
1314                 sc->sc_ramsize = a + HIFN_SRAM_STEP_SIZE;
1315         }
1316
1317         return (0);
1318 }
1319
1320 /*
1321  * XXX For dram boards, one should really try all of the
1322  * HIFN_PUCNFG_DSZ_*'s.  This just assumes that PUCNFG
1323  * is already set up correctly.
1324  */
1325 static int
1326 hifn_dramsize(struct hifn_softc *sc)
1327 {
1328         u_int32_t cnfg;
1329
1330         if (sc->sc_flags & HIFN_IS_7956) {
1331                 /*
1332                  * 7955/7956 have a fixed internal ram of only 32K.
1333                  */
1334                 sc->sc_ramsize = 32768;
1335         } else {
1336                 cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) &
1337                     HIFN_PUCNFG_DRAMMASK;
1338                 sc->sc_ramsize = 1 << ((cnfg >> 13) + 18);
1339         }
1340         return (0);
1341 }
1342
1343 static void
1344 hifn_alloc_slot(struct hifn_softc *sc, int *cmdp, int *srcp, int *dstp, int *resp)
1345 {
1346         struct hifn_dma *dma = sc->sc_dma;
1347
1348         if (sc->sc_cmdi == HIFN_D_CMD_RSIZE) {
1349                 sc->sc_cmdi = 0;
1350                 dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID |
1351                     HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1352                 HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE,
1353                     BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1354         }
1355         *cmdp = sc->sc_cmdi++;
1356         sc->sc_cmdk = sc->sc_cmdi;
1357
1358         if (sc->sc_srci == HIFN_D_SRC_RSIZE) {
1359                 sc->sc_srci = 0;
1360                 dma->srcr[HIFN_D_SRC_RSIZE].l = htole32(HIFN_D_VALID |
1361                     HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1362                 HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE,
1363                     BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1364         }
1365         *srcp = sc->sc_srci++;
1366         sc->sc_srck = sc->sc_srci;
1367
1368         if (sc->sc_dsti == HIFN_D_DST_RSIZE) {
1369                 sc->sc_dsti = 0;
1370                 dma->dstr[HIFN_D_DST_RSIZE].l = htole32(HIFN_D_VALID |
1371                     HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1372                 HIFN_DSTR_SYNC(sc, HIFN_D_DST_RSIZE,
1373                     BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1374         }
1375         *dstp = sc->sc_dsti++;
1376         sc->sc_dstk = sc->sc_dsti;
1377
1378         if (sc->sc_resi == HIFN_D_RES_RSIZE) {
1379                 sc->sc_resi = 0;
1380                 dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID |
1381                     HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1382                 HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE,
1383                     BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1384         }
1385         *resp = sc->sc_resi++;
1386         sc->sc_resk = sc->sc_resi;
1387 }
1388
1389 static int
1390 hifn_writeramaddr(struct hifn_softc *sc, int addr, u_int8_t *data)
1391 {
1392         struct hifn_dma *dma = sc->sc_dma;
1393         hifn_base_command_t wc;
1394         const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ;
1395         int r, cmdi, resi, srci, dsti;
1396
1397         wc.masks = htole16(3 << 13);
1398         wc.session_num = htole16(addr >> 14);
1399         wc.total_source_count = htole16(8);
1400         wc.total_dest_count = htole16(addr & 0x3fff);
1401
1402         hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi);
1403
1404         WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1405             HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA |
1406             HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA);
1407
1408         /* build write command */
1409         bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND);
1410         *(hifn_base_command_t *)dma->command_bufs[cmdi] = wc;
1411         bcopy(data, &dma->test_src, sizeof(dma->test_src));
1412
1413         dma->srcr[srci].p = htole32(sc->sc_dma_physaddr
1414             + offsetof(struct hifn_dma, test_src));
1415         dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr
1416             + offsetof(struct hifn_dma, test_dst));
1417
1418         dma->cmdr[cmdi].l = htole32(16 | masks);
1419         dma->srcr[srci].l = htole32(8 | masks);
1420         dma->dstr[dsti].l = htole32(4 | masks);
1421         dma->resr[resi].l = htole32(4 | masks);
1422
1423         bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1424             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1425
1426         for (r = 10000; r >= 0; r--) {
1427                 DELAY(10);
1428                 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1429                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1430                 if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0)
1431                         break;
1432                 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1433                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1434         }
1435         if (r == 0) {
1436                 device_printf(sc->sc_dev, "writeramaddr -- "
1437                     "result[%d](addr %d) still valid\n", resi, addr);
1438                 r = -1;
1439                 return (-1);
1440         } else
1441                 r = 0;
1442
1443         WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1444             HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS |
1445             HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS);
1446
1447         return (r);
1448 }
1449
1450 static int
1451 hifn_readramaddr(struct hifn_softc *sc, int addr, u_int8_t *data)
1452 {
1453         struct hifn_dma *dma = sc->sc_dma;
1454         hifn_base_command_t rc;
1455         const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ;
1456         int r, cmdi, srci, dsti, resi;
1457
1458         rc.masks = htole16(2 << 13);
1459         rc.session_num = htole16(addr >> 14);
1460         rc.total_source_count = htole16(addr & 0x3fff);
1461         rc.total_dest_count = htole16(8);
1462
1463         hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi);
1464
1465         WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1466             HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA |
1467             HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA);
1468
1469         bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND);
1470         *(hifn_base_command_t *)dma->command_bufs[cmdi] = rc;
1471
1472         dma->srcr[srci].p = htole32(sc->sc_dma_physaddr +
1473             offsetof(struct hifn_dma, test_src));
1474         dma->test_src = 0;
1475         dma->dstr[dsti].p =  htole32(sc->sc_dma_physaddr +
1476             offsetof(struct hifn_dma, test_dst));
1477         dma->test_dst = 0;
1478         dma->cmdr[cmdi].l = htole32(8 | masks);
1479         dma->srcr[srci].l = htole32(8 | masks);
1480         dma->dstr[dsti].l = htole32(8 | masks);
1481         dma->resr[resi].l = htole32(HIFN_MAX_RESULT | masks);
1482
1483         bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1484             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1485
1486         for (r = 10000; r >= 0; r--) {
1487                 DELAY(10);
1488                 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1489                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1490                 if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0)
1491                         break;
1492                 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1493                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1494         }
1495         if (r == 0) {
1496                 device_printf(sc->sc_dev, "readramaddr -- "
1497                     "result[%d](addr %d) still valid\n", resi, addr);
1498                 r = -1;
1499         } else {
1500                 r = 0;
1501                 bcopy(&dma->test_dst, data, sizeof(dma->test_dst));
1502         }
1503
1504         WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1505             HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS |
1506             HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS);
1507
1508         return (r);
1509 }
1510
1511 /*
1512  * Initialize the descriptor rings.
1513  */
1514 static void
1515 hifn_init_dma(struct hifn_softc *sc)
1516 {
1517         struct hifn_dma *dma = sc->sc_dma;
1518         int i;
1519
1520         hifn_set_retry(sc);
1521
1522         /* initialize static pointer values */
1523         for (i = 0; i < HIFN_D_CMD_RSIZE; i++)
1524                 dma->cmdr[i].p = htole32(sc->sc_dma_physaddr +
1525                     offsetof(struct hifn_dma, command_bufs[i][0]));
1526         for (i = 0; i < HIFN_D_RES_RSIZE; i++)
1527                 dma->resr[i].p = htole32(sc->sc_dma_physaddr +
1528                     offsetof(struct hifn_dma, result_bufs[i][0]));
1529
1530         dma->cmdr[HIFN_D_CMD_RSIZE].p =
1531             htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, cmdr[0]));
1532         dma->srcr[HIFN_D_SRC_RSIZE].p =
1533             htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, srcr[0]));
1534         dma->dstr[HIFN_D_DST_RSIZE].p =
1535             htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, dstr[0]));
1536         dma->resr[HIFN_D_RES_RSIZE].p =
1537             htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, resr[0]));
1538
1539         sc->sc_cmdu = sc->sc_srcu = sc->sc_dstu = sc->sc_resu = 0;
1540         sc->sc_cmdi = sc->sc_srci = sc->sc_dsti = sc->sc_resi = 0;
1541         sc->sc_cmdk = sc->sc_srck = sc->sc_dstk = sc->sc_resk = 0;
1542 }
1543
1544 /*
1545  * Writes out the raw command buffer space.  Returns the
1546  * command buffer size.
1547  */
1548 static u_int
1549 hifn_write_command(struct hifn_command *cmd, u_int8_t *buf)
1550 {
1551         u_int8_t *buf_pos;
1552         hifn_base_command_t *base_cmd;
1553         hifn_mac_command_t *mac_cmd;
1554         hifn_crypt_command_t *cry_cmd;
1555         int using_mac, using_crypt, len, ivlen;
1556         u_int32_t dlen, slen;
1557
1558         buf_pos = buf;
1559         using_mac = cmd->base_masks & HIFN_BASE_CMD_MAC;
1560         using_crypt = cmd->base_masks & HIFN_BASE_CMD_CRYPT;
1561
1562         base_cmd = (hifn_base_command_t *)buf_pos;
1563         base_cmd->masks = htole16(cmd->base_masks);
1564         slen = cmd->src_mapsize;
1565         if (cmd->sloplen)
1566                 dlen = cmd->dst_mapsize - cmd->sloplen + sizeof(u_int32_t);
1567         else
1568                 dlen = cmd->dst_mapsize;
1569         base_cmd->total_source_count = htole16(slen & HIFN_BASE_CMD_LENMASK_LO);
1570         base_cmd->total_dest_count = htole16(dlen & HIFN_BASE_CMD_LENMASK_LO);
1571         dlen >>= 16;
1572         slen >>= 16;
1573         base_cmd->session_num = htole16(
1574             ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) |
1575             ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M));
1576         buf_pos += sizeof(hifn_base_command_t);
1577
1578         if (using_mac) {
1579                 mac_cmd = (hifn_mac_command_t *)buf_pos;
1580                 dlen = cmd->maccrd->crd_len;
1581                 mac_cmd->source_count = htole16(dlen & 0xffff);
1582                 dlen >>= 16;
1583                 mac_cmd->masks = htole16(cmd->mac_masks |
1584                     ((dlen << HIFN_MAC_CMD_SRCLEN_S) & HIFN_MAC_CMD_SRCLEN_M));
1585                 mac_cmd->header_skip = htole16(cmd->maccrd->crd_skip);
1586                 mac_cmd->reserved = 0;
1587                 buf_pos += sizeof(hifn_mac_command_t);
1588         }
1589
1590         if (using_crypt) {
1591                 cry_cmd = (hifn_crypt_command_t *)buf_pos;
1592                 dlen = cmd->enccrd->crd_len;
1593                 cry_cmd->source_count = htole16(dlen & 0xffff);
1594                 dlen >>= 16;
1595                 cry_cmd->masks = htole16(cmd->cry_masks |
1596                     ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & HIFN_CRYPT_CMD_SRCLEN_M));
1597                 cry_cmd->header_skip = htole16(cmd->enccrd->crd_skip);
1598                 cry_cmd->reserved = 0;
1599                 buf_pos += sizeof(hifn_crypt_command_t);
1600         }
1601
1602         if (using_mac && cmd->mac_masks & HIFN_MAC_CMD_NEW_KEY) {
1603                 bcopy(cmd->mac, buf_pos, HIFN_MAC_KEY_LENGTH);
1604                 buf_pos += HIFN_MAC_KEY_LENGTH;
1605         }
1606
1607         if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_KEY) {
1608                 switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) {
1609                 case HIFN_CRYPT_CMD_ALG_3DES:
1610                         bcopy(cmd->ck, buf_pos, HIFN_3DES_KEY_LENGTH);
1611                         buf_pos += HIFN_3DES_KEY_LENGTH;
1612                         break;
1613                 case HIFN_CRYPT_CMD_ALG_DES:
1614                         bcopy(cmd->ck, buf_pos, HIFN_DES_KEY_LENGTH);
1615                         buf_pos += HIFN_DES_KEY_LENGTH;
1616                         break;
1617                 case HIFN_CRYPT_CMD_ALG_RC4:
1618                         len = 256;
1619                         do {
1620                                 int clen;
1621
1622                                 clen = MIN(cmd->cklen, len);
1623                                 bcopy(cmd->ck, buf_pos, clen);
1624                                 len -= clen;
1625                                 buf_pos += clen;
1626                         } while (len > 0);
1627                         bzero(buf_pos, 4);
1628                         buf_pos += 4;
1629                         break;
1630                 case HIFN_CRYPT_CMD_ALG_AES:
1631                         /*
1632                          * AES keys are variable 128, 192 and
1633                          * 256 bits (16, 24 and 32 bytes).
1634                          */
1635                         bcopy(cmd->ck, buf_pos, cmd->cklen);
1636                         buf_pos += cmd->cklen;
1637                         break;
1638                 }
1639         }
1640
1641         if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_IV) {
1642                 switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) {
1643                 case HIFN_CRYPT_CMD_ALG_AES:
1644                         ivlen = HIFN_AES_IV_LENGTH;
1645                         break;
1646                 default:
1647                         ivlen = HIFN_IV_LENGTH;
1648                         break;
1649                 }
1650                 bcopy(cmd->iv, buf_pos, ivlen);
1651                 buf_pos += ivlen;
1652         }
1653
1654         if ((cmd->base_masks & (HIFN_BASE_CMD_MAC|HIFN_BASE_CMD_CRYPT)) == 0) {
1655                 bzero(buf_pos, 8);
1656                 buf_pos += 8;
1657         }
1658
1659         return (buf_pos - buf);
1660 }
1661
1662 static int
1663 hifn_dmamap_aligned(struct hifn_operand *op)
1664 {
1665         int i;
1666
1667         for (i = 0; i < op->nsegs; i++) {
1668                 if (op->segs[i].ds_addr & 3)
1669                         return (0);
1670                 if ((i != (op->nsegs - 1)) && (op->segs[i].ds_len & 3))
1671                         return (0);
1672         }
1673         return (1);
1674 }
1675
1676 static __inline int
1677 hifn_dmamap_dstwrap(struct hifn_softc *sc, int idx)
1678 {
1679         struct hifn_dma *dma = sc->sc_dma;
1680
1681         if (++idx == HIFN_D_DST_RSIZE) {
1682                 dma->dstr[idx].l = htole32(HIFN_D_VALID | HIFN_D_JUMP |
1683                     HIFN_D_MASKDONEIRQ);
1684                 HIFN_DSTR_SYNC(sc, idx,
1685                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1686                 idx = 0;
1687         }
1688         return (idx);
1689 }
1690
1691 static int
1692 hifn_dmamap_load_dst(struct hifn_softc *sc, struct hifn_command *cmd)
1693 {
1694         struct hifn_dma *dma = sc->sc_dma;
1695         struct hifn_operand *dst = &cmd->dst;
1696         u_int32_t p, l;
1697         int idx, used = 0, i;
1698
1699         idx = sc->sc_dsti;
1700         for (i = 0; i < dst->nsegs - 1; i++) {
1701                 dma->dstr[idx].p = htole32(dst->segs[i].ds_addr);
1702                 dma->dstr[idx].l = htole32(HIFN_D_VALID |
1703                     HIFN_D_MASKDONEIRQ | dst->segs[i].ds_len);
1704                 HIFN_DSTR_SYNC(sc, idx,
1705                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1706                 used++;
1707
1708                 idx = hifn_dmamap_dstwrap(sc, idx);
1709         }
1710
1711         if (cmd->sloplen == 0) {
1712                 p = dst->segs[i].ds_addr;
1713                 l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST |
1714                     dst->segs[i].ds_len;
1715         } else {
1716                 p = sc->sc_dma_physaddr +
1717                     offsetof(struct hifn_dma, slop[cmd->slopidx]);
1718                 l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST |
1719                     sizeof(u_int32_t);
1720
1721                 if ((dst->segs[i].ds_len - cmd->sloplen) != 0) {
1722                         dma->dstr[idx].p = htole32(dst->segs[i].ds_addr);
1723                         dma->dstr[idx].l = htole32(HIFN_D_VALID |
1724                             HIFN_D_MASKDONEIRQ |
1725                             (dst->segs[i].ds_len - cmd->sloplen));
1726                         HIFN_DSTR_SYNC(sc, idx,
1727                             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1728                         used++;
1729
1730                         idx = hifn_dmamap_dstwrap(sc, idx);
1731                 }
1732         }
1733         dma->dstr[idx].p = htole32(p);
1734         dma->dstr[idx].l = htole32(l);
1735         HIFN_DSTR_SYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1736         used++;
1737
1738         idx = hifn_dmamap_dstwrap(sc, idx);
1739
1740         sc->sc_dsti = idx;
1741         sc->sc_dstu += used;
1742         return (idx);
1743 }
1744
1745 static __inline int
1746 hifn_dmamap_srcwrap(struct hifn_softc *sc, int idx)
1747 {
1748         struct hifn_dma *dma = sc->sc_dma;
1749
1750         if (++idx == HIFN_D_SRC_RSIZE) {
1751                 dma->srcr[idx].l = htole32(HIFN_D_VALID |
1752                     HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1753                 HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE,
1754                     BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1755                 idx = 0;
1756         }
1757         return (idx);
1758 }
1759
1760 static int
1761 hifn_dmamap_load_src(struct hifn_softc *sc, struct hifn_command *cmd)
1762 {
1763         struct hifn_dma *dma = sc->sc_dma;
1764         struct hifn_operand *src = &cmd->src;
1765         int idx, i;
1766         u_int32_t last = 0;
1767
1768         idx = sc->sc_srci;
1769         for (i = 0; i < src->nsegs; i++) {
1770                 if (i == src->nsegs - 1)
1771                         last = HIFN_D_LAST;
1772
1773                 dma->srcr[idx].p = htole32(src->segs[i].ds_addr);
1774                 dma->srcr[idx].l = htole32(src->segs[i].ds_len |
1775                     HIFN_D_VALID | HIFN_D_MASKDONEIRQ | last);
1776                 HIFN_SRCR_SYNC(sc, idx,
1777                     BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1778
1779                 idx = hifn_dmamap_srcwrap(sc, idx);
1780         }
1781         sc->sc_srci = idx;
1782         sc->sc_srcu += src->nsegs;
1783         return (idx);
1784 }
1785
1786 static void
1787 hifn_op_cb(void* arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error)
1788 {
1789         struct hifn_operand *op = arg;
1790
1791         KASSERT(nsegs <= MAX_SCATTER,
1792                 ("hifn_op_cb: too many DMA segments (%u > %u) "
1793                  "returned when mapping operand", nsegs, MAX_SCATTER));
1794         op->mapsize = mapsize;
1795         op->nsegs = nsegs;
1796         bcopy(seg, op->segs, nsegs * sizeof (seg[0]));
1797 }
1798
1799 static int
1800 hifn_crypto(
1801         struct hifn_softc *sc,
1802         struct hifn_command *cmd,
1803         struct cryptop *crp,
1804         int hint)
1805 {
1806         struct  hifn_dma *dma = sc->sc_dma;
1807         u_int32_t cmdlen, csr;
1808         int cmdi, resi, err = 0;
1809
1810         /*
1811          * need 1 cmd, and 1 res
1812          *
1813          * NB: check this first since it's easy.
1814          */
1815         HIFN_LOCK(sc);
1816         if ((sc->sc_cmdu + 1) > HIFN_D_CMD_RSIZE ||
1817             (sc->sc_resu + 1) > HIFN_D_RES_RSIZE) {
1818 #ifdef HIFN_DEBUG
1819                 if (hifn_debug) {
1820                         device_printf(sc->sc_dev,
1821                                 "cmd/result exhaustion, cmdu %u resu %u\n",
1822                                 sc->sc_cmdu, sc->sc_resu);
1823                 }
1824 #endif
1825                 hifnstats.hst_nomem_cr++;
1826                 HIFN_UNLOCK(sc);
1827                 return (ERESTART);
1828         }
1829
1830         if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->src_map)) {
1831                 hifnstats.hst_nomem_map++;
1832                 HIFN_UNLOCK(sc);
1833                 return (ENOMEM);
1834         }
1835
1836         if (crp->crp_flags & CRYPTO_F_IMBUF) {
1837                 if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->src_map,
1838                     cmd->src_m, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) {
1839                         hifnstats.hst_nomem_load++;
1840                         err = ENOMEM;
1841                         goto err_srcmap1;
1842                 }
1843         } else if (crp->crp_flags & CRYPTO_F_IOV) {
1844                 if (bus_dmamap_load_uio(sc->sc_dmat, cmd->src_map,
1845                     cmd->src_io, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) {
1846                         hifnstats.hst_nomem_load++;
1847                         err = ENOMEM;
1848                         goto err_srcmap1;
1849                 }
1850         } else {
1851                 err = EINVAL;
1852                 goto err_srcmap1;
1853         }
1854
1855         if (hifn_dmamap_aligned(&cmd->src)) {
1856                 cmd->sloplen = cmd->src_mapsize & 3;
1857                 cmd->dst = cmd->src;
1858         } else {
1859                 if (crp->crp_flags & CRYPTO_F_IOV) {
1860                         err = EINVAL;
1861                         goto err_srcmap;
1862                 } else if (crp->crp_flags & CRYPTO_F_IMBUF) {
1863                         int totlen, len;
1864                         struct mbuf *m, *m0, *mlast;
1865
1866                         KASSERT(cmd->dst_m == cmd->src_m,
1867                                 ("hifn_crypto: dst_m initialized improperly"));
1868                         hifnstats.hst_unaligned++;
1869                         /*
1870                          * Source is not aligned on a longword boundary.
1871                          * Copy the data to insure alignment.  If we fail
1872                          * to allocate mbufs or clusters while doing this
1873                          * we return ERESTART so the operation is requeued
1874                          * at the crypto later, but only if there are
1875                          * ops already posted to the hardware; otherwise we
1876                          * have no guarantee that we'll be re-entered.
1877                          */
1878                         totlen = cmd->src_mapsize;
1879                         if (cmd->src_m->m_flags & M_PKTHDR) {
1880                                 len = MHLEN;
1881                                 MGETHDR(m0, M_NOWAIT, MT_DATA);
1882                                 if (m0 && !m_dup_pkthdr(m0, cmd->src_m, M_NOWAIT)) {
1883                                         m_free(m0);
1884                                         m0 = NULL;
1885                                 }
1886                         } else {
1887                                 len = MLEN;
1888                                 MGET(m0, M_NOWAIT, MT_DATA);
1889                         }
1890                         if (m0 == NULL) {
1891                                 hifnstats.hst_nomem_mbuf++;
1892                                 err = sc->sc_cmdu ? ERESTART : ENOMEM;
1893                                 goto err_srcmap;
1894                         }
1895                         if (totlen >= MINCLSIZE) {
1896                                 MCLGET(m0, M_NOWAIT);
1897                                 if ((m0->m_flags & M_EXT) == 0) {
1898                                         hifnstats.hst_nomem_mcl++;
1899                                         err = sc->sc_cmdu ? ERESTART : ENOMEM;
1900                                         m_freem(m0);
1901                                         goto err_srcmap;
1902                                 }
1903                                 len = MCLBYTES;
1904                         }
1905                         totlen -= len;
1906                         m0->m_pkthdr.len = m0->m_len = len;
1907                         mlast = m0;
1908
1909                         while (totlen > 0) {
1910                                 MGET(m, M_NOWAIT, MT_DATA);
1911                                 if (m == NULL) {
1912                                         hifnstats.hst_nomem_mbuf++;
1913                                         err = sc->sc_cmdu ? ERESTART : ENOMEM;
1914                                         m_freem(m0);
1915                                         goto err_srcmap;
1916                                 }
1917                                 len = MLEN;
1918                                 if (totlen >= MINCLSIZE) {
1919                                         MCLGET(m, M_NOWAIT);
1920                                         if ((m->m_flags & M_EXT) == 0) {
1921                                                 hifnstats.hst_nomem_mcl++;
1922                                                 err = sc->sc_cmdu ? ERESTART : ENOMEM;
1923                                                 mlast->m_next = m;
1924                                                 m_freem(m0);
1925                                                 goto err_srcmap;
1926                                         }
1927                                         len = MCLBYTES;
1928                                 }
1929
1930                                 m->m_len = len;
1931                                 m0->m_pkthdr.len += len;
1932                                 totlen -= len;
1933
1934                                 mlast->m_next = m;
1935                                 mlast = m;
1936                         }
1937                         cmd->dst_m = m0;
1938                 }
1939         }
1940
1941         if (cmd->dst_map == NULL) {
1942                 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->dst_map)) {
1943                         hifnstats.hst_nomem_map++;
1944                         err = ENOMEM;
1945                         goto err_srcmap;
1946                 }
1947                 if (crp->crp_flags & CRYPTO_F_IMBUF) {
1948                         if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->dst_map,
1949                             cmd->dst_m, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) {
1950                                 hifnstats.hst_nomem_map++;
1951                                 err = ENOMEM;
1952                                 goto err_dstmap1;
1953                         }
1954                 } else if (crp->crp_flags & CRYPTO_F_IOV) {
1955                         if (bus_dmamap_load_uio(sc->sc_dmat, cmd->dst_map,
1956                             cmd->dst_io, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) {
1957                                 hifnstats.hst_nomem_load++;
1958                                 err = ENOMEM;
1959                                 goto err_dstmap1;
1960                         }
1961                 }
1962         }
1963
1964 #ifdef HIFN_DEBUG
1965         if (hifn_debug) {
1966                 device_printf(sc->sc_dev,
1967                     "Entering cmd: stat %8x ien %8x u %d/%d/%d/%d n %d/%d\n",
1968                     READ_REG_1(sc, HIFN_1_DMA_CSR),
1969                     READ_REG_1(sc, HIFN_1_DMA_IER),
1970                     sc->sc_cmdu, sc->sc_srcu, sc->sc_dstu, sc->sc_resu,
1971                     cmd->src_nsegs, cmd->dst_nsegs);
1972         }
1973 #endif
1974
1975         if (cmd->src_map == cmd->dst_map) {
1976                 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
1977                     BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1978         } else {
1979                 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
1980                     BUS_DMASYNC_PREWRITE);
1981                 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map,
1982                     BUS_DMASYNC_PREREAD);
1983         }
1984
1985         /*
1986          * need N src, and N dst
1987          */
1988         if ((sc->sc_srcu + cmd->src_nsegs) > HIFN_D_SRC_RSIZE ||
1989             (sc->sc_dstu + cmd->dst_nsegs + 1) > HIFN_D_DST_RSIZE) {
1990 #ifdef HIFN_DEBUG
1991                 if (hifn_debug) {
1992                         device_printf(sc->sc_dev,
1993                                 "src/dst exhaustion, srcu %u+%u dstu %u+%u\n",
1994                                 sc->sc_srcu, cmd->src_nsegs,
1995                                 sc->sc_dstu, cmd->dst_nsegs);
1996                 }
1997 #endif
1998                 hifnstats.hst_nomem_sd++;
1999                 err = ERESTART;
2000                 goto err_dstmap;
2001         }
2002
2003         if (sc->sc_cmdi == HIFN_D_CMD_RSIZE) {
2004                 sc->sc_cmdi = 0;
2005                 dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID |
2006                     HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
2007                 HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE,
2008                     BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2009         }
2010         cmdi = sc->sc_cmdi++;
2011         cmdlen = hifn_write_command(cmd, dma->command_bufs[cmdi]);
2012         HIFN_CMD_SYNC(sc, cmdi, BUS_DMASYNC_PREWRITE);
2013
2014         /* .p for command/result already set */
2015         dma->cmdr[cmdi].l = htole32(cmdlen | HIFN_D_VALID | HIFN_D_LAST |
2016             HIFN_D_MASKDONEIRQ);
2017         HIFN_CMDR_SYNC(sc, cmdi,
2018             BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2019         sc->sc_cmdu++;
2020
2021         /*
2022          * We don't worry about missing an interrupt (which a "command wait"
2023          * interrupt salvages us from), unless there is more than one command
2024          * in the queue.
2025          */
2026         if (sc->sc_cmdu > 1) {
2027                 sc->sc_dmaier |= HIFN_DMAIER_C_WAIT;
2028                 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
2029         }
2030
2031         hifnstats.hst_ipackets++;
2032         hifnstats.hst_ibytes += cmd->src_mapsize;
2033
2034         hifn_dmamap_load_src(sc, cmd);
2035
2036         /*
2037          * Unlike other descriptors, we don't mask done interrupt from
2038          * result descriptor.
2039          */
2040 #ifdef HIFN_DEBUG
2041         if (hifn_debug)
2042                 printf("load res\n");
2043 #endif
2044         if (sc->sc_resi == HIFN_D_RES_RSIZE) {
2045                 sc->sc_resi = 0;
2046                 dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID |
2047                     HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
2048                 HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE,
2049                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2050         }
2051         resi = sc->sc_resi++;
2052         KASSERT(sc->sc_hifn_commands[resi] == NULL,
2053                 ("hifn_crypto: command slot %u busy", resi));
2054         sc->sc_hifn_commands[resi] = cmd;
2055         HIFN_RES_SYNC(sc, resi, BUS_DMASYNC_PREREAD);
2056         if ((hint & CRYPTO_HINT_MORE) && sc->sc_curbatch < hifn_maxbatch) {
2057                 dma->resr[resi].l = htole32(HIFN_MAX_RESULT |
2058                     HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ);
2059                 sc->sc_curbatch++;
2060                 if (sc->sc_curbatch > hifnstats.hst_maxbatch)
2061                         hifnstats.hst_maxbatch = sc->sc_curbatch;
2062                 hifnstats.hst_totbatch++;
2063         } else {
2064                 dma->resr[resi].l = htole32(HIFN_MAX_RESULT |
2065                     HIFN_D_VALID | HIFN_D_LAST);
2066                 sc->sc_curbatch = 0;
2067         }
2068         HIFN_RESR_SYNC(sc, resi,
2069             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2070         sc->sc_resu++;
2071
2072         if (cmd->sloplen)
2073                 cmd->slopidx = resi;
2074
2075         hifn_dmamap_load_dst(sc, cmd);
2076
2077         csr = 0;
2078         if (sc->sc_c_busy == 0) {
2079                 csr |= HIFN_DMACSR_C_CTRL_ENA;
2080                 sc->sc_c_busy = 1;
2081         }
2082         if (sc->sc_s_busy == 0) {
2083                 csr |= HIFN_DMACSR_S_CTRL_ENA;
2084                 sc->sc_s_busy = 1;
2085         }
2086         if (sc->sc_r_busy == 0) {
2087                 csr |= HIFN_DMACSR_R_CTRL_ENA;
2088                 sc->sc_r_busy = 1;
2089         }
2090         if (sc->sc_d_busy == 0) {
2091                 csr |= HIFN_DMACSR_D_CTRL_ENA;
2092                 sc->sc_d_busy = 1;
2093         }
2094         if (csr)
2095                 WRITE_REG_1(sc, HIFN_1_DMA_CSR, csr);
2096
2097 #ifdef HIFN_DEBUG
2098         if (hifn_debug) {
2099                 device_printf(sc->sc_dev, "command: stat %8x ier %8x\n",
2100                     READ_REG_1(sc, HIFN_1_DMA_CSR),
2101                     READ_REG_1(sc, HIFN_1_DMA_IER));
2102         }
2103 #endif
2104
2105         sc->sc_active = 5;
2106         HIFN_UNLOCK(sc);
2107         KASSERT(err == 0, ("hifn_crypto: success with error %u", err));
2108         return (err);           /* success */
2109
2110 err_dstmap:
2111         if (cmd->src_map != cmd->dst_map)
2112                 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map);
2113 err_dstmap1:
2114         if (cmd->src_map != cmd->dst_map)
2115                 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map);
2116 err_srcmap:
2117         if (crp->crp_flags & CRYPTO_F_IMBUF) {
2118                 if (cmd->src_m != cmd->dst_m)
2119                         m_freem(cmd->dst_m);
2120         }
2121         bus_dmamap_unload(sc->sc_dmat, cmd->src_map);
2122 err_srcmap1:
2123         bus_dmamap_destroy(sc->sc_dmat, cmd->src_map);
2124         HIFN_UNLOCK(sc);
2125         return (err);
2126 }
2127
2128 static void
2129 hifn_tick(void* vsc)
2130 {
2131         struct hifn_softc *sc = vsc;
2132
2133         HIFN_LOCK(sc);
2134         if (sc->sc_active == 0) {
2135                 u_int32_t r = 0;
2136
2137                 if (sc->sc_cmdu == 0 && sc->sc_c_busy) {
2138                         sc->sc_c_busy = 0;
2139                         r |= HIFN_DMACSR_C_CTRL_DIS;
2140                 }
2141                 if (sc->sc_srcu == 0 && sc->sc_s_busy) {
2142                         sc->sc_s_busy = 0;
2143                         r |= HIFN_DMACSR_S_CTRL_DIS;
2144                 }
2145                 if (sc->sc_dstu == 0 && sc->sc_d_busy) {
2146                         sc->sc_d_busy = 0;
2147                         r |= HIFN_DMACSR_D_CTRL_DIS;
2148                 }
2149                 if (sc->sc_resu == 0 && sc->sc_r_busy) {
2150                         sc->sc_r_busy = 0;
2151                         r |= HIFN_DMACSR_R_CTRL_DIS;
2152                 }
2153                 if (r)
2154                         WRITE_REG_1(sc, HIFN_1_DMA_CSR, r);
2155         } else
2156                 sc->sc_active--;
2157         HIFN_UNLOCK(sc);
2158         callout_reset(&sc->sc_tickto, hz, hifn_tick, sc);
2159 }
2160
2161 static void
2162 hifn_intr(void *arg)
2163 {
2164         struct hifn_softc *sc = arg;
2165         struct hifn_dma *dma;
2166         u_int32_t dmacsr, restart;
2167         int i, u;
2168
2169         dmacsr = READ_REG_1(sc, HIFN_1_DMA_CSR);
2170
2171         /* Nothing in the DMA unit interrupted */
2172         if ((dmacsr & sc->sc_dmaier) == 0)
2173                 return;
2174
2175         HIFN_LOCK(sc);
2176
2177         dma = sc->sc_dma;
2178
2179 #ifdef HIFN_DEBUG
2180         if (hifn_debug) {
2181                 device_printf(sc->sc_dev,
2182                     "irq: stat %08x ien %08x damier %08x i %d/%d/%d/%d k %d/%d/%d/%d u %d/%d/%d/%d\n",
2183                     dmacsr, READ_REG_1(sc, HIFN_1_DMA_IER), sc->sc_dmaier,
2184                     sc->sc_cmdi, sc->sc_srci, sc->sc_dsti, sc->sc_resi,
2185                     sc->sc_cmdk, sc->sc_srck, sc->sc_dstk, sc->sc_resk,
2186                     sc->sc_cmdu, sc->sc_srcu, sc->sc_dstu, sc->sc_resu);
2187         }
2188 #endif
2189
2190         WRITE_REG_1(sc, HIFN_1_DMA_CSR, dmacsr & sc->sc_dmaier);
2191
2192         if ((sc->sc_flags & HIFN_HAS_PUBLIC) &&
2193             (dmacsr & HIFN_DMACSR_PUBDONE))
2194                 WRITE_REG_1(sc, HIFN_1_PUB_STATUS,
2195                     READ_REG_1(sc, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE);
2196
2197         restart = dmacsr & (HIFN_DMACSR_D_OVER | HIFN_DMACSR_R_OVER);
2198         if (restart)
2199                 device_printf(sc->sc_dev, "overrun %x\n", dmacsr);
2200
2201         if (sc->sc_flags & HIFN_IS_7811) {
2202                 if (dmacsr & HIFN_DMACSR_ILLR)
2203                         device_printf(sc->sc_dev, "illegal read\n");
2204                 if (dmacsr & HIFN_DMACSR_ILLW)
2205                         device_printf(sc->sc_dev, "illegal write\n");
2206         }
2207
2208         restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT |
2209             HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT);
2210         if (restart) {
2211                 device_printf(sc->sc_dev, "abort, resetting.\n");
2212                 hifnstats.hst_abort++;
2213                 hifn_abort(sc);
2214                 HIFN_UNLOCK(sc);
2215                 return;
2216         }
2217
2218         if ((dmacsr & HIFN_DMACSR_C_WAIT) && (sc->sc_cmdu == 0)) {
2219                 /*
2220                  * If no slots to process and we receive a "waiting on
2221                  * command" interrupt, we disable the "waiting on command"
2222                  * (by clearing it).
2223                  */
2224                 sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT;
2225                 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
2226         }
2227
2228         /* clear the rings */
2229         i = sc->sc_resk; u = sc->sc_resu;
2230         while (u != 0) {
2231                 HIFN_RESR_SYNC(sc, i,
2232                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2233                 if (dma->resr[i].l & htole32(HIFN_D_VALID)) {
2234                         HIFN_RESR_SYNC(sc, i,
2235                             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2236                         break;
2237                 }
2238
2239                 if (i != HIFN_D_RES_RSIZE) {
2240                         struct hifn_command *cmd;
2241                         u_int8_t *macbuf = NULL;
2242
2243                         HIFN_RES_SYNC(sc, i, BUS_DMASYNC_POSTREAD);
2244                         cmd = sc->sc_hifn_commands[i];
2245                         KASSERT(cmd != NULL,
2246                                 ("hifn_intr: null command slot %u", i));
2247                         sc->sc_hifn_commands[i] = NULL;
2248
2249                         if (cmd->base_masks & HIFN_BASE_CMD_MAC) {
2250                                 macbuf = dma->result_bufs[i];
2251                                 macbuf += 12;
2252                         }
2253
2254                         hifn_callback(sc, cmd, macbuf);
2255                         hifnstats.hst_opackets++;
2256                         u--;
2257                 }
2258
2259                 if (++i == (HIFN_D_RES_RSIZE + 1))
2260                         i = 0;
2261         }
2262         sc->sc_resk = i; sc->sc_resu = u;
2263
2264         i = sc->sc_srck; u = sc->sc_srcu;
2265         while (u != 0) {
2266                 if (i == HIFN_D_SRC_RSIZE)
2267                         i = 0;
2268                 HIFN_SRCR_SYNC(sc, i,
2269                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2270                 if (dma->srcr[i].l & htole32(HIFN_D_VALID)) {
2271                         HIFN_SRCR_SYNC(sc, i,
2272                             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2273                         break;
2274                 }
2275                 i++, u--;
2276         }
2277         sc->sc_srck = i; sc->sc_srcu = u;
2278
2279         i = sc->sc_cmdk; u = sc->sc_cmdu;
2280         while (u != 0) {
2281                 HIFN_CMDR_SYNC(sc, i,
2282                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2283                 if (dma->cmdr[i].l & htole32(HIFN_D_VALID)) {
2284                         HIFN_CMDR_SYNC(sc, i,
2285                             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2286                         break;
2287                 }
2288                 if (i != HIFN_D_CMD_RSIZE) {
2289                         u--;
2290                         HIFN_CMD_SYNC(sc, i, BUS_DMASYNC_POSTWRITE);
2291                 }
2292                 if (++i == (HIFN_D_CMD_RSIZE + 1))
2293                         i = 0;
2294         }
2295         sc->sc_cmdk = i; sc->sc_cmdu = u;
2296
2297         HIFN_UNLOCK(sc);
2298
2299         if (sc->sc_needwakeup) {                /* XXX check high watermark */
2300                 int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ);
2301 #ifdef HIFN_DEBUG
2302                 if (hifn_debug)
2303                         device_printf(sc->sc_dev,
2304                                 "wakeup crypto (%x) u %d/%d/%d/%d\n",
2305                                 sc->sc_needwakeup,
2306                                 sc->sc_cmdu, sc->sc_srcu, sc->sc_dstu, sc->sc_resu);
2307 #endif
2308                 sc->sc_needwakeup &= ~wakeup;
2309                 crypto_unblock(sc->sc_cid, wakeup);
2310         }
2311 }
2312
2313 /*
2314  * Allocate a new 'session' and return an encoded session id.  'sidp'
2315  * contains our registration id, and should contain an encoded session
2316  * id on successful allocation.
2317  */
2318 static int
2319 hifn_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri)
2320 {
2321         struct hifn_softc *sc = device_get_softc(dev);
2322         struct cryptoini *c;
2323         int mac = 0, cry = 0, sesn;
2324         struct hifn_session *ses = NULL;
2325
2326         KASSERT(sc != NULL, ("hifn_newsession: null softc"));
2327         if (sidp == NULL || cri == NULL || sc == NULL)
2328                 return (EINVAL);
2329
2330         HIFN_LOCK(sc);
2331         if (sc->sc_sessions == NULL) {
2332                 ses = sc->sc_sessions = (struct hifn_session *)malloc(
2333                     sizeof(*ses), M_DEVBUF, M_NOWAIT);
2334                 if (ses == NULL) {
2335                         HIFN_UNLOCK(sc);
2336                         return (ENOMEM);
2337                 }
2338                 sesn = 0;
2339                 sc->sc_nsessions = 1;
2340         } else {
2341                 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) {
2342                         if (!sc->sc_sessions[sesn].hs_used) {
2343                                 ses = &sc->sc_sessions[sesn];
2344                                 break;
2345                         }
2346                 }
2347
2348                 if (ses == NULL) {
2349                         sesn = sc->sc_nsessions;
2350                         ses = (struct hifn_session *)malloc((sesn + 1) *
2351                             sizeof(*ses), M_DEVBUF, M_NOWAIT);
2352                         if (ses == NULL) {
2353                                 HIFN_UNLOCK(sc);
2354                                 return (ENOMEM);
2355                         }
2356                         bcopy(sc->sc_sessions, ses, sesn * sizeof(*ses));
2357                         bzero(sc->sc_sessions, sesn * sizeof(*ses));
2358                         free(sc->sc_sessions, M_DEVBUF);
2359                         sc->sc_sessions = ses;
2360                         ses = &sc->sc_sessions[sesn];
2361                         sc->sc_nsessions++;
2362                 }
2363         }
2364         HIFN_UNLOCK(sc);
2365
2366         bzero(ses, sizeof(*ses));
2367         ses->hs_used = 1;
2368
2369         for (c = cri; c != NULL; c = c->cri_next) {
2370                 switch (c->cri_alg) {
2371                 case CRYPTO_MD5:
2372                 case CRYPTO_SHA1:
2373                 case CRYPTO_MD5_HMAC:
2374                 case CRYPTO_SHA1_HMAC:
2375                         if (mac)
2376                                 return (EINVAL);
2377                         mac = 1;
2378                         ses->hs_mlen = c->cri_mlen;
2379                         if (ses->hs_mlen == 0) {
2380                                 switch (c->cri_alg) {
2381                                 case CRYPTO_MD5:
2382                                 case CRYPTO_MD5_HMAC:
2383                                         ses->hs_mlen = 16;
2384                                         break;
2385                                 case CRYPTO_SHA1:
2386                                 case CRYPTO_SHA1_HMAC:
2387                                         ses->hs_mlen = 20;
2388                                         break;
2389                                 }
2390                         }
2391                         break;
2392                 case CRYPTO_DES_CBC:
2393                 case CRYPTO_3DES_CBC:
2394                 case CRYPTO_AES_CBC:
2395                         /* XXX this may read fewer, does it matter? */
2396                         read_random(ses->hs_iv,
2397                                 c->cri_alg == CRYPTO_AES_CBC ?
2398                                         HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH);
2399                         /*FALLTHROUGH*/
2400                 case CRYPTO_ARC4:
2401                         if (cry)
2402                                 return (EINVAL);
2403                         cry = 1;
2404                         break;
2405                 default:
2406                         return (EINVAL);
2407                 }
2408         }
2409         if (mac == 0 && cry == 0)
2410                 return (EINVAL);
2411
2412         *sidp = HIFN_SID(device_get_unit(sc->sc_dev), sesn);
2413
2414         return (0);
2415 }
2416
2417 /*
2418  * Deallocate a session.
2419  * XXX this routine should run a zero'd mac/encrypt key into context ram.
2420  * XXX to blow away any keys already stored there.
2421  */
2422 static int
2423 hifn_freesession(device_t dev, u_int64_t tid)
2424 {
2425         struct hifn_softc *sc = device_get_softc(dev);
2426         int session, error;
2427         u_int32_t sid = CRYPTO_SESID2LID(tid);
2428
2429         KASSERT(sc != NULL, ("hifn_freesession: null softc"));
2430         if (sc == NULL)
2431                 return (EINVAL);
2432
2433         HIFN_LOCK(sc);
2434         session = HIFN_SESSION(sid);
2435         if (session < sc->sc_nsessions) {
2436                 bzero(&sc->sc_sessions[session], sizeof(struct hifn_session));
2437                 error = 0;
2438         } else
2439                 error = EINVAL;
2440         HIFN_UNLOCK(sc);
2441
2442         return (error);
2443 }
2444
2445 static int
2446 hifn_process(device_t dev, struct cryptop *crp, int hint)
2447 {
2448         struct hifn_softc *sc = device_get_softc(dev);
2449         struct hifn_command *cmd = NULL;
2450         int session, err, ivlen;
2451         struct cryptodesc *crd1, *crd2, *maccrd, *enccrd;
2452
2453         if (crp == NULL || crp->crp_callback == NULL) {
2454                 hifnstats.hst_invalid++;
2455                 return (EINVAL);
2456         }
2457         session = HIFN_SESSION(crp->crp_sid);
2458
2459         if (sc == NULL || session >= sc->sc_nsessions) {
2460                 err = EINVAL;
2461                 goto errout;
2462         }
2463
2464         cmd = malloc(sizeof(struct hifn_command), M_DEVBUF, M_NOWAIT | M_ZERO);
2465         if (cmd == NULL) {
2466                 hifnstats.hst_nomem++;
2467                 err = ENOMEM;
2468                 goto errout;
2469         }
2470
2471         if (crp->crp_flags & CRYPTO_F_IMBUF) {
2472                 cmd->src_m = (struct mbuf *)crp->crp_buf;
2473                 cmd->dst_m = (struct mbuf *)crp->crp_buf;
2474         } else if (crp->crp_flags & CRYPTO_F_IOV) {
2475                 cmd->src_io = (struct uio *)crp->crp_buf;
2476                 cmd->dst_io = (struct uio *)crp->crp_buf;
2477         } else {
2478                 err = EINVAL;
2479                 goto errout;    /* XXX we don't handle contiguous buffers! */
2480         }
2481
2482         crd1 = crp->crp_desc;
2483         if (crd1 == NULL) {
2484                 err = EINVAL;
2485                 goto errout;
2486         }
2487         crd2 = crd1->crd_next;
2488
2489         if (crd2 == NULL) {
2490                 if (crd1->crd_alg == CRYPTO_MD5_HMAC ||
2491                     crd1->crd_alg == CRYPTO_SHA1_HMAC ||
2492                     crd1->crd_alg == CRYPTO_SHA1 ||
2493                     crd1->crd_alg == CRYPTO_MD5) {
2494                         maccrd = crd1;
2495                         enccrd = NULL;
2496                 } else if (crd1->crd_alg == CRYPTO_DES_CBC ||
2497                     crd1->crd_alg == CRYPTO_3DES_CBC ||
2498                     crd1->crd_alg == CRYPTO_AES_CBC ||
2499                     crd1->crd_alg == CRYPTO_ARC4) {
2500                         if ((crd1->crd_flags & CRD_F_ENCRYPT) == 0)
2501                                 cmd->base_masks |= HIFN_BASE_CMD_DECODE;
2502                         maccrd = NULL;
2503                         enccrd = crd1;
2504                 } else {
2505                         err = EINVAL;
2506                         goto errout;
2507                 }
2508         } else {
2509                 if ((crd1->crd_alg == CRYPTO_MD5_HMAC ||
2510                      crd1->crd_alg == CRYPTO_SHA1_HMAC ||
2511                      crd1->crd_alg == CRYPTO_MD5 ||
2512                      crd1->crd_alg == CRYPTO_SHA1) &&
2513                     (crd2->crd_alg == CRYPTO_DES_CBC ||
2514                      crd2->crd_alg == CRYPTO_3DES_CBC ||
2515                      crd2->crd_alg == CRYPTO_AES_CBC ||
2516                      crd2->crd_alg == CRYPTO_ARC4) &&
2517                     ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) {
2518                         cmd->base_masks = HIFN_BASE_CMD_DECODE;
2519                         maccrd = crd1;
2520                         enccrd = crd2;
2521                 } else if ((crd1->crd_alg == CRYPTO_DES_CBC ||
2522                      crd1->crd_alg == CRYPTO_ARC4 ||
2523                      crd1->crd_alg == CRYPTO_3DES_CBC ||
2524                      crd1->crd_alg == CRYPTO_AES_CBC) &&
2525                     (crd2->crd_alg == CRYPTO_MD5_HMAC ||
2526                      crd2->crd_alg == CRYPTO_SHA1_HMAC ||
2527                      crd2->crd_alg == CRYPTO_MD5 ||
2528                      crd2->crd_alg == CRYPTO_SHA1) &&
2529                     (crd1->crd_flags & CRD_F_ENCRYPT)) {
2530                         enccrd = crd1;
2531                         maccrd = crd2;
2532                 } else {
2533                         /*
2534                          * We cannot order the 7751 as requested
2535                          */
2536                         err = EINVAL;
2537                         goto errout;
2538                 }
2539         }
2540
2541         if (enccrd) {
2542                 cmd->enccrd = enccrd;
2543                 cmd->base_masks |= HIFN_BASE_CMD_CRYPT;
2544                 switch (enccrd->crd_alg) {
2545                 case CRYPTO_ARC4:
2546                         cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_RC4;
2547                         break;
2548                 case CRYPTO_DES_CBC:
2549                         cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_DES |
2550                             HIFN_CRYPT_CMD_MODE_CBC |
2551                             HIFN_CRYPT_CMD_NEW_IV;
2552                         break;
2553                 case CRYPTO_3DES_CBC:
2554                         cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_3DES |
2555                             HIFN_CRYPT_CMD_MODE_CBC |
2556                             HIFN_CRYPT_CMD_NEW_IV;
2557                         break;
2558                 case CRYPTO_AES_CBC:
2559                         cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_AES |
2560                             HIFN_CRYPT_CMD_MODE_CBC |
2561                             HIFN_CRYPT_CMD_NEW_IV;
2562                         break;
2563                 default:
2564                         err = EINVAL;
2565                         goto errout;
2566                 }
2567                 if (enccrd->crd_alg != CRYPTO_ARC4) {
2568                         ivlen = ((enccrd->crd_alg == CRYPTO_AES_CBC) ?
2569                                 HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH);
2570                         if (enccrd->crd_flags & CRD_F_ENCRYPT) {
2571                                 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
2572                                         bcopy(enccrd->crd_iv, cmd->iv, ivlen);
2573                                 else
2574                                         bcopy(sc->sc_sessions[session].hs_iv,
2575                                             cmd->iv, ivlen);
2576
2577                                 if ((enccrd->crd_flags & CRD_F_IV_PRESENT)
2578                                     == 0) {
2579                                         crypto_copyback(crp->crp_flags,
2580                                             crp->crp_buf, enccrd->crd_inject,
2581                                             ivlen, cmd->iv);
2582                                 }
2583                         } else {
2584                                 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
2585                                         bcopy(enccrd->crd_iv, cmd->iv, ivlen);
2586                                 else {
2587                                         crypto_copydata(crp->crp_flags,
2588                                             crp->crp_buf, enccrd->crd_inject,
2589                                             ivlen, cmd->iv);
2590                                 }
2591                         }
2592                 }
2593
2594                 if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT)
2595                         cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY;
2596                 cmd->ck = enccrd->crd_key;
2597                 cmd->cklen = enccrd->crd_klen >> 3;
2598                 cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY;
2599
2600                 /*
2601                  * Need to specify the size for the AES key in the masks.
2602                  */
2603                 if ((cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) ==
2604                     HIFN_CRYPT_CMD_ALG_AES) {
2605                         switch (cmd->cklen) {
2606                         case 16:
2607                                 cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_128;
2608                                 break;
2609                         case 24:
2610                                 cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_192;
2611                                 break;
2612                         case 32:
2613                                 cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_256;
2614                                 break;
2615                         default:
2616                                 err = EINVAL;
2617                                 goto errout;
2618                         }
2619                 }
2620         }
2621
2622         if (maccrd) {
2623                 cmd->maccrd = maccrd;
2624                 cmd->base_masks |= HIFN_BASE_CMD_MAC;
2625
2626                 switch (maccrd->crd_alg) {
2627                 case CRYPTO_MD5:
2628                         cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 |
2629                             HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH |
2630                             HIFN_MAC_CMD_POS_IPSEC;
2631                        break;
2632                 case CRYPTO_MD5_HMAC:
2633                         cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 |
2634                             HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC |
2635                             HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC;
2636                         break;
2637                 case CRYPTO_SHA1:
2638                         cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 |
2639                             HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH |
2640                             HIFN_MAC_CMD_POS_IPSEC;
2641                         break;
2642                 case CRYPTO_SHA1_HMAC:
2643                         cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 |
2644                             HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC |
2645                             HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC;
2646                         break;
2647                 }
2648
2649                 if (maccrd->crd_alg == CRYPTO_SHA1_HMAC ||
2650                      maccrd->crd_alg == CRYPTO_MD5_HMAC) {
2651                         cmd->mac_masks |= HIFN_MAC_CMD_NEW_KEY;
2652                         bcopy(maccrd->crd_key, cmd->mac, maccrd->crd_klen >> 3);
2653                         bzero(cmd->mac + (maccrd->crd_klen >> 3),
2654                             HIFN_MAC_KEY_LENGTH - (maccrd->crd_klen >> 3));
2655                 }
2656         }
2657
2658         cmd->crp = crp;
2659         cmd->session_num = session;
2660         cmd->softc = sc;
2661
2662         err = hifn_crypto(sc, cmd, crp, hint);
2663         if (!err) {
2664                 return 0;
2665         } else if (err == ERESTART) {
2666                 /*
2667                  * There weren't enough resources to dispatch the request
2668                  * to the part.  Notify the caller so they'll requeue this
2669                  * request and resubmit it again soon.
2670                  */
2671 #ifdef HIFN_DEBUG
2672                 if (hifn_debug)
2673                         device_printf(sc->sc_dev, "requeue request\n");
2674 #endif
2675                 free(cmd, M_DEVBUF);
2676                 sc->sc_needwakeup |= CRYPTO_SYMQ;
2677                 return (err);
2678         }
2679
2680 errout:
2681         if (cmd != NULL)
2682                 free(cmd, M_DEVBUF);
2683         if (err == EINVAL)
2684                 hifnstats.hst_invalid++;
2685         else
2686                 hifnstats.hst_nomem++;
2687         crp->crp_etype = err;
2688         crypto_done(crp);
2689         return (err);
2690 }
2691
2692 static void
2693 hifn_abort(struct hifn_softc *sc)
2694 {
2695         struct hifn_dma *dma = sc->sc_dma;
2696         struct hifn_command *cmd;
2697         struct cryptop *crp;
2698         int i, u;
2699
2700         i = sc->sc_resk; u = sc->sc_resu;
2701         while (u != 0) {
2702                 cmd = sc->sc_hifn_commands[i];
2703                 KASSERT(cmd != NULL, ("hifn_abort: null command slot %u", i));
2704                 sc->sc_hifn_commands[i] = NULL;
2705                 crp = cmd->crp;
2706
2707                 if ((dma->resr[i].l & htole32(HIFN_D_VALID)) == 0) {
2708                         /* Salvage what we can. */
2709                         u_int8_t *macbuf;
2710
2711                         if (cmd->base_masks & HIFN_BASE_CMD_MAC) {
2712                                 macbuf = dma->result_bufs[i];
2713                                 macbuf += 12;
2714                         } else
2715                                 macbuf = NULL;
2716                         hifnstats.hst_opackets++;
2717                         hifn_callback(sc, cmd, macbuf);
2718                 } else {
2719                         if (cmd->src_map == cmd->dst_map) {
2720                                 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2721                                     BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2722                         } else {
2723                                 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2724                                     BUS_DMASYNC_POSTWRITE);
2725                                 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map,
2726                                     BUS_DMASYNC_POSTREAD);
2727                         }
2728
2729                         if (cmd->src_m != cmd->dst_m) {
2730                                 m_freem(cmd->src_m);
2731                                 crp->crp_buf = (caddr_t)cmd->dst_m;
2732                         }
2733
2734                         /* non-shared buffers cannot be restarted */
2735                         if (cmd->src_map != cmd->dst_map) {
2736                                 /*
2737                                  * XXX should be EAGAIN, delayed until
2738                                  * after the reset.
2739                                  */
2740                                 crp->crp_etype = ENOMEM;
2741                                 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map);
2742                                 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map);
2743                         } else
2744                                 crp->crp_etype = ENOMEM;
2745
2746                         bus_dmamap_unload(sc->sc_dmat, cmd->src_map);
2747                         bus_dmamap_destroy(sc->sc_dmat, cmd->src_map);
2748
2749                         free(cmd, M_DEVBUF);
2750                         if (crp->crp_etype != EAGAIN)
2751                                 crypto_done(crp);
2752                 }
2753
2754                 if (++i == HIFN_D_RES_RSIZE)
2755                         i = 0;
2756                 u--;
2757         }
2758         sc->sc_resk = i; sc->sc_resu = u;
2759
2760         hifn_reset_board(sc, 1);
2761         hifn_init_dma(sc);
2762         hifn_init_pci_registers(sc);
2763 }
2764
2765 static void
2766 hifn_callback(struct hifn_softc *sc, struct hifn_command *cmd, u_int8_t *macbuf)
2767 {
2768         struct hifn_dma *dma = sc->sc_dma;
2769         struct cryptop *crp = cmd->crp;
2770         struct cryptodesc *crd;
2771         struct mbuf *m;
2772         int totlen, i, u, ivlen;
2773
2774         if (cmd->src_map == cmd->dst_map) {
2775                 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2776                     BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2777         } else {
2778                 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2779                     BUS_DMASYNC_POSTWRITE);
2780                 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map,
2781                     BUS_DMASYNC_POSTREAD);
2782         }
2783
2784         if (crp->crp_flags & CRYPTO_F_IMBUF) {
2785                 if (cmd->src_m != cmd->dst_m) {
2786                         crp->crp_buf = (caddr_t)cmd->dst_m;
2787                         totlen = cmd->src_mapsize;
2788                         for (m = cmd->dst_m; m != NULL; m = m->m_next) {
2789                                 if (totlen < m->m_len) {
2790                                         m->m_len = totlen;
2791                                         totlen = 0;
2792                                 } else
2793                                         totlen -= m->m_len;
2794                         }
2795                         cmd->dst_m->m_pkthdr.len = cmd->src_m->m_pkthdr.len;
2796                         m_freem(cmd->src_m);
2797                 }
2798         }
2799
2800         if (cmd->sloplen != 0) {
2801                 crypto_copyback(crp->crp_flags, crp->crp_buf,
2802                     cmd->src_mapsize - cmd->sloplen, cmd->sloplen,
2803                     (caddr_t)&dma->slop[cmd->slopidx]);
2804         }
2805
2806         i = sc->sc_dstk; u = sc->sc_dstu;
2807         while (u != 0) {
2808                 if (i == HIFN_D_DST_RSIZE)
2809                         i = 0;
2810                 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
2811                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2812                 if (dma->dstr[i].l & htole32(HIFN_D_VALID)) {
2813                         bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
2814                             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2815                         break;
2816                 }
2817                 i++, u--;
2818         }
2819         sc->sc_dstk = i; sc->sc_dstu = u;
2820
2821         hifnstats.hst_obytes += cmd->dst_mapsize;
2822
2823         if ((cmd->base_masks & (HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE)) ==
2824             HIFN_BASE_CMD_CRYPT) {
2825                 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
2826                         if (crd->crd_alg != CRYPTO_DES_CBC &&
2827                             crd->crd_alg != CRYPTO_3DES_CBC &&
2828                             crd->crd_alg != CRYPTO_AES_CBC)
2829                                 continue;
2830                         ivlen = ((crd->crd_alg == CRYPTO_AES_CBC) ?
2831                                 HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH);
2832                         crypto_copydata(crp->crp_flags, crp->crp_buf,
2833                             crd->crd_skip + crd->crd_len - ivlen, ivlen,
2834                             cmd->softc->sc_sessions[cmd->session_num].hs_iv);
2835                         break;
2836                 }
2837         }
2838
2839         if (macbuf != NULL) {
2840                 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
2841                         int len;
2842
2843                         if (crd->crd_alg != CRYPTO_MD5 &&
2844                             crd->crd_alg != CRYPTO_SHA1 &&
2845                             crd->crd_alg != CRYPTO_MD5_HMAC &&
2846                             crd->crd_alg != CRYPTO_SHA1_HMAC) {
2847                                 continue;
2848                         }
2849                         len = cmd->softc->sc_sessions[cmd->session_num].hs_mlen;
2850                         crypto_copyback(crp->crp_flags, crp->crp_buf,
2851                             crd->crd_inject, len, macbuf);
2852                         break;
2853                 }
2854         }
2855
2856         if (cmd->src_map != cmd->dst_map) {
2857                 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map);
2858                 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map);
2859         }
2860         bus_dmamap_unload(sc->sc_dmat, cmd->src_map);
2861         bus_dmamap_destroy(sc->sc_dmat, cmd->src_map);
2862         free(cmd, M_DEVBUF);
2863         crypto_done(crp);
2864 }
2865
2866 /*
2867  * 7811 PB3 rev/2 parts lock-up on burst writes to Group 0
2868  * and Group 1 registers; avoid conditions that could create
2869  * burst writes by doing a read in between the writes.
2870  *
2871  * NB: The read we interpose is always to the same register;
2872  *     we do this because reading from an arbitrary (e.g. last)
2873  *     register may not always work.
2874  */
2875 static void
2876 hifn_write_reg_0(struct hifn_softc *sc, bus_size_t reg, u_int32_t val)
2877 {
2878         if (sc->sc_flags & HIFN_IS_7811) {
2879                 if (sc->sc_bar0_lastreg == reg - 4)
2880                         bus_space_read_4(sc->sc_st0, sc->sc_sh0, HIFN_0_PUCNFG);
2881                 sc->sc_bar0_lastreg = reg;
2882         }
2883         bus_space_write_4(sc->sc_st0, sc->sc_sh0, reg, val);
2884 }
2885
2886 static void
2887 hifn_write_reg_1(struct hifn_softc *sc, bus_size_t reg, u_int32_t val)
2888 {
2889         if (sc->sc_flags & HIFN_IS_7811) {
2890                 if (sc->sc_bar1_lastreg == reg - 4)
2891                         bus_space_read_4(sc->sc_st1, sc->sc_sh1, HIFN_1_REVID);
2892                 sc->sc_bar1_lastreg = reg;
2893         }
2894         bus_space_write_4(sc->sc_st1, sc->sc_sh1, reg, val);
2895 }
2896
2897 #ifdef HIFN_VULCANDEV
2898 /*
2899  * this code provides support for mapping the PK engine's register
2900  * into a userspace program.
2901  *
2902  */
2903 static int
2904 vulcanpk_mmap(struct cdev *dev, vm_ooffset_t offset,
2905               vm_paddr_t *paddr, int nprot, vm_memattr_t *memattr)
2906 {
2907         struct hifn_softc *sc;
2908         vm_paddr_t pd;
2909         void *b;
2910
2911         sc = dev->si_drv1;
2912
2913         pd = rman_get_start(sc->sc_bar1res);
2914         b = rman_get_virtual(sc->sc_bar1res);
2915
2916 #if 0
2917         printf("vpk mmap: %p(%016llx) offset=%lld\n", b,
2918             (unsigned long long)pd, offset);
2919         hexdump(b, HIFN_1_PUB_MEMEND, "vpk", 0);
2920 #endif
2921
2922         if (offset == 0) {
2923                 *paddr = pd;
2924                 return (0);
2925         }
2926         return (-1);
2927 }
2928
2929 static struct cdevsw vulcanpk_cdevsw = {
2930         .d_version =    D_VERSION,
2931         .d_mmap =       vulcanpk_mmap,
2932         .d_name =       "vulcanpk",
2933 };
2934 #endif /* HIFN_VULCANDEV */