2 * Copyright (c) 2008 Joseph Koshy
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
37 #include <sys/pmckern.h>
38 #include <sys/systm.h>
40 #include <machine/intr_machdep.h>
41 #include <machine/apicvar.h>
42 #include <machine/cpu.h>
43 #include <machine/cpufunc.h>
44 #include <machine/md_var.h>
45 #include <machine/specialreg.h>
47 #define CORE_CPUID_REQUEST 0xA
48 #define CORE_CPUID_REQUEST_SIZE 0x4
49 #define CORE_CPUID_EAX 0x0
50 #define CORE_CPUID_EBX 0x1
51 #define CORE_CPUID_ECX 0x2
52 #define CORE_CPUID_EDX 0x3
54 #define IAF_PMC_CAPS \
55 (PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INTERRUPT | \
56 PMC_CAP_USER | PMC_CAP_SYSTEM)
57 #define IAF_RI_TO_MSR(RI) ((RI) + (1 << 30))
59 #define IAP_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \
60 PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \
61 PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE)
63 #define EV_IS_NOTARCH 0
64 #define EV_IS_ARCH_SUPP 1
65 #define EV_IS_ARCH_NOTSUPP -1
68 * "Architectural" events defined by Intel. The values of these
69 * symbols correspond to positions in the bitmask returned by
70 * the CPUID.0AH instruction.
72 enum core_arch_events {
73 CORE_AE_BRANCH_INSTRUCTION_RETIRED = 5,
74 CORE_AE_BRANCH_MISSES_RETIRED = 6,
75 CORE_AE_INSTRUCTION_RETIRED = 1,
76 CORE_AE_LLC_MISSES = 4,
77 CORE_AE_LLC_REFERENCE = 3,
78 CORE_AE_UNHALTED_REFERENCE_CYCLES = 2,
79 CORE_AE_UNHALTED_CORE_CYCLES = 0
82 static enum pmc_cputype core_cputype;
85 volatile uint32_t pc_resync;
86 volatile uint32_t pc_iafctrl; /* Fixed function control. */
87 volatile uint64_t pc_globalctrl; /* Global control register. */
88 struct pmc_hw pc_corepmcs[];
91 static struct core_cpu **core_pcpu;
93 static uint32_t core_architectural_events;
94 static uint64_t core_pmcmask;
96 static int core_iaf_ri; /* relative index of fixed counters */
97 static int core_iaf_width;
98 static int core_iaf_npmc;
100 static int core_iap_width;
101 static int core_iap_npmc;
104 core_pcpu_noop(struct pmc_mdep *md, int cpu)
112 core_pcpu_init(struct pmc_mdep *md, int cpu)
117 int core_ri, n, npmc;
119 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
120 ("[iaf,%d] insane cpu number %d", __LINE__, cpu));
122 PMCDBG(MDP,INI,1,"core-init cpu=%d", cpu);
124 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri;
125 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num;
127 if (core_cputype != PMC_CPU_INTEL_CORE)
128 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num;
130 cc = malloc(sizeof(struct core_cpu) + npmc * sizeof(struct pmc_hw),
131 M_PMC, M_WAITOK | M_ZERO);
136 KASSERT(pc != NULL && cc != NULL,
137 ("[core,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu));
139 for (n = 0, phw = cc->pc_corepmcs; n < npmc; n++, phw++) {
140 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED |
141 PMC_PHW_CPU_TO_STATE(cpu) |
142 PMC_PHW_INDEX_TO_STATE(n + core_ri);
144 pc->pc_hwpmcs[n + core_ri] = phw;
151 core_pcpu_fini(struct pmc_mdep *md, int cpu)
153 int core_ri, n, npmc;
158 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
159 ("[core,%d] insane cpu number (%d)", __LINE__, cpu));
161 PMCDBG(MDP,INI,1,"core-pcpu-fini cpu=%d", cpu);
163 if ((cc = core_pcpu[cpu]) == NULL)
166 core_pcpu[cpu] = NULL;
170 KASSERT(pc != NULL, ("[core,%d] NULL per-cpu %d state", __LINE__,
173 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num;
174 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri;
176 for (n = 0; n < npmc; n++) {
177 msr = rdmsr(IAP_EVSEL0 + n) & ~IAP_EVSEL_MASK;
178 wrmsr(IAP_EVSEL0 + n, msr);
181 if (core_cputype != PMC_CPU_INTEL_CORE) {
182 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
183 wrmsr(IAF_CTRL, msr);
184 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num;
187 for (n = 0; n < npmc; n++)
188 pc->pc_hwpmcs[n + core_ri] = NULL;
196 * Fixed function counters.
200 iaf_perfctr_value_to_reload_count(pmc_value_t v)
202 v &= (1ULL << core_iaf_width) - 1;
203 return (1ULL << core_iaf_width) - v;
207 iaf_reload_count_to_perfctr_value(pmc_value_t rlc)
209 return (1ULL << core_iaf_width) - rlc;
213 iaf_allocate_pmc(int cpu, int ri, struct pmc *pm,
214 const struct pmc_op_pmcallocate *a)
217 uint32_t caps, flags, validflags;
219 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
220 ("[core,%d] illegal CPU %d", __LINE__, cpu));
222 PMCDBG(MDP,ALL,1, "iaf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps);
224 if (ri < 0 || ri > core_iaf_npmc)
229 if (a->pm_class != PMC_CLASS_IAF ||
230 (caps & IAF_PMC_CAPS) != caps)
234 if (ev < PMC_EV_IAF_FIRST || ev > PMC_EV_IAF_LAST)
237 if (ev == PMC_EV_IAF_INSTR_RETIRED_ANY && ri != 0)
239 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_CORE && ri != 1)
241 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_REF && ri != 2)
244 flags = a->pm_md.pm_iaf.pm_iaf_flags;
246 validflags = IAF_MASK;
248 if (core_cputype != PMC_CPU_INTEL_ATOM)
249 validflags &= ~IAF_ANY;
251 if ((flags & ~validflags) != 0)
254 if (caps & PMC_CAP_INTERRUPT)
256 if (caps & PMC_CAP_SYSTEM)
258 if (caps & PMC_CAP_USER)
260 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0)
261 flags |= (IAF_OS | IAF_USR);
263 pm->pm_md.pm_iaf.pm_iaf_ctrl = (flags << (ri * 4));
265 PMCDBG(MDP,ALL,2, "iaf-allocate config=0x%jx",
266 (uintmax_t) pm->pm_md.pm_iaf.pm_iaf_ctrl);
272 iaf_config_pmc(int cpu, int ri, struct pmc *pm)
274 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
275 ("[core,%d] illegal CPU %d", __LINE__, cpu));
277 KASSERT(ri >= 0 && ri < core_iaf_npmc,
278 ("[core,%d] illegal row-index %d", __LINE__, ri));
280 PMCDBG(MDP,CFG,1, "iaf-config cpu=%d ri=%d pm=%p", cpu, ri, pm);
282 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__,
285 core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc = pm;
291 iaf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
295 char iaf_name[PMC_NAME_MAX];
297 phw = &core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri];
299 (void) snprintf(iaf_name, sizeof(iaf_name), "IAF-%d", ri);
300 if ((error = copystr(iaf_name, pi->pm_name, PMC_NAME_MAX,
304 pi->pm_class = PMC_CLASS_IAF;
306 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
307 pi->pm_enabled = TRUE;
308 *ppmc = phw->phw_pmc;
310 pi->pm_enabled = FALSE;
318 iaf_get_config(int cpu, int ri, struct pmc **ppm)
320 *ppm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
326 iaf_get_msr(int ri, uint32_t *msr)
328 KASSERT(ri >= 0 && ri < core_iaf_npmc,
329 ("[iaf,%d] ri %d out of range", __LINE__, ri));
331 *msr = IAF_RI_TO_MSR(ri);
337 iaf_read_pmc(int cpu, int ri, pmc_value_t *v)
342 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
343 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
344 KASSERT(ri >= 0 && ri < core_iaf_npmc,
345 ("[core,%d] illegal row-index %d", __LINE__, ri));
347 pm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
350 ("[core,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu,
351 ri, ri + core_iaf_ri));
353 tmp = rdpmc(IAF_RI_TO_MSR(ri));
355 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
356 *v = iaf_perfctr_value_to_reload_count(tmp);
360 PMCDBG(MDP,REA,1, "iaf-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri,
361 IAF_RI_TO_MSR(ri), *v);
367 iaf_release_pmc(int cpu, int ri, struct pmc *pmc)
369 PMCDBG(MDP,REL,1, "iaf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc);
371 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
372 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
373 KASSERT(ri >= 0 && ri < core_iaf_npmc,
374 ("[core,%d] illegal row-index %d", __LINE__, ri));
376 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc == NULL,
377 ("[core,%d] PHW pmc non-NULL", __LINE__));
383 iaf_start_pmc(int cpu, int ri)
386 struct core_cpu *iafc;
389 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
390 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
391 KASSERT(ri >= 0 && ri < core_iaf_npmc,
392 ("[core,%d] illegal row-index %d", __LINE__, ri));
394 PMCDBG(MDP,STA,1,"iaf-start cpu=%d ri=%d", cpu, ri);
396 iafc = core_pcpu[cpu];
397 pm = iafc->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
399 iafc->pc_iafctrl |= pm->pm_md.pm_iaf.pm_iaf_ctrl;
401 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
402 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK));
406 iafc->pc_globalctrl |= (1ULL << (ri + IAF_OFFSET));
407 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK;
408 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl &
409 IAF_GLOBAL_CTRL_MASK));
410 } while (iafc->pc_resync != 0);
412 PMCDBG(MDP,STA,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)",
413 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL),
414 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL));
420 iaf_stop_pmc(int cpu, int ri)
423 struct core_cpu *iafc;
426 PMCDBG(MDP,STO,1,"iaf-stop cpu=%d ri=%d", cpu, ri);
428 iafc = core_pcpu[cpu];
430 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
431 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
432 KASSERT(ri >= 0 && ri < core_iaf_npmc,
433 ("[core,%d] illegal row-index %d", __LINE__, ri));
435 fc = (IAF_MASK << (ri * 4));
437 if (core_cputype != PMC_CPU_INTEL_ATOM)
440 iafc->pc_iafctrl &= ~fc;
442 PMCDBG(MDP,STO,1,"iaf-stop iafctrl=%x", iafc->pc_iafctrl);
443 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
444 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK));
448 iafc->pc_globalctrl &= ~(1ULL << (ri + IAF_OFFSET));
449 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK;
450 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl &
451 IAF_GLOBAL_CTRL_MASK));
452 } while (iafc->pc_resync != 0);
454 PMCDBG(MDP,STO,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)",
455 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL),
456 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL));
462 iaf_write_pmc(int cpu, int ri, pmc_value_t v)
468 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
469 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
470 KASSERT(ri >= 0 && ri < core_iaf_npmc,
471 ("[core,%d] illegal row-index %d", __LINE__, ri));
474 pm = cc->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
477 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri));
479 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
480 v = iaf_reload_count_to_perfctr_value(v);
482 /* Turn off fixed counters */
483 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
484 wrmsr(IAF_CTRL, msr);
486 wrmsr(IAF_CTR0 + ri, v & ((1ULL << core_iaf_width) - 1));
488 /* Turn on fixed counters */
489 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
490 wrmsr(IAF_CTRL, msr | (cc->pc_iafctrl & IAF_CTRL_MASK));
492 PMCDBG(MDP,WRI,1, "iaf-write cpu=%d ri=%d msr=0x%x v=%jx iafctrl=%jx "
493 "pmc=%jx", cpu, ri, IAF_RI_TO_MSR(ri), v,
494 (uintmax_t) rdmsr(IAF_CTRL),
495 (uintmax_t) rdpmc(IAF_RI_TO_MSR(ri)));
502 iaf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth)
504 struct pmc_classdep *pcd;
506 KASSERT(md != NULL, ("[iaf,%d] md is NULL", __LINE__));
508 PMCDBG(MDP,INI,1, "%s", "iaf-initialize");
510 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF];
512 pcd->pcd_caps = IAF_PMC_CAPS;
513 pcd->pcd_class = PMC_CLASS_IAF;
515 pcd->pcd_ri = md->pmd_npmc;
516 pcd->pcd_width = pmcwidth;
518 pcd->pcd_allocate_pmc = iaf_allocate_pmc;
519 pcd->pcd_config_pmc = iaf_config_pmc;
520 pcd->pcd_describe = iaf_describe;
521 pcd->pcd_get_config = iaf_get_config;
522 pcd->pcd_get_msr = iaf_get_msr;
523 pcd->pcd_pcpu_fini = core_pcpu_noop;
524 pcd->pcd_pcpu_init = core_pcpu_noop;
525 pcd->pcd_read_pmc = iaf_read_pmc;
526 pcd->pcd_release_pmc = iaf_release_pmc;
527 pcd->pcd_start_pmc = iaf_start_pmc;
528 pcd->pcd_stop_pmc = iaf_stop_pmc;
529 pcd->pcd_write_pmc = iaf_write_pmc;
531 md->pmd_npmc += npmc;
535 * Intel programmable PMCs.
539 * Event descriptor tables.
541 * For each event id, we track:
543 * 1. The CPUs that the event is valid for.
545 * 2. If the event uses a fixed UMASK, the value of the umask field.
546 * If the event doesn't use a fixed UMASK, a mask of legal bits
550 struct iap_event_descr {
551 enum pmc_event iap_ev;
552 unsigned char iap_evcode;
553 unsigned char iap_umask;
554 unsigned int iap_flags;
557 #define IAP_F_CC (1 << 0) /* CPU: Core */
558 #define IAP_F_CC2 (1 << 1) /* CPU: Core2 family */
559 #define IAP_F_CC2E (1 << 2) /* CPU: Core2 Extreme only */
560 #define IAP_F_CA (1 << 3) /* CPU: Atom */
561 #define IAP_F_I7 (1 << 4) /* CPU: Core i7 */
562 #define IAP_F_I7O (1 << 4) /* CPU: Core i7 (old) */
563 #define IAP_F_WM (1 << 5) /* CPU: Westmere */
564 #define IAP_F_SB (1 << 6) /* CPU: Sandy Bridge */
565 #define IAP_F_IB (1 << 7) /* CPU: Ivy Bridge */
566 #define IAP_F_SBX (1 << 8) /* CPU: Sandy Bridge Xeon */
567 #define IAP_F_IBX (1 << 9) /* CPU: Ivy Bridge Xeon */
568 #define IAP_F_HW (1 << 10) /* CPU: Haswell */
569 #define IAP_F_FM (1 << 11) /* Fixed mask */
571 #define IAP_F_ALLCPUSCORE2 \
572 (IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA)
574 /* Sub fields of UMASK that this event supports. */
575 #define IAP_M_CORE (1 << 0) /* Core specificity */
576 #define IAP_M_AGENT (1 << 1) /* Agent specificity */
577 #define IAP_M_PREFETCH (1 << 2) /* Prefetch */
578 #define IAP_M_MESI (1 << 3) /* MESI */
579 #define IAP_M_SNOOPRESPONSE (1 << 4) /* Snoop response */
580 #define IAP_M_SNOOPTYPE (1 << 5) /* Snoop type */
581 #define IAP_M_TRANSITION (1 << 6) /* Transition */
583 #define IAP_F_CORE (0x3 << 14) /* Core specificity */
584 #define IAP_F_AGENT (0x1 << 13) /* Agent specificity */
585 #define IAP_F_PREFETCH (0x3 << 12) /* Prefetch */
586 #define IAP_F_MESI (0xF << 8) /* MESI */
587 #define IAP_F_SNOOPRESPONSE (0xB << 8) /* Snoop response */
588 #define IAP_F_SNOOPTYPE (0x3 << 8) /* Snoop type */
589 #define IAP_F_TRANSITION (0x1 << 12) /* Transition */
591 #define IAP_PREFETCH_RESERVED (0x2 << 12)
592 #define IAP_CORE_THIS (0x1 << 14)
593 #define IAP_CORE_ALL (0x3 << 14)
594 #define IAP_F_CMASK 0xFF000000
596 static struct iap_event_descr iap_events[] = {
598 #define IAPDESCR(N,EV,UM,FLAGS) { \
599 .iap_ev = PMC_EV_IAP_EVENT_##N, \
600 .iap_evcode = (EV), \
602 .iap_flags = (FLAGS) \
605 IAPDESCR(02H_01H, 0x02, 0x01, IAP_F_FM | IAP_F_I7O),
606 IAPDESCR(02H_81H, 0x02, 0x81, IAP_F_FM | IAP_F_CA),
608 IAPDESCR(03H_00H, 0x03, 0x00, IAP_F_FM | IAP_F_CC),
609 IAPDESCR(03H_01H, 0x03, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB |
611 IAPDESCR(03H_02H, 0x03, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
612 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
613 IAPDESCR(03H_04H, 0x03, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O),
614 IAPDESCR(03H_08H, 0x03, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB |
616 IAPDESCR(03H_10H, 0x03, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB |
618 IAPDESCR(03H_20H, 0x03, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
620 IAPDESCR(04H_00H, 0x04, 0x00, IAP_F_FM | IAP_F_CC),
621 IAPDESCR(04H_01H, 0x04, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O),
622 IAPDESCR(04H_02H, 0x04, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
623 IAPDESCR(04H_07H, 0x04, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
624 IAPDESCR(04H_08H, 0x04, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
626 IAPDESCR(05H_00H, 0x05, 0x00, IAP_F_FM | IAP_F_CC),
627 IAPDESCR(05H_01H, 0x05, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB |
628 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
629 IAPDESCR(05H_02H, 0x05, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_WM | IAP_F_SB |
630 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
631 IAPDESCR(05H_03H, 0x05, 0x03, IAP_F_FM | IAP_F_I7O),
633 IAPDESCR(06H_00H, 0x06, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2 |
634 IAP_F_CC2E | IAP_F_CA),
635 IAPDESCR(06H_01H, 0x06, 0x01, IAP_F_FM | IAP_F_I7O),
636 IAPDESCR(06H_02H, 0x06, 0x02, IAP_F_FM | IAP_F_I7O),
637 IAPDESCR(06H_04H, 0x06, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
638 IAPDESCR(06H_08H, 0x06, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
639 IAPDESCR(06H_0FH, 0x06, 0x0F, IAP_F_FM | IAP_F_I7O),
641 IAPDESCR(07H_00H, 0x07, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
642 IAPDESCR(07H_01H, 0x07, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
643 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX |
645 IAPDESCR(07H_02H, 0x07, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2),
646 IAPDESCR(07H_03H, 0x07, 0x03, IAP_F_FM | IAP_F_ALLCPUSCORE2),
647 IAPDESCR(07H_06H, 0x07, 0x06, IAP_F_FM | IAP_F_CA),
648 IAPDESCR(07H_08H, 0x07, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_SB |
651 IAPDESCR(08H_01H, 0x08, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
652 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW),
653 IAPDESCR(08H_02H, 0x08, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
654 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW),
655 IAPDESCR(08H_04H, 0x08, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
656 IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW),
657 IAPDESCR(08H_05H, 0x08, 0x05, IAP_F_FM | IAP_F_CA),
658 IAPDESCR(08H_06H, 0x08, 0x06, IAP_F_FM | IAP_F_CA),
659 IAPDESCR(08H_07H, 0x08, 0x07, IAP_F_FM | IAP_F_CA),
660 IAPDESCR(08H_08H, 0x08, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
661 IAPDESCR(08H_09H, 0x08, 0x09, IAP_F_FM | IAP_F_CA),
662 IAPDESCR(08H_0EH, 0x08, 0x0E, IAP_F_FM | IAP_F_HW),
663 IAPDESCR(08H_10H, 0x08, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
664 IAP_F_SBX | IAP_F_HW),
665 IAPDESCR(08H_20H, 0x08, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_HW),
666 IAPDESCR(08H_40H, 0x08, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW),
667 IAPDESCR(08H_60H, 0x08, 0x60, IAP_F_FM | IAP_F_HW),
668 IAPDESCR(08H_80H, 0x08, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_HW),
669 IAPDESCR(08H_81H, 0x08, 0x81, IAP_F_FM | IAP_F_IB | IAP_F_IBX),
670 IAPDESCR(08H_82H, 0x08, 0x82, IAP_F_FM | IAP_F_IB | IAP_F_IBX),
671 IAPDESCR(08H_84H, 0x08, 0x84, IAP_F_FM | IAP_F_IB | IAP_F_IBX),
673 IAPDESCR(09H_01H, 0x09, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O),
674 IAPDESCR(09H_02H, 0x09, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O),
675 IAPDESCR(09H_04H, 0x09, 0x04, IAP_F_FM | IAP_F_I7O),
676 IAPDESCR(09H_08H, 0x09, 0x08, IAP_F_FM | IAP_F_I7O),
678 IAPDESCR(0BH_01H, 0x0B, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
679 IAPDESCR(0BH_02H, 0x0B, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
680 IAPDESCR(0BH_10H, 0x0B, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
682 IAPDESCR(0CH_01H, 0x0C, 0x01, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 |
684 IAPDESCR(0CH_02H, 0x0C, 0x02, IAP_F_FM | IAP_F_CC2),
685 IAPDESCR(0CH_03H, 0x0C, 0x03, IAP_F_FM | IAP_F_CA),
687 IAPDESCR(0DH_03H, 0x0D, 0x03, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_HW),
688 IAPDESCR(0DH_40H, 0x0D, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
690 IAPDESCR(0EH_01H, 0x0E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
691 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
692 IAPDESCR(0EH_02H, 0x0E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
693 IAPDESCR(0EH_10H, 0x0E, 0x10, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
694 IAPDESCR(0EH_20H, 0x0E, 0x20, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
695 IAPDESCR(0EH_40H, 0x0E, 0x40, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
697 IAPDESCR(0FH_01H, 0x0F, 0x01, IAP_F_FM | IAP_F_I7),
698 IAPDESCR(0FH_02H, 0x0F, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
699 IAPDESCR(0FH_08H, 0x0F, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
700 IAPDESCR(0FH_10H, 0x0F, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
701 IAPDESCR(0FH_20H, 0x0F, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
702 IAPDESCR(0FH_80H, 0x0F, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
704 IAPDESCR(10H_00H, 0x10, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
705 IAPDESCR(10H_01H, 0x10, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
706 IAP_F_WM | IAP_F_SB | IAP_F_SBX),
707 IAPDESCR(10H_02H, 0x10, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
708 IAPDESCR(10H_04H, 0x10, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
709 IAPDESCR(10H_08H, 0x10, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
710 IAPDESCR(10H_10H, 0x10, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
712 IAPDESCR(10H_20H, 0x10, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
714 IAPDESCR(10H_40H, 0x10, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
716 IAPDESCR(10H_80H, 0x10, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
718 IAPDESCR(10H_81H, 0x10, 0x81, IAP_F_FM | IAP_F_CA),
720 IAPDESCR(11H_00H, 0x11, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
721 IAPDESCR(11H_01H, 0x11, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_SB |
723 IAPDESCR(11H_02H, 0x11, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
724 IAPDESCR(11H_81H, 0x11, 0x81, IAP_F_FM | IAP_F_CA),
726 IAPDESCR(12H_00H, 0x12, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
727 IAPDESCR(12H_01H, 0x12, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM),
728 IAPDESCR(12H_02H, 0x12, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
729 IAPDESCR(12H_04H, 0x12, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
730 IAPDESCR(12H_08H, 0x12, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
731 IAPDESCR(12H_10H, 0x12, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
732 IAPDESCR(12H_20H, 0x12, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
733 IAPDESCR(12H_40H, 0x12, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
734 IAPDESCR(12H_81H, 0x12, 0x81, IAP_F_FM | IAP_F_CA),
736 IAPDESCR(13H_00H, 0x13, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
737 IAPDESCR(13H_01H, 0x13, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM),
738 IAPDESCR(13H_02H, 0x13, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
739 IAPDESCR(13H_04H, 0x13, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
740 IAPDESCR(13H_07H, 0x13, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
741 IAPDESCR(13H_81H, 0x13, 0x81, IAP_F_FM | IAP_F_CA),
743 IAPDESCR(14H_00H, 0x14, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
744 IAPDESCR(14H_01H, 0x14, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
745 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
746 IAPDESCR(14H_02H, 0x14, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
748 IAPDESCR(17H_01H, 0x17, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
751 IAPDESCR(18H_00H, 0x18, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
752 IAPDESCR(18H_01H, 0x18, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
754 IAPDESCR(19H_00H, 0x19, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
755 IAPDESCR(19H_01H, 0x19, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
756 IAP_F_I7 | IAP_F_WM),
757 IAPDESCR(19H_02H, 0x19, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
759 IAPDESCR(1DH_01H, 0x1D, 0x01, IAP_F_FM | IAP_F_I7O),
760 IAPDESCR(1DH_02H, 0x1D, 0x02, IAP_F_FM | IAP_F_I7O),
761 IAPDESCR(1DH_04H, 0x1D, 0x04, IAP_F_FM | IAP_F_I7O),
763 IAPDESCR(1EH_01H, 0x1E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
765 IAPDESCR(20H_01H, 0x20, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
766 IAPDESCR(21H, 0x21, IAP_M_CORE, IAP_F_ALLCPUSCORE2),
767 IAPDESCR(22H, 0x22, IAP_M_CORE, IAP_F_CC2),
768 IAPDESCR(23H, 0x23, IAP_M_CORE, IAP_F_ALLCPUSCORE2),
770 IAPDESCR(24H, 0x24, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2),
771 IAPDESCR(24H_01H, 0x24, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
772 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
773 IAPDESCR(24H_02H, 0x24, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
774 IAPDESCR(24H_03H, 0x24, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
775 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
776 IAPDESCR(24H_04H, 0x24, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
777 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
778 IAPDESCR(24H_08H, 0x24, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
779 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
780 IAPDESCR(24H_0CH, 0x24, 0x0C, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
781 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
782 IAPDESCR(24H_10H, 0x24, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
783 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
784 IAPDESCR(24H_20H, 0x24, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
785 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
786 IAPDESCR(24H_21H, 0x24, 0x21, IAP_F_FM | IAP_F_HW),
787 IAPDESCR(24H_22H, 0x24, 0x22, IAP_F_FM | IAP_F_HW),
788 IAPDESCR(24H_24H, 0x24, 0x24, IAP_F_FM | IAP_F_HW),
789 IAPDESCR(24H_27H, 0x24, 0x27, IAP_F_FM | IAP_F_HW),
790 IAPDESCR(24H_30H, 0x24, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
791 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
792 IAPDESCR(24H_40H, 0x24, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
793 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
794 IAPDESCR(24H_41H, 0x24, 0x41, IAP_F_FM | IAP_F_HW),
795 IAPDESCR(24H_42H, 0x24, 0x42, IAP_F_FM | IAP_F_HW),
796 IAPDESCR(24H_44H, 0x24, 0x44, IAP_F_FM | IAP_F_HW),
797 IAPDESCR(24H_50H, 0x24, 0x50, IAP_F_FM | IAP_F_HW),
798 IAPDESCR(24H_80H, 0x24, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
799 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
800 IAPDESCR(24H_C0H, 0x24, 0xC0, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
801 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
802 IAPDESCR(24H_E1H, 0x24, 0xE1, IAP_F_FM | IAP_F_HW),
803 IAPDESCR(24H_E2H, 0x24, 0xE2, IAP_F_FM | IAP_F_HW),
804 IAPDESCR(24H_E4H, 0x24, 0xE4, IAP_F_FM | IAP_F_HW),
805 IAPDESCR(24H_E7H, 0x24, 0xE7, IAP_F_FM | IAP_F_HW),
806 IAPDESCR(24H_AAH, 0x24, 0xAA, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
807 IAPDESCR(24H_F8H, 0x24, 0xF8, IAP_F_FM | IAP_F_HW),
808 IAPDESCR(24H_3FH, 0x24, 0x3F, IAP_F_FM | IAP_F_HW),
809 IAPDESCR(24H_FFH, 0x24, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_HW),
811 IAPDESCR(25H, 0x25, IAP_M_CORE, IAP_F_ALLCPUSCORE2),
813 IAPDESCR(26H, 0x26, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2),
814 IAPDESCR(26H_01H, 0x26, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
815 IAPDESCR(26H_02H, 0x26, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
816 IAPDESCR(26H_04H, 0x26, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
817 IAPDESCR(26H_08H, 0x26, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
818 IAPDESCR(26H_0FH, 0x26, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
819 IAPDESCR(26H_10H, 0x26, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
820 IAPDESCR(26H_20H, 0x26, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
821 IAPDESCR(26H_40H, 0x26, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
822 IAPDESCR(26H_80H, 0x26, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
823 IAPDESCR(26H_F0H, 0x26, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
824 IAPDESCR(26H_FFH, 0x26, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
826 IAPDESCR(27H, 0x27, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2),
827 IAPDESCR(27H_01H, 0x27, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
828 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
829 IAPDESCR(27H_02H, 0x27, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
830 IAPDESCR(27H_04H, 0x27, 0x04, IAP_F_FM | IAP_F_I7O | IAP_F_SB |
832 IAPDESCR(27H_08H, 0x27, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
833 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
834 IAPDESCR(27H_0EH, 0x27, 0x0E, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
835 IAPDESCR(27H_0FH, 0x27, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
836 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
837 IAPDESCR(27H_10H, 0x27, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
838 IAPDESCR(27H_20H, 0x27, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
839 IAPDESCR(27H_40H, 0x27, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
840 IAPDESCR(27H_50H, 0x27, 0x50, IAP_F_FM | IAP_F_HW),
841 IAPDESCR(27H_80H, 0x27, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
842 IAPDESCR(27H_E0H, 0x27, 0xE0, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
843 IAPDESCR(27H_F0H, 0x27, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
845 IAPDESCR(28H, 0x28, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2),
846 IAPDESCR(28H_01H, 0x28, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB |
847 IAP_F_SBX | IAP_F_IBX),
848 IAPDESCR(28H_02H, 0x28, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SBX),
849 IAPDESCR(28H_04H, 0x28, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
850 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
851 IAPDESCR(28H_08H, 0x28, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
852 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
853 IAPDESCR(28H_0FH, 0x28, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB |
854 IAP_F_SBX | IAP_F_IBX),
856 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI, IAP_F_CC),
857 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH,
858 IAP_F_CA | IAP_F_CC2),
859 IAPDESCR(2AH, 0x2A, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2),
860 IAPDESCR(2BH, 0x2B, IAP_M_CORE | IAP_M_MESI, IAP_F_CA | IAP_F_CC2),
862 IAPDESCR(2EH, 0x2E, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH,
864 IAPDESCR(2EH_01H, 0x2E, 0x01, IAP_F_FM | IAP_F_WM),
865 IAPDESCR(2EH_02H, 0x2E, 0x02, IAP_F_FM | IAP_F_WM),
866 IAPDESCR(2EH_41H, 0x2E, 0x41, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 |
867 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
868 IAPDESCR(2EH_4FH, 0x2E, 0x4F, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 |
869 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
871 IAPDESCR(30H, 0x30, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH,
873 IAPDESCR(32H, 0x32, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, IAP_F_CC),
874 IAPDESCR(32H, 0x32, IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
876 IAPDESCR(3AH, 0x3A, IAP_M_TRANSITION, IAP_F_CC),
877 IAPDESCR(3AH_00H, 0x3A, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
879 IAPDESCR(3BH_C0H, 0x3B, 0xC0, IAP_F_FM | IAP_F_ALLCPUSCORE2),
881 IAPDESCR(3CH_00H, 0x3C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
882 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX |
884 IAPDESCR(3CH_01H, 0x3C, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
885 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX |
887 IAPDESCR(3CH_02H, 0x3C, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2),
889 IAPDESCR(3DH_01H, 0x3D, 0x01, IAP_F_FM | IAP_F_I7O),
891 IAPDESCR(40H, 0x40, IAP_M_MESI, IAP_F_CC | IAP_F_CC2),
892 IAPDESCR(40H_01H, 0x40, 0x01, IAP_F_FM | IAP_F_I7),
893 IAPDESCR(40H_02H, 0x40, 0x02, IAP_F_FM | IAP_F_I7),
894 IAPDESCR(40H_04H, 0x40, 0x04, IAP_F_FM | IAP_F_I7),
895 IAPDESCR(40H_08H, 0x40, 0x08, IAP_F_FM | IAP_F_I7),
896 IAPDESCR(40H_0FH, 0x40, 0x0F, IAP_F_FM | IAP_F_I7),
897 IAPDESCR(40H_21H, 0x40, 0x21, IAP_F_FM | IAP_F_CA),
899 IAPDESCR(41H, 0x41, IAP_M_MESI, IAP_F_CC | IAP_F_CC2),
900 IAPDESCR(41H_01H, 0x41, 0x01, IAP_F_FM | IAP_F_I7O),
901 IAPDESCR(41H_02H, 0x41, 0x02, IAP_F_FM | IAP_F_I7),
902 IAPDESCR(41H_04H, 0x41, 0x04, IAP_F_FM | IAP_F_I7),
903 IAPDESCR(41H_08H, 0x41, 0x08, IAP_F_FM | IAP_F_I7),
904 IAPDESCR(41H_0FH, 0x41, 0x0F, IAP_F_FM | IAP_F_I7O),
905 IAPDESCR(41H_22H, 0x41, 0x22, IAP_F_FM | IAP_F_CA),
907 IAPDESCR(42H, 0x42, IAP_M_MESI, IAP_F_ALLCPUSCORE2),
908 IAPDESCR(42H_01H, 0x42, 0x01, IAP_F_FM | IAP_F_I7),
909 IAPDESCR(42H_02H, 0x42, 0x02, IAP_F_FM | IAP_F_I7),
910 IAPDESCR(42H_04H, 0x42, 0x04, IAP_F_FM | IAP_F_I7),
911 IAPDESCR(42H_08H, 0x42, 0x08, IAP_F_FM | IAP_F_I7),
912 IAPDESCR(42H_10H, 0x42, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
914 IAPDESCR(43H_01H, 0x43, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
916 IAPDESCR(43H_02H, 0x43, 0x02, IAP_F_FM | IAP_F_CA |
917 IAP_F_CC2 | IAP_F_I7),
919 IAPDESCR(44H_02H, 0x44, 0x02, IAP_F_FM | IAP_F_CC),
921 IAPDESCR(45H_0FH, 0x45, 0x0F, IAP_F_FM | IAP_F_ALLCPUSCORE2),
923 IAPDESCR(46H_00H, 0x46, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
924 IAPDESCR(47H_00H, 0x47, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
926 IAPDESCR(48H_00H, 0x48, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
927 IAPDESCR(48H_01H, 0x48, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
928 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
929 IAPDESCR(48H_02H, 0x48, 0x02, IAP_F_FM | IAP_F_I7O),
931 IAPDESCR(49H_00H, 0x49, 0x00, IAP_F_FM | IAP_F_CC),
932 IAPDESCR(49H_01H, 0x49, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
933 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX |
935 IAPDESCR(49H_02H, 0x49, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
936 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX |
938 IAPDESCR(49H_04H, 0x49, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB |
939 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
940 IAPDESCR(49H_0EH, 0x49, 0x0E, IAP_F_FM | IAP_F_HW),
941 IAPDESCR(49H_10H, 0x49, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
942 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
943 IAPDESCR(49H_20H, 0x49, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_HW),
944 IAPDESCR(49H_40H, 0x49, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW),
945 IAPDESCR(49H_60H, 0x49, 0x60, IAP_F_FM | IAP_F_HW),
946 IAPDESCR(49H_80H, 0x49, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7 | IAP_F_HW),
948 IAPDESCR(4BH_00H, 0x4B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
949 IAPDESCR(4BH_01H, 0x4B, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7O),
950 IAPDESCR(4BH_02H, 0x4B, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2),
951 IAPDESCR(4BH_03H, 0x4B, 0x03, IAP_F_FM | IAP_F_CC),
952 IAPDESCR(4BH_08H, 0x4B, 0x08, IAP_F_FM | IAP_F_I7O),
954 IAPDESCR(4CH_00H, 0x4C, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
955 IAPDESCR(4CH_01H, 0x4C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
956 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
957 IAPDESCR(4CH_02H, 0x4C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB |
958 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
960 IAPDESCR(4DH_01H, 0x4D, 0x01, IAP_F_FM | IAP_F_I7O),
962 IAPDESCR(4EH_01H, 0x4E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
963 IAPDESCR(4EH_02H, 0x4E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
964 IAP_F_SB | IAP_F_SBX),
965 IAPDESCR(4EH_04H, 0x4E, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
966 IAPDESCR(4EH_10H, 0x4E, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
968 IAPDESCR(4FH_00H, 0x4F, 0x00, IAP_F_FM | IAP_F_CC),
969 IAPDESCR(4FH_02H, 0x4F, 0x02, IAP_F_FM | IAP_F_I7O),
970 IAPDESCR(4FH_04H, 0x4F, 0x04, IAP_F_FM | IAP_F_I7O),
971 IAPDESCR(4FH_08H, 0x4F, 0x08, IAP_F_FM | IAP_F_I7O),
972 IAPDESCR(4FH_10H, 0x4F, 0x10, IAP_F_FM | IAP_F_WM),
974 IAPDESCR(51H_01H, 0x51, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
975 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
976 IAPDESCR(51H_02H, 0x51, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
977 IAP_F_SB | IAP_F_SBX),
978 IAPDESCR(51H_04H, 0x51, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
979 IAP_F_SB | IAP_F_SBX),
980 IAPDESCR(51H_08H, 0x51, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
981 IAP_F_SB | IAP_F_SBX),
983 IAPDESCR(52H_01H, 0x52, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
985 IAPDESCR(53H_01H, 0x53, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
987 IAPDESCR(58H_01H, 0x58, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
988 IAPDESCR(58H_02H, 0x58, 0x02, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
989 IAPDESCR(58H_04H, 0x58, 0x04, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
990 IAPDESCR(58H_08H, 0x58, 0x08, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
992 IAPDESCR(59H_20H, 0x59, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
993 IAPDESCR(59H_40H, 0x59, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
994 IAPDESCR(59H_80H, 0x59, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
996 IAPDESCR(5BH_0CH, 0x5B, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
997 IAPDESCR(5BH_0FH, 0x5B, 0x0F, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
998 IAPDESCR(5BH_40H, 0x5B, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
999 IAPDESCR(5BH_4FH, 0x5B, 0x4F, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1001 IAPDESCR(5CH_01H, 0x5C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1002 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1003 IAPDESCR(5CH_02H, 0x5C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1004 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1006 IAPDESCR(5EH_01H, 0x5E, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1007 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1009 IAPDESCR(5FH_01H, 0x5F, 0x01, IAP_F_FM | IAP_F_IB),
1010 IAPDESCR(5FH_04H, 0x5F, 0x04, IAP_F_IBX),
1012 IAPDESCR(60H, 0x60, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1013 IAPDESCR(60H_01H, 0x60, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
1014 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1015 IAPDESCR(60H_02H, 0x60, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB |
1016 IAP_F_IBX | IAP_F_HW),
1017 IAPDESCR(60H_04H, 0x60, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
1018 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1019 IAPDESCR(60H_08H, 0x60, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
1020 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1022 IAPDESCR(61H, 0x61, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2),
1023 IAPDESCR(61H_00H, 0x61, 0x00, IAP_F_FM | IAP_F_CC),
1025 IAPDESCR(62H, 0x62, IAP_M_AGENT, IAP_F_ALLCPUSCORE2),
1026 IAPDESCR(62H_00H, 0x62, 0x00, IAP_F_FM | IAP_F_CC),
1028 IAPDESCR(63H, 0x63, IAP_M_AGENT | IAP_M_CORE,
1029 IAP_F_CA | IAP_F_CC2),
1030 IAPDESCR(63H, 0x63, IAP_M_CORE, IAP_F_CC),
1031 IAPDESCR(63H_01H, 0x63, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1032 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1033 IAPDESCR(63H_02H, 0x63, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1034 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1036 IAPDESCR(64H, 0x64, IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1037 IAPDESCR(64H_40H, 0x64, 0x40, IAP_F_FM | IAP_F_CC),
1039 IAPDESCR(65H, 0x65, IAP_M_AGENT | IAP_M_CORE,
1040 IAP_F_CA | IAP_F_CC2),
1041 IAPDESCR(65H, 0x65, IAP_M_CORE, IAP_F_CC),
1043 IAPDESCR(66H, 0x66, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1045 IAPDESCR(67H, 0x67, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1046 IAPDESCR(67H, 0x67, IAP_M_AGENT, IAP_F_CC),
1048 IAPDESCR(68H, 0x68, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1049 IAPDESCR(69H, 0x69, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1050 IAPDESCR(6AH, 0x6A, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1051 IAPDESCR(6BH, 0x6B, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1053 IAPDESCR(6CH, 0x6C, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1054 IAPDESCR(6CH_01H, 0x6C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1056 IAPDESCR(6DH, 0x6D, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1057 IAPDESCR(6DH, 0x6D, IAP_M_CORE, IAP_F_CC),
1059 IAPDESCR(6EH, 0x6E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1060 IAPDESCR(6EH, 0x6E, IAP_M_CORE, IAP_F_CC),
1062 IAPDESCR(6FH, 0x6F, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1063 IAPDESCR(6FH, 0x6F, IAP_M_CORE, IAP_F_CC),
1065 IAPDESCR(70H, 0x70, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1066 IAPDESCR(70H, 0x70, IAP_M_CORE, IAP_F_CC),
1068 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_SNOOPRESPONSE,
1069 IAP_F_CA | IAP_F_CC2),
1070 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_MESI, IAP_F_CC),
1072 IAPDESCR(78H, 0x78, IAP_M_CORE, IAP_F_CC),
1073 IAPDESCR(78H, 0x78, IAP_M_CORE | IAP_M_SNOOPTYPE, IAP_F_CA | IAP_F_CC2),
1075 IAPDESCR(79H_02H, 0x79, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1076 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1077 IAPDESCR(79H_04H, 0x79, 0x04, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1078 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1079 IAPDESCR(79H_08H, 0x79, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1080 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1081 IAPDESCR(79H_10H, 0x79, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1082 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1083 IAPDESCR(79H_20H, 0x79, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1084 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1085 IAPDESCR(79H_30H, 0x79, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1086 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1087 IAPDESCR(79H_18H, 0x79, 0x18, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
1088 IAPDESCR(79H_24H, 0x79, 0x24, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
1089 IAPDESCR(79H_3CH, 0x79, 0x3C, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
1091 IAPDESCR(7AH, 0x7A, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2),
1093 IAPDESCR(7BH, 0x7B, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2),
1095 IAPDESCR(7DH, 0x7D, IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1097 IAPDESCR(7EH, 0x7E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1098 IAPDESCR(7EH_00H, 0x7E, 0x00, IAP_F_FM | IAP_F_CC),
1100 IAPDESCR(7FH, 0x7F, IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1102 IAPDESCR(80H_00H, 0x80, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1103 IAPDESCR(80H_01H, 0x80, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1104 IAPDESCR(80H_02H, 0x80, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
1105 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1106 IAPDESCR(80H_03H, 0x80, 0x03, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
1108 IAPDESCR(80H_04H, 0x80, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1110 IAPDESCR(81H_00H, 0x81, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1111 IAPDESCR(81H_01H, 0x81, 0x01, IAP_F_FM | IAP_F_I7O),
1112 IAPDESCR(81H_02H, 0x81, 0x02, IAP_F_FM | IAP_F_I7O),
1114 IAPDESCR(82H_01H, 0x82, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1115 IAPDESCR(82H_02H, 0x82, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1116 IAPDESCR(82H_04H, 0x82, 0x04, IAP_F_FM | IAP_F_CA),
1117 IAPDESCR(82H_10H, 0x82, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1118 IAPDESCR(82H_12H, 0x82, 0x12, IAP_F_FM | IAP_F_CC2),
1119 IAPDESCR(82H_40H, 0x82, 0x40, IAP_F_FM | IAP_F_CC2),
1121 IAPDESCR(83H_01H, 0x83, 0x01, IAP_F_FM | IAP_F_I7O),
1122 IAPDESCR(83H_02H, 0x83, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1124 IAPDESCR(85H_00H, 0x85, 0x00, IAP_F_FM | IAP_F_CC),
1125 IAPDESCR(85H_01H, 0x85, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1126 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1127 IAPDESCR(85H_02H, 0x85, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1128 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1129 IAPDESCR(85H_04H, 0x85, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
1130 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1131 IAPDESCR(85H_0EH, 0x85, 0x0E, IAP_F_FM | IAP_F_HW),
1132 IAPDESCR(85H_10H, 0x85, 0x10, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB |
1133 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1134 IAPDESCR(85H_20H, 0x85, 0x20, IAP_F_FM | IAP_F_I7O | IAP_F_HW),
1135 IAPDESCR(85H_40H, 0x85, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW),
1136 IAPDESCR(85H_60H, 0x85, 0x60, IAP_F_FM | IAP_F_HW),
1137 IAPDESCR(85H_80H, 0x85, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
1139 IAPDESCR(86H_00H, 0x86, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1141 IAPDESCR(87H_00H, 0x87, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1142 IAPDESCR(87H_01H, 0x87, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1143 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1144 IAPDESCR(87H_02H, 0x87, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1145 IAPDESCR(87H_04H, 0x87, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1146 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1147 IAPDESCR(87H_08H, 0x87, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1148 IAPDESCR(87H_0FH, 0x87, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1150 IAPDESCR(88H_00H, 0x88, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1151 IAPDESCR(88H_01H, 0x88, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1152 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1153 IAPDESCR(88H_02H, 0x88, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1154 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1155 IAPDESCR(88H_04H, 0x88, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1156 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1157 IAPDESCR(88H_07H, 0x88, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1158 IAPDESCR(88H_08H, 0x88, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1159 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1160 IAPDESCR(88H_10H, 0x88, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1161 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1162 IAPDESCR(88H_20H, 0x88, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1163 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1164 IAPDESCR(88H_30H, 0x88, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1165 IAPDESCR(88H_40H, 0x88, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1166 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1167 IAPDESCR(88H_7FH, 0x88, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1168 IAPDESCR(88H_80H, 0x88, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1169 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1170 IAPDESCR(88H_FFH, 0x88, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1171 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1173 IAPDESCR(89H_00H, 0x89, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1174 IAPDESCR(89H_01H, 0x89, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1175 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1176 IAPDESCR(89H_02H, 0x89, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1177 IAPDESCR(89H_04H, 0x89, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1178 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1179 IAPDESCR(89H_07H, 0x89, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1180 IAPDESCR(89H_08H, 0x89, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1181 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1182 IAPDESCR(89H_10H, 0x89, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1183 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1184 IAPDESCR(89H_20H, 0x89, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1185 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1186 IAPDESCR(89H_30H, 0x89, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1187 IAPDESCR(89H_40H, 0x89, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1188 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1189 IAPDESCR(89H_7FH, 0x89, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1190 IAPDESCR(89H_80H, 0x89, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1191 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1192 IAPDESCR(89H_FFH, 0x89, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1193 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1195 IAPDESCR(8AH_00H, 0x8A, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1196 IAPDESCR(8BH_00H, 0x8B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1197 IAPDESCR(8CH_00H, 0x8C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1198 IAPDESCR(8DH_00H, 0x8D, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1199 IAPDESCR(8EH_00H, 0x8E, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1200 IAPDESCR(8FH_00H, 0x8F, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1202 IAPDESCR(90H_00H, 0x90, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1203 IAPDESCR(91H_00H, 0x91, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1204 IAPDESCR(92H_00H, 0x92, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1205 IAPDESCR(93H_00H, 0x93, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1206 IAPDESCR(94H_00H, 0x94, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1208 IAPDESCR(9CH_01H, 0x9C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1209 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1211 IAPDESCR(97H_00H, 0x97, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1212 IAPDESCR(98H_00H, 0x98, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1213 IAPDESCR(A0H_00H, 0xA0, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1215 IAPDESCR(A1H_01H, 0xA1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1216 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1217 IAPDESCR(A1H_02H, 0xA1, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1218 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1219 IAPDESCR(A1H_04H, 0xA1, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1220 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1221 IAPDESCR(A1H_08H, 0xA1, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1222 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1223 IAPDESCR(A1H_0CH, 0xA1, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1224 IAP_F_SBX | IAP_F_IBX),
1225 IAPDESCR(A1H_10H, 0xA1, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1226 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1227 IAPDESCR(A1H_20H, 0xA1, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1228 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1229 IAPDESCR(A1H_30H, 0xA1, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1230 IAP_F_SBX | IAP_F_IBX),
1231 IAPDESCR(A1H_40H, 0xA1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1232 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1233 IAPDESCR(A1H_80H, 0xA1, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1234 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1236 IAPDESCR(A2H_00H, 0xA2, 0x00, IAP_F_FM | IAP_F_CC),
1237 IAPDESCR(A2H_01H, 0xA2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1238 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1239 IAPDESCR(A2H_02H, 0xA2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1240 IAP_F_SB | IAP_F_SBX),
1241 IAPDESCR(A2H_04H, 0xA2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1242 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1243 IAPDESCR(A2H_08H, 0xA2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1244 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1245 IAPDESCR(A2H_10H, 0xA2, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1246 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1247 IAPDESCR(A2H_20H, 0xA2, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1248 IAP_F_SB | IAP_F_SBX),
1249 IAPDESCR(A2H_40H, 0xA2, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1250 IAP_F_SB | IAP_F_SBX),
1251 IAPDESCR(A2H_80H, 0xA2, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1252 IAP_F_SB | IAP_F_SBX),
1254 IAPDESCR(A3H_01H, 0xA3, 0x01, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1255 IAPDESCR(A3H_02H, 0xA3, 0x02, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1256 IAPDESCR(A3H_04H, 0xA3, 0x04, IAP_F_FM | IAP_F_SBX | IAP_F_IBX),
1257 IAPDESCR(A3H_05H, 0xA3, 0x05, IAP_F_FM | IAP_F_HW),
1258 IAPDESCR(A3H_08H, 0xA3, 0x08, IAP_F_FM | IAP_F_IBX | IAP_F_HW),
1260 IAPDESCR(A6H_01H, 0xA6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1261 IAPDESCR(A7H_01H, 0xA7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1262 IAPDESCR(A8H_01H, 0xA8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1264 IAPDESCR(AAH_01H, 0xAA, 0x01, IAP_F_FM | IAP_F_CC2),
1265 IAPDESCR(AAH_02H, 0xAA, 0x02, IAP_F_FM | IAP_F_CA),
1266 IAPDESCR(AAH_03H, 0xAA, 0x03, IAP_F_FM | IAP_F_CA),
1267 IAPDESCR(AAH_08H, 0xAA, 0x08, IAP_F_FM | IAP_F_CC2),
1269 IAPDESCR(ABH_01H, 0xAB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1270 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1271 IAPDESCR(ABH_02H, 0xAB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1272 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1274 IAPDESCR(ACH_02H, 0xAC, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1275 IAPDESCR(ACH_08H, 0xAC, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1276 IAP_F_SBX | IAP_F_IBX),
1277 IAPDESCR(ACH_0AH, 0xAC, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1279 IAPDESCR(AEH_01H, 0xAE, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1280 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1282 IAPDESCR(B0H_00H, 0xB0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1283 IAPDESCR(B0H_01H, 0xB0, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
1284 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1285 IAPDESCR(B0H_02H, 0xB0, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB |
1286 IAP_F_IBX | IAP_F_HW),
1287 IAPDESCR(B0H_04H, 0xB0, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
1288 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1289 IAPDESCR(B0H_08H, 0xB0, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
1290 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1291 IAPDESCR(B0H_10H, 0xB0, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
1292 IAPDESCR(B0H_20H, 0xB0, 0x20, IAP_F_FM | IAP_F_I7O),
1293 IAPDESCR(B0H_40H, 0xB0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1294 IAPDESCR(B0H_80H, 0xB0, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_WM | IAP_F_I7O),
1296 IAPDESCR(B1H_00H, 0xB1, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1297 IAPDESCR(B1H_01H, 0xB1, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1298 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1299 IAPDESCR(B1H_02H, 0xB1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1300 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1301 IAPDESCR(B1H_04H, 0xB1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1302 IAPDESCR(B1H_08H, 0xB1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1303 IAPDESCR(B1H_10H, 0xB1, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1304 IAPDESCR(B1H_1FH, 0xB1, 0x1F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1305 IAPDESCR(B1H_20H, 0xB1, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1306 IAPDESCR(B1H_3FH, 0xB1, 0x3F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1307 IAPDESCR(B1H_40H, 0xB1, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1308 IAPDESCR(B1H_80H, 0xB1, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
1311 IAPDESCR(B2H_01H, 0xB2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1312 IAP_F_SB | IAP_F_SBX),
1314 IAPDESCR(B3H_01H, 0xB3, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1315 IAP_F_WM | IAP_F_I7O),
1316 IAPDESCR(B3H_02H, 0xB3, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1317 IAP_F_WM | IAP_F_I7O),
1318 IAPDESCR(B3H_04H, 0xB3, 0x04, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1319 IAP_F_WM | IAP_F_I7O),
1320 IAPDESCR(B3H_08H, 0xB3, 0x08, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1321 IAPDESCR(B3H_10H, 0xB3, 0x10, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1322 IAPDESCR(B3H_20H, 0xB3, 0x20, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1323 IAPDESCR(B3H_81H, 0xB3, 0x81, IAP_F_FM | IAP_F_CA),
1324 IAPDESCR(B3H_82H, 0xB3, 0x82, IAP_F_FM | IAP_F_CA),
1325 IAPDESCR(B3H_84H, 0xB3, 0x84, IAP_F_FM | IAP_F_CA),
1326 IAPDESCR(B3H_88H, 0xB3, 0x88, IAP_F_FM | IAP_F_CA),
1327 IAPDESCR(B3H_90H, 0xB3, 0x90, IAP_F_FM | IAP_F_CA),
1328 IAPDESCR(B3H_A0H, 0xB3, 0xA0, IAP_F_FM | IAP_F_CA),
1330 IAPDESCR(B4H_01H, 0xB4, 0x01, IAP_F_FM | IAP_F_WM),
1331 IAPDESCR(B4H_02H, 0xB4, 0x02, IAP_F_FM | IAP_F_WM),
1332 IAPDESCR(B4H_04H, 0xB4, 0x04, IAP_F_FM | IAP_F_WM),
1334 IAPDESCR(B6H_01H, 0xB6, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1336 IAPDESCR(B7H_01H, 0xB7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1337 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1339 IAPDESCR(B8H_01H, 0xB8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1340 IAPDESCR(B8H_02H, 0xB8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1341 IAPDESCR(B8H_04H, 0xB8, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1343 IAPDESCR(BAH_01H, 0xBA, 0x01, IAP_F_FM | IAP_F_I7O),
1344 IAPDESCR(BAH_02H, 0xBA, 0x02, IAP_F_FM | IAP_F_I7O),
1346 IAPDESCR(BBH_01H, 0xBB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1347 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1349 IAPDESCR(BCH_11H, 0xBC, 0x11, IAP_F_FM | IAP_F_HW),
1350 IAPDESCR(BCH_12H, 0xBC, 0x12, IAP_F_FM | IAP_F_HW),
1351 IAPDESCR(BCH_14H, 0xBC, 0x14, IAP_F_FM | IAP_F_HW),
1352 IAPDESCR(BCH_18H, 0xBC, 0x18, IAP_F_FM | IAP_F_HW),
1353 IAPDESCR(BCH_21H, 0xBC, 0x21, IAP_F_FM | IAP_F_HW),
1354 IAPDESCR(BCH_22H, 0xBC, 0x22, IAP_F_FM | IAP_F_HW),
1355 IAPDESCR(BCH_24H, 0xBC, 0x24, IAP_F_FM | IAP_F_HW),
1356 IAPDESCR(BCH_28H, 0xBC, 0x28, IAP_F_FM | IAP_F_HW),
1358 IAPDESCR(BDH_01H, 0xBD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1359 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1360 IAPDESCR(BDH_20H, 0xBD, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1361 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1363 IAPDESCR(BFH_05H, 0xBF, 0x05, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1365 IAPDESCR(C0H_00H, 0xC0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1366 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1367 IAPDESCR(C0H_01H, 0xC0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1368 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1369 IAP_F_IBX | IAP_F_HW),
1370 IAPDESCR(C0H_02H, 0xC0, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1371 IAP_F_I7 | IAP_F_WM | IAP_F_SB),
1372 IAPDESCR(C0H_04H, 0xC0, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1373 IAP_F_I7 | IAP_F_WM),
1374 IAPDESCR(C0H_08H, 0xC0, 0x08, IAP_F_FM | IAP_F_CC2E),
1376 IAPDESCR(C1H_00H, 0xC1, 0x00, IAP_F_FM | IAP_F_CC),
1377 IAPDESCR(C1H_01H, 0xC1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1378 IAPDESCR(C1H_02H, 0xC1, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1379 IAPDESCR(C1H_08H, 0xC1, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1380 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1381 IAPDESCR(C1H_10H, 0xC1, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1382 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1383 IAPDESCR(C1H_20H, 0xC1, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1384 IAP_F_SBX | IAP_F_IBX),
1385 IAPDESCR(C1H_40H, 0xC1, 0x40, IAP_F_FM | IAP_F_HW),
1386 IAPDESCR(C1H_FEH, 0xC1, 0xFE, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1388 IAPDESCR(C2H_00H, 0xC2, 0x00, IAP_F_FM | IAP_F_CC),
1389 IAPDESCR(C2H_01H, 0xC2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1390 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1391 IAP_F_IBX | IAP_F_HW),
1392 IAPDESCR(C2H_02H, 0xC2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1393 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1394 IAP_F_IBX | IAP_F_HW),
1395 IAPDESCR(C2H_04H, 0xC2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1396 IAP_F_I7 | IAP_F_WM),
1397 IAPDESCR(C2H_07H, 0xC2, 0x07, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1398 IAPDESCR(C2H_08H, 0xC2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1399 IAPDESCR(C2H_0FH, 0xC2, 0x0F, IAP_F_FM | IAP_F_CC2),
1400 IAPDESCR(C2H_10H, 0xC2, 0x10, IAP_F_FM | IAP_F_CA),
1402 IAPDESCR(C3H_00H, 0xC3, 0x00, IAP_F_FM | IAP_F_CC),
1403 IAPDESCR(C3H_01H, 0xC3, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1404 IAP_F_I7 | IAP_F_WM),
1405 IAPDESCR(C3H_02H, 0xC3, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1406 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1407 IAPDESCR(C3H_04H, 0xC3, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1408 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1409 IAP_F_IBX | IAP_F_HW),
1410 IAPDESCR(C3H_10H, 0xC3, 0x10, IAP_F_FM | IAP_F_I7O),
1411 IAPDESCR(C3H_20H, 0xC3, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1412 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1414 IAPDESCR(C4H_00H, 0xC4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1415 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1416 IAP_F_IBX | IAP_F_HW),
1417 IAPDESCR(C4H_01H, 0xC4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1418 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1419 IAP_F_IBX | IAP_F_HW),
1420 IAPDESCR(C4H_02H, 0xC4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1421 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1422 IAP_F_IBX | IAP_F_HW),
1423 IAPDESCR(C4H_04H, 0xC4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1424 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1425 IAP_F_IBX | IAP_F_HW),
1426 IAPDESCR(C4H_08H, 0xC4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1427 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1428 IAPDESCR(C4H_0CH, 0xC4, 0x0C, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1429 IAPDESCR(C4H_0FH, 0xC4, 0x0F, IAP_F_FM | IAP_F_CA),
1430 IAPDESCR(C4H_10H, 0xC4, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1431 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1432 IAPDESCR(C4H_20H, 0xC4, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1433 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1434 IAPDESCR(C4H_40H, 0xC4, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1435 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1437 IAPDESCR(C5H_00H, 0xC5, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1438 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1439 IAP_F_IBX | IAP_F_HW),
1440 IAPDESCR(C5H_01H, 0xC5, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB |
1441 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1442 IAPDESCR(C5H_02H, 0xC5, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1443 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1444 IAPDESCR(C5H_04H, 0xC5, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB |
1445 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1446 IAPDESCR(C5H_10H, 0xC5, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1447 IAP_F_SBX | IAP_F_IBX),
1448 IAPDESCR(C5H_20H, 0xC5, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1449 IAP_F_SBX | IAP_F_IBX),
1451 IAPDESCR(C6H_00H, 0xC6, 0x00, IAP_F_FM | IAP_F_CC),
1452 IAPDESCR(C6H_01H, 0xC6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1453 IAPDESCR(C6H_02H, 0xC6, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1455 IAPDESCR(C7H_00H, 0xC7, 0x00, IAP_F_FM | IAP_F_CC),
1456 IAPDESCR(C7H_01H, 0xC7, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1457 IAP_F_I7 | IAP_F_WM),
1458 IAPDESCR(C7H_02H, 0xC7, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1459 IAP_F_I7 | IAP_F_WM),
1460 IAPDESCR(C7H_04H, 0xC7, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1461 IAP_F_I7 | IAP_F_WM),
1462 IAPDESCR(C7H_08H, 0xC7, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1463 IAP_F_I7 | IAP_F_WM),
1464 IAPDESCR(C7H_10H, 0xC7, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1465 IAP_F_I7 | IAP_F_WM),
1466 IAPDESCR(C7H_1FH, 0xC7, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1468 IAPDESCR(C8H_00H, 0xC8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1469 IAPDESCR(C8H_20H, 0xC8, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1471 IAPDESCR(C9H_00H, 0xC9, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1473 IAPDESCR(CAH_00H, 0xCA, 0x00, IAP_F_FM | IAP_F_CC),
1474 IAPDESCR(CAH_01H, 0xCA, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1475 IAPDESCR(CAH_02H, 0xCA, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1476 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1477 IAPDESCR(CAH_04H, 0xCA, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1478 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1479 IAPDESCR(CAH_08H, 0xCA, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1480 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1481 IAPDESCR(CAH_10H, 0xCA, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1482 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1483 IAPDESCR(CAH_1EH, 0xCA, 0x1E, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1484 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1486 IAPDESCR(CBH_01H, 0xCB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1487 IAP_F_I7 | IAP_F_WM),
1488 IAPDESCR(CBH_02H, 0xCB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1489 IAP_F_I7 | IAP_F_WM),
1490 IAPDESCR(CBH_04H, 0xCB, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1491 IAP_F_I7 | IAP_F_WM),
1492 IAPDESCR(CBH_08H, 0xCB, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1493 IAP_F_I7 | IAP_F_WM),
1494 IAPDESCR(CBH_10H, 0xCB, 0x10, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 |
1496 IAPDESCR(CBH_40H, 0xCB, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1497 IAPDESCR(CBH_80H, 0xCB, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1499 IAPDESCR(CCH_00H, 0xCC, 0x00, IAP_F_FM | IAP_F_CC),
1500 IAPDESCR(CCH_01H, 0xCC, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1501 IAP_F_I7 | IAP_F_WM),
1502 IAPDESCR(CCH_02H, 0xCC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1503 IAP_F_I7 | IAP_F_WM),
1504 IAPDESCR(CCH_03H, 0xCC, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1505 IAPDESCR(CCH_20H, 0xCC, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1506 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1508 IAPDESCR(CDH_00H, 0xCD, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1509 IAPDESCR(CDH_01H, 0xCD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1510 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1511 IAPDESCR(CDH_02H, 0xCD, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1512 IAP_F_SBX | IAP_F_IBX),
1514 IAPDESCR(CEH_00H, 0xCE, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1515 IAPDESCR(CFH_00H, 0xCF, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1517 /* Sandy Bridge / Sandy Bridge Xeon - 11, 12, 21, 41, 42, 81, 82 */
1518 IAPDESCR(D0H_00H, 0xD0, 0x00, IAP_F_FM | IAP_F_CC),
1519 IAPDESCR(D0H_01H, 0xD0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB |
1520 IAP_F_IBX | IAP_F_HW),
1521 IAPDESCR(D0H_02H, 0xD0, 0x02, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
1522 IAPDESCR(D0H_10H, 0xD0, 0x10, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
1523 IAPDESCR(D0H_11H, 0xD0, 0x11, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1524 IAPDESCR(D0H_12H, 0xD0, 0x12, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1525 IAPDESCR(D0H_20H, 0xD0, 0x20, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
1526 IAPDESCR(D0H_21H, 0xD0, 0x21, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1527 IAPDESCR(D0H_40H, 0xD0, 0x40, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
1528 IAPDESCR(D0H_41H, 0xD0, 0x41, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1529 IAPDESCR(D0H_42H, 0xD0, 0x42, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1530 IAPDESCR(D0H_80H, 0xD0, 0x80, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
1531 IAPDESCR(D0H_81H, 0xD0, 0x81, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1532 IAPDESCR(D0H_82H, 0xD0, 0x82, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1534 IAPDESCR(D1H_01H, 0xD1, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB |
1535 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1536 IAPDESCR(D1H_02H, 0xD1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1537 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1538 IAPDESCR(D1H_04H, 0xD1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1539 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1540 IAPDESCR(D1H_08H, 0xD1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1541 IAPDESCR(D1H_10H, 0xD1, 0x10, IAP_F_HW),
1542 IAPDESCR(D1H_20H, 0xD1, 0x20, IAP_F_FM | IAP_F_SBX | IAP_F_IBX),
1543 IAPDESCR(D1H_40H, 0xD1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1544 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1546 IAPDESCR(D2H_01H, 0xD2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1547 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB |
1548 IAP_F_IBX | IAP_F_HW),
1549 IAPDESCR(D2H_02H, 0xD2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1550 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB |
1551 IAP_F_IBX | IAP_F_HW),
1552 IAPDESCR(D2H_04H, 0xD2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1553 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB |
1554 IAP_F_IBX | IAP_F_HW),
1555 IAPDESCR(D2H_08H, 0xD2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1556 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB |
1557 IAP_F_IBX | IAP_F_HW),
1558 IAPDESCR(D2H_0FH, 0xD2, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1559 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB |
1560 IAP_F_IBX | IAP_F_HW),
1562 IAPDESCR(D2H_10H, 0xD2, 0x10, IAP_F_FM | IAP_F_CC2E),
1564 IAPDESCR(D3H_01H, 0xD3, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_SBX |
1565 IAP_F_IBX | IAP_F_HW),
1566 IAPDESCR(D3H_04H, 0xD3, 0x04, IAP_F_FM | IAP_F_SBX | IAP_F_IBX),
1567 IAPDESCR(D3H_10H, 0xD3, 0x10, IAP_F_IBX),
1568 IAPDESCR(D3H_20H, 0xD3, 0x20, IAP_F_IBX),
1570 IAPDESCR(D4H_01H, 0xD4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1571 IAP_F_I7 | IAP_F_WM),
1572 IAPDESCR(D4H_02H, 0xD4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1573 IAP_F_SB | IAP_F_SBX),
1574 IAPDESCR(D4H_04H, 0xD4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1575 IAPDESCR(D4H_08H, 0xD4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1576 IAPDESCR(D4H_0FH, 0xD4, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1578 IAPDESCR(D5H_01H, 0xD5, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1579 IAP_F_I7 | IAP_F_WM),
1580 IAPDESCR(D5H_02H, 0xD5, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1581 IAPDESCR(D5H_04H, 0xD5, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1582 IAPDESCR(D5H_08H, 0xD5, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1583 IAPDESCR(D5H_0FH, 0xD5, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1585 IAPDESCR(D7H_00H, 0xD7, 0x00, IAP_F_FM | IAP_F_CC),
1587 IAPDESCR(D8H_00H, 0xD8, 0x00, IAP_F_FM | IAP_F_CC),
1588 IAPDESCR(D8H_01H, 0xD8, 0x01, IAP_F_FM | IAP_F_CC),
1589 IAPDESCR(D8H_02H, 0xD8, 0x02, IAP_F_FM | IAP_F_CC),
1590 IAPDESCR(D8H_03H, 0xD8, 0x03, IAP_F_FM | IAP_F_CC),
1591 IAPDESCR(D8H_04H, 0xD8, 0x04, IAP_F_FM | IAP_F_CC),
1593 IAPDESCR(D9H_00H, 0xD9, 0x00, IAP_F_FM | IAP_F_CC),
1594 IAPDESCR(D9H_01H, 0xD9, 0x01, IAP_F_FM | IAP_F_CC),
1595 IAPDESCR(D9H_02H, 0xD9, 0x02, IAP_F_FM | IAP_F_CC),
1596 IAPDESCR(D9H_03H, 0xD9, 0x03, IAP_F_FM | IAP_F_CC),
1598 IAPDESCR(DAH_00H, 0xDA, 0x00, IAP_F_FM | IAP_F_CC),
1599 IAPDESCR(DAH_01H, 0xDA, 0x01, IAP_F_FM | IAP_F_CC),
1600 IAPDESCR(DAH_02H, 0xDA, 0x02, IAP_F_FM | IAP_F_CC),
1602 IAPDESCR(DBH_00H, 0xDB, 0x00, IAP_F_FM | IAP_F_CC),
1603 IAPDESCR(DBH_01H, 0xDB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1605 IAPDESCR(DCH_01H, 0xDC, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1606 IAPDESCR(DCH_02H, 0xDC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1607 IAPDESCR(DCH_04H, 0xDC, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1608 IAPDESCR(DCH_08H, 0xDC, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1609 IAPDESCR(DCH_10H, 0xDC, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1610 IAPDESCR(DCH_1FH, 0xDC, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1612 IAPDESCR(E0H_00H, 0xE0, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
1613 IAPDESCR(E0H_01H, 0xE0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
1616 IAPDESCR(E2H_00H, 0xE2, 0x00, IAP_F_FM | IAP_F_CC),
1618 IAPDESCR(E4H_00H, 0xE4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1619 IAPDESCR(E4H_01H, 0xE4, 0x01, IAP_F_FM | IAP_F_I7O),
1621 IAPDESCR(E5H_01H, 0xE5, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1623 IAPDESCR(E6H_00H, 0xE6, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
1624 IAPDESCR(E6H_01H, 0xE6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
1625 IAP_F_WM | IAP_F_SBX),
1626 IAPDESCR(E6H_02H, 0xE6, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1627 IAPDESCR(E6H_1FH, 0xE6, 0x1F, IAP_F_FM | IAP_F_IBX | IAP_F_HW),
1629 IAPDESCR(E8H_01H, 0xE8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1630 IAPDESCR(E8H_02H, 0xE8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1631 IAPDESCR(E8H_03H, 0xE8, 0x03, IAP_F_FM | IAP_F_I7O),
1633 IAPDESCR(ECH_01H, 0xEC, 0x01, IAP_F_FM | IAP_F_WM),
1635 IAPDESCR(F0H_00H, 0xF0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1636 IAPDESCR(F0H_01H, 0xF0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1637 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1638 IAPDESCR(F0H_02H, 0xF0, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1639 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1640 IAPDESCR(F0H_04H, 0xF0, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1641 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1642 IAPDESCR(F0H_08H, 0xF0, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1643 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1644 IAPDESCR(F0H_10H, 0xF0, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1645 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1646 IAPDESCR(F0H_20H, 0xF0, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1647 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1648 IAPDESCR(F0H_40H, 0xF0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1649 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1650 IAPDESCR(F0H_80H, 0xF0, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1651 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1653 IAPDESCR(F1H_01H, 0xF1, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1654 IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1655 IAPDESCR(F1H_02H, 0xF1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1656 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1657 IAPDESCR(F1H_04H, 0xF1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1658 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1659 IAPDESCR(F1H_07H, 0xF1, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1660 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW),
1662 IAPDESCR(F2H_01H, 0xF2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1663 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1664 IAPDESCR(F2H_02H, 0xF2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1665 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1666 IAPDESCR(F2H_04H, 0xF2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1667 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1668 IAPDESCR(F2H_05H, 0xF2, 0x05, IAP_F_FM | IAP_F_HW),
1669 IAPDESCR(F2H_06H, 0xF2, 0x06, IAP_F_FM | IAP_F_HW),
1670 IAPDESCR(F2H_08H, 0xF2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1671 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1672 IAPDESCR(F2H_0AH, 0xF2, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX |
1674 IAPDESCR(F2H_0FH, 0xF2, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1676 IAPDESCR(F3H_01H, 0xF3, 0x01, IAP_F_FM | IAP_F_I7O),
1677 IAPDESCR(F3H_02H, 0xF3, 0x02, IAP_F_FM | IAP_F_I7O),
1678 IAPDESCR(F3H_04H, 0xF3, 0x04, IAP_F_FM | IAP_F_I7O),
1679 IAPDESCR(F3H_08H, 0xF3, 0x08, IAP_F_FM | IAP_F_I7O),
1680 IAPDESCR(F3H_10H, 0xF3, 0x10, IAP_F_FM | IAP_F_I7O),
1681 IAPDESCR(F3H_20H, 0xF3, 0x20, IAP_F_FM | IAP_F_I7O),
1683 IAPDESCR(F4H_01H, 0xF4, 0x01, IAP_F_FM | IAP_F_I7O),
1684 IAPDESCR(F4H_02H, 0xF4, 0x02, IAP_F_FM | IAP_F_I7O),
1685 IAPDESCR(F4H_04H, 0xF4, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
1686 IAPDESCR(F4H_08H, 0xF4, 0x08, IAP_F_FM | IAP_F_I7O),
1687 IAPDESCR(F4H_10H, 0xF4, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1688 IAP_F_SB | IAP_F_SBX),
1690 IAPDESCR(F6H_01H, 0xF6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1692 IAPDESCR(F7H_01H, 0xF7, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1693 IAPDESCR(F7H_02H, 0xF7, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1694 IAPDESCR(F7H_04H, 0xF7, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1696 IAPDESCR(F8H_00H, 0xF8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1697 IAPDESCR(F8H_01H, 0xF8, 0x01, IAP_F_FM | IAP_F_I7O),
1699 IAPDESCR(FDH_01H, 0xFD, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1700 IAPDESCR(FDH_02H, 0xFD, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1701 IAPDESCR(FDH_04H, 0xFD, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1702 IAPDESCR(FDH_08H, 0xFD, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1703 IAPDESCR(FDH_10H, 0xFD, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1704 IAPDESCR(FDH_20H, 0xFD, 0x20, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1705 IAPDESCR(FDH_40H, 0xFD, 0x40, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1708 static const int niap_events = sizeof(iap_events) / sizeof(iap_events[0]);
1711 iap_perfctr_value_to_reload_count(pmc_value_t v)
1713 v &= (1ULL << core_iap_width) - 1;
1714 return (1ULL << core_iap_width) - v;
1718 iap_reload_count_to_perfctr_value(pmc_value_t rlc)
1720 return (1ULL << core_iap_width) - rlc;
1724 iap_pmc_has_overflowed(int ri)
1729 * We treat a Core (i.e., Intel architecture v1) PMC as has
1730 * having overflowed if its MSB is zero.
1733 return ((v & (1ULL << (core_iap_width - 1))) == 0);
1737 * Check an event against the set of supported architectural events.
1739 * If the event is not architectural EV_IS_NOTARCH is returned.
1740 * If the event is architectural and supported on this CPU, the correct
1741 * event+umask mapping is returned in map, and EV_IS_ARCH_SUPP is returned.
1742 * Otherwise, the function returns EV_IS_ARCH_NOTSUPP.
1746 iap_is_event_architectural(enum pmc_event pe, enum pmc_event *map)
1748 enum core_arch_events ae;
1751 case PMC_EV_IAP_ARCH_UNH_COR_CYC:
1752 ae = CORE_AE_UNHALTED_CORE_CYCLES;
1753 *map = PMC_EV_IAP_EVENT_C4H_00H;
1755 case PMC_EV_IAP_ARCH_INS_RET:
1756 ae = CORE_AE_INSTRUCTION_RETIRED;
1757 *map = PMC_EV_IAP_EVENT_C0H_00H;
1759 case PMC_EV_IAP_ARCH_UNH_REF_CYC:
1760 ae = CORE_AE_UNHALTED_REFERENCE_CYCLES;
1761 *map = PMC_EV_IAP_EVENT_3CH_01H;
1763 case PMC_EV_IAP_ARCH_LLC_REF:
1764 ae = CORE_AE_LLC_REFERENCE;
1765 *map = PMC_EV_IAP_EVENT_2EH_4FH;
1767 case PMC_EV_IAP_ARCH_LLC_MIS:
1768 ae = CORE_AE_LLC_MISSES;
1769 *map = PMC_EV_IAP_EVENT_2EH_41H;
1771 case PMC_EV_IAP_ARCH_BR_INS_RET:
1772 ae = CORE_AE_BRANCH_INSTRUCTION_RETIRED;
1773 *map = PMC_EV_IAP_EVENT_C4H_00H;
1775 case PMC_EV_IAP_ARCH_BR_MIS_RET:
1776 ae = CORE_AE_BRANCH_MISSES_RETIRED;
1777 *map = PMC_EV_IAP_EVENT_C5H_00H;
1780 default: /* Non architectural event. */
1781 return (EV_IS_NOTARCH);
1784 return (((core_architectural_events & (1 << ae)) == 0) ?
1785 EV_IS_ARCH_NOTSUPP : EV_IS_ARCH_SUPP);
1789 iap_event_corei7_ok_on_counter(enum pmc_event pe, int ri)
1795 * Events valid only on counter 0, 1.
1797 case PMC_EV_IAP_EVENT_40H_01H:
1798 case PMC_EV_IAP_EVENT_40H_02H:
1799 case PMC_EV_IAP_EVENT_40H_04H:
1800 case PMC_EV_IAP_EVENT_40H_08H:
1801 case PMC_EV_IAP_EVENT_40H_0FH:
1802 case PMC_EV_IAP_EVENT_41H_02H:
1803 case PMC_EV_IAP_EVENT_41H_04H:
1804 case PMC_EV_IAP_EVENT_41H_08H:
1805 case PMC_EV_IAP_EVENT_42H_01H:
1806 case PMC_EV_IAP_EVENT_42H_02H:
1807 case PMC_EV_IAP_EVENT_42H_04H:
1808 case PMC_EV_IAP_EVENT_42H_08H:
1809 case PMC_EV_IAP_EVENT_43H_01H:
1810 case PMC_EV_IAP_EVENT_43H_02H:
1811 case PMC_EV_IAP_EVENT_51H_01H:
1812 case PMC_EV_IAP_EVENT_51H_02H:
1813 case PMC_EV_IAP_EVENT_51H_04H:
1814 case PMC_EV_IAP_EVENT_51H_08H:
1815 case PMC_EV_IAP_EVENT_63H_01H:
1816 case PMC_EV_IAP_EVENT_63H_02H:
1821 mask = ~0; /* Any row index is ok. */
1824 return (mask & (1 << ri));
1828 iap_event_westmere_ok_on_counter(enum pmc_event pe, int ri)
1834 * Events valid only on counter 0.
1836 case PMC_EV_IAP_EVENT_60H_01H:
1837 case PMC_EV_IAP_EVENT_60H_02H:
1838 case PMC_EV_IAP_EVENT_60H_04H:
1839 case PMC_EV_IAP_EVENT_60H_08H:
1840 case PMC_EV_IAP_EVENT_B3H_01H:
1841 case PMC_EV_IAP_EVENT_B3H_02H:
1842 case PMC_EV_IAP_EVENT_B3H_04H:
1847 * Events valid only on counter 0, 1.
1849 case PMC_EV_IAP_EVENT_4CH_01H:
1850 case PMC_EV_IAP_EVENT_4EH_01H:
1851 case PMC_EV_IAP_EVENT_4EH_02H:
1852 case PMC_EV_IAP_EVENT_4EH_04H:
1853 case PMC_EV_IAP_EVENT_51H_01H:
1854 case PMC_EV_IAP_EVENT_51H_02H:
1855 case PMC_EV_IAP_EVENT_51H_04H:
1856 case PMC_EV_IAP_EVENT_51H_08H:
1857 case PMC_EV_IAP_EVENT_63H_01H:
1858 case PMC_EV_IAP_EVENT_63H_02H:
1863 mask = ~0; /* Any row index is ok. */
1866 return (mask & (1 << ri));
1870 iap_event_sb_sbx_ib_ibx_ok_on_counter(enum pmc_event pe, int ri)
1875 /* Events valid only on counter 0. */
1876 case PMC_EV_IAP_EVENT_B7H_01H:
1879 /* Events valid only on counter 1. */
1880 case PMC_EV_IAP_EVENT_C0H_01H:
1883 /* Events valid only on counter 2. */
1884 case PMC_EV_IAP_EVENT_48H_01H:
1885 case PMC_EV_IAP_EVENT_A2H_02H:
1888 /* Events valid only on counter 3. */
1889 case PMC_EV_IAP_EVENT_A3H_08H:
1890 case PMC_EV_IAP_EVENT_BBH_01H:
1891 case PMC_EV_IAP_EVENT_CDH_01H:
1892 case PMC_EV_IAP_EVENT_CDH_02H:
1896 mask = ~0; /* Any row index is ok. */
1899 return (mask & (1 << ri));
1903 iap_event_ok_on_counter(enum pmc_event pe, int ri)
1909 * Events valid only on counter 0.
1911 case PMC_EV_IAP_EVENT_10H_00H:
1912 case PMC_EV_IAP_EVENT_14H_00H:
1913 case PMC_EV_IAP_EVENT_18H_00H:
1914 case PMC_EV_IAP_EVENT_B3H_01H:
1915 case PMC_EV_IAP_EVENT_B3H_02H:
1916 case PMC_EV_IAP_EVENT_B3H_04H:
1917 case PMC_EV_IAP_EVENT_C1H_00H:
1918 case PMC_EV_IAP_EVENT_CBH_01H:
1919 case PMC_EV_IAP_EVENT_CBH_02H:
1924 * Events valid only on counter 1.
1926 case PMC_EV_IAP_EVENT_11H_00H:
1927 case PMC_EV_IAP_EVENT_12H_00H:
1928 case PMC_EV_IAP_EVENT_13H_00H:
1933 mask = ~0; /* Any row index is ok. */
1936 return (mask & (1 << ri));
1940 iap_allocate_pmc(int cpu, int ri, struct pmc *pm,
1941 const struct pmc_op_pmcallocate *a)
1944 enum pmc_event ev, map;
1945 struct iap_event_descr *ie;
1946 uint32_t c, caps, config, cpuflag, evsel, mask;
1948 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
1949 ("[core,%d] illegal CPU %d", __LINE__, cpu));
1950 KASSERT(ri >= 0 && ri < core_iap_npmc,
1951 ("[core,%d] illegal row-index value %d", __LINE__, ri));
1953 /* check requested capabilities */
1955 if ((IAP_PMC_CAPS & caps) != caps)
1957 map = 0; /* XXX: silent GCC warning */
1958 arch = iap_is_event_architectural(pm->pm_event, &map);
1959 if (arch == EV_IS_ARCH_NOTSUPP)
1960 return (EOPNOTSUPP);
1961 else if (arch == EV_IS_ARCH_SUPP)
1967 * A small number of events are not supported in all the
1968 * processors based on a given microarchitecture.
1970 if (ev == PMC_EV_IAP_EVENT_0FH_01H || ev == PMC_EV_IAP_EVENT_0FH_80H) {
1971 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4);
1972 if (core_cputype == PMC_CPU_INTEL_COREI7 && model != 0x2E)
1976 switch (core_cputype) {
1977 case PMC_CPU_INTEL_COREI7:
1978 if (iap_event_corei7_ok_on_counter(ev, ri) == 0)
1981 case PMC_CPU_INTEL_SANDYBRIDGE:
1982 case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
1983 case PMC_CPU_INTEL_IVYBRIDGE:
1984 case PMC_CPU_INTEL_IVYBRIDGE_XEON:
1985 case PMC_CPU_INTEL_HASWELL:
1986 if (iap_event_sb_sbx_ib_ibx_ok_on_counter(ev, ri) == 0)
1989 case PMC_CPU_INTEL_WESTMERE:
1990 if (iap_event_westmere_ok_on_counter(ev, ri) == 0)
1994 if (iap_event_ok_on_counter(ev, ri) == 0)
1999 * Look for an event descriptor with matching CPU and event id
2003 switch (core_cputype) {
2005 case PMC_CPU_INTEL_ATOM:
2008 case PMC_CPU_INTEL_CORE:
2011 case PMC_CPU_INTEL_CORE2:
2012 cpuflag = IAP_F_CC2;
2014 case PMC_CPU_INTEL_CORE2EXTREME:
2015 cpuflag = IAP_F_CC2 | IAP_F_CC2E;
2017 case PMC_CPU_INTEL_COREI7:
2020 case PMC_CPU_INTEL_HASWELL:
2023 case PMC_CPU_INTEL_IVYBRIDGE:
2026 case PMC_CPU_INTEL_IVYBRIDGE_XEON:
2027 cpuflag = IAP_F_IBX;
2029 case PMC_CPU_INTEL_SANDYBRIDGE:
2032 case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
2033 cpuflag = IAP_F_SBX;
2035 case PMC_CPU_INTEL_WESTMERE:
2040 for (n = 0, ie = iap_events; n < niap_events; n++, ie++)
2041 if (ie->iap_ev == ev && ie->iap_flags & cpuflag)
2044 if (n == niap_events)
2048 * A matching event descriptor has been found, so start
2049 * assembling the contents of the event select register.
2051 evsel = ie->iap_evcode;
2053 config = a->pm_md.pm_iap.pm_iap_config & ~IAP_F_CMASK;
2056 * If the event uses a fixed umask value, reject any umask
2057 * bits set by the user.
2059 if (ie->iap_flags & IAP_F_FM) {
2061 if (IAP_UMASK(config) != 0)
2064 evsel |= (ie->iap_umask << 8);
2069 * Otherwise, the UMASK value needs to be taken from
2070 * the MD fields of the allocation request. Reject
2071 * requests that specify reserved bits.
2076 if (ie->iap_umask & IAP_M_CORE) {
2077 if ((c = (config & IAP_F_CORE)) != IAP_CORE_ALL &&
2083 if (ie->iap_umask & IAP_M_AGENT)
2084 mask |= IAP_F_AGENT;
2086 if (ie->iap_umask & IAP_M_PREFETCH) {
2088 if ((c = (config & IAP_F_PREFETCH)) ==
2089 IAP_PREFETCH_RESERVED)
2092 mask |= IAP_F_PREFETCH;
2095 if (ie->iap_umask & IAP_M_MESI)
2098 if (ie->iap_umask & IAP_M_SNOOPRESPONSE)
2099 mask |= IAP_F_SNOOPRESPONSE;
2101 if (ie->iap_umask & IAP_M_SNOOPTYPE)
2102 mask |= IAP_F_SNOOPTYPE;
2104 if (ie->iap_umask & IAP_M_TRANSITION)
2105 mask |= IAP_F_TRANSITION;
2108 * If bits outside of the allowed set of umask bits
2109 * are set, reject the request.
2114 evsel |= (config & mask);
2119 * Only Atom and SandyBridge CPUs support the 'ANY' qualifier.
2121 if (core_cputype == PMC_CPU_INTEL_ATOM ||
2122 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE ||
2123 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON)
2124 evsel |= (config & IAP_ANY);
2125 else if (config & IAP_ANY)
2129 * Check offcore response configuration.
2131 if (a->pm_md.pm_iap.pm_iap_rsp != 0) {
2132 if (ev != PMC_EV_IAP_EVENT_B7H_01H &&
2133 ev != PMC_EV_IAP_EVENT_BBH_01H)
2135 if (core_cputype == PMC_CPU_INTEL_COREI7 &&
2136 ev == PMC_EV_IAP_EVENT_BBH_01H)
2138 if ((core_cputype == PMC_CPU_INTEL_COREI7 ||
2139 core_cputype == PMC_CPU_INTEL_WESTMERE) &&
2140 a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_I7WM)
2142 else if ((core_cputype == PMC_CPU_INTEL_SANDYBRIDGE ||
2143 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON ||
2144 core_cputype == PMC_CPU_INTEL_IVYBRIDGE ||
2145 core_cputype == PMC_CPU_INTEL_IVYBRIDGE_XEON) &&
2146 a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_SBIB)
2148 pm->pm_md.pm_iap.pm_iap_rsp = a->pm_md.pm_iap.pm_iap_rsp;
2151 if (caps & PMC_CAP_THRESHOLD)
2152 evsel |= (a->pm_md.pm_iap.pm_iap_config & IAP_F_CMASK);
2153 if (caps & PMC_CAP_USER)
2155 if (caps & PMC_CAP_SYSTEM)
2157 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0)
2158 evsel |= (IAP_OS | IAP_USR);
2159 if (caps & PMC_CAP_EDGE)
2161 if (caps & PMC_CAP_INVERT)
2163 if (caps & PMC_CAP_INTERRUPT)
2166 pm->pm_md.pm_iap.pm_iap_evsel = evsel;
2172 iap_config_pmc(int cpu, int ri, struct pmc *pm)
2174 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
2175 ("[core,%d] illegal CPU %d", __LINE__, cpu));
2177 KASSERT(ri >= 0 && ri < core_iap_npmc,
2178 ("[core,%d] illegal row-index %d", __LINE__, ri));
2180 PMCDBG(MDP,CFG,1, "iap-config cpu=%d ri=%d pm=%p", cpu, ri, pm);
2182 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__,
2185 core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc = pm;
2191 iap_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
2195 char iap_name[PMC_NAME_MAX];
2197 phw = &core_pcpu[cpu]->pc_corepmcs[ri];
2199 (void) snprintf(iap_name, sizeof(iap_name), "IAP-%d", ri);
2200 if ((error = copystr(iap_name, pi->pm_name, PMC_NAME_MAX,
2204 pi->pm_class = PMC_CLASS_IAP;
2206 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
2207 pi->pm_enabled = TRUE;
2208 *ppmc = phw->phw_pmc;
2210 pi->pm_enabled = FALSE;
2218 iap_get_config(int cpu, int ri, struct pmc **ppm)
2220 *ppm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc;
2226 iap_get_msr(int ri, uint32_t *msr)
2228 KASSERT(ri >= 0 && ri < core_iap_npmc,
2229 ("[iap,%d] ri %d out of range", __LINE__, ri));
2237 iap_read_pmc(int cpu, int ri, pmc_value_t *v)
2242 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
2243 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
2244 KASSERT(ri >= 0 && ri < core_iap_npmc,
2245 ("[core,%d] illegal row-index %d", __LINE__, ri));
2247 pm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc;
2250 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu,
2254 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
2255 *v = iap_perfctr_value_to_reload_count(tmp);
2257 *v = tmp & ((1ULL << core_iap_width) - 1);
2259 PMCDBG(MDP,REA,1, "iap-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri,
2266 iap_release_pmc(int cpu, int ri, struct pmc *pm)
2270 PMCDBG(MDP,REL,1, "iap-release cpu=%d ri=%d pm=%p", cpu, ri,
2273 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
2274 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
2275 KASSERT(ri >= 0 && ri < core_iap_npmc,
2276 ("[core,%d] illegal row-index %d", __LINE__, ri));
2278 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc
2279 == NULL, ("[core,%d] PHW pmc non-NULL", __LINE__));
2285 iap_start_pmc(int cpu, int ri)
2289 struct core_cpu *cc;
2291 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
2292 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
2293 KASSERT(ri >= 0 && ri < core_iap_npmc,
2294 ("[core,%d] illegal row-index %d", __LINE__, ri));
2296 cc = core_pcpu[cpu];
2297 pm = cc->pc_corepmcs[ri].phw_pmc;
2300 ("[core,%d] starting cpu%d,ri%d with no pmc configured",
2301 __LINE__, cpu, ri));
2303 PMCDBG(MDP,STA,1, "iap-start cpu=%d ri=%d", cpu, ri);
2305 evsel = pm->pm_md.pm_iap.pm_iap_evsel;
2307 PMCDBG(MDP,STA,2, "iap-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x",
2308 cpu, ri, IAP_EVSEL0 + ri, evsel);
2310 /* Event specific configuration. */
2311 switch (pm->pm_event) {
2312 case PMC_EV_IAP_EVENT_B7H_01H:
2313 wrmsr(IA_OFFCORE_RSP0, pm->pm_md.pm_iap.pm_iap_rsp);
2315 case PMC_EV_IAP_EVENT_BBH_01H:
2316 wrmsr(IA_OFFCORE_RSP1, pm->pm_md.pm_iap.pm_iap_rsp);
2322 wrmsr(IAP_EVSEL0 + ri, evsel | IAP_EN);
2324 if (core_cputype == PMC_CPU_INTEL_CORE)
2329 cc->pc_globalctrl |= (1ULL << ri);
2330 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl);
2331 } while (cc->pc_resync != 0);
2337 iap_stop_pmc(int cpu, int ri)
2340 struct core_cpu *cc;
2343 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
2344 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
2345 KASSERT(ri >= 0 && ri < core_iap_npmc,
2346 ("[core,%d] illegal row index %d", __LINE__, ri));
2348 cc = core_pcpu[cpu];
2349 pm = cc->pc_corepmcs[ri].phw_pmc;
2352 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__,
2355 PMCDBG(MDP,STO,1, "iap-stop cpu=%d ri=%d", cpu, ri);
2357 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK;
2358 wrmsr(IAP_EVSEL0 + ri, msr); /* stop hw */
2360 if (core_cputype == PMC_CPU_INTEL_CORE)
2366 cc->pc_globalctrl &= ~(1ULL << ri);
2367 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK;
2368 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl);
2369 } while (cc->pc_resync != 0);
2375 iap_write_pmc(int cpu, int ri, pmc_value_t v)
2378 struct core_cpu *cc;
2380 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
2381 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
2382 KASSERT(ri >= 0 && ri < core_iap_npmc,
2383 ("[core,%d] illegal row index %d", __LINE__, ri));
2385 cc = core_pcpu[cpu];
2386 pm = cc->pc_corepmcs[ri].phw_pmc;
2389 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__,
2392 PMCDBG(MDP,WRI,1, "iap-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri,
2395 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
2396 v = iap_reload_count_to_perfctr_value(v);
2399 * Write the new value to the counter. The counter will be in
2400 * a stopped state when the pcd_write() entry point is called.
2403 wrmsr(IAP_PMC0 + ri, v & ((1ULL << core_iap_width) - 1));
2410 iap_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth,
2413 struct pmc_classdep *pcd;
2415 KASSERT(md != NULL, ("[iap,%d] md is NULL", __LINE__));
2417 PMCDBG(MDP,INI,1, "%s", "iap-initialize");
2419 /* Remember the set of architectural events supported. */
2420 core_architectural_events = ~flags;
2422 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP];
2424 pcd->pcd_caps = IAP_PMC_CAPS;
2425 pcd->pcd_class = PMC_CLASS_IAP;
2426 pcd->pcd_num = npmc;
2427 pcd->pcd_ri = md->pmd_npmc;
2428 pcd->pcd_width = pmcwidth;
2430 pcd->pcd_allocate_pmc = iap_allocate_pmc;
2431 pcd->pcd_config_pmc = iap_config_pmc;
2432 pcd->pcd_describe = iap_describe;
2433 pcd->pcd_get_config = iap_get_config;
2434 pcd->pcd_get_msr = iap_get_msr;
2435 pcd->pcd_pcpu_fini = core_pcpu_fini;
2436 pcd->pcd_pcpu_init = core_pcpu_init;
2437 pcd->pcd_read_pmc = iap_read_pmc;
2438 pcd->pcd_release_pmc = iap_release_pmc;
2439 pcd->pcd_start_pmc = iap_start_pmc;
2440 pcd->pcd_stop_pmc = iap_stop_pmc;
2441 pcd->pcd_write_pmc = iap_write_pmc;
2443 md->pmd_npmc += npmc;
2447 core_intr(int cpu, struct trapframe *tf)
2451 struct core_cpu *cc;
2452 int error, found_interrupt, ri;
2455 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf,
2456 TRAPF_USERMODE(tf));
2458 found_interrupt = 0;
2459 cc = core_pcpu[cpu];
2461 for (ri = 0; ri < core_iap_npmc; ri++) {
2463 if ((pm = cc->pc_corepmcs[ri].phw_pmc) == NULL ||
2464 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
2467 if (!iap_pmc_has_overflowed(ri))
2470 found_interrupt = 1;
2472 if (pm->pm_state != PMC_STATE_RUNNING)
2475 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf,
2476 TRAPF_USERMODE(tf));
2478 v = pm->pm_sc.pm_reloadcount;
2479 v = iaf_reload_count_to_perfctr_value(v);
2482 * Stop the counter, reload it but only restart it if
2483 * the PMC is not stalled.
2485 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK;
2486 wrmsr(IAP_EVSEL0 + ri, msr);
2487 wrmsr(IAP_PMC0 + ri, v);
2492 wrmsr(IAP_EVSEL0 + ri, msr | (pm->pm_md.pm_iap.pm_iap_evsel |
2496 if (found_interrupt)
2497 lapic_reenable_pmc();
2499 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed :
2500 &pmc_stats.pm_intr_ignored, 1);
2502 return (found_interrupt);
2506 core2_intr(int cpu, struct trapframe *tf)
2508 int error, found_interrupt, n;
2509 uint64_t flag, intrstatus, intrenable, msr;
2511 struct core_cpu *cc;
2514 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf,
2515 TRAPF_USERMODE(tf));
2518 * The IA_GLOBAL_STATUS (MSR 0x38E) register indicates which
2519 * PMCs have a pending PMI interrupt. We take a 'snapshot' of
2520 * the current set of interrupting PMCs and process these
2521 * after stopping them.
2523 intrstatus = rdmsr(IA_GLOBAL_STATUS);
2524 intrenable = intrstatus & core_pmcmask;
2526 PMCDBG(MDP,INT, 1, "cpu=%d intrstatus=%jx", cpu,
2527 (uintmax_t) intrstatus);
2529 found_interrupt = 0;
2530 cc = core_pcpu[cpu];
2532 KASSERT(cc != NULL, ("[core,%d] null pcpu", __LINE__));
2534 cc->pc_globalctrl &= ~intrenable;
2535 cc->pc_resync = 1; /* MSRs now potentially out of sync. */
2538 * Stop PMCs and clear overflow status bits.
2540 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK;
2541 wrmsr(IA_GLOBAL_CTRL, msr);
2542 wrmsr(IA_GLOBAL_OVF_CTRL, intrenable |
2543 IA_GLOBAL_STATUS_FLAG_OVFBUF |
2544 IA_GLOBAL_STATUS_FLAG_CONDCHG);
2547 * Look for interrupts from fixed function PMCs.
2549 for (n = 0, flag = (1ULL << IAF_OFFSET); n < core_iaf_npmc;
2552 if ((intrstatus & flag) == 0)
2555 found_interrupt = 1;
2557 pm = cc->pc_corepmcs[n + core_iaf_ri].phw_pmc;
2558 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING ||
2559 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
2562 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf,
2563 TRAPF_USERMODE(tf));
2565 intrenable &= ~flag;
2567 v = iaf_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount);
2569 /* Reload sampling count. */
2570 wrmsr(IAF_CTR0 + n, v);
2572 PMCDBG(MDP,INT, 1, "iaf-intr cpu=%d error=%d v=%jx(%jx)", cpu,
2573 error, (uintmax_t) v, (uintmax_t) rdpmc(IAF_RI_TO_MSR(n)));
2577 * Process interrupts from the programmable counters.
2579 for (n = 0, flag = 1; n < core_iap_npmc; n++, flag <<= 1) {
2580 if ((intrstatus & flag) == 0)
2583 found_interrupt = 1;
2585 pm = cc->pc_corepmcs[n].phw_pmc;
2586 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING ||
2587 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
2590 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf,
2591 TRAPF_USERMODE(tf));
2593 intrenable &= ~flag;
2595 v = iap_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount);
2597 PMCDBG(MDP,INT, 1, "iap-intr cpu=%d error=%d v=%jx", cpu, error,
2600 /* Reload sampling count. */
2601 wrmsr(IAP_PMC0 + n, v);
2605 * Reenable all non-stalled PMCs.
2607 PMCDBG(MDP,INT, 1, "cpu=%d intrenable=%jx", cpu,
2608 (uintmax_t) intrenable);
2610 cc->pc_globalctrl |= intrenable;
2612 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl & IA_GLOBAL_CTRL_MASK);
2614 PMCDBG(MDP,INT, 1, "cpu=%d fixedctrl=%jx globalctrl=%jx status=%jx "
2615 "ovf=%jx", cpu, (uintmax_t) rdmsr(IAF_CTRL),
2616 (uintmax_t) rdmsr(IA_GLOBAL_CTRL),
2617 (uintmax_t) rdmsr(IA_GLOBAL_STATUS),
2618 (uintmax_t) rdmsr(IA_GLOBAL_OVF_CTRL));
2620 if (found_interrupt)
2621 lapic_reenable_pmc();
2623 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed :
2624 &pmc_stats.pm_intr_ignored, 1);
2626 return (found_interrupt);
2630 pmc_core_initialize(struct pmc_mdep *md, int maxcpu)
2632 int cpuid[CORE_CPUID_REQUEST_SIZE];
2633 int ipa_version, flags, nflags;
2635 do_cpuid(CORE_CPUID_REQUEST, cpuid);
2637 ipa_version = cpuid[CORE_CPUID_EAX] & 0xFF;
2639 PMCDBG(MDP,INI,1,"core-init cputype=%d ncpu=%d ipa-version=%d",
2640 md->pmd_cputype, maxcpu, ipa_version);
2642 if (ipa_version < 1 || ipa_version > 3) {
2643 /* Unknown PMC architecture. */
2644 printf("hwpc_core: unknown PMC architecture: %d\n",
2646 return (EPROGMISMATCH);
2649 core_cputype = md->pmd_cputype;
2654 * Initialize programmable counters.
2656 KASSERT(ipa_version >= 1,
2657 ("[core,%d] ipa_version %d too small", __LINE__, ipa_version));
2659 core_iap_npmc = (cpuid[CORE_CPUID_EAX] >> 8) & 0xFF;
2660 core_iap_width = (cpuid[CORE_CPUID_EAX] >> 16) & 0xFF;
2662 core_pmcmask |= ((1ULL << core_iap_npmc) - 1);
2664 nflags = (cpuid[CORE_CPUID_EAX] >> 24) & 0xFF;
2665 flags = cpuid[CORE_CPUID_EBX] & ((1 << nflags) - 1);
2667 iap_initialize(md, maxcpu, core_iap_npmc, core_iap_width, flags);
2670 * Initialize fixed function counters, if present.
2672 if (core_cputype != PMC_CPU_INTEL_CORE) {
2673 KASSERT(ipa_version >= 2,
2674 ("[core,%d] ipa_version %d too small", __LINE__,
2677 core_iaf_ri = core_iap_npmc;
2678 core_iaf_npmc = cpuid[CORE_CPUID_EDX] & 0x1F;
2679 core_iaf_width = (cpuid[CORE_CPUID_EDX] >> 5) & 0xFF;
2681 iaf_initialize(md, maxcpu, core_iaf_npmc, core_iaf_width);
2682 core_pmcmask |= ((1ULL << core_iaf_npmc) - 1) << IAF_OFFSET;
2685 PMCDBG(MDP,INI,1,"core-init pmcmask=0x%jx iafri=%d", core_pmcmask,
2688 core_pcpu = malloc(sizeof(struct core_cpu **) * maxcpu, M_PMC,
2692 * Choose the appropriate interrupt handler.
2694 if (ipa_version == 1)
2695 md->pmd_intr = core_intr;
2697 md->pmd_intr = core2_intr;
2699 md->pmd_pcpu_fini = NULL;
2700 md->pmd_pcpu_init = NULL;
2706 pmc_core_finalize(struct pmc_mdep *md)
2708 PMCDBG(MDP,INI,1, "%s", "core-finalize");
2710 free(core_pcpu, M_PMC);