sys/dev/hwpmc/hwpmc_intel.c

   1 /*-
   2  * Copyright (c) 2008 Joseph Koshy
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 /*
  28  * Common code for handling Intel CPUs.
  29  */
  30
  31 #include <sys/cdefs.h>
  32 __FBSDID("$FreeBSD$");
  33
  34 #include <sys/param.h>
  35 #include <sys/pmc.h>
  36 #include <sys/pmckern.h>
  37 #include <sys/systm.h>
  38
  39 #include <machine/cpu.h>
  40 #include <machine/cputypes.h>
  41 #include <machine/md_var.h>
  42 #include <machine/specialreg.h>
  43
  44 static int
  45 intel_switch_in(struct pmc_cpu *pc, struct pmc_process *pp)
  46 {
  47         (void) pc;
  48
  49         PMCDBG(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp,
  50             pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS);
  51
  52         /* allow the RDPMC instruction if needed */
  53         if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS)
  54                 load_cr4(rcr4() | CR4_PCE);
  55
  56         PMCDBG(MDP,SWI,1, "cr4=0x%jx", (uintmax_t) rcr4());
  57
  58         return 0;
  59 }
  60
  61 static int
  62 intel_switch_out(struct pmc_cpu *pc, struct pmc_process *pp)
  63 {
  64         (void) pc;
  65         (void) pp;              /* can be NULL */
  66
  67         PMCDBG(MDP,SWO,1, "pc=%p pp=%p cr4=0x%jx", pc, pp,
  68             (uintmax_t) rcr4());
  69
  70         /* always turn off the RDPMC instruction */
  71         load_cr4(rcr4() & ~CR4_PCE);
  72
  73         return 0;
  74 }
  75
  76 struct pmc_mdep *
  77 pmc_intel_initialize(void)
  78 {
  79         struct pmc_mdep *pmc_mdep;
  80         enum pmc_cputype cputype;
  81         int error, model, nclasses, ncpus;
  82
  83         KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL,
  84             ("[intel,%d] Initializing non-intel processor", __LINE__));
  85
  86         PMCDBG(MDP,INI,0, "intel-initialize cpuid=0x%x", cpu_id);
  87
  88         cputype = -1;
  89         nclasses = 2;
  90         error = 0;
  91         model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4);
  92
  93         switch (cpu_id & 0xF00) {
  94 #if     defined(__i386__)
  95         case 0x500:             /* Pentium family processors */
  96                 cputype = PMC_CPU_INTEL_P5;
  97                 break;
  98 #endif
  99         case 0x600:             /* Pentium Pro, Celeron, Pentium II & III */
 100                 switch (model) {
 101 #if     defined(__i386__)
 102                 case 0x1:
 103                         cputype = PMC_CPU_INTEL_P6;
 104                         break;
 105                 case 0x3: case 0x5:
 106                         cputype = PMC_CPU_INTEL_PII;
 107                         break;
 108                 case 0x6: case 0x16:
 109                         cputype = PMC_CPU_INTEL_CL;
 110                         break;
 111                 case 0x7: case 0x8: case 0xA: case 0xB:
 112                         cputype = PMC_CPU_INTEL_PIII;
 113                         break;
 114                 case 0x9: case 0xD:
 115                         cputype = PMC_CPU_INTEL_PM;
 116                         break;
 117 #endif
 118                 case 0xE:
 119                         cputype = PMC_CPU_INTEL_CORE;
 120                         break;
 121                 case 0xF:
 122                         cputype = PMC_CPU_INTEL_CORE2;
 123                         nclasses = 3;
 124                         break;
 125                 case 0x17:
 126                         cputype = PMC_CPU_INTEL_CORE2EXTREME;
 127                         nclasses = 3;
 128                         break;
 129                 case 0x1C:      /* Per Intel document 320047-002. */
 130                         cputype = PMC_CPU_INTEL_ATOM;
 131                         nclasses = 3;
 132                         break;
 133                 case 0x1A:
 134                 case 0x1E:      /*
 135                                  * Per Intel document 253669-032 9/2009,
 136                                  * pages A-2 and A-57
 137                                  */
 138                 case 0x1F:      /*
 139                                  * Per Intel document 253669-032 9/2009,
 140                                  * pages A-2 and A-57
 141                                  */
 142                 case 0x2E:
 143                         cputype = PMC_CPU_INTEL_COREI7;
 144                         nclasses = 5;
 145                         break;
 146                 case 0x25:      /* Per Intel document 253669-033US 12/2009. */
 147                 case 0x2C:      /* Per Intel document 253669-033US 12/2009. */
 148                         cputype = PMC_CPU_INTEL_WESTMERE;
 149                         nclasses = 5;
 150                         break;
 151                 case 0x2A:      /* Per Intel document 253669-039US 05/2011. */
 152                         cputype = PMC_CPU_INTEL_SANDYBRIDGE;
 153                         nclasses = 5;
 154                         break;
 155                 case 0x2D:      /* Per Intel document 253669-044US 08/2012. */
 156                         cputype = PMC_CPU_INTEL_SANDYBRIDGE_XEON;
 157                         nclasses = 3;
 158                         break;
 159                 case 0x3A:      /* Per Intel document 253669-043US 05/2012. */
 160                         cputype = PMC_CPU_INTEL_IVYBRIDGE;
 161                         nclasses = 3;
 162                         break;
 163                 case 0x3E:      /* Per Intel document 325462-045US 01/2013. */
 164                         cputype = PMC_CPU_INTEL_IVYBRIDGE_XEON;
 165                         nclasses = 3;
 166                         break;
 167                 case 0x3C:      /* Per Intel document 325462-045US 01/2013. */
 168                         cputype = PMC_CPU_INTEL_HASWELL;
 169                         nclasses = 5;
 170                         break;
 171                 }
 172                 break;
 173 #if     defined(__i386__) || defined(__amd64__)
 174         case 0xF00:             /* P4 */
 175                 if (model >= 0 && model <= 6) /* known models */
 176                         cputype = PMC_CPU_INTEL_PIV;
 177                 break;
 178         }
 179 #endif
 180
 181         if ((int) cputype == -1) {
 182                 printf("pmc: Unknown Intel CPU.\n");
 183                 return (NULL);
 184         }
 185
 186         /* Allocate base class and initialize machine dependent struct */
 187         pmc_mdep = pmc_mdep_alloc(nclasses);
 188
 189         pmc_mdep->pmd_cputype    = cputype;
 190         pmc_mdep->pmd_switch_in  = intel_switch_in;
 191         pmc_mdep->pmd_switch_out = intel_switch_out;
 192
 193         ncpus = pmc_cpu_max();
 194         error = pmc_tsc_initialize(pmc_mdep, ncpus);
 195         if (error)
 196                 goto error;
 197         switch (cputype) {
 198 #if     defined(__i386__) || defined(__amd64__)
 199                 /*
 200                  * Intel Core, Core 2 and Atom processors.
 201                  */
 202         case PMC_CPU_INTEL_ATOM:
 203         case PMC_CPU_INTEL_CORE:
 204         case PMC_CPU_INTEL_CORE2:
 205         case PMC_CPU_INTEL_CORE2EXTREME:
 206         case PMC_CPU_INTEL_COREI7:
 207         case PMC_CPU_INTEL_IVYBRIDGE:
 208         case PMC_CPU_INTEL_SANDYBRIDGE:
 209         case PMC_CPU_INTEL_WESTMERE:
 210         case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
 211         case PMC_CPU_INTEL_IVYBRIDGE_XEON:
 212         case PMC_CPU_INTEL_HASWELL:
 213                 error = pmc_core_initialize(pmc_mdep, ncpus);
 214                 break;
 215
 216                 /*
 217                  * Intel Pentium 4 Processors, and P4/EMT64 processors.
 218                  */
 219
 220         case PMC_CPU_INTEL_PIV:
 221                 error = pmc_p4_initialize(pmc_mdep, ncpus);
 222                 break;
 223 #endif
 224
 225 #if     defined(__i386__)
 226                 /*
 227                  * P6 Family Processors
 228                  */
 229
 230         case PMC_CPU_INTEL_P6:
 231         case PMC_CPU_INTEL_CL:
 232         case PMC_CPU_INTEL_PII:
 233         case PMC_CPU_INTEL_PIII:
 234         case PMC_CPU_INTEL_PM:
 235                 error = pmc_p6_initialize(pmc_mdep, ncpus);
 236                 break;
 237
 238                 /*
 239                  * Intel Pentium PMCs.
 240                  */
 241
 242         case PMC_CPU_INTEL_P5:
 243                 error = pmc_p5_initialize(pmc_mdep, ncpus);
 244                 break;
 245 #endif
 246
 247         default:
 248                 KASSERT(0, ("[intel,%d] Unknown CPU type", __LINE__));
 249         }
 250
 251         if (error) {
 252                 pmc_tsc_finalize(pmc_mdep);
 253                 goto error;
 254         }
 255
 256         /*
 257          * Init the uncore class.
 258          */
 259 #if     defined(__i386__) || defined(__amd64__)
 260         switch (cputype) {
 261                 /*
 262                  * Intel Corei7 and Westmere processors.
 263                  */
 264         case PMC_CPU_INTEL_COREI7:
 265         case PMC_CPU_INTEL_HASWELL:
 266         case PMC_CPU_INTEL_SANDYBRIDGE:
 267         case PMC_CPU_INTEL_WESTMERE:
 268                 error = pmc_uncore_initialize(pmc_mdep, ncpus);
 269                 break;
 270         default:
 271                 break;
 272         }
 273 #endif
 274   error:
 275         if (error) {
 276                 pmc_mdep_free(pmc_mdep);
 277                 pmc_mdep = NULL;
 278         }
 279
 280         return (pmc_mdep);
 281 }
 282
 283 void
 284 pmc_intel_finalize(struct pmc_mdep *md)
 285 {
 286         pmc_tsc_finalize(md);
 287
 288         switch (md->pmd_cputype) {
 289 #if     defined(__i386__) || defined(__amd64__)
 290         case PMC_CPU_INTEL_ATOM:
 291         case PMC_CPU_INTEL_CORE:
 292         case PMC_CPU_INTEL_CORE2:
 293         case PMC_CPU_INTEL_CORE2EXTREME:
 294         case PMC_CPU_INTEL_COREI7:
 295         case PMC_CPU_INTEL_HASWELL:
 296         case PMC_CPU_INTEL_IVYBRIDGE:
 297         case PMC_CPU_INTEL_SANDYBRIDGE:
 298         case PMC_CPU_INTEL_WESTMERE:
 299         case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
 300         case PMC_CPU_INTEL_IVYBRIDGE_XEON:
 301                 pmc_core_finalize(md);
 302                 break;
 303
 304         case PMC_CPU_INTEL_PIV:
 305                 pmc_p4_finalize(md);
 306                 break;
 307 #endif
 308 #if     defined(__i386__)
 309         case PMC_CPU_INTEL_P6:
 310         case PMC_CPU_INTEL_CL:
 311         case PMC_CPU_INTEL_PII:
 312         case PMC_CPU_INTEL_PIII:
 313         case PMC_CPU_INTEL_PM:
 314                 pmc_p6_finalize(md);
 315                 break;
 316         case PMC_CPU_INTEL_P5:
 317                 pmc_p5_finalize(md);
 318                 break;
 319 #endif
 320         default:
 321                 KASSERT(0, ("[intel,%d] unknown CPU type", __LINE__));
 322         }
 323
 324         /*
 325          * Uncore.
 326          */
 327 #if     defined(__i386__) || defined(__amd64__)
 328         switch (md->pmd_cputype) {
 329         case PMC_CPU_INTEL_COREI7:
 330         case PMC_CPU_INTEL_HASWELL:
 331         case PMC_CPU_INTEL_SANDYBRIDGE:
 332         case PMC_CPU_INTEL_WESTMERE:
 333                 pmc_uncore_finalize(md);
 334                 break;
 335         default:
 336                 break;
 337         }
 338 #endif
 339 }