2 * Copyright (c) 2009 Rui Paulo <rpaulo@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/systm.h>
34 #include <sys/pmckern.h>
36 #include <machine/pmc_mdep.h>
38 * Support for the Intel XScale network processors
40 * XScale processors have up to now three generations.
42 * The first generation has two PMC; the event selection, interrupt config
43 * and overflow flag setup are done by writing to the PMNC register.
44 * It also has less monitoring events than the latter generations.
46 * The second and third generatiosn have four PMCs, one register for the event
47 * selection, one register for the interrupt config and one register for
50 static int xscale_npmcs;
51 static int xscale_gen; /* XScale Core generation */
53 struct xscale_event_code_map {
58 const struct xscale_event_code_map xscale_event_codes[] = {
59 /* 1st and 2nd Generation XScale cores */
60 { PMC_EV_XSCALE_IC_FETCH, 0x00 },
61 { PMC_EV_XSCALE_IC_MISS, 0x01 },
62 { PMC_EV_XSCALE_DATA_DEPENDENCY_STALLED,0x02 },
63 { PMC_EV_XSCALE_ITLB_MISS, 0x03 },
64 { PMC_EV_XSCALE_DTLB_MISS, 0x04 },
65 { PMC_EV_XSCALE_BRANCH_RETIRED, 0x05 },
66 { PMC_EV_XSCALE_BRANCH_MISPRED, 0x06 },
67 { PMC_EV_XSCALE_INSTR_RETIRED, 0x07 },
68 { PMC_EV_XSCALE_DC_FULL_CYCLE, 0x08 },
69 { PMC_EV_XSCALE_DC_FULL_CONTIG, 0x09 },
70 { PMC_EV_XSCALE_DC_ACCESS, 0x0a },
71 { PMC_EV_XSCALE_DC_MISS, 0x0b },
72 { PMC_EV_XSCALE_DC_WRITEBACK, 0x0c },
73 { PMC_EV_XSCALE_PC_CHANGE, 0x0d },
74 /* 3rd Generation XScale cores */
75 { PMC_EV_XSCALE_BRANCH_RETIRED_ALL, 0x0e },
76 { PMC_EV_XSCALE_INSTR_CYCLE, 0x0f },
77 { PMC_EV_XSCALE_CP_STALL, 0x17 },
78 { PMC_EV_XSCALE_PC_CHANGE_ALL, 0x18 },
79 { PMC_EV_XSCALE_PIPELINE_FLUSH, 0x19 },
80 { PMC_EV_XSCALE_BACKEND_STALL, 0x1a },
81 { PMC_EV_XSCALE_MULTIPLIER_USE, 0x1b },
82 { PMC_EV_XSCALE_MULTIPLIER_STALLED, 0x1c },
83 { PMC_EV_XSCALE_DATA_CACHE_STALLED, 0x1e },
84 { PMC_EV_XSCALE_L2_CACHE_REQ, 0x20 },
85 { PMC_EV_XSCALE_L2_CACHE_MISS, 0x23 },
86 { PMC_EV_XSCALE_ADDRESS_BUS_TRANS, 0x40 },
87 { PMC_EV_XSCALE_SELF_ADDRESS_BUS_TRANS, 0x41 },
88 { PMC_EV_XSCALE_DATA_BUS_TRANS, 0x48 },
91 const int xscale_event_codes_size =
92 sizeof(xscale_event_codes) / sizeof(xscale_event_codes[0]);
95 * Per-processor information.
98 struct pmc_hw *pc_xscalepmcs;
101 static struct xscale_cpu **xscale_pcpu;
104 * Performance Monitor Control Register
106 static __inline uint32_t
107 xscale_pmnc_read(void)
111 __asm __volatile("mrc p14, 0, %0, c0, c1, 0" : "=r" (reg));
117 xscale_pmnc_write(uint32_t reg)
119 __asm __volatile("mcr p14, 0, %0, c0, c1, 0" : : "r" (reg));
123 * Clock Counter Register
125 static __inline uint32_t
126 xscale_ccnt_read(void)
130 __asm __volatile("mrc p14, 0, %0, c1, c1, 0" : "=r" (reg));
136 xscale_ccnt_write(uint32_t reg)
138 __asm __volatile("mcr p14, 0, %0, c1, c1, 0" : : "r" (reg));
142 * Interrupt Enable Register
144 static __inline uint32_t
145 xscale_inten_read(void)
149 __asm __volatile("mrc p14, 0, %0, c4, c1, 0" : "=r" (reg));
155 xscale_inten_write(uint32_t reg)
157 __asm __volatile("mcr p14, 0, %0, c4, c1, 0" : : "r" (reg));
161 * Overflow Flag Register
163 static __inline uint32_t
164 xscale_flag_read(void)
168 __asm __volatile("mrc p14, 0, %0, c5, c1, 0" : "=r" (reg));
174 xscale_flag_write(uint32_t reg)
176 __asm __volatile("mcr p14, 0, %0, c5, c1, 0" : : "r" (reg));
180 * Event Selection Register
182 static __inline uint32_t
183 xscale_evtsel_read(void)
187 __asm __volatile("mrc p14, 0, %0, c8, c1, 0" : "=r" (reg));
193 xscale_evtsel_write(uint32_t reg)
195 __asm __volatile("mcr p14, 0, %0, c8, c1, 0" : : "r" (reg));
199 * Performance Count Register N
202 xscale_pmcn_read(unsigned int pmc)
206 KASSERT(pmc < 4, ("[xscale,%d] illegal PMC number %d", __LINE__, pmc));
210 __asm __volatile("mrc p14, 0, %0, c0, c2, 0" : "=r" (reg));
213 __asm __volatile("mrc p14, 0, %0, c1, c2, 0" : "=r" (reg));
216 __asm __volatile("mrc p14, 0, %0, c2, c2, 0" : "=r" (reg));
219 __asm __volatile("mrc p14, 0, %0, c3, c2, 0" : "=r" (reg));
227 xscale_pmcn_write(unsigned int pmc, uint32_t reg)
230 KASSERT(pmc < 4, ("[xscale,%d] illegal PMC number %d", __LINE__, pmc));
234 __asm __volatile("mcr p14, 0, %0, c0, c2, 0" : : "r" (reg));
237 __asm __volatile("mcr p14, 0, %0, c1, c2, 0" : : "r" (reg));
240 __asm __volatile("mcr p14, 0, %0, c2, c2, 0" : : "r" (reg));
243 __asm __volatile("mcr p14, 0, %0, c3, c2, 0" : : "r" (reg));
251 xscale_allocate_pmc(int cpu, int ri, struct pmc *pm,
252 const struct pmc_op_pmcallocate *a)
255 uint32_t caps, config;
258 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
259 ("[xscale,%d] illegal CPU value %d", __LINE__, cpu));
260 KASSERT(ri >= 0 && ri < xscale_npmcs,
261 ("[xscale,%d] illegal row index %d", __LINE__, ri));
264 if (a->pm_class != PMC_CLASS_XSCALE)
267 for (i = 0; i < xscale_event_codes_size; i++) {
268 if (xscale_event_codes[i].pe_ev == pe) {
269 config = xscale_event_codes[i].pe_code;
273 if (i == xscale_event_codes_size)
275 /* Generation 1 has fewer events */
276 if (xscale_gen == 1 && i > PMC_EV_XSCALE_PC_CHANGE)
278 pm->pm_md.pm_xscale.pm_xscale_evsel = config;
280 PMCDBG(MDP,ALL,2,"xscale-allocate ri=%d -> config=0x%x", ri, config);
287 xscale_read_pmc(int cpu, int ri, pmc_value_t *v)
292 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
293 ("[xscale,%d] illegal CPU value %d", __LINE__, cpu));
294 KASSERT(ri >= 0 && ri < xscale_npmcs,
295 ("[xscale,%d] illegal row index %d", __LINE__, ri));
297 pm = xscale_pcpu[cpu]->pc_xscalepmcs[ri].phw_pmc;
298 tmp = xscale_pmcn_read(ri);
299 PMCDBG(MDP,REA,2,"xscale-read id=%d -> %jd", ri, tmp);
300 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
301 *v = XSCALE_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp);
309 xscale_write_pmc(int cpu, int ri, pmc_value_t v)
313 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
314 ("[xscale,%d] illegal CPU value %d", __LINE__, cpu));
315 KASSERT(ri >= 0 && ri < xscale_npmcs,
316 ("[xscale,%d] illegal row-index %d", __LINE__, ri));
318 pm = xscale_pcpu[cpu]->pc_xscalepmcs[ri].phw_pmc;
320 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
321 v = XSCALE_RELOAD_COUNT_TO_PERFCTR_VALUE(v);
323 PMCDBG(MDP,WRI,1,"xscale-write cpu=%d ri=%d v=%jx", cpu, ri, v);
325 xscale_pmcn_write(ri, v);
331 xscale_config_pmc(int cpu, int ri, struct pmc *pm)
335 PMCDBG(MDP,CFG,1, "cpu=%d ri=%d pm=%p", cpu, ri, pm);
337 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
338 ("[xscale,%d] illegal CPU value %d", __LINE__, cpu));
339 KASSERT(ri >= 0 && ri < xscale_npmcs,
340 ("[xscale,%d] illegal row-index %d", __LINE__, ri));
342 phw = &xscale_pcpu[cpu]->pc_xscalepmcs[ri];
344 KASSERT(pm == NULL || phw->phw_pmc == NULL,
345 ("[xscale,%d] pm=%p phw->pm=%p hwpmc not unconfigured",
346 __LINE__, pm, phw->phw_pmc));
354 xscale_start_pmc(int cpu, int ri)
356 uint32_t pmnc, config, evtsel;
360 phw = &xscale_pcpu[cpu]->pc_xscalepmcs[ri];
362 config = pm->pm_md.pm_xscale.pm_xscale_evsel;
365 * Configure the event selection.
367 * On the XScale 2nd Generation there's no EVTSEL register.
369 if (xscale_npmcs == 2) {
370 pmnc = xscale_pmnc_read();
373 pmnc &= ~XSCALE_PMNC_EVT0_MASK;
374 pmnc |= (config << 12) & XSCALE_PMNC_EVT0_MASK;
377 pmnc &= ~XSCALE_PMNC_EVT1_MASK;
378 pmnc |= (config << 20) & XSCALE_PMNC_EVT1_MASK;
384 xscale_pmnc_write(pmnc);
386 evtsel = xscale_evtsel_read();
389 evtsel &= ~XSCALE_EVTSEL_EVT0_MASK;
390 evtsel |= config & XSCALE_EVTSEL_EVT0_MASK;
393 evtsel &= ~XSCALE_EVTSEL_EVT1_MASK;
394 evtsel |= (config << 8) & XSCALE_EVTSEL_EVT1_MASK;
397 evtsel &= ~XSCALE_EVTSEL_EVT2_MASK;
398 evtsel |= (config << 16) & XSCALE_EVTSEL_EVT2_MASK;
401 evtsel &= ~XSCALE_EVTSEL_EVT3_MASK;
402 evtsel |= (config << 24) & XSCALE_EVTSEL_EVT3_MASK;
408 xscale_evtsel_write(evtsel);
413 * Note that XScale provides only one bit to enable/disable _all_
414 * performance monitoring units.
416 pmnc = xscale_pmnc_read();
417 pmnc |= XSCALE_PMNC_ENABLE;
418 xscale_pmnc_write(pmnc);
424 xscale_stop_pmc(int cpu, int ri)
426 uint32_t pmnc, evtsel;
430 phw = &xscale_pcpu[cpu]->pc_xscalepmcs[ri];
436 * Note that XScale provides only one bit to enable/disable _all_
437 * performance monitoring units.
439 pmnc = xscale_pmnc_read();
440 pmnc &= ~XSCALE_PMNC_ENABLE;
441 xscale_pmnc_write(pmnc);
443 * A value of 0xff makes the corresponding PMU go into
446 if (xscale_npmcs == 2) {
447 pmnc = xscale_pmnc_read();
450 pmnc |= XSCALE_PMNC_EVT0_MASK;
453 pmnc |= XSCALE_PMNC_EVT1_MASK;
459 xscale_pmnc_write(pmnc);
461 evtsel = xscale_evtsel_read();
464 evtsel |= XSCALE_EVTSEL_EVT0_MASK;
467 evtsel |= XSCALE_EVTSEL_EVT1_MASK;
470 evtsel |= XSCALE_EVTSEL_EVT2_MASK;
473 evtsel |= XSCALE_EVTSEL_EVT3_MASK;
479 xscale_evtsel_write(evtsel);
486 xscale_release_pmc(int cpu, int ri, struct pmc *pmc)
490 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
491 ("[xscale,%d] illegal CPU value %d", __LINE__, cpu));
492 KASSERT(ri >= 0 && ri < xscale_npmcs,
493 ("[xscale,%d] illegal row-index %d", __LINE__, ri));
495 phw = &xscale_pcpu[cpu]->pc_xscalepmcs[ri];
496 KASSERT(phw->phw_pmc == NULL,
497 ("[xscale,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc));
503 xscale_intr(int cpu, struct trapframe *tf)
510 xscale_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
514 char xscale_name[PMC_NAME_MAX];
516 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
517 ("[xscale,%d], illegal CPU %d", __LINE__, cpu));
518 KASSERT(ri >= 0 && ri < xscale_npmcs,
519 ("[xscale,%d] row-index %d out of range", __LINE__, ri));
521 phw = &xscale_pcpu[cpu]->pc_xscalepmcs[ri];
522 snprintf(xscale_name, sizeof(xscale_name), "XSCALE-%d", ri);
523 if ((error = copystr(xscale_name, pi->pm_name, PMC_NAME_MAX,
526 pi->pm_class = PMC_CLASS_XSCALE;
527 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
528 pi->pm_enabled = TRUE;
529 *ppmc = phw->phw_pmc;
531 pi->pm_enabled = FALSE;
539 xscale_get_config(int cpu, int ri, struct pmc **ppm)
541 *ppm = xscale_pcpu[cpu]->pc_xscalepmcs[ri].phw_pmc;
547 * XXX don't know what we should do here.
550 xscale_switch_in(struct pmc_cpu *pc, struct pmc_process *pp)
556 xscale_switch_out(struct pmc_cpu *pc, struct pmc_process *pp)
562 xscale_pcpu_init(struct pmc_mdep *md, int cpu)
566 struct xscale_cpu *pac;
569 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
570 ("[xscale,%d] wrong cpu number %d", __LINE__, cpu));
571 PMCDBG(MDP,INI,1,"xscale-init cpu=%d", cpu);
573 xscale_pcpu[cpu] = pac = malloc(sizeof(struct xscale_cpu), M_PMC,
575 pac->pc_xscalepmcs = malloc(sizeof(struct pmc_hw) * xscale_npmcs,
576 M_PMC, M_WAITOK|M_ZERO);
578 first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_XSCALE].pcd_ri;
579 KASSERT(pc != NULL, ("[xscale,%d] NULL per-cpu pointer", __LINE__));
581 for (i = 0, phw = pac->pc_xscalepmcs; i < xscale_npmcs; i++, phw++) {
582 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED |
583 PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(i);
585 pc->pc_hwpmcs[i + first_ri] = phw;
589 * Disable and put the PMUs into power save mode.
591 if (xscale_npmcs == 2) {
592 xscale_pmnc_write(XSCALE_PMNC_EVT1_MASK |
593 XSCALE_PMNC_EVT0_MASK);
595 xscale_evtsel_write(XSCALE_EVTSEL_EVT3_MASK |
596 XSCALE_EVTSEL_EVT2_MASK | XSCALE_EVTSEL_EVT1_MASK |
597 XSCALE_EVTSEL_EVT0_MASK);
604 xscale_pcpu_fini(struct pmc_mdep *md, int cpu)
610 pmc_xscale_initialize()
612 struct pmc_mdep *pmc_mdep;
613 struct pmc_classdep *pcd;
616 /* Get the Core Generation from CP15 */
617 __asm __volatile("mrc p15, 0, %0, c0, c0, 0" : "=r" (idreg));
618 xscale_gen = (idreg >> 13) & 0x3;
619 switch (xscale_gen) {
628 printf("%s: unknown XScale core generation\n", __func__);
631 PMCDBG(MDP,INI,1,"xscale-init npmcs=%d", xscale_npmcs);
634 * Allocate space for pointers to PMC HW descriptors and for
635 * the MDEP structure used by MI code.
637 xscale_pcpu = malloc(sizeof(struct xscale_cpu *) * pmc_cpu_max(), M_PMC,
641 pmc_mdep = pmc_mdep_alloc(1);
643 pmc_mdep->pmd_cputype = PMC_CPU_INTEL_XSCALE;
645 pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_XSCALE];
646 pcd->pcd_caps = XSCALE_PMC_CAPS;
647 pcd->pcd_class = PMC_CLASS_XSCALE;
648 pcd->pcd_num = xscale_npmcs;
649 pcd->pcd_ri = pmc_mdep->pmd_npmc;
652 pcd->pcd_allocate_pmc = xscale_allocate_pmc;
653 pcd->pcd_config_pmc = xscale_config_pmc;
654 pcd->pcd_pcpu_fini = xscale_pcpu_fini;
655 pcd->pcd_pcpu_init = xscale_pcpu_init;
656 pcd->pcd_describe = xscale_describe;
657 pcd->pcd_get_config = xscale_get_config;
658 pcd->pcd_read_pmc = xscale_read_pmc;
659 pcd->pcd_release_pmc = xscale_release_pmc;
660 pcd->pcd_start_pmc = xscale_start_pmc;
661 pcd->pcd_stop_pmc = xscale_stop_pmc;
662 pcd->pcd_write_pmc = xscale_write_pmc;
664 pmc_mdep->pmd_intr = xscale_intr;
665 pmc_mdep->pmd_switch_in = xscale_switch_in;
666 pmc_mdep->pmd_switch_out = xscale_switch_out;
668 pmc_mdep->pmd_npmc += xscale_npmcs;
674 pmc_xscale_finalize(struct pmc_mdep *md)