2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2000, 2001
4 * Bill Paul <william.paul@windriver.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
38 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public
39 * documentation not available, but ask me nicely.
41 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs.
42 * It's a 64-bit PCI part that supports TCP/IP checksum offload,
43 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There
44 * are three supported methods for data transfer between host and
45 * NIC: programmed I/O, traditional scatter/gather DMA and Packet
46 * Propulsion Technology (tm) DMA. The latter mechanism is a form
47 * of double buffer DMA where the packet data is copied to a
48 * pre-allocated DMA buffer who's physical address has been loaded
49 * into a table at device initialization time. The rationale is that
50 * the virtual to physical address translation needed for normal
51 * scatter/gather DMA is more expensive than the data copy needed
52 * for double buffering. This may be true in Windows NT and the like,
53 * but it isn't true for us, at least on the x86 arch. This driver
54 * uses the scatter/gather I/O method for both TX and RX.
56 * The LXT1001 only supports TCP/IP checksum offload on receive.
57 * Also, the VLAN tagging is done using a 16-entry table which allows
58 * the chip to perform hardware filtering based on VLAN tags. Sadly,
59 * our vlan support doesn't currently play well with this kind of
63 * - Jeff James at Intel, for arranging to have the LXT1001 manual
64 * released (at long last)
65 * - Beny Chen at D-Link, for actually sending it to me
66 * - Brad Short and Keith Alexis at SMC, for sending me sample
67 * SMC9462SX and SMC9462TX adapters for testing
68 * - Paul Saab at Y!, for not killing me (though it remains to be seen
69 * if in fact he did me much of a favor)
72 #include <sys/param.h>
73 #include <sys/systm.h>
74 #include <sys/sockio.h>
76 #include <sys/malloc.h>
77 #include <sys/kernel.h>
78 #include <sys/module.h>
79 #include <sys/socket.h>
82 #include <net/if_arp.h>
83 #include <net/ethernet.h>
84 #include <net/if_dl.h>
85 #include <net/if_media.h>
86 #include <net/if_types.h>
90 #include <vm/vm.h> /* for vtophys */
91 #include <vm/pmap.h> /* for vtophys */
92 #include <machine/bus.h>
93 #include <machine/resource.h>
97 #include <dev/mii/mii.h>
98 #include <dev/mii/miivar.h>
100 #include <dev/pci/pcireg.h>
101 #include <dev/pci/pcivar.h>
103 #define LGE_USEIOSPACE
105 #include <dev/lge/if_lgereg.h>
107 /* "device miibus" required. See GENERIC if you get errors here. */
108 #include "miibus_if.h"
111 * Various supported device vendors/types and their names.
113 static const struct lge_type lge_devs[] = {
114 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" },
118 static int lge_probe(device_t);
119 static int lge_attach(device_t);
120 static int lge_detach(device_t);
122 static int lge_alloc_jumbo_mem(struct lge_softc *);
123 static void lge_free_jumbo_mem(struct lge_softc *);
124 static void *lge_jalloc(struct lge_softc *);
125 static int lge_jfree(struct mbuf *, void *, void *);
127 static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, struct mbuf *);
128 static int lge_encap(struct lge_softc *, struct mbuf *, u_int32_t *);
129 static void lge_rxeof(struct lge_softc *, int);
130 static void lge_rxeoc(struct lge_softc *);
131 static void lge_txeof(struct lge_softc *);
132 static void lge_intr(void *);
133 static void lge_tick(void *);
134 static void lge_start(struct ifnet *);
135 static void lge_start_locked(struct ifnet *);
136 static int lge_ioctl(struct ifnet *, u_long, caddr_t);
137 static void lge_init(void *);
138 static void lge_init_locked(struct lge_softc *);
139 static void lge_stop(struct lge_softc *);
140 static void lge_watchdog(struct lge_softc *);
141 static int lge_shutdown(device_t);
142 static int lge_ifmedia_upd(struct ifnet *);
143 static void lge_ifmedia_upd_locked(struct ifnet *);
144 static void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
146 static void lge_eeprom_getword(struct lge_softc *, int, u_int16_t *);
147 static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int, int);
149 static int lge_miibus_readreg(device_t, int, int);
150 static int lge_miibus_writereg(device_t, int, int, int);
151 static void lge_miibus_statchg(device_t);
153 static void lge_setmulti(struct lge_softc *);
154 static void lge_reset(struct lge_softc *);
155 static int lge_list_rx_init(struct lge_softc *);
156 static int lge_list_tx_init(struct lge_softc *);
158 #ifdef LGE_USEIOSPACE
159 #define LGE_RES SYS_RES_IOPORT
160 #define LGE_RID LGE_PCI_LOIO
162 #define LGE_RES SYS_RES_MEMORY
163 #define LGE_RID LGE_PCI_LOMEM
166 static device_method_t lge_methods[] = {
167 /* Device interface */
168 DEVMETHOD(device_probe, lge_probe),
169 DEVMETHOD(device_attach, lge_attach),
170 DEVMETHOD(device_detach, lge_detach),
171 DEVMETHOD(device_shutdown, lge_shutdown),
174 DEVMETHOD(miibus_readreg, lge_miibus_readreg),
175 DEVMETHOD(miibus_writereg, lge_miibus_writereg),
176 DEVMETHOD(miibus_statchg, lge_miibus_statchg),
181 static driver_t lge_driver = {
184 sizeof(struct lge_softc)
187 static devclass_t lge_devclass;
189 DRIVER_MODULE(lge, pci, lge_driver, lge_devclass, 0, 0);
190 DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0);
191 MODULE_DEPEND(lge, pci, 1, 1, 1);
192 MODULE_DEPEND(lge, ether, 1, 1, 1);
193 MODULE_DEPEND(lge, miibus, 1, 1, 1);
195 #define LGE_SETBIT(sc, reg, x) \
196 CSR_WRITE_4(sc, reg, \
197 CSR_READ_4(sc, reg) | (x))
199 #define LGE_CLRBIT(sc, reg, x) \
200 CSR_WRITE_4(sc, reg, \
201 CSR_READ_4(sc, reg) & ~(x))
204 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x)
207 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x)
210 * Read a word of data stored in the EEPROM at address 'addr.'
213 lge_eeprom_getword(sc, addr, dest)
214 struct lge_softc *sc;
221 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ|
222 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8));
224 for (i = 0; i < LGE_TIMEOUT; i++)
225 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ))
228 if (i == LGE_TIMEOUT) {
229 device_printf(sc->lge_dev, "EEPROM read timed out\n");
233 val = CSR_READ_4(sc, LGE_EEDATA);
236 *dest = (val >> 16) & 0xFFFF;
238 *dest = val & 0xFFFF;
244 * Read a sequence of words from the EEPROM.
247 lge_read_eeprom(sc, dest, off, cnt, swap)
248 struct lge_softc *sc;
255 u_int16_t word = 0, *ptr;
257 for (i = 0; i < cnt; i++) {
258 lge_eeprom_getword(sc, off + i, &word);
259 ptr = (u_int16_t *)(dest + (i * 2));
270 lge_miibus_readreg(dev, phy, reg)
274 struct lge_softc *sc;
277 sc = device_get_softc(dev);
280 * If we have a non-PCS PHY, pretend that the internal
281 * autoneg stuff at PHY address 0 isn't there so that
282 * the miibus code will find only the GMII PHY.
284 if (sc->lge_pcs == 0 && phy == 0)
287 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ);
289 for (i = 0; i < LGE_TIMEOUT; i++)
290 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
293 if (i == LGE_TIMEOUT) {
294 device_printf(sc->lge_dev, "PHY read timed out\n");
298 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16);
302 lge_miibus_writereg(dev, phy, reg, data)
306 struct lge_softc *sc;
309 sc = device_get_softc(dev);
311 CSR_WRITE_4(sc, LGE_GMIICTL,
312 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE);
314 for (i = 0; i < LGE_TIMEOUT; i++)
315 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
318 if (i == LGE_TIMEOUT) {
319 device_printf(sc->lge_dev, "PHY write timed out\n");
327 lge_miibus_statchg(dev)
330 struct lge_softc *sc;
331 struct mii_data *mii;
333 sc = device_get_softc(dev);
334 mii = device_get_softc(sc->lge_miibus);
336 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED);
337 switch (IFM_SUBTYPE(mii->mii_media_active)) {
340 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
343 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100);
346 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10);
350 * Choose something, even if it's wrong. Clearing
351 * all the bits will hose autoneg on the internal
354 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
358 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
359 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
361 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
369 struct lge_softc *sc;
372 struct ifmultiaddr *ifma;
373 u_int32_t h = 0, hashes[2] = { 0, 0 };
378 /* Make sure multicast hash table is enabled. */
379 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST);
381 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
382 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF);
383 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF);
387 /* first, zot all the existing hash bits */
388 CSR_WRITE_4(sc, LGE_MAR0, 0);
389 CSR_WRITE_4(sc, LGE_MAR1, 0);
391 /* now program new ones */
393 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
394 if (ifma->ifma_addr->sa_family != AF_LINK)
396 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
397 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
399 hashes[0] |= (1 << h);
401 hashes[1] |= (1 << (h - 32));
403 if_maddr_runlock(ifp);
405 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]);
406 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]);
413 struct lge_softc *sc;
417 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST);
419 for (i = 0; i < LGE_TIMEOUT; i++) {
420 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST))
424 if (i == LGE_TIMEOUT)
425 device_printf(sc->lge_dev, "reset never completed\n");
427 /* Wait a little while for the chip to get its brains in order. */
434 * Probe for a Level 1 chip. Check the PCI vendor and device
435 * IDs against our list and return a device name if we find a match.
441 const struct lge_type *t;
445 while(t->lge_name != NULL) {
446 if ((pci_get_vendor(dev) == t->lge_vid) &&
447 (pci_get_device(dev) == t->lge_did)) {
448 device_set_desc(dev, t->lge_name);
449 return(BUS_PROBE_DEFAULT);
458 * Attach the interface. Allocate softc structures, do ifmedia
459 * setup and ethernet/BPF attach.
465 u_char eaddr[ETHER_ADDR_LEN];
466 struct lge_softc *sc;
467 struct ifnet *ifp = NULL;
470 sc = device_get_softc(dev);
473 mtx_init(&sc->lge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
475 callout_init_mtx(&sc->lge_stat_callout, &sc->lge_mtx, 0);
478 * Map control/status registers.
480 pci_enable_busmaster(dev);
483 sc->lge_res = bus_alloc_resource_any(dev, LGE_RES, &rid, RF_ACTIVE);
485 if (sc->lge_res == NULL) {
486 device_printf(dev, "couldn't map ports/memory\n");
491 sc->lge_btag = rman_get_bustag(sc->lge_res);
492 sc->lge_bhandle = rman_get_bushandle(sc->lge_res);
494 /* Allocate interrupt */
496 sc->lge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
497 RF_SHAREABLE | RF_ACTIVE);
499 if (sc->lge_irq == NULL) {
500 device_printf(dev, "couldn't map interrupt\n");
505 /* Reset the adapter. */
509 * Get station address from the EEPROM.
511 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0);
512 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0);
513 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0);
515 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF,
516 M_NOWAIT | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0);
518 if (sc->lge_ldata == NULL) {
519 device_printf(dev, "no memory for list buffers!\n");
524 /* Try to allocate memory for jumbo buffers. */
525 if (lge_alloc_jumbo_mem(sc)) {
526 device_printf(dev, "jumbo buffer allocation failed\n");
531 ifp = sc->lge_ifp = if_alloc(IFT_ETHER);
533 device_printf(dev, "can not if_alloc()\n");
538 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
539 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
540 ifp->if_ioctl = lge_ioctl;
541 ifp->if_start = lge_start;
542 ifp->if_init = lge_init;
543 ifp->if_snd.ifq_maxlen = LGE_TX_LIST_CNT - 1;
544 ifp->if_capabilities = IFCAP_RXCSUM;
545 ifp->if_capenable = ifp->if_capabilities;
547 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH)
555 error = mii_attach(dev, &sc->lge_miibus, ifp, lge_ifmedia_upd,
556 lge_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
558 device_printf(dev, "attaching PHYs failed\n");
563 * Call MI attach routine.
565 ether_ifattach(ifp, eaddr);
567 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET | INTR_MPSAFE,
568 NULL, lge_intr, sc, &sc->lge_intrhand);
572 device_printf(dev, "couldn't set up irq\n");
578 lge_free_jumbo_mem(sc);
580 contigfree(sc->lge_ldata,
581 sizeof(struct lge_list_data), M_DEVBUF);
585 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
587 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
588 mtx_destroy(&sc->lge_mtx);
596 struct lge_softc *sc;
599 sc = device_get_softc(dev);
606 callout_drain(&sc->lge_stat_callout);
609 bus_generic_detach(dev);
610 device_delete_child(dev, sc->lge_miibus);
612 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
613 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
614 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
616 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF);
618 lge_free_jumbo_mem(sc);
619 mtx_destroy(&sc->lge_mtx);
625 * Initialize the transmit descriptors.
629 struct lge_softc *sc;
631 struct lge_list_data *ld;
632 struct lge_ring_data *cd;
637 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
638 ld->lge_tx_list[i].lge_mbuf = NULL;
639 ld->lge_tx_list[i].lge_ctl = 0;
642 cd->lge_tx_prod = cd->lge_tx_cons = 0;
649 * Initialize the RX descriptors and allocate mbufs for them. Note that
650 * we arralge the descriptors in a closed ring, so that the last descriptor
651 * points back to the first.
655 struct lge_softc *sc;
657 struct lge_list_data *ld;
658 struct lge_ring_data *cd;
664 cd->lge_rx_prod = cd->lge_rx_cons = 0;
666 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
668 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
669 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0)
671 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS)
675 /* Clear possible 'rx command queue empty' interrupt. */
676 CSR_READ_4(sc, LGE_ISR);
682 * Initialize an RX descriptor and attach an MBUF cluster.
686 struct lge_softc *sc;
687 struct lge_rx_desc *c;
690 struct mbuf *m_new = NULL;
694 MGETHDR(m_new, M_NOWAIT, MT_DATA);
696 device_printf(sc->lge_dev, "no memory for rx list "
697 "-- packet dropped!\n");
701 /* Allocate the jumbo buffer */
702 buf = lge_jalloc(sc);
705 device_printf(sc->lge_dev, "jumbo allocation failed "
706 "-- packet dropped!\n");
711 /* Attach the buffer to the mbuf */
712 m_new->m_data = (void *)buf;
713 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN;
714 MEXTADD(m_new, buf, LGE_JUMBO_FRAMELEN, lge_jfree,
715 buf, (struct lge_softc *)sc, 0, EXT_NET_DRV);
718 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN;
719 m_new->m_data = m_new->m_ext.ext_buf;
723 * Adjust alignment so packet payload begins on a
724 * longword boundary. Mandatory for Alpha, useful on
727 m_adj(m_new, ETHER_ALIGN);
730 c->lge_fragptr_hi = 0;
731 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t));
732 c->lge_fraglen = m_new->m_len;
733 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1);
737 * Put this buffer in the RX command FIFO. To do this,
738 * we just write the physical address of the descriptor
739 * into the RX descriptor address registers. Note that
740 * there are two registers, one high DWORD and one low
741 * DWORD, which lets us specify a 64-bit address if
742 * desired. We only use a 32-bit address for now.
743 * Writing to the low DWORD register is what actually
744 * causes the command to be issued, so we do that
747 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c));
748 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT);
754 lge_alloc_jumbo_mem(sc)
755 struct lge_softc *sc;
759 struct lge_jpool_entry *entry;
761 /* Grab a big chunk o' storage. */
762 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF,
763 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
765 if (sc->lge_cdata.lge_jumbo_buf == NULL) {
766 device_printf(sc->lge_dev, "no memory for jumbo buffers!\n");
770 SLIST_INIT(&sc->lge_jfree_listhead);
771 SLIST_INIT(&sc->lge_jinuse_listhead);
774 * Now divide it up into 9K pieces and save the addresses
777 ptr = sc->lge_cdata.lge_jumbo_buf;
778 for (i = 0; i < LGE_JSLOTS; i++) {
779 sc->lge_cdata.lge_jslots[i] = ptr;
781 entry = malloc(sizeof(struct lge_jpool_entry),
784 device_printf(sc->lge_dev, "no memory for jumbo "
789 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead,
790 entry, jpool_entries);
797 lge_free_jumbo_mem(sc)
798 struct lge_softc *sc;
800 struct lge_jpool_entry *entry;
802 if (sc->lge_cdata.lge_jumbo_buf == NULL)
805 while ((entry = SLIST_FIRST(&sc->lge_jinuse_listhead))) {
806 device_printf(sc->lge_dev,
807 "asked to free buffer that is in use!\n");
808 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries);
809 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry,
812 while (!SLIST_EMPTY(&sc->lge_jfree_listhead)) {
813 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
814 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
815 free(entry, M_DEVBUF);
818 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF);
824 * Allocate a jumbo buffer.
828 struct lge_softc *sc;
830 struct lge_jpool_entry *entry;
832 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
836 device_printf(sc->lge_dev, "no free jumbo buffers\n");
841 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
842 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries);
843 return(sc->lge_cdata.lge_jslots[entry->slot]);
847 * Release a jumbo buffer.
850 lge_jfree(struct mbuf *m, void *buf, void *args)
852 struct lge_softc *sc;
854 struct lge_jpool_entry *entry;
856 /* Extract the softc struct pointer. */
860 panic("lge_jfree: can't find softc pointer!");
862 /* calculate the slot this buffer belongs to */
863 i = ((vm_offset_t)buf
864 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN;
866 if ((i < 0) || (i >= LGE_JSLOTS))
867 panic("lge_jfree: asked to free buffer that we don't manage!");
869 entry = SLIST_FIRST(&sc->lge_jinuse_listhead);
871 panic("lge_jfree: buffer not in use!");
873 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries);
874 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries);
876 return (EXT_FREE_OK);
880 * A frame has been uploaded: pass the resulting mbuf chain up to
881 * the higher level protocols.
885 struct lge_softc *sc;
890 struct lge_rx_desc *cur_rx;
891 int c, i, total_len = 0;
892 u_int32_t rxsts, rxctl;
896 /* Find out how many frames were processed. */
898 i = sc->lge_cdata.lge_rx_cons;
902 struct mbuf *m0 = NULL;
904 cur_rx = &sc->lge_ldata->lge_rx_list[i];
905 rxctl = cur_rx->lge_ctl;
906 rxsts = cur_rx->lge_sts;
907 m = cur_rx->lge_mbuf;
908 cur_rx->lge_mbuf = NULL;
909 total_len = LGE_RXBYTES(cur_rx);
910 LGE_INC(i, LGE_RX_LIST_CNT);
914 * If an error occurs, update stats, clear the
915 * status word and leave the mbuf cluster in place:
916 * it should simply get re-used next time this descriptor
917 * comes up in the ring.
919 if (rxctl & LGE_RXCTL_ERRMASK) {
921 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
925 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) {
926 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN,
928 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
930 device_printf(sc->lge_dev, "no receive buffers "
931 "available -- packet dropped!\n");
937 m->m_pkthdr.rcvif = ifp;
938 m->m_pkthdr.len = m->m_len = total_len;
943 /* Do IP checksum checking. */
944 if (rxsts & LGE_RXSTS_ISIP)
945 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
946 if (!(rxsts & LGE_RXSTS_IPCSUMERR))
947 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
948 if ((rxsts & LGE_RXSTS_ISTCP &&
949 !(rxsts & LGE_RXSTS_TCPCSUMERR)) ||
950 (rxsts & LGE_RXSTS_ISUDP &&
951 !(rxsts & LGE_RXSTS_UDPCSUMERR))) {
952 m->m_pkthdr.csum_flags |=
953 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
954 m->m_pkthdr.csum_data = 0xffff;
958 (*ifp->if_input)(ifp, m);
962 sc->lge_cdata.lge_rx_cons = i;
969 struct lge_softc *sc;
974 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
980 * A frame was downloaded to the chip. It's safe for us to clean up
986 struct lge_softc *sc;
988 struct lge_tx_desc *cur_tx = NULL;
990 u_int32_t idx, txdone;
994 /* Clear the timeout timer. */
998 * Go through our tx list and free mbufs for those
999 * frames that have been transmitted.
1001 idx = sc->lge_cdata.lge_tx_cons;
1002 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT);
1004 while (idx != sc->lge_cdata.lge_tx_prod && txdone) {
1005 cur_tx = &sc->lge_ldata->lge_tx_list[idx];
1008 if (cur_tx->lge_mbuf != NULL) {
1009 m_freem(cur_tx->lge_mbuf);
1010 cur_tx->lge_mbuf = NULL;
1012 cur_tx->lge_ctl = 0;
1015 LGE_INC(idx, LGE_TX_LIST_CNT);
1019 sc->lge_cdata.lge_tx_cons = idx;
1022 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1031 struct lge_softc *sc;
1032 struct mii_data *mii;
1037 LGE_LOCK_ASSERT(sc);
1039 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS);
1040 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL);
1041 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS);
1042 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL);
1044 if (!sc->lge_link) {
1045 mii = device_get_softc(sc->lge_miibus);
1047 if (mii->mii_media_status & IFM_ACTIVE &&
1048 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1051 (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX||
1052 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T))
1053 device_printf(sc->lge_dev, "gigabit link up\n");
1054 if (ifp->if_snd.ifq_head != NULL)
1055 lge_start_locked(ifp);
1059 if (sc->lge_timer != 0 && --sc->lge_timer == 0)
1061 callout_reset(&sc->lge_stat_callout, hz, lge_tick, sc);
1070 struct lge_softc *sc;
1078 /* Supress unwanted interrupts */
1079 if (!(ifp->if_flags & IFF_UP)) {
1087 * Reading the ISR register clears all interrupts, and
1088 * clears the 'interrupts enabled' bit in the IMR
1091 status = CSR_READ_4(sc, LGE_ISR);
1093 if ((status & LGE_INTRS) == 0)
1096 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE)))
1099 if (status & LGE_ISR_RXDMA_DONE)
1100 lge_rxeof(sc, LGE_RX_DMACNT(status));
1102 if (status & LGE_ISR_RXCMDFIFO_EMPTY)
1105 if (status & LGE_ISR_PHY_INTR) {
1107 callout_stop(&sc->lge_stat_callout);
1112 /* Re-enable interrupts. */
1113 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB);
1115 if (ifp->if_snd.ifq_head != NULL)
1116 lge_start_locked(ifp);
1123 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1124 * pointers to the fragment pointers.
1127 lge_encap(sc, m_head, txidx)
1128 struct lge_softc *sc;
1129 struct mbuf *m_head;
1132 struct lge_frag *f = NULL;
1133 struct lge_tx_desc *cur_tx;
1135 int frag = 0, tot_len = 0;
1138 * Start packing the mbufs in this chain into
1139 * the fragment pointers. Stop when we run out
1140 * of fragments or hit the end of the mbuf chain.
1143 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx];
1146 for (m = m_head; m != NULL; m = m->m_next) {
1147 if (m->m_len != 0) {
1148 tot_len += m->m_len;
1149 f = &cur_tx->lge_frags[frag];
1150 f->lge_fraglen = m->m_len;
1151 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t));
1152 f->lge_fragptr_hi = 0;
1160 cur_tx->lge_mbuf = m_head;
1161 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len;
1162 LGE_INC((*txidx), LGE_TX_LIST_CNT);
1164 /* Queue for transmit */
1165 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx));
1171 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1172 * to the mbuf data regions directly in the transmit lists. We also save a
1173 * copy of the pointers since the transmit list fragment pointers are
1174 * physical addresses.
1181 struct lge_softc *sc;
1185 lge_start_locked(ifp);
1190 lge_start_locked(ifp)
1193 struct lge_softc *sc;
1194 struct mbuf *m_head = NULL;
1202 idx = sc->lge_cdata.lge_tx_prod;
1204 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
1207 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) {
1208 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0)
1211 IF_DEQUEUE(&ifp->if_snd, m_head);
1215 if (lge_encap(sc, m_head, &idx)) {
1216 IF_PREPEND(&ifp->if_snd, m_head);
1217 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1222 * If there's a BPF listener, bounce a copy of this frame
1225 BPF_MTAP(ifp, m_head);
1228 sc->lge_cdata.lge_tx_prod = idx;
1231 * Set a timeout in case the chip goes out to lunch.
1242 struct lge_softc *sc = xsc;
1245 lge_init_locked(sc);
1251 struct lge_softc *sc;
1253 struct ifnet *ifp = sc->lge_ifp;
1255 LGE_LOCK_ASSERT(sc);
1256 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1260 * Cancel pending I/O and free all RX/TX buffers.
1265 /* Set MAC address */
1266 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&IF_LLADDR(sc->lge_ifp)[0]));
1267 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&IF_LLADDR(sc->lge_ifp)[4]));
1269 /* Init circular RX list. */
1270 if (lge_list_rx_init(sc) == ENOBUFS) {
1271 device_printf(sc->lge_dev, "initialization failed: no "
1272 "memory for rx buffers\n");
1278 * Init tx descriptors.
1280 lge_list_tx_init(sc);
1282 /* Set initial value for MODE1 register. */
1283 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST|
1284 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD|
1285 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0|
1286 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2);
1288 /* If we want promiscuous mode, set the allframes bit. */
1289 if (ifp->if_flags & IFF_PROMISC) {
1290 CSR_WRITE_4(sc, LGE_MODE1,
1291 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC);
1293 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC);
1297 * Set the capture broadcast bit to capture broadcast frames.
1299 if (ifp->if_flags & IFF_BROADCAST) {
1300 CSR_WRITE_4(sc, LGE_MODE1,
1301 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST);
1303 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST);
1306 /* Packet padding workaround? */
1307 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD);
1309 /* No error frames */
1310 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS);
1312 /* Receive large frames */
1313 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS);
1315 /* Workaround: disable RX/TX flow control */
1316 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL);
1317 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL);
1319 /* Make sure to strip CRC from received frames */
1320 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC);
1322 /* Turn off magic packet mode */
1323 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB);
1325 /* Turn off all VLAN stuff */
1326 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX|
1327 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT);
1329 /* Workarond: FIFO overflow */
1330 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF);
1331 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT);
1334 * Load the multicast filter.
1339 * Enable hardware checksum validation for all received IPv4
1340 * packets, do not reject packets with bad checksums.
1342 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM|
1343 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM|
1344 LGE_MODE2_RX_ERRCSUM);
1347 * Enable the delivery of PHY interrupts based on
1348 * link/speed/duplex status chalges.
1350 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL);
1352 /* Enable receiver and transmitter. */
1353 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
1354 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB);
1356 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0);
1357 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB);
1360 * Enable interrupts.
1362 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|
1363 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS);
1365 lge_ifmedia_upd_locked(ifp);
1367 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1368 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1370 callout_reset(&sc->lge_stat_callout, hz, lge_tick, sc);
1376 * Set media options.
1379 lge_ifmedia_upd(ifp)
1382 struct lge_softc *sc;
1386 lge_ifmedia_upd_locked(ifp);
1393 lge_ifmedia_upd_locked(ifp)
1396 struct lge_softc *sc;
1397 struct mii_data *mii;
1398 struct mii_softc *miisc;
1402 LGE_LOCK_ASSERT(sc);
1403 mii = device_get_softc(sc->lge_miibus);
1405 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1411 * Report current media status.
1414 lge_ifmedia_sts(ifp, ifmr)
1416 struct ifmediareq *ifmr;
1418 struct lge_softc *sc;
1419 struct mii_data *mii;
1424 mii = device_get_softc(sc->lge_miibus);
1426 ifmr->ifm_active = mii->mii_media_active;
1427 ifmr->ifm_status = mii->mii_media_status;
1434 lge_ioctl(ifp, command, data)
1439 struct lge_softc *sc = ifp->if_softc;
1440 struct ifreq *ifr = (struct ifreq *) data;
1441 struct mii_data *mii;
1447 if (ifr->ifr_mtu > LGE_JUMBO_MTU)
1450 ifp->if_mtu = ifr->ifr_mtu;
1455 if (ifp->if_flags & IFF_UP) {
1456 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1457 ifp->if_flags & IFF_PROMISC &&
1458 !(sc->lge_if_flags & IFF_PROMISC)) {
1459 CSR_WRITE_4(sc, LGE_MODE1,
1460 LGE_MODE1_SETRST_CTL1|
1461 LGE_MODE1_RX_PROMISC);
1462 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1463 !(ifp->if_flags & IFF_PROMISC) &&
1464 sc->lge_if_flags & IFF_PROMISC) {
1465 CSR_WRITE_4(sc, LGE_MODE1,
1466 LGE_MODE1_RX_PROMISC);
1468 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1469 lge_init_locked(sc);
1472 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1475 sc->lge_if_flags = ifp->if_flags;
1488 mii = device_get_softc(sc->lge_miibus);
1489 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1492 error = ether_ioctl(ifp, command, data);
1501 struct lge_softc *sc;
1505 LGE_LOCK_ASSERT(sc);
1509 if_printf(ifp, "watchdog timeout\n");
1513 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1514 lge_init_locked(sc);
1516 if (ifp->if_snd.ifq_head != NULL)
1517 lge_start_locked(ifp);
1521 * Stop the adapter and free any mbufs allocated to the
1526 struct lge_softc *sc;
1531 LGE_LOCK_ASSERT(sc);
1534 callout_stop(&sc->lge_stat_callout);
1535 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB);
1537 /* Disable receiver and transmitter. */
1538 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB);
1542 * Free data in the RX lists.
1544 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
1545 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) {
1546 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf);
1547 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL;
1550 bzero((char *)&sc->lge_ldata->lge_rx_list,
1551 sizeof(sc->lge_ldata->lge_rx_list));
1554 * Free the TX list buffers.
1556 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
1557 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) {
1558 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf);
1559 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL;
1563 bzero((char *)&sc->lge_ldata->lge_tx_list,
1564 sizeof(sc->lge_ldata->lge_tx_list));
1566 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1572 * Stop all chip I/O so that the kernel's probe routines don't
1573 * get confused by errant DMAs when rebooting.
1579 struct lge_softc *sc;
1581 sc = device_get_softc(dev);