sys/dev/mii/brgphy.c

   1 /*-
   2  * Copyright (c) 2000
   3  *      Bill Paul <wpaul@ee.columbia.edu>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. All advertising materials mentioning features or use of this software
  14  *    must display the following acknowledgement:
  15  *      This product includes software developed by Bill Paul.
  16  * 4. Neither the name of the author nor the names of any co-contributors
  17  *    may be used to endorse or promote products derived from this software
  18  *    without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  30  * THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <sys/cdefs.h>
  34 __FBSDID("$FreeBSD$");
  35
  36 /*
  37  * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY.
  38  */
  39
  40 #include <sys/param.h>
  41 #include <sys/systm.h>
  42 #include <sys/kernel.h>
  43 #include <sys/module.h>
  44 #include <sys/socket.h>
  45 #include <sys/bus.h>
  46
  47 #include <net/if.h>
  48 #include <net/ethernet.h>
  49 #include <net/if_media.h>
  50
  51 #include <dev/mii/mii.h>
  52 #include <dev/mii/miivar.h>
  53 #include "miidevs.h"
  54
  55 #include <dev/mii/brgphyreg.h>
  56 #include <net/if_arp.h>
  57 #include <machine/bus.h>
  58 #include <dev/bge/if_bgereg.h>
  59 #include <dev/bce/if_bcereg.h>
  60
  61 #include <dev/pci/pcireg.h>
  62 #include <dev/pci/pcivar.h>
  63
  64 #include "miibus_if.h"
  65
  66 static int brgphy_probe(device_t);
  67 static int brgphy_attach(device_t);
  68
  69 struct brgphy_softc {
  70         struct mii_softc mii_sc;
  71         int serdes_flags;       /* Keeps track of the serdes type used */
  72 #define BRGPHY_5706S            0x0001
  73 #define BRGPHY_5708S            0x0002
  74 #define BRGPHY_NOANWAIT         0x0004
  75 #define BRGPHY_5709S            0x0008
  76         int bce_phy_flags;      /* PHY flags transferred from the MAC driver */
  77 };
  78
  79 static device_method_t brgphy_methods[] = {
  80         /* device interface */
  81         DEVMETHOD(device_probe,         brgphy_probe),
  82         DEVMETHOD(device_attach,        brgphy_attach),
  83         DEVMETHOD(device_detach,        mii_phy_detach),
  84         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  85         DEVMETHOD_END
  86 };
  87
  88 static devclass_t brgphy_devclass;
  89
  90 static driver_t brgphy_driver = {
  91         "brgphy",
  92         brgphy_methods,
  93         sizeof(struct brgphy_softc)
  94 };
  95
  96 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0);
  97
  98 static int      brgphy_service(struct mii_softc *, struct mii_data *, int);
  99 static void     brgphy_setmedia(struct mii_softc *, int);
 100 static void     brgphy_status(struct mii_softc *);
 101 static void     brgphy_mii_phy_auto(struct mii_softc *, int);
 102 static void     brgphy_reset(struct mii_softc *);
 103 static void     brgphy_enable_loopback(struct mii_softc *);
 104 static void     bcm5401_load_dspcode(struct mii_softc *);
 105 static void     bcm5411_load_dspcode(struct mii_softc *);
 106 static void     bcm54k2_load_dspcode(struct mii_softc *);
 107 static void     brgphy_fixup_5704_a0_bug(struct mii_softc *);
 108 static void     brgphy_fixup_adc_bug(struct mii_softc *);
 109 static void     brgphy_fixup_adjust_trim(struct mii_softc *);
 110 static void     brgphy_fixup_ber_bug(struct mii_softc *);
 111 static void     brgphy_fixup_crc_bug(struct mii_softc *);
 112 static void     brgphy_fixup_jitter_bug(struct mii_softc *);
 113 static void     brgphy_ethernet_wirespeed(struct mii_softc *);
 114 static void     brgphy_jumbo_settings(struct mii_softc *, u_long);
 115
 116 static const struct mii_phydesc brgphys[] = {
 117         MII_PHY_DESC(BROADCOM, BCM5400),
 118         MII_PHY_DESC(BROADCOM, BCM5401),
 119         MII_PHY_DESC(BROADCOM, BCM5411),
 120         MII_PHY_DESC(BROADCOM, BCM54K2),
 121         MII_PHY_DESC(BROADCOM, BCM5701),
 122         MII_PHY_DESC(BROADCOM, BCM5703),
 123         MII_PHY_DESC(BROADCOM, BCM5704),
 124         MII_PHY_DESC(BROADCOM, BCM5705),
 125         MII_PHY_DESC(BROADCOM, BCM5706),
 126         MII_PHY_DESC(BROADCOM, BCM5714),
 127         MII_PHY_DESC(BROADCOM, BCM5421),
 128         MII_PHY_DESC(BROADCOM, BCM5750),
 129         MII_PHY_DESC(BROADCOM, BCM5752),
 130         MII_PHY_DESC(BROADCOM, BCM5780),
 131         MII_PHY_DESC(BROADCOM, BCM5708C),
 132         MII_PHY_DESC(BROADCOM2, BCM5482),
 133         MII_PHY_DESC(BROADCOM2, BCM5708S),
 134         MII_PHY_DESC(BROADCOM2, BCM5709C),
 135         MII_PHY_DESC(BROADCOM2, BCM5709S),
 136         MII_PHY_DESC(BROADCOM2, BCM5709CAX),
 137         MII_PHY_DESC(BROADCOM2, BCM5722),
 138         MII_PHY_DESC(BROADCOM2, BCM5755),
 139         MII_PHY_DESC(BROADCOM2, BCM5754),
 140         MII_PHY_DESC(BROADCOM2, BCM5761),
 141         MII_PHY_DESC(BROADCOM2, BCM5784),
 142 #ifdef notyet   /* better handled by ukphy(4) until WARs are implemented */
 143         MII_PHY_DESC(BROADCOM2, BCM5785),
 144 #endif
 145         MII_PHY_DESC(BROADCOM3, BCM5717C),
 146         MII_PHY_DESC(BROADCOM3, BCM5719C),
 147         MII_PHY_DESC(BROADCOM3, BCM5720C),
 148         MII_PHY_DESC(BROADCOM3, BCM57765),
 149         MII_PHY_DESC(BROADCOM3, BCM57780),
 150         MII_PHY_DESC(BROADCOM4, BCM5725C),
 151         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5906),
 152         MII_PHY_END
 153 };
 154
 155 static const struct mii_phy_funcs brgphy_funcs = {
 156         brgphy_service,
 157         brgphy_status,
 158         brgphy_reset
 159 };
 160
 161 #define HS21_PRODUCT_ID "IBM eServer BladeCenter HS21"
 162 #define HS21_BCM_CHIPID 0x57081021
 163
 164 static int
 165 detect_hs21(struct bce_softc *bce_sc)
 166 {
 167         char *sysenv;
 168         int found;
 169
 170         found = 0;
 171         if (bce_sc->bce_chipid == HS21_BCM_CHIPID) {
 172                 sysenv = getenv("smbios.system.product");
 173                 if (sysenv != NULL) {
 174                         if (strncmp(sysenv, HS21_PRODUCT_ID,
 175                             strlen(HS21_PRODUCT_ID)) == 0)
 176                                 found = 1;
 177                         freeenv(sysenv);
 178                 }
 179         }
 180         return (found);
 181 }
 182
 183 /* Search for our PHY in the list of known PHYs */
 184 static int
 185 brgphy_probe(device_t dev)
 186 {
 187
 188         return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT));
 189 }
 190
 191 /* Attach the PHY to the MII bus */
 192 static int
 193 brgphy_attach(device_t dev)
 194 {
 195         struct brgphy_softc *bsc;
 196         struct bge_softc *bge_sc = NULL;
 197         struct bce_softc *bce_sc = NULL;
 198         struct mii_softc *sc;
 199         struct ifnet *ifp;
 200
 201         bsc = device_get_softc(dev);
 202         sc = &bsc->mii_sc;
 203
 204         mii_phy_dev_attach(dev, MIIF_NOISOLATE | MIIF_NOMANPAUSE,
 205             &brgphy_funcs, 0);
 206
 207         bsc->serdes_flags = 0;
 208         ifp = sc->mii_pdata->mii_ifp;
 209
 210         /* Find the MAC driver associated with this PHY. */
 211         if (strcmp(ifp->if_dname, "bge") == 0)
 212                 bge_sc = ifp->if_softc;
 213         else if (strcmp(ifp->if_dname, "bce") == 0)
 214                 bce_sc = ifp->if_softc;
 215
 216         /* Handle any special cases based on the PHY ID */
 217         switch (sc->mii_mpd_oui) {
 218         case MII_OUI_BROADCOM:
 219                 switch (sc->mii_mpd_model) {
 220                 case MII_MODEL_BROADCOM_BCM5706:
 221                 case MII_MODEL_BROADCOM_BCM5714:
 222                         /*
 223                          * The 5464 PHY used in the 5706 supports both copper
 224                          * and fiber interfaces over GMII.  Need to check the
 225                          * shadow registers to see which mode is actually
 226                          * in effect, and therefore whether we have 5706C or
 227                          * 5706S.
 228                          */
 229                         PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C,
 230                                 BRGPHY_SHADOW_1C_MODE_CTRL);
 231                         if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) &
 232                                 BRGPHY_SHADOW_1C_ENA_1000X) {
 233                                 bsc->serdes_flags |= BRGPHY_5706S;
 234                                 sc->mii_flags |= MIIF_HAVEFIBER;
 235                         }
 236                         break;
 237                 }
 238                 break;
 239         case MII_OUI_BROADCOM2:
 240                 switch (sc->mii_mpd_model) {
 241                 case MII_MODEL_BROADCOM2_BCM5708S:
 242                         bsc->serdes_flags |= BRGPHY_5708S;
 243                         sc->mii_flags |= MIIF_HAVEFIBER;
 244                         break;
 245                 case MII_MODEL_BROADCOM2_BCM5709S:
 246                         /*
 247                          * XXX
 248                          * 5720S and 5709S shares the same PHY id.
 249                          * Assume 5720S PHY if parent device is bge(4).
 250                          */
 251                         if (bge_sc != NULL)
 252                                 bsc->serdes_flags |= BRGPHY_5708S;
 253                         else
 254                                 bsc->serdes_flags |= BRGPHY_5709S;
 255                         sc->mii_flags |= MIIF_HAVEFIBER;
 256                         break;
 257                 }
 258                 break;
 259         }
 260
 261         PHY_RESET(sc);
 262
 263         /* Read the PHY's capabilities. */
 264         sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & sc->mii_capmask;
 265         if (sc->mii_capabilities & BMSR_EXTSTAT)
 266                 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
 267         device_printf(dev, " ");
 268
 269 #define ADD(m, c)       ifmedia_add(&sc->mii_pdata->mii_media, (m), (c), NULL)
 270
 271         /* Add the supported media types */
 272         if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
 273                 mii_phy_add_media(sc);
 274                 printf("\n");
 275         } else {
 276                 sc->mii_anegticks = MII_ANEGTICKS_GIGE;
 277                 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst),
 278                         BRGPHY_S1000 | BRGPHY_BMCR_FDX);
 279                 printf("1000baseSX-FDX, ");
 280                 /* 2.5G support is a software enabled feature on the 5708S and 5709S. */
 281                 if (bce_sc && (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
 282                         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX, sc->mii_inst), 0);
 283                         printf("2500baseSX-FDX, ");
 284                 } else if ((bsc->serdes_flags & BRGPHY_5708S) && bce_sc &&
 285                     (detect_hs21(bce_sc) != 0)) {
 286                         /*
 287                          * There appears to be certain silicon revision
 288                          * in IBM HS21 blades that is having issues with
 289                          * this driver wating for the auto-negotiation to
 290                          * complete. This happens with a specific chip id
 291                          * only and when the 1000baseSX-FDX is the only
 292                          * mode. Workaround this issue since it's unlikely
 293                          * to be ever addressed.
 294                          */
 295                         printf("auto-neg workaround, ");
 296                         bsc->serdes_flags |= BRGPHY_NOANWAIT;
 297                 }
 298                 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0);
 299                 printf("auto\n");
 300         }
 301
 302 #undef ADD
 303         MIIBUS_MEDIAINIT(sc->mii_dev);
 304         return (0);
 305 }
 306
 307 static int
 308 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
 309 {
 310         struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
 311         int val;
 312
 313         switch (cmd) {
 314         case MII_POLLSTAT:
 315                 break;
 316         case MII_MEDIACHG:
 317                 /* If the interface is not up, don't do anything. */
 318                 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
 319                         break;
 320
 321                 /* Todo: Why is this here?  Is it really needed? */
 322                 PHY_RESET(sc);  /* XXX hardware bug work-around */
 323
 324                 switch (IFM_SUBTYPE(ife->ifm_media)) {
 325                 case IFM_AUTO:
 326                         brgphy_mii_phy_auto(sc, ife->ifm_media);
 327                         break;
 328                 case IFM_2500_SX:
 329                 case IFM_1000_SX:
 330                 case IFM_1000_T:
 331                 case IFM_100_TX:
 332                 case IFM_10_T:
 333                         brgphy_setmedia(sc, ife->ifm_media);
 334                         break;
 335                 default:
 336                         return (EINVAL);
 337                 }
 338                 break;
 339         case MII_TICK:
 340                 /* Bail if the interface isn't up. */
 341                 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
 342                         return (0);
 343
 344
 345                 /* Bail if autoneg isn't in process. */
 346                 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
 347                         sc->mii_ticks = 0;
 348                         break;
 349                 }
 350
 351                 /*
 352                  * Check to see if we have link.  If we do, we don't
 353                  * need to restart the autonegotiation process.
 354                  */
 355                 val = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
 356                 if (val & BMSR_LINK) {
 357                         sc->mii_ticks = 0;      /* Reset autoneg timer. */
 358                         break;
 359                 }
 360
 361                 /* Announce link loss right after it happens. */
 362                 if (sc->mii_ticks++ == 0)
 363                         break;
 364
 365                 /* Only retry autonegotiation every mii_anegticks seconds. */
 366                 if (sc->mii_ticks <= sc->mii_anegticks)
 367                         break;
 368
 369
 370                 /* Retry autonegotiation */
 371                 sc->mii_ticks = 0;
 372                 brgphy_mii_phy_auto(sc, ife->ifm_media);
 373                 break;
 374         }
 375
 376         /* Update the media status. */
 377         PHY_STATUS(sc);
 378
 379         /*
 380          * Callback if something changed. Note that we need to poke
 381          * the DSP on the Broadcom PHYs if the media changes.
 382          */
 383         if (sc->mii_media_active != mii->mii_media_active ||
 384             sc->mii_media_status != mii->mii_media_status ||
 385             cmd == MII_MEDIACHG) {
 386                 switch (sc->mii_mpd_oui) {
 387                 case MII_OUI_BROADCOM:
 388                         switch (sc->mii_mpd_model) {
 389                         case MII_MODEL_BROADCOM_BCM5400:
 390                                 bcm5401_load_dspcode(sc);
 391                                 break;
 392                         case MII_MODEL_BROADCOM_BCM5401:
 393                                 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3)
 394                                         bcm5401_load_dspcode(sc);
 395                                 break;
 396                         case MII_MODEL_BROADCOM_BCM5411:
 397                                 bcm5411_load_dspcode(sc);
 398                                 break;
 399                         case MII_MODEL_BROADCOM_BCM54K2:
 400                                 bcm54k2_load_dspcode(sc);
 401                                 break;
 402                         }
 403                         break;
 404                 }
 405         }
 406         mii_phy_update(sc, cmd);
 407         return (0);
 408 }
 409
 410 /****************************************************************************/
 411 /* Sets the PHY link speed.                                                 */
 412 /*                                                                          */
 413 /* Returns:                                                                 */
 414 /*   None                                                                   */
 415 /****************************************************************************/
 416 static void
 417 brgphy_setmedia(struct mii_softc *sc, int media)
 418 {
 419         int bmcr = 0, gig;
 420
 421         switch (IFM_SUBTYPE(media)) {
 422         case IFM_2500_SX:
 423                 break;
 424         case IFM_1000_SX:
 425         case IFM_1000_T:
 426                 bmcr = BRGPHY_S1000;
 427                 break;
 428         case IFM_100_TX:
 429                 bmcr = BRGPHY_S100;
 430                 break;
 431         case IFM_10_T:
 432         default:
 433                 bmcr = BRGPHY_S10;
 434                 break;
 435         }
 436
 437         if ((media & IFM_FDX) != 0) {
 438                 bmcr |= BRGPHY_BMCR_FDX;
 439                 gig = BRGPHY_1000CTL_AFD;
 440         } else {
 441                 gig = BRGPHY_1000CTL_AHD;
 442         }
 443
 444         /* Force loopback to disconnect PHY from Ethernet medium. */
 445         brgphy_enable_loopback(sc);
 446
 447         PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
 448         PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
 449
 450         if (IFM_SUBTYPE(media) != IFM_1000_T &&
 451             IFM_SUBTYPE(media) != IFM_1000_SX) {
 452                 PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr);
 453                 return;
 454         }
 455
 456         if (IFM_SUBTYPE(media) == IFM_1000_T) {
 457                 gig |= BRGPHY_1000CTL_MSE;
 458                 if ((media & IFM_ETH_MASTER) != 0)
 459                         gig |= BRGPHY_1000CTL_MSC;
 460         }
 461         PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig);
 462         PHY_WRITE(sc, BRGPHY_MII_BMCR,
 463             bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
 464 }
 465
 466 /****************************************************************************/
 467 /* Set the media status based on the PHY settings.                          */
 468 /*                                                                          */
 469 /* Returns:                                                                 */
 470 /*   None                                                                   */
 471 /****************************************************************************/
 472 static void
 473 brgphy_status(struct mii_softc *sc)
 474 {
 475         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
 476         struct mii_data *mii = sc->mii_pdata;
 477         int aux, bmcr, bmsr, val, xstat;
 478         u_int flowstat;
 479
 480         mii->mii_media_status = IFM_AVALID;
 481         mii->mii_media_active = IFM_ETHER;
 482
 483         bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR);
 484         bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
 485
 486         if (bmcr & BRGPHY_BMCR_LOOP) {
 487                 mii->mii_media_active |= IFM_LOOP;
 488         }
 489
 490         if ((bmcr & BRGPHY_BMCR_AUTOEN) &&
 491             (bmsr & BRGPHY_BMSR_ACOMP) == 0 &&
 492             (bsc->serdes_flags & BRGPHY_NOANWAIT) == 0) {
 493                 /* Erg, still trying, I guess... */
 494                 mii->mii_media_active |= IFM_NONE;
 495                 return;
 496         }
 497
 498         if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
 499                 /*
 500                  * NB: reading the ANAR, ANLPAR or 1000STS after the AUXSTS
 501                  * wedges at least the PHY of BCM5704 (but not others).
 502                  */
 503                 flowstat = mii_phy_flowstatus(sc);
 504                 xstat = PHY_READ(sc, BRGPHY_MII_1000STS);
 505                 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS);
 506
 507                 /* If copper link is up, get the negotiated speed/duplex. */
 508                 if (aux & BRGPHY_AUXSTS_LINK) {
 509                         mii->mii_media_status |= IFM_ACTIVE;
 510                         switch (aux & BRGPHY_AUXSTS_AN_RES) {
 511                         case BRGPHY_RES_1000FD:
 512                                 mii->mii_media_active |= IFM_1000_T | IFM_FDX;  break;
 513                         case BRGPHY_RES_1000HD:
 514                                 mii->mii_media_active |= IFM_1000_T | IFM_HDX;  break;
 515                         case BRGPHY_RES_100FD:
 516                                 mii->mii_media_active |= IFM_100_TX | IFM_FDX; break;
 517                         case BRGPHY_RES_100T4:
 518                                 mii->mii_media_active |= IFM_100_T4; break;
 519                         case BRGPHY_RES_100HD:
 520                                 mii->mii_media_active |= IFM_100_TX | IFM_HDX;  break;
 521                         case BRGPHY_RES_10FD:
 522                                 mii->mii_media_active |= IFM_10_T | IFM_FDX; break;
 523                         case BRGPHY_RES_10HD:
 524                                 mii->mii_media_active |= IFM_10_T | IFM_HDX; break;
 525                         default:
 526                                 mii->mii_media_active |= IFM_NONE; break;
 527                         }
 528
 529                         if ((mii->mii_media_active & IFM_FDX) != 0)
 530                                 mii->mii_media_active |= flowstat;
 531
 532                         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T &&
 533                             (xstat & BRGPHY_1000STS_MSR) != 0)
 534                                 mii->mii_media_active |= IFM_ETH_MASTER;
 535                 }
 536         } else {
 537                 /* Todo: Add support for flow control. */
 538                 /* If serdes link is up, get the negotiated speed/duplex. */
 539                 if (bmsr & BRGPHY_BMSR_LINK) {
 540                         mii->mii_media_status |= IFM_ACTIVE;
 541                 }
 542
 543                 /* Check the link speed/duplex based on the PHY type. */
 544                 if (bsc->serdes_flags & BRGPHY_5706S) {
 545                         mii->mii_media_active |= IFM_1000_SX;
 546
 547                         /* If autoneg enabled, read negotiated duplex settings */
 548                         if (bmcr & BRGPHY_BMCR_AUTOEN) {
 549                                 val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR);
 550                                 if (val & BRGPHY_SERDES_ANAR_FDX)
 551                                         mii->mii_media_active |= IFM_FDX;
 552                                 else
 553                                         mii->mii_media_active |= IFM_HDX;
 554                         }
 555                 } else if (bsc->serdes_flags & BRGPHY_5708S) {
 556                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
 557                         xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1);
 558
 559                         /* Check for MRBE auto-negotiated speed results. */
 560                         switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) {
 561                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10:
 562                                 mii->mii_media_active |= IFM_10_FL; break;
 563                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100:
 564                                 mii->mii_media_active |= IFM_100_FX; break;
 565                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G:
 566                                 mii->mii_media_active |= IFM_1000_SX; break;
 567                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G:
 568                                 mii->mii_media_active |= IFM_2500_SX; break;
 569                         }
 570
 571                         /* Check for MRBE auto-negotiated duplex results. */
 572                         if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX)
 573                                 mii->mii_media_active |= IFM_FDX;
 574                         else
 575                                 mii->mii_media_active |= IFM_HDX;
 576                 } else if (bsc->serdes_flags & BRGPHY_5709S) {
 577                         /* Select GP Status Block of the AN MMD, get autoneg results. */
 578                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS);
 579                         xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS);
 580
 581                         /* Restore IEEE0 block (assumed in all brgphy(4) code). */
 582                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
 583
 584                         /* Check for MRBE auto-negotiated speed results. */
 585                         switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) {
 586                                 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10:
 587                                         mii->mii_media_active |= IFM_10_FL; break;
 588                                 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100:
 589                                         mii->mii_media_active |= IFM_100_FX; break;
 590                                 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G:
 591                                         mii->mii_media_active |= IFM_1000_SX; break;
 592                                 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G:
 593                                         mii->mii_media_active |= IFM_2500_SX; break;
 594                         }
 595
 596                         /* Check for MRBE auto-negotiated duplex results. */
 597                         if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX)
 598                                 mii->mii_media_active |= IFM_FDX;
 599                         else
 600                                 mii->mii_media_active |= IFM_HDX;
 601                 }
 602         }
 603 }
 604
 605 static void
 606 brgphy_mii_phy_auto(struct mii_softc *sc, int media)
 607 {
 608         int anar, ktcr = 0;
 609
 610         PHY_RESET(sc);
 611
 612         if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
 613                 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
 614                 if ((media & IFM_FLOW) != 0 ||
 615                     (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
 616                         anar |= BRGPHY_ANAR_PC | BRGPHY_ANAR_ASP;
 617                 PHY_WRITE(sc, BRGPHY_MII_ANAR, anar);
 618                 ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD;
 619                 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701)
 620                         ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC;
 621                 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr);
 622                 PHY_READ(sc, BRGPHY_MII_1000CTL);
 623         } else {
 624                 anar = BRGPHY_SERDES_ANAR_FDX | BRGPHY_SERDES_ANAR_HDX;
 625                 if ((media & IFM_FLOW) != 0 ||
 626                     (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
 627                         anar |= BRGPHY_SERDES_ANAR_BOTH_PAUSE;
 628                 PHY_WRITE(sc, BRGPHY_SERDES_ANAR, anar);
 629         }
 630
 631         PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_AUTOEN |
 632             BRGPHY_BMCR_STARTNEG);
 633         PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
 634 }
 635
 636 /* Enable loopback to force the link down. */
 637 static void
 638 brgphy_enable_loopback(struct mii_softc *sc)
 639 {
 640         int i;
 641
 642         PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP);
 643         for (i = 0; i < 15000; i++) {
 644                 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK))
 645                         break;
 646                 DELAY(10);
 647         }
 648 }
 649
 650 /* Turn off tap power management on 5401. */
 651 static void
 652 bcm5401_load_dspcode(struct mii_softc *sc)
 653 {
 654         static const struct {
 655                 int             reg;
 656                 uint16_t        val;
 657         } dspcode[] = {
 658                 { BRGPHY_MII_AUXCTL,            0x0c20 },
 659                 { BRGPHY_MII_DSP_ADDR_REG,      0x0012 },
 660                 { BRGPHY_MII_DSP_RW_PORT,       0x1804 },
 661                 { BRGPHY_MII_DSP_ADDR_REG,      0x0013 },
 662                 { BRGPHY_MII_DSP_RW_PORT,       0x1204 },
 663                 { BRGPHY_MII_DSP_ADDR_REG,      0x8006 },
 664                 { BRGPHY_MII_DSP_RW_PORT,       0x0132 },
 665                 { BRGPHY_MII_DSP_ADDR_REG,      0x8006 },
 666                 { BRGPHY_MII_DSP_RW_PORT,       0x0232 },
 667                 { BRGPHY_MII_DSP_ADDR_REG,      0x201f },
 668                 { BRGPHY_MII_DSP_RW_PORT,       0x0a20 },
 669                 { 0,                            0 },
 670         };
 671         int i;
 672
 673         for (i = 0; dspcode[i].reg != 0; i++)
 674                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 675         DELAY(40);
 676 }
 677
 678 static void
 679 bcm5411_load_dspcode(struct mii_softc *sc)
 680 {
 681         static const struct {
 682                 int             reg;
 683                 uint16_t        val;
 684         } dspcode[] = {
 685                 { 0x1c,                         0x8c23 },
 686                 { 0x1c,                         0x8ca3 },
 687                 { 0x1c,                         0x8c23 },
 688                 { 0,                            0 },
 689         };
 690         int i;
 691
 692         for (i = 0; dspcode[i].reg != 0; i++)
 693                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 694 }
 695
 696 void
 697 bcm54k2_load_dspcode(struct mii_softc *sc)
 698 {
 699         static const struct {
 700                 int             reg;
 701                 uint16_t        val;
 702         } dspcode[] = {
 703                 { 4,                            0x01e1 },
 704                 { 9,                            0x0300 },
 705                 { 0,                            0 },
 706         };
 707         int i;
 708
 709         for (i = 0; dspcode[i].reg != 0; i++)
 710                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 711
 712 }
 713
 714 static void
 715 brgphy_fixup_5704_a0_bug(struct mii_softc *sc)
 716 {
 717         static const struct {
 718                 int             reg;
 719                 uint16_t        val;
 720         } dspcode[] = {
 721                 { 0x1c,                         0x8d68 },
 722                 { 0x1c,                         0x8d68 },
 723                 { 0,                            0 },
 724         };
 725         int i;
 726
 727         for (i = 0; dspcode[i].reg != 0; i++)
 728                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 729 }
 730
 731 static void
 732 brgphy_fixup_adc_bug(struct mii_softc *sc)
 733 {
 734         static const struct {
 735                 int             reg;
 736                 uint16_t        val;
 737         } dspcode[] = {
 738                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 739                 { BRGPHY_MII_DSP_ADDR_REG,      0x201f },
 740                 { BRGPHY_MII_DSP_RW_PORT,       0x2aaa },
 741                 { 0,                            0 },
 742         };
 743         int i;
 744
 745         for (i = 0; dspcode[i].reg != 0; i++)
 746                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 747 }
 748
 749 static void
 750 brgphy_fixup_adjust_trim(struct mii_softc *sc)
 751 {
 752         static const struct {
 753                 int             reg;
 754                 uint16_t        val;
 755         } dspcode[] = {
 756                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 757                 { BRGPHY_MII_DSP_ADDR_REG,      0x000a },
 758                 { BRGPHY_MII_DSP_RW_PORT,       0x110b },
 759                 { BRGPHY_MII_TEST1,                     0x0014 },
 760                 { BRGPHY_MII_AUXCTL,            0x0400 },
 761                 { 0,                            0 },
 762         };
 763         int i;
 764
 765         for (i = 0; dspcode[i].reg != 0; i++)
 766                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 767 }
 768
 769 static void
 770 brgphy_fixup_ber_bug(struct mii_softc *sc)
 771 {
 772         static const struct {
 773                 int             reg;
 774                 uint16_t        val;
 775         } dspcode[] = {
 776                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 777                 { BRGPHY_MII_DSP_ADDR_REG,      0x000a },
 778                 { BRGPHY_MII_DSP_RW_PORT,       0x310b },
 779                 { BRGPHY_MII_DSP_ADDR_REG,      0x201f },
 780                 { BRGPHY_MII_DSP_RW_PORT,       0x9506 },
 781                 { BRGPHY_MII_DSP_ADDR_REG,      0x401f },
 782                 { BRGPHY_MII_DSP_RW_PORT,       0x14e2 },
 783                 { BRGPHY_MII_AUXCTL,            0x0400 },
 784                 { 0,                            0 },
 785         };
 786         int i;
 787
 788         for (i = 0; dspcode[i].reg != 0; i++)
 789                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 790 }
 791
 792 static void
 793 brgphy_fixup_crc_bug(struct mii_softc *sc)
 794 {
 795         static const struct {
 796                 int             reg;
 797                 uint16_t        val;
 798         } dspcode[] = {
 799                 { BRGPHY_MII_DSP_RW_PORT,       0x0a75 },
 800                 { 0x1c,                         0x8c68 },
 801                 { 0x1c,                         0x8d68 },
 802                 { 0x1c,                         0x8c68 },
 803                 { 0,                            0 },
 804         };
 805         int i;
 806
 807         for (i = 0; dspcode[i].reg != 0; i++)
 808                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 809 }
 810
 811 static void
 812 brgphy_fixup_jitter_bug(struct mii_softc *sc)
 813 {
 814         static const struct {
 815                 int             reg;
 816                 uint16_t        val;
 817         } dspcode[] = {
 818                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 819                 { BRGPHY_MII_DSP_ADDR_REG,      0x000a },
 820                 { BRGPHY_MII_DSP_RW_PORT,       0x010b },
 821                 { BRGPHY_MII_AUXCTL,            0x0400 },
 822                 { 0,                            0 },
 823         };
 824         int i;
 825
 826         for (i = 0; dspcode[i].reg != 0; i++)
 827                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 828 }
 829
 830 static void
 831 brgphy_fixup_disable_early_dac(struct mii_softc *sc)
 832 {
 833         uint32_t val;
 834
 835         PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08);
 836         val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT);
 837         val &= ~(1 << 8);
 838         PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val);
 839
 840 }
 841
 842 static void
 843 brgphy_ethernet_wirespeed(struct mii_softc *sc)
 844 {
 845         uint32_t        val;
 846
 847         /* Enable Ethernet@WireSpeed. */
 848         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
 849         val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 850         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4));
 851 }
 852
 853 static void
 854 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu)
 855 {
 856         uint32_t        val;
 857
 858         /* Set or clear jumbo frame settings in the PHY. */
 859         if (mtu > ETHER_MAX_LEN) {
 860                 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5401) {
 861                         /* BCM5401 PHY cannot read-modify-write. */
 862                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20);
 863                 } else {
 864                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
 865                         val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 866                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
 867                             val | BRGPHY_AUXCTL_LONG_PKT);
 868                 }
 869
 870                 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
 871                 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
 872                     val | BRGPHY_PHY_EXTCTL_HIGH_LA);
 873         } else {
 874                 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
 875                 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 876                 PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
 877                     val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7));
 878
 879                 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
 880                 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
 881                         val & ~BRGPHY_PHY_EXTCTL_HIGH_LA);
 882         }
 883 }
 884
 885 static void
 886 brgphy_reset(struct mii_softc *sc)
 887 {
 888         struct bge_softc *bge_sc = NULL;
 889         struct bce_softc *bce_sc = NULL;
 890         struct ifnet *ifp;
 891         int i, val;
 892
 893         /*
 894          * Perform a reset.  Note that at least some Broadcom PHYs default to
 895          * being powered down as well as isolated after a reset but don't work
 896          * if one or both of these bits are cleared.  However, they just work
 897          * fine if both bits remain set, so we don't use mii_phy_reset() here.
 898          */
 899         PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
 900
 901         /* Wait 100ms for it to complete. */
 902         for (i = 0; i < 100; i++) {
 903                 if ((PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_RESET) == 0)
 904                         break;
 905                 DELAY(1000);
 906         }
 907
 908         /* Handle any PHY specific procedures following the reset. */
 909         switch (sc->mii_mpd_oui) {
 910         case MII_OUI_BROADCOM:
 911                 switch (sc->mii_mpd_model) {
 912                 case MII_MODEL_BROADCOM_BCM5400:
 913                         bcm5401_load_dspcode(sc);
 914                         break;
 915                 case MII_MODEL_BROADCOM_BCM5401:
 916                         if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3)
 917                                 bcm5401_load_dspcode(sc);
 918                         break;
 919                 case MII_MODEL_BROADCOM_BCM5411:
 920                         bcm5411_load_dspcode(sc);
 921                         break;
 922                 case MII_MODEL_BROADCOM_BCM54K2:
 923                         bcm54k2_load_dspcode(sc);
 924                         break;
 925                 }
 926                 break;
 927         case MII_OUI_BROADCOM3:
 928                 switch (sc->mii_mpd_model) {
 929                 case MII_MODEL_BROADCOM3_BCM5717C:
 930                 case MII_MODEL_BROADCOM3_BCM5719C:
 931                 case MII_MODEL_BROADCOM3_BCM5720C:
 932                 case MII_MODEL_BROADCOM3_BCM57765:
 933                         return;
 934                 }
 935                 break;
 936         case MII_OUI_BROADCOM4:
 937                 return;
 938         }
 939
 940         ifp = sc->mii_pdata->mii_ifp;
 941
 942         /* Find the driver associated with this PHY. */
 943         if (strcmp(ifp->if_dname, "bge") == 0)  {
 944                 bge_sc = ifp->if_softc;
 945         } else if (strcmp(ifp->if_dname, "bce") == 0) {
 946                 bce_sc = ifp->if_softc;
 947         }
 948
 949         if (bge_sc) {
 950                 /* Fix up various bugs */
 951                 if (bge_sc->bge_phy_flags & BGE_PHY_5704_A0_BUG)
 952                         brgphy_fixup_5704_a0_bug(sc);
 953                 if (bge_sc->bge_phy_flags & BGE_PHY_ADC_BUG)
 954                         brgphy_fixup_adc_bug(sc);
 955                 if (bge_sc->bge_phy_flags & BGE_PHY_ADJUST_TRIM)
 956                         brgphy_fixup_adjust_trim(sc);
 957                 if (bge_sc->bge_phy_flags & BGE_PHY_BER_BUG)
 958                         brgphy_fixup_ber_bug(sc);
 959                 if (bge_sc->bge_phy_flags & BGE_PHY_CRC_BUG)
 960                         brgphy_fixup_crc_bug(sc);
 961                 if (bge_sc->bge_phy_flags & BGE_PHY_JITTER_BUG)
 962                         brgphy_fixup_jitter_bug(sc);
 963
 964                 if (bge_sc->bge_flags & BGE_FLAG_JUMBO)
 965                         brgphy_jumbo_settings(sc, ifp->if_mtu);
 966
 967                 if ((bge_sc->bge_phy_flags & BGE_PHY_NO_WIRESPEED) == 0)
 968                         brgphy_ethernet_wirespeed(sc);
 969
 970                 /* Enable Link LED on Dell boxes */
 971                 if (bge_sc->bge_phy_flags & BGE_PHY_NO_3LED) {
 972                         PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
 973                             PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) &
 974                             ~BRGPHY_PHY_EXTCTL_3_LED);
 975                 }
 976
 977                 /* Adjust output voltage (From Linux driver) */
 978                 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906)
 979                         PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);
 980         } else if (bce_sc) {
 981                 if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 &&
 982                         (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
 983
 984                         /* Store autoneg capabilities/results in digital block (Page 0) */
 985                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2);
 986                         PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0,
 987                                 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE);
 988                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
 989
 990                         /* Enable fiber mode and autodetection */
 991                         PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1,
 992                                 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) |
 993                                 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN |
 994                                 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE);
 995
 996                         /* Enable parallel detection */
 997                         PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2,
 998                                 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) |
 999                                 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN);
1000
1001                         /* Advertise 2.5G support through next page during autoneg */
1002                         if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1003                                 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
1004                                         PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) |
1005                                         BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
1006
1007                         /* Increase TX signal amplitude */
1008                         if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) ||
1009                             (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) ||
1010                             (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) {
1011                                 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1012                                         BRGPHY_5708S_TX_MISC_PG5);
1013                                 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1,
1014                                         PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30);
1015                                 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1016                                         BRGPHY_5708S_DIG_PG0);
1017                         }
1018
1019                         /* Backplanes use special driver/pre-driver/pre-emphasis values. */
1020                         if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) &&
1021                                 (bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) {
1022                                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1023                                                 BRGPHY_5708S_TX_MISC_PG5);
1024                                         PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3,
1025                                                 bce_sc->bce_port_hw_cfg &
1026                                                 BCE_PORT_HW_CFG_CFG_TXCTL3_MASK);
1027                                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1028                                                 BRGPHY_5708S_DIG_PG0);
1029                         }
1030                 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 &&
1031                         (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
1032
1033                         /* Select the SerDes Digital block of the AN MMD. */
1034                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG);
1035                         val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1);
1036                         val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET;
1037                         val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER;
1038                         PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val);
1039
1040                         /* Select the Over 1G block of the AN MMD. */
1041                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G);
1042
1043                         /* Enable autoneg "Next Page" to advertise 2.5G support. */
1044                         val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1);
1045                         if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1046                                 val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
1047                         else
1048                                 val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
1049                         PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val);
1050
1051                         /* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */
1052                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE);
1053
1054                         /* Enable MRBE speed autoneg. */
1055                         val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP);
1056                         val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE |
1057                             BRGPHY_MRBE_MSG_PG5_NP_T2;
1058                         PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val);
1059
1060                         /* Select the Clause 73 User B0 block of the AN MMD. */
1061                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0);
1062
1063                         /* Enable MRBE speed autoneg. */
1064                         PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1,
1065                             BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP |
1066                             BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR |
1067                             BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG);
1068
1069                         /* Restore IEEE0 block (assumed in all brgphy(4) code). */
1070                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
1071         } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) {
1072                         if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) ||
1073                                 (BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx))
1074                                 brgphy_fixup_disable_early_dac(sc);
1075
1076                         brgphy_jumbo_settings(sc, ifp->if_mtu);
1077                         brgphy_ethernet_wirespeed(sc);
1078                 } else {
1079                         brgphy_fixup_ber_bug(sc);
1080                         brgphy_jumbo_settings(sc, ifp->if_mtu);
1081                         brgphy_ethernet_wirespeed(sc);
1082                 }
1083         }
1084 }