sys/dev/nxge/include/xgehal-ring.h

   1 /*-
   2  * Copyright (c) 2002-2007 Neterion, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  *
  26  * $FreeBSD$
  27  */
  28
  29 #ifndef XGE_HAL_RING_H
  30 #define XGE_HAL_RING_H
  31
  32 #include <dev/nxge/include/xgehal-channel.h>
  33 #include <dev/nxge/include/xgehal-config.h>
  34 #include <dev/nxge/include/xgehal-mm.h>
  35
  36 __EXTERN_BEGIN_DECLS
  37
  38 /* HW ring configuration */
  39 #define XGE_HAL_RING_RXDBLOCK_SIZE  0x1000
  40
  41 #define XGE_HAL_RXD_T_CODE_OK       0x0
  42 #define XGE_HAL_RXD_T_CODE_PARITY   0x1
  43 #define XGE_HAL_RXD_T_CODE_ABORT    0x2
  44 #define XGE_HAL_RXD_T_CODE_PARITY_ABORT 0x3
  45 #define XGE_HAL_RXD_T_CODE_RDA_FAILURE  0x4
  46 #define XGE_HAL_RXD_T_CODE_UNKNOWN_PROTO 0x5
  47 #define XGE_HAL_RXD_T_CODE_BAD_FCS  0x6
  48 #define XGE_HAL_RXD_T_CODE_BUFF_SIZE    0x7
  49 #define XGE_HAL_RXD_T_CODE_BAD_ECC  0x8
  50 #define XGE_HAL_RXD_T_CODE_UNUSED_C 0xC
  51 #define XGE_HAL_RXD_T_CODE_UNKNOWN  0xF
  52
  53 #define XGE_HAL_RING_USE_MTU        -1
  54
  55 /* control_1 and control_2 formatting - same for all buffer modes */
  56 #define XGE_HAL_RXD_GET_L3_CKSUM(control_1) ((u16)(control_1>>16) & 0xFFFF)
  57 #define XGE_HAL_RXD_GET_L4_CKSUM(control_1) ((u16)(control_1 & 0xFFFF))
  58
  59 #define XGE_HAL_RXD_MASK_VLAN_TAG       vBIT(0xFFFF,48,16)
  60 #define XGE_HAL_RXD_SET_VLAN_TAG(control_2, val) control_2 |= (u16)val
  61 #define XGE_HAL_RXD_GET_VLAN_TAG(control_2) ((u16)(control_2 & 0xFFFF))
  62
  63 #define XGE_HAL_RXD_POSTED_4_XFRAME     BIT(7)  /* control_1 */
  64 #define XGE_HAL_RXD_NOT_COMPLETED               BIT(0)  /* control_2 */
  65 #define XGE_HAL_RXD_T_CODE      (BIT(12)|BIT(13)|BIT(14)|BIT(15))
  66 #define XGE_HAL_RXD_GET_T_CODE(control_1)   \
  67                     ((control_1 & XGE_HAL_RXD_T_CODE)>>48)
  68 #define XGE_HAL_RXD_SET_T_CODE(control_1, val) \
  69                     (control_1 |= (((u64)val & 0xF) << 48))
  70
  71 #define XGE_HAL_RXD_MASK_FRAME_TYPE     vBIT(0x3,25,2)
  72 #define XGE_HAL_RXD_MASK_FRAME_PROTO        vBIT(0xFFFF,24,8)
  73 #define XGE_HAL_RXD_GET_FRAME_TYPE(control_1)   \
  74             (u8)(0x3 & ((control_1 & XGE_HAL_RXD_MASK_FRAME_TYPE) >> 37))
  75 #define XGE_HAL_RXD_GET_FRAME_PROTO(control_1)  \
  76                 (u8)((control_1 & XGE_HAL_RXD_MASK_FRAME_PROTO) >> 32)
  77 #define XGE_HAL_RXD_FRAME_PROTO_VLAN_TAGGED BIT(24)
  78 #define XGE_HAL_RXD_FRAME_PROTO_IPV4        BIT(27)
  79 #define XGE_HAL_RXD_FRAME_PROTO_IPV6        BIT(28)
  80 #define XGE_HAL_RXD_FRAME_PROTO_IP_FRAGMENTED   BIT(29)
  81 #define XGE_HAL_RXD_FRAME_PROTO_TCP     BIT(30)
  82 #define XGE_HAL_RXD_FRAME_PROTO_UDP     BIT(31)
  83 #define XGE_HAL_RXD_FRAME_TCP_OR_UDP (XGE_HAL_RXD_FRAME_PROTO_TCP | \
  84                     XGE_HAL_RXD_FRAME_PROTO_UDP)
  85
  86 /**
  87  * enum xge_hal_frame_type_e - Ethernet frame format.
  88  * @XGE_HAL_FRAME_TYPE_DIX: DIX (Ethernet II) format.
  89  * @XGE_HAL_FRAME_TYPE_LLC: LLC format.
  90  * @XGE_HAL_FRAME_TYPE_SNAP: SNAP format.
  91  * @XGE_HAL_FRAME_TYPE_IPX: IPX format.
  92  *
  93  * Ethernet frame format.
  94  */
  95 typedef enum xge_hal_frame_type_e {
  96         XGE_HAL_FRAME_TYPE_DIX          = 0x0,
  97         XGE_HAL_FRAME_TYPE_LLC          = 0x1,
  98         XGE_HAL_FRAME_TYPE_SNAP         = 0x2,
  99         XGE_HAL_FRAME_TYPE_IPX          = 0x3,
 100 } xge_hal_frame_type_e;
 101
 102 /**
 103  * enum xge_hal_frame_proto_e - Higher-layer ethernet protocols.
 104  * @XGE_HAL_FRAME_PROTO_VLAN_TAGGED: VLAN.
 105  * @XGE_HAL_FRAME_PROTO_IPV4: IPv4.
 106  * @XGE_HAL_FRAME_PROTO_IPV6: IPv6.
 107  * @XGE_HAL_FRAME_PROTO_IP_FRAGMENTED: IP fragmented.
 108  * @XGE_HAL_FRAME_PROTO_TCP: TCP.
 109  * @XGE_HAL_FRAME_PROTO_UDP: UDP.
 110  * @XGE_HAL_FRAME_PROTO_TCP_OR_UDP: TCP or UDP.
 111  *
 112  * Higher layer ethernet protocols and options.
 113  */
 114 typedef enum xge_hal_frame_proto_e {
 115         XGE_HAL_FRAME_PROTO_VLAN_TAGGED     = 0x80,
 116         XGE_HAL_FRAME_PROTO_IPV4        = 0x10,
 117         XGE_HAL_FRAME_PROTO_IPV6        = 0x08,
 118         XGE_HAL_FRAME_PROTO_IP_FRAGMENTED   = 0x04,
 119         XGE_HAL_FRAME_PROTO_TCP         = 0x02,
 120         XGE_HAL_FRAME_PROTO_UDP         = 0x01,
 121         XGE_HAL_FRAME_PROTO_TCP_OR_UDP      = (XGE_HAL_FRAME_PROTO_TCP | \
 122                                XGE_HAL_FRAME_PROTO_UDP)
 123 } xge_hal_frame_proto_e;
 124
 125 /*
 126  * xge_hal_ring_rxd_1_t
 127  */
 128 typedef struct {
 129         u64 host_control;
 130         u64 control_1;
 131         u64 control_2;
 132 #define XGE_HAL_RXD_1_MASK_BUFFER0_SIZE     vBIT(0xFFFF,0,16)
 133 #define XGE_HAL_RXD_1_SET_BUFFER0_SIZE(val) vBIT(val,0,16)
 134 #define XGE_HAL_RXD_1_GET_BUFFER0_SIZE(Control_2) \
 135                 (int)((Control_2 & vBIT(0xFFFF,0,16))>>48)
 136 #define XGE_HAL_RXD_1_GET_RTH_VALUE(Control_2) \
 137                 (u32)((Control_2 & vBIT(0xFFFFFFFF,16,32))>>16)
 138         u64 buffer0_ptr;
 139 } xge_hal_ring_rxd_1_t;
 140
 141 /*
 142  * xge_hal_ring_rxd_3_t
 143  */
 144 typedef struct {
 145         u64 host_control;
 146         u64 control_1;
 147
 148         u64 control_2;
 149 #define XGE_HAL_RXD_3_MASK_BUFFER0_SIZE     vBIT(0xFF,8,8)
 150 #define XGE_HAL_RXD_3_SET_BUFFER0_SIZE(val) vBIT(val,8,8)
 151 #define XGE_HAL_RXD_3_MASK_BUFFER1_SIZE     vBIT(0xFFFF,16,16)
 152 #define XGE_HAL_RXD_3_SET_BUFFER1_SIZE(val) vBIT(val,16,16)
 153 #define XGE_HAL_RXD_3_MASK_BUFFER2_SIZE     vBIT(0xFFFF,32,16)
 154 #define XGE_HAL_RXD_3_SET_BUFFER2_SIZE(val) vBIT(val,32,16)
 155
 156
 157 #define XGE_HAL_RXD_3_GET_BUFFER0_SIZE(Control_2) \
 158                     (int)((Control_2 & vBIT(0xFF,8,8))>>48)
 159 #define XGE_HAL_RXD_3_GET_BUFFER1_SIZE(Control_2) \
 160                     (int)((Control_2 & vBIT(0xFFFF,16,16))>>32)
 161 #define XGE_HAL_RXD_3_GET_BUFFER2_SIZE(Control_2) \
 162                     (int)((Control_2 & vBIT(0xFFFF,32,16))>>16)
 163
 164         u64 buffer0_ptr;
 165         u64 buffer1_ptr;
 166         u64 buffer2_ptr;
 167 } xge_hal_ring_rxd_3_t;
 168
 169 /*
 170  * xge_hal_ring_rxd_5_t
 171  */
 172 typedef struct {
 173 #ifdef XGE_OS_HOST_BIG_ENDIAN
 174         u32 host_control;
 175         u32 control_3;
 176 #else
 177         u32 control_3;
 178         u32 host_control;
 179 #endif
 180
 181
 182 #define XGE_HAL_RXD_5_MASK_BUFFER3_SIZE     vBIT(0xFFFF,32,16)
 183 #define XGE_HAL_RXD_5_SET_BUFFER3_SIZE(val) vBIT(val,32,16)
 184 #define XGE_HAL_RXD_5_MASK_BUFFER4_SIZE     vBIT(0xFFFF,48,16)
 185 #define XGE_HAL_RXD_5_SET_BUFFER4_SIZE(val) vBIT(val,48,16)
 186
 187 #define XGE_HAL_RXD_5_GET_BUFFER3_SIZE(Control_3) \
 188                     (int)((Control_3 & vBIT(0xFFFF,32,16))>>16)
 189 #define XGE_HAL_RXD_5_GET_BUFFER4_SIZE(Control_3) \
 190                     (int)((Control_3 & vBIT(0xFFFF,48,16)))
 191
 192         u64 control_1;
 193         u64 control_2;
 194
 195 #define XGE_HAL_RXD_5_MASK_BUFFER0_SIZE     vBIT(0xFFFF,0,16)
 196 #define XGE_HAL_RXD_5_SET_BUFFER0_SIZE(val) vBIT(val,0,16)
 197 #define XGE_HAL_RXD_5_MASK_BUFFER1_SIZE     vBIT(0xFFFF,16,16)
 198 #define XGE_HAL_RXD_5_SET_BUFFER1_SIZE(val) vBIT(val,16,16)
 199 #define XGE_HAL_RXD_5_MASK_BUFFER2_SIZE     vBIT(0xFFFF,32,16)
 200 #define XGE_HAL_RXD_5_SET_BUFFER2_SIZE(val) vBIT(val,32,16)
 201
 202
 203 #define XGE_HAL_RXD_5_GET_BUFFER0_SIZE(Control_2) \
 204                 (int)((Control_2 & vBIT(0xFFFF,0,16))>>48)
 205 #define XGE_HAL_RXD_5_GET_BUFFER1_SIZE(Control_2) \
 206                 (int)((Control_2 & vBIT(0xFFFF,16,16))>>32)
 207 #define XGE_HAL_RXD_5_GET_BUFFER2_SIZE(Control_2) \
 208                 (int)((Control_2 & vBIT(0xFFFF,32,16))>>16)
 209         u64 buffer0_ptr;
 210         u64 buffer1_ptr;
 211         u64 buffer2_ptr;
 212         u64 buffer3_ptr;
 213         u64 buffer4_ptr;
 214 } xge_hal_ring_rxd_5_t;
 215
 216 #define XGE_HAL_RXD_GET_RTH_SPDM_HIT(Control_1) \
 217             (u8)((Control_1 & BIT(18))>>45)
 218 #define XGE_HAL_RXD_GET_RTH_IT_HIT(Control_1) \
 219             (u8)((Control_1 & BIT(19))>>44)
 220 #define XGE_HAL_RXD_GET_RTH_HASH_TYPE(Control_1) \
 221             (u8)((Control_1 & vBIT(0xF,20,4))>>40)
 222
 223 #define XGE_HAL_RXD_HASH_TYPE_NONE              0x0
 224 #define XGE_HAL_RXD_HASH_TYPE_TCP_IPV4          0x1
 225 #define XGE_HAL_RXD_HASH_TYPE_UDP_IPV4          0x2
 226 #define XGE_HAL_RXD_HASH_TYPE_IPV4              0x3
 227 #define XGE_HAL_RXD_HASH_TYPE_TCP_IPV6          0x4
 228 #define XGE_HAL_RXD_HASH_TYPE_UDP_IPV6          0x5
 229 #define XGE_HAL_RXD_HASH_TYPE_IPV6              0x6
 230 #define XGE_HAL_RXD_HASH_TYPE_TCP_IPV6_EX       0x7
 231 #define XGE_HAL_RXD_HASH_TYPE_UDP_IPV6_EX       0x8
 232 #define XGE_HAL_RXD_HASH_TYPE_IPV6_EX           0x9
 233
 234 typedef u8 xge_hal_ring_block_t[XGE_HAL_RING_RXDBLOCK_SIZE];
 235
 236 #define XGE_HAL_RING_NEXT_BLOCK_POINTER_OFFSET  0xFF8
 237 #define XGE_HAL_RING_MEMBLOCK_IDX_OFFSET    0xFF0
 238
 239 #define XGE_HAL_RING_RXD_SIZEOF(n) \
 240         (n==1 ? sizeof(xge_hal_ring_rxd_1_t) : \
 241             (n==3 ? sizeof(xge_hal_ring_rxd_3_t) : \
 242                 sizeof(xge_hal_ring_rxd_5_t)))
 243
 244 #define XGE_HAL_RING_RXDS_PER_BLOCK(n) \
 245         (n==1 ? 127 : (n==3 ? 85 : 63))
 246
 247 /**
 248  * struct xge_hal_ring_rxd_priv_t - Receive descriptor HAL-private data.
 249  * @dma_addr: DMA (mapped) address of _this_ descriptor.
 250  * @dma_handle: DMA handle used to map the descriptor onto device.
 251  * @dma_offset: Descriptor's offset in the memory block. HAL allocates
 252  *              descriptors in memory blocks of
 253  *              %XGE_HAL_RING_RXDBLOCK_SIZE
 254  *              bytes. Each memblock is contiguous DMA-able memory. Each
 255  *              memblock contains 1 or more 4KB RxD blocks visible to the
 256  *              Xframe hardware.
 257  * @dma_object: DMA address and handle of the memory block that contains
 258  *              the descriptor. This member is used only in the "checked"
 259  *              version of the HAL (to enforce certain assertions);
 260  *              otherwise it gets compiled out.
 261  * @allocated: True if the descriptor is reserved, 0 otherwise. Internal usage.
 262  *
 263  * Per-receive decsriptor HAL-private data. HAL uses the space to keep DMA
 264  * information associated with the descriptor. Note that ULD can ask HAL
 265  * to allocate additional per-descriptor space for its own (ULD-specific)
 266  * purposes.
 267  */
 268 typedef struct xge_hal_ring_rxd_priv_t {
 269         dma_addr_t      dma_addr;
 270         pci_dma_h       dma_handle;
 271         ptrdiff_t       dma_offset;
 272 #ifdef XGE_DEBUG_ASSERT
 273         xge_hal_mempool_dma_t   *dma_object;
 274 #endif
 275 #ifdef XGE_OS_MEMORY_CHECK
 276         int         allocated;
 277 #endif
 278 } xge_hal_ring_rxd_priv_t;
 279
 280 /**
 281  * struct xge_hal_ring_t - Ring channel.
 282  * @channel: Channel "base" of this ring, the common part of all HAL
 283  *           channels.
 284  * @buffer_mode: 1, 3, or 5. The value specifies a receive buffer mode,
 285  *          as per Xframe User Guide.
 286  * @indicate_max_pkts: Maximum number of packets processed within a single
 287  *          interrupt. Can be used to limit the time spent inside hw
 288  *          interrupt.
 289  * @config: Ring configuration, part of device configuration
 290  *          (see xge_hal_device_config_t{}).
 291  * @rxd_size: RxD sizes for 1-, 3- or 5- buffer modes. As per Xframe spec,
 292  *            1-buffer mode descriptor is 32 byte long, etc.
 293  * @rxd_priv_size: Per RxD size reserved (by HAL) for ULD to keep per-descriptor
 294  *                 data (e.g., DMA handle for Solaris)
 295  * @rxds_per_block: Number of descriptors per hardware-defined RxD
 296  *                  block. Depends on the (1-,3-,5-) buffer mode.
 297  * @mempool: Memory pool, the pool from which descriptors get allocated.
 298  *           (See xge_hal_mm.h).
 299  * @rxdblock_priv_size: Reserved at the end of each RxD block. HAL internal
 300  *                      usage. Not to confuse with @rxd_priv_size.
 301  * @reserved_rxds_arr: Array of RxD pointers. At any point in time each
 302  *                     entry in this array is available for allocation
 303  *                     (via xge_hal_ring_dtr_reserve()) and posting.
 304  * @cmpl_cnt: Completion counter. Is reset to zero upon entering the ISR.
 305  *            Used in conjunction with @indicate_max_pkts.
 306  * Ring channel.
 307  *
 308  * Note: The structure is cache line aligned to better utilize
 309  *       CPU cache performance.
 310  */
 311 typedef struct xge_hal_ring_t {
 312         xge_hal_channel_t       channel;
 313         int             buffer_mode;
 314         int             indicate_max_pkts;
 315         xge_hal_ring_config_t       *config;
 316         int             rxd_size;
 317         int             rxd_priv_size;
 318         int             rxds_per_block;
 319         xge_hal_mempool_t       *mempool;
 320         int             rxdblock_priv_size;
 321         void                **reserved_rxds_arr;
 322         int             cmpl_cnt;
 323 } __xge_os_attr_cacheline_aligned xge_hal_ring_t;
 324
 325 /**
 326  * struct xge_hal_dtr_info_t - Extended information associated with a
 327  * completed ring descriptor.
 328  * @l3_cksum: Result of IP checksum check (by Xframe hardware).
 329  *            This field containing XGE_HAL_L3_CKSUM_OK would mean that
 330  *            the checksum is correct, otherwise - the datagram is
 331  *            corrupted.
 332  * @l4_cksum: Result of TCP/UDP checksum check (by Xframe hardware).
 333  *            This field containing XGE_HAL_L4_CKSUM_OK would mean that
 334  *            the checksum is correct. Otherwise - the packet is
 335  *            corrupted.
 336  * @frame: See xge_hal_frame_type_e{}.
 337  * @proto:    Reporting bits for various higher-layer protocols, including (but
 338  *        note restricted to) TCP and UDP. See xge_hal_frame_proto_e{}.
 339  * @vlan:     VLAN tag extracted from the received frame.
 340  * @rth_value: Receive Traffic Hashing(RTH) hash value. Produced by Xframe II
 341  *             hardware if RTH is enabled.
 342  * @rth_it_hit: Set, If RTH hash value calculated by the Xframe II hardware
 343  *             has a matching entry in the Indirection table.
 344  * @rth_spdm_hit: Set, If RTH hash value calculated by the Xframe II hardware
 345  *             has a matching entry in the Socket Pair Direct Match table.
 346  * @rth_hash_type: RTH hash code of the function used to calculate the hash.
 347  * @reserved_pad: Unused byte.
 348  */
 349 typedef struct xge_hal_dtr_info_t {
 350         int l3_cksum;
 351         int l4_cksum;
 352         int frame; /* zero or more of xge_hal_frame_type_e flags */
 353         int proto; /* zero or more of xge_hal_frame_proto_e flags */
 354         int vlan;
 355         u32 rth_value;
 356         u8  rth_it_hit;
 357         u8  rth_spdm_hit;
 358         u8  rth_hash_type;
 359         u8  reserved_pad;
 360 } xge_hal_dtr_info_t;
 361
 362 /* ========================== RING PRIVATE API ============================ */
 363
 364 xge_hal_status_e __hal_ring_open(xge_hal_channel_h channelh,
 365                 xge_hal_channel_attr_t  *attr);
 366
 367 void __hal_ring_close(xge_hal_channel_h channelh);
 368
 369 void __hal_ring_hw_initialize(xge_hal_device_h devh);
 370
 371 void __hal_ring_mtu_set(xge_hal_device_h devh, int new_mtu);
 372
 373 void __hal_ring_prc_enable(xge_hal_channel_h channelh);
 374
 375 void __hal_ring_prc_disable(xge_hal_channel_h channelh);
 376
 377 xge_hal_status_e __hal_ring_initial_replenish(xge_hal_channel_t *channel,
 378                               xge_hal_channel_reopen_e reopen);
 379
 380 #if defined(XGE_DEBUG_FP) && (XGE_DEBUG_FP & XGE_DEBUG_FP_RING)
 381 #define __HAL_STATIC_RING
 382 #define __HAL_INLINE_RING
 383
 384 __HAL_STATIC_RING __HAL_INLINE_RING int
 385 __hal_ring_block_memblock_idx(xge_hal_ring_block_t *block);
 386
 387 __HAL_STATIC_RING __HAL_INLINE_RING void
 388 __hal_ring_block_memblock_idx_set(xge_hal_ring_block_t*block, int memblock_idx);
 389
 390 __HAL_STATIC_RING __HAL_INLINE_RING dma_addr_t
 391 __hal_ring_block_next_pointer(xge_hal_ring_block_t *block);
 392
 393 __HAL_STATIC_RING __HAL_INLINE_RING void
 394 __hal_ring_block_next_pointer_set(xge_hal_ring_block_t*block,
 395                 dma_addr_t dma_next);
 396
 397 __HAL_STATIC_RING __HAL_INLINE_RING xge_hal_ring_rxd_priv_t*
 398 __hal_ring_rxd_priv(xge_hal_ring_t *ring, xge_hal_dtr_h dtrh);
 399
 400 /* =========================== RING PUBLIC API ============================ */
 401
 402 __HAL_STATIC_RING __HAL_INLINE_RING xge_hal_status_e
 403 xge_hal_ring_dtr_reserve(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh);
 404
 405 __HAL_STATIC_RING __HAL_INLINE_RING void*
 406 xge_hal_ring_dtr_private(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
 407
 408 __HAL_STATIC_RING __HAL_INLINE_RING void
 409 xge_hal_ring_dtr_1b_set(xge_hal_dtr_h dtrh, dma_addr_t dma_pointer, int size);
 410
 411 __HAL_STATIC_RING __HAL_INLINE_RING void
 412 xge_hal_ring_dtr_info_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
 413                 xge_hal_dtr_info_t *ext_info);
 414
 415 __HAL_STATIC_RING __HAL_INLINE_RING void
 416 xge_hal_ring_dtr_1b_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
 417                 dma_addr_t *dma_pointer, int *pkt_length);
 418
 419 __HAL_STATIC_RING __HAL_INLINE_RING void
 420 xge_hal_ring_dtr_3b_set(xge_hal_dtr_h dtrh, dma_addr_t dma_pointers[],
 421                 int sizes[]);
 422
 423 __HAL_STATIC_RING __HAL_INLINE_RING void
 424 xge_hal_ring_dtr_3b_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
 425                 dma_addr_t dma_pointers[], int sizes[]);
 426
 427 __HAL_STATIC_RING __HAL_INLINE_RING void
 428 xge_hal_ring_dtr_5b_set(xge_hal_dtr_h dtrh, dma_addr_t dma_pointers[],
 429                 int sizes[]);
 430
 431 __HAL_STATIC_RING __HAL_INLINE_RING void
 432 xge_hal_ring_dtr_5b_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
 433                 dma_addr_t dma_pointer[], int sizes[]);
 434
 435 __HAL_STATIC_RING __HAL_INLINE_RING void
 436 xge_hal_ring_dtr_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
 437
 438 __HAL_STATIC_RING __HAL_INLINE_RING void
 439 xge_hal_ring_dtr_pre_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
 440
 441 __HAL_STATIC_RING __HAL_INLINE_RING void
 442 xge_hal_ring_dtr_post_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
 443
 444 __HAL_STATIC_RING __HAL_INLINE_RING void
 445 xge_hal_ring_dtr_post_post_wmb(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
 446
 447 __HAL_STATIC_RING __HAL_INLINE_RING xge_hal_status_e
 448 xge_hal_ring_dtr_next_completed(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh,
 449                 u8 *t_code);
 450
 451 __HAL_STATIC_RING __HAL_INLINE_RING void
 452 xge_hal_ring_dtr_free(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
 453
 454 __HAL_STATIC_RING __HAL_INLINE_RING xge_hal_status_e
 455 xge_hal_ring_is_next_dtr_completed(xge_hal_channel_h channelh);
 456
 457 #else /* XGE_FASTPATH_EXTERN */
 458 #define __HAL_STATIC_RING static
 459 #define __HAL_INLINE_RING inline
 460 #include <dev/nxge/xgehal/xgehal-ring-fp.c>
 461 #endif /* XGE_FASTPATH_INLINE */
 462
 463 __EXTERN_END_DECLS
 464
 465 #endif /* XGE_HAL_RING_H */