sys/dev/nxge/xgehal/xgehal-config.c

   1 /*-
   2  * Copyright (c) 2002-2007 Neterion, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  *
  26  * $FreeBSD$
  27  */
  28
  29 #include <dev/nxge/include/xgehal-config.h>
  30 #include <dev/nxge/include/xge-debug.h>
  31
  32 /*
  33  * __hal_tti_config_check - Check tti configuration
  34  * @new_config: tti configuration information
  35  *
  36  * Returns: XGE_HAL_OK - success,
  37  * otherwise one of the xge_hal_status_e{} enumerated error codes.
  38  */
  39 static xge_hal_status_e
  40 __hal_tti_config_check (xge_hal_tti_config_t *new_config)
  41 {
  42         if ((new_config->urange_a < XGE_HAL_MIN_TX_URANGE_A) ||
  43             (new_config->urange_a > XGE_HAL_MAX_TX_URANGE_A)) {
  44             return XGE_HAL_BADCFG_TX_URANGE_A;
  45         }
  46
  47         if ((new_config->ufc_a < XGE_HAL_MIN_TX_UFC_A) ||
  48             (new_config->ufc_a > XGE_HAL_MAX_TX_UFC_A)) {
  49             return XGE_HAL_BADCFG_TX_UFC_A;
  50         }
  51
  52         if ((new_config->urange_b < XGE_HAL_MIN_TX_URANGE_B) ||
  53             (new_config->urange_b > XGE_HAL_MAX_TX_URANGE_B)) {
  54             return XGE_HAL_BADCFG_TX_URANGE_B;
  55         }
  56
  57         if ((new_config->ufc_b < XGE_HAL_MIN_TX_UFC_B) ||
  58             (new_config->ufc_b > XGE_HAL_MAX_TX_UFC_B)) {
  59             return XGE_HAL_BADCFG_TX_UFC_B;
  60         }
  61
  62         if ((new_config->urange_c < XGE_HAL_MIN_TX_URANGE_C) ||
  63             (new_config->urange_c > XGE_HAL_MAX_TX_URANGE_C)) {
  64             return XGE_HAL_BADCFG_TX_URANGE_C;
  65         }
  66
  67         if ((new_config->ufc_c < XGE_HAL_MIN_TX_UFC_C) ||
  68             (new_config->ufc_c > XGE_HAL_MAX_TX_UFC_C)) {
  69             return XGE_HAL_BADCFG_TX_UFC_C;
  70         }
  71
  72         if ((new_config->ufc_d < XGE_HAL_MIN_TX_UFC_D) ||
  73             (new_config->ufc_d > XGE_HAL_MAX_TX_UFC_D)) {
  74             return XGE_HAL_BADCFG_TX_UFC_D;
  75         }
  76
  77         if ((new_config->timer_val_us < XGE_HAL_MIN_TX_TIMER_VAL) ||
  78             (new_config->timer_val_us > XGE_HAL_MAX_TX_TIMER_VAL)) {
  79             return XGE_HAL_BADCFG_TX_TIMER_VAL;
  80         }
  81
  82         if ((new_config->timer_ci_en < XGE_HAL_MIN_TX_TIMER_CI_EN) ||
  83             (new_config->timer_ci_en > XGE_HAL_MAX_TX_TIMER_CI_EN)) {
  84             return XGE_HAL_BADCFG_TX_TIMER_CI_EN;
  85         }
  86
  87         if ((new_config->timer_ac_en < XGE_HAL_MIN_TX_TIMER_AC_EN) ||
  88             (new_config->timer_ac_en > XGE_HAL_MAX_TX_TIMER_AC_EN)) {
  89             return XGE_HAL_BADCFG_TX_TIMER_AC_EN;
  90         }
  91
  92         return XGE_HAL_OK;
  93 }
  94
  95 /*
  96  * __hal_rti_config_check - Check rti configuration
  97  * @new_config: rti configuration information
  98  *
  99  * Returns: XGE_HAL_OK - success,
 100  * otherwise one of the xge_hal_status_e{} enumerated error codes.
 101  */
 102 static xge_hal_status_e
 103 __hal_rti_config_check (xge_hal_rti_config_t *new_config)
 104 {
 105         if ((new_config->urange_a < XGE_HAL_MIN_RX_URANGE_A) ||
 106             (new_config->urange_a > XGE_HAL_MAX_RX_URANGE_A)) {
 107             return XGE_HAL_BADCFG_RX_URANGE_A;
 108         }
 109
 110         if ((new_config->ufc_a < XGE_HAL_MIN_RX_UFC_A) ||
 111             (new_config->ufc_a > XGE_HAL_MAX_RX_UFC_A)) {
 112             return XGE_HAL_BADCFG_RX_UFC_A;
 113         }
 114
 115         if ((new_config->urange_b < XGE_HAL_MIN_RX_URANGE_B) ||
 116             (new_config->urange_b > XGE_HAL_MAX_RX_URANGE_B)) {
 117             return XGE_HAL_BADCFG_RX_URANGE_B;
 118         }
 119
 120         if ((new_config->ufc_b < XGE_HAL_MIN_RX_UFC_B) ||
 121             (new_config->ufc_b > XGE_HAL_MAX_RX_UFC_B)) {
 122             return XGE_HAL_BADCFG_RX_UFC_B;
 123         }
 124
 125         if ((new_config->urange_c < XGE_HAL_MIN_RX_URANGE_C) ||
 126             (new_config->urange_c > XGE_HAL_MAX_RX_URANGE_C)) {
 127             return XGE_HAL_BADCFG_RX_URANGE_C;
 128         }
 129
 130         if ((new_config->ufc_c < XGE_HAL_MIN_RX_UFC_C) ||
 131             (new_config->ufc_c > XGE_HAL_MAX_RX_UFC_C)) {
 132             return XGE_HAL_BADCFG_RX_UFC_C;
 133         }
 134
 135         if ((new_config->ufc_d < XGE_HAL_MIN_RX_UFC_D) ||
 136             (new_config->ufc_d > XGE_HAL_MAX_RX_UFC_D)) {
 137             return XGE_HAL_BADCFG_RX_UFC_D;
 138         }
 139
 140         if ((new_config->timer_val_us < XGE_HAL_MIN_RX_TIMER_VAL) ||
 141             (new_config->timer_val_us > XGE_HAL_MAX_RX_TIMER_VAL)) {
 142             return XGE_HAL_BADCFG_RX_TIMER_VAL;
 143         }
 144
 145         if ((new_config->timer_ac_en < XGE_HAL_MIN_RX_TIMER_AC_EN) ||
 146             (new_config->timer_ac_en > XGE_HAL_MAX_RX_TIMER_AC_EN)) {
 147             return XGE_HAL_BADCFG_RX_TIMER_AC_EN;
 148         }
 149
 150         return XGE_HAL_OK;
 151 }
 152
 153
 154 /*
 155  * __hal_fifo_queue_check - Check fifo queue configuration
 156  * @new_config: fifo queue configuration information
 157  *
 158  * Returns: XGE_HAL_OK - success,
 159  * otherwise one of the xge_hal_status_e{} enumerated error codes.
 160  */
 161 static xge_hal_status_e
 162 __hal_fifo_queue_check (xge_hal_fifo_config_t *new_config,
 163                 xge_hal_fifo_queue_t *new_queue)
 164 {
 165         int i;
 166
 167         if ((new_queue->initial < XGE_HAL_MIN_FIFO_QUEUE_LENGTH) ||
 168             (new_queue->initial > XGE_HAL_MAX_FIFO_QUEUE_LENGTH)) {
 169             return XGE_HAL_BADCFG_FIFO_QUEUE_INITIAL_LENGTH;
 170         }
 171
 172         /* FIXME: queue "grow" feature is not supported.
 173          *        Use "initial" queue size as the "maximum";
 174          *        Remove the next line when fixed. */
 175         new_queue->max = new_queue->initial;
 176
 177         if ((new_queue->max < XGE_HAL_MIN_FIFO_QUEUE_LENGTH) ||
 178             (new_queue->max > XGE_HAL_MAX_FIFO_QUEUE_LENGTH)) {
 179             return XGE_HAL_BADCFG_FIFO_QUEUE_MAX_LENGTH;
 180         }
 181
 182         if (new_queue->max < new_config->reserve_threshold) {
 183             return XGE_HAL_BADCFG_FIFO_RESERVE_THRESHOLD;
 184         }
 185
 186         if ((new_queue->intr < XGE_HAL_MIN_FIFO_QUEUE_INTR) ||
 187             (new_queue->intr > XGE_HAL_MAX_FIFO_QUEUE_INTR)) {
 188             return XGE_HAL_BADCFG_FIFO_QUEUE_INTR;
 189         }
 190
 191         if ((new_queue->intr_vector < XGE_HAL_MIN_FIFO_QUEUE_INTR_VECTOR) ||
 192             (new_queue->intr_vector > XGE_HAL_MAX_FIFO_QUEUE_INTR_VECTOR)) {
 193             return XGE_HAL_BADCFG_FIFO_QUEUE_INTR_VECTOR;
 194         }
 195
 196         for(i = 0;  i < XGE_HAL_MAX_FIFO_TTI_NUM; i++) {
 197             /*
 198              * Validate the tti configuration parameters only if
 199              * the TTI feature is enabled.
 200              */
 201             if (new_queue->tti[i].enabled) {
 202                 xge_hal_status_e status;
 203
 204                 if ((status = __hal_tti_config_check(
 205                          &new_queue->tti[i])) != XGE_HAL_OK) {
 206                     return status;
 207                 }
 208             }
 209         }
 210
 211         return XGE_HAL_OK;
 212 }
 213
 214 /*
 215  * __hal_ring_queue_check - Check ring queue configuration
 216  * @new_config: ring queue configuration information
 217  *
 218  * Returns: XGE_HAL_OK - success,
 219  * otherwise one of the xge_hal_status_e{} enumerated error codes.
 220  */
 221 static xge_hal_status_e
 222 __hal_ring_queue_check (xge_hal_ring_queue_t *new_config)
 223 {
 224
 225         if ((new_config->initial < XGE_HAL_MIN_RING_QUEUE_BLOCKS) ||
 226             (new_config->initial > XGE_HAL_MAX_RING_QUEUE_BLOCKS)) {
 227             return XGE_HAL_BADCFG_RING_QUEUE_INITIAL_BLOCKS;
 228         }
 229
 230         /* FIXME: queue "grow" feature is not supported.
 231          *        Use "initial" queue size as the "maximum";
 232          *        Remove the next line when fixed. */
 233         new_config->max = new_config->initial;
 234
 235         if ((new_config->max < XGE_HAL_MIN_RING_QUEUE_BLOCKS) ||
 236             (new_config->max > XGE_HAL_MAX_RING_QUEUE_BLOCKS)) {
 237             return XGE_HAL_BADCFG_RING_QUEUE_MAX_BLOCKS;
 238         }
 239
 240         if ((new_config->buffer_mode != XGE_HAL_RING_QUEUE_BUFFER_MODE_1) &&
 241             (new_config->buffer_mode != XGE_HAL_RING_QUEUE_BUFFER_MODE_3) &&
 242             (new_config->buffer_mode != XGE_HAL_RING_QUEUE_BUFFER_MODE_5)) {
 243             return XGE_HAL_BADCFG_RING_QUEUE_BUFFER_MODE;
 244         }
 245
 246             /*
 247          * Herc has less DRAM; the check is done later inside
 248          * device_initialize()
 249          */
 250         if (((new_config->dram_size_mb < XGE_HAL_MIN_RING_QUEUE_SIZE) ||
 251              (new_config->dram_size_mb > XGE_HAL_MAX_RING_QUEUE_SIZE_XENA)) &&
 252               new_config->dram_size_mb != XGE_HAL_DEFAULT_USE_HARDCODE)
 253             return XGE_HAL_BADCFG_RING_QUEUE_SIZE;
 254
 255         if ((new_config->backoff_interval_us <
 256                 XGE_HAL_MIN_BACKOFF_INTERVAL_US) ||
 257             (new_config->backoff_interval_us >
 258                 XGE_HAL_MAX_BACKOFF_INTERVAL_US)) {
 259             return XGE_HAL_BADCFG_BACKOFF_INTERVAL_US;
 260         }
 261
 262         if ((new_config->max_frm_len < XGE_HAL_MIN_MAX_FRM_LEN) ||
 263             (new_config->max_frm_len > XGE_HAL_MAX_MAX_FRM_LEN)) {
 264             return XGE_HAL_BADCFG_MAX_FRM_LEN;
 265         }
 266
 267         if ((new_config->priority < XGE_HAL_MIN_RING_PRIORITY) ||
 268             (new_config->priority > XGE_HAL_MAX_RING_PRIORITY)) {
 269             return XGE_HAL_BADCFG_RING_PRIORITY;
 270         }
 271
 272         if ((new_config->rth_en < XGE_HAL_MIN_RING_RTH_EN) ||
 273             (new_config->rth_en > XGE_HAL_MAX_RING_RTH_EN)) {
 274             return XGE_HAL_BADCFG_RING_RTH_EN;
 275         }
 276
 277         if ((new_config->rts_mac_en < XGE_HAL_MIN_RING_RTS_MAC_EN) ||
 278             (new_config->rts_mac_en > XGE_HAL_MAX_RING_RTS_MAC_EN)) {
 279             return XGE_HAL_BADCFG_RING_RTS_MAC_EN;
 280         }
 281
 282         if ((new_config->rts_mac_en < XGE_HAL_MIN_RING_RTS_PORT_EN) ||
 283             (new_config->rts_mac_en > XGE_HAL_MAX_RING_RTS_PORT_EN)) {
 284             return XGE_HAL_BADCFG_RING_RTS_PORT_EN;
 285         }
 286
 287         if ((new_config->intr_vector < XGE_HAL_MIN_RING_QUEUE_INTR_VECTOR) ||
 288             (new_config->intr_vector > XGE_HAL_MAX_RING_QUEUE_INTR_VECTOR)) {
 289             return XGE_HAL_BADCFG_RING_QUEUE_INTR_VECTOR;
 290         }
 291
 292         if (new_config->indicate_max_pkts <
 293         XGE_HAL_MIN_RING_INDICATE_MAX_PKTS ||
 294             new_config->indicate_max_pkts >
 295             XGE_HAL_MAX_RING_INDICATE_MAX_PKTS) {
 296             return XGE_HAL_BADCFG_RING_INDICATE_MAX_PKTS;
 297         }
 298
 299         return __hal_rti_config_check(&new_config->rti);
 300 }
 301
 302 /*
 303  * __hal_mac_config_check - Check mac configuration
 304  * @new_config: mac configuration information
 305  *
 306  * Returns: XGE_HAL_OK - success,
 307  * otherwise one of the xge_hal_status_e{} enumerated error codes.
 308  */
 309 static xge_hal_status_e
 310 __hal_mac_config_check (xge_hal_mac_config_t *new_config)
 311 {
 312         if ((new_config->tmac_util_period < XGE_HAL_MIN_TMAC_UTIL_PERIOD) ||
 313             (new_config->tmac_util_period > XGE_HAL_MAX_TMAC_UTIL_PERIOD)) {
 314             return XGE_HAL_BADCFG_TMAC_UTIL_PERIOD;
 315         }
 316
 317         if ((new_config->rmac_util_period < XGE_HAL_MIN_RMAC_UTIL_PERIOD) ||
 318             (new_config->rmac_util_period > XGE_HAL_MAX_RMAC_UTIL_PERIOD)) {
 319             return XGE_HAL_BADCFG_RMAC_UTIL_PERIOD;
 320         }
 321
 322         if ((new_config->rmac_bcast_en < XGE_HAL_MIN_RMAC_BCAST_EN) ||
 323             (new_config->rmac_bcast_en > XGE_HAL_MAX_RMAC_BCAST_EN)) {
 324             return XGE_HAL_BADCFG_RMAC_BCAST_EN;
 325         }
 326
 327         if ((new_config->rmac_pause_gen_en < XGE_HAL_MIN_RMAC_PAUSE_GEN_EN) ||
 328             (new_config->rmac_pause_gen_en>XGE_HAL_MAX_RMAC_PAUSE_GEN_EN)) {
 329             return XGE_HAL_BADCFG_RMAC_PAUSE_GEN_EN;
 330         }
 331
 332         if ((new_config->rmac_pause_rcv_en < XGE_HAL_MIN_RMAC_PAUSE_RCV_EN) ||
 333             (new_config->rmac_pause_rcv_en>XGE_HAL_MAX_RMAC_PAUSE_RCV_EN)) {
 334             return XGE_HAL_BADCFG_RMAC_PAUSE_RCV_EN;
 335         }
 336
 337         if ((new_config->rmac_pause_time < XGE_HAL_MIN_RMAC_HIGH_PTIME) ||
 338             (new_config->rmac_pause_time > XGE_HAL_MAX_RMAC_HIGH_PTIME)) {
 339             return XGE_HAL_BADCFG_RMAC_HIGH_PTIME;
 340         }
 341
 342         if ((new_config->media < XGE_HAL_MIN_MEDIA) ||
 343             (new_config->media > XGE_HAL_MAX_MEDIA)) {
 344             return XGE_HAL_BADCFG_MEDIA;
 345         }
 346
 347         if ((new_config->mc_pause_threshold_q0q3 <
 348                 XGE_HAL_MIN_MC_PAUSE_THRESHOLD_Q0Q3) ||
 349             (new_config->mc_pause_threshold_q0q3 >
 350                 XGE_HAL_MAX_MC_PAUSE_THRESHOLD_Q0Q3)) {
 351             return XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q0Q3;
 352         }
 353
 354         if ((new_config->mc_pause_threshold_q4q7 <
 355                 XGE_HAL_MIN_MC_PAUSE_THRESHOLD_Q4Q7) ||
 356             (new_config->mc_pause_threshold_q4q7 >
 357                 XGE_HAL_MAX_MC_PAUSE_THRESHOLD_Q4Q7)) {
 358             return XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q4Q7;
 359         }
 360
 361         return XGE_HAL_OK;
 362 }
 363
 364 /*
 365  * __hal_fifo_config_check - Check fifo configuration
 366  * @new_config: fifo configuration information
 367  *
 368  * Returns: XGE_HAL_OK - success,
 369  * otherwise one of the xge_hal_status_e{} enumerated error codes.
 370  */
 371 static xge_hal_status_e
 372 __hal_fifo_config_check (xge_hal_fifo_config_t *new_config)
 373 {
 374         int i;
 375         int total_fifo_length = 0;
 376
 377         /*
 378          * recompute max_frags to be multiple of 4,
 379          * which means, multiple of 128 for TxDL
 380          */
 381         new_config->max_frags = ((new_config->max_frags + 3) >> 2) << 2;
 382
 383         if ((new_config->max_frags < XGE_HAL_MIN_FIFO_FRAGS) ||
 384             (new_config->max_frags > XGE_HAL_MAX_FIFO_FRAGS))  {
 385             return XGE_HAL_BADCFG_FIFO_FRAGS;
 386         }
 387
 388         if ((new_config->reserve_threshold <
 389                 XGE_HAL_MIN_FIFO_RESERVE_THRESHOLD) ||
 390             (new_config->reserve_threshold >
 391                 XGE_HAL_MAX_FIFO_RESERVE_THRESHOLD)) {
 392             return XGE_HAL_BADCFG_FIFO_RESERVE_THRESHOLD;
 393         }
 394
 395         if ((new_config->memblock_size < XGE_HAL_MIN_FIFO_MEMBLOCK_SIZE) ||
 396             (new_config->memblock_size > XGE_HAL_MAX_FIFO_MEMBLOCK_SIZE)) {
 397             return XGE_HAL_BADCFG_FIFO_MEMBLOCK_SIZE;
 398         }
 399
 400         for(i = 0;  i < XGE_HAL_MAX_FIFO_NUM; i++) {
 401             xge_hal_status_e status;
 402
 403             if (!new_config->queue[i].configured)
 404                             continue;
 405
 406             if ((status = __hal_fifo_queue_check(new_config,
 407                          &new_config->queue[i])) != XGE_HAL_OK) {
 408                 return status;
 409             }
 410
 411                 total_fifo_length += new_config->queue[i].max;
 412         }
 413
 414         if(total_fifo_length > XGE_HAL_MAX_FIFO_QUEUE_LENGTH){
 415             return XGE_HAL_BADCFG_FIFO_QUEUE_MAX_LENGTH;
 416         }
 417
 418         return XGE_HAL_OK;
 419 }
 420
 421 /*
 422  * __hal_ring_config_check - Check ring configuration
 423  * @new_config: Ring configuration information
 424  *
 425  * Returns: XGE_HAL_OK - success,
 426  * otherwise one of the xge_hal_status_e{} enumerated error codes.
 427  */
 428 static xge_hal_status_e
 429 __hal_ring_config_check (xge_hal_ring_config_t *new_config)
 430 {
 431         int i;
 432
 433         if ((new_config->memblock_size < XGE_HAL_MIN_RING_MEMBLOCK_SIZE) ||
 434             (new_config->memblock_size > XGE_HAL_MAX_RING_MEMBLOCK_SIZE)) {
 435             return XGE_HAL_BADCFG_RING_MEMBLOCK_SIZE;
 436         }
 437
 438         for(i = 0;  i < XGE_HAL_MAX_RING_NUM; i++) {
 439             xge_hal_status_e status;
 440
 441             if (!new_config->queue[i].configured)
 442                             continue;
 443
 444             if ((status = __hal_ring_queue_check(&new_config->queue[i]))
 445                         != XGE_HAL_OK) {
 446                 return status;
 447             }
 448         }
 449
 450         return XGE_HAL_OK;
 451 }
 452
 453
 454 /*
 455  * __hal_device_config_check_common - Check device configuration.
 456  * @new_config: Device configuration information
 457  *
 458  * Check part of configuration that is common to
 459  * Xframe-I and Xframe-II.
 460  *
 461  * Returns: XGE_HAL_OK - success,
 462  * otherwise one of the xge_hal_status_e{} enumerated error codes.
 463  *
 464  * See also: __hal_device_config_check_xena().
 465  */
 466 xge_hal_status_e
 467 __hal_device_config_check_common (xge_hal_device_config_t *new_config)
 468 {
 469         xge_hal_status_e status;
 470
 471         if ((new_config->mtu < XGE_HAL_MIN_MTU) ||
 472             (new_config->mtu > XGE_HAL_MAX_MTU)) {
 473             return XGE_HAL_BADCFG_MAX_MTU;
 474         }
 475
 476         if ((new_config->bimodal_interrupts < XGE_HAL_BIMODAL_INTR_MIN) ||
 477             (new_config->bimodal_interrupts > XGE_HAL_BIMODAL_INTR_MAX)) {
 478             return XGE_HAL_BADCFG_BIMODAL_INTR;
 479         }
 480
 481         if (new_config->bimodal_interrupts &&
 482             ((new_config->bimodal_timer_lo_us < XGE_HAL_BIMODAL_TIMER_LO_US_MIN) ||
 483             (new_config->bimodal_timer_lo_us > XGE_HAL_BIMODAL_TIMER_LO_US_MAX))) {
 484             return XGE_HAL_BADCFG_BIMODAL_TIMER_LO_US;
 485         }
 486
 487         if (new_config->bimodal_interrupts &&
 488             ((new_config->bimodal_timer_hi_us < XGE_HAL_BIMODAL_TIMER_HI_US_MIN) ||
 489             (new_config->bimodal_timer_hi_us > XGE_HAL_BIMODAL_TIMER_HI_US_MAX))) {
 490             return XGE_HAL_BADCFG_BIMODAL_TIMER_HI_US;
 491         }
 492
 493         if ((new_config->no_isr_events < XGE_HAL_NO_ISR_EVENTS_MIN) ||
 494             (new_config->no_isr_events > XGE_HAL_NO_ISR_EVENTS_MAX)) {
 495             return XGE_HAL_BADCFG_NO_ISR_EVENTS;
 496         }
 497
 498         if ((new_config->isr_polling_cnt < XGE_HAL_MIN_ISR_POLLING_CNT) ||
 499             (new_config->isr_polling_cnt > XGE_HAL_MAX_ISR_POLLING_CNT)) {
 500             return XGE_HAL_BADCFG_ISR_POLLING_CNT;
 501         }
 502
 503         if (new_config->latency_timer &&
 504             new_config->latency_timer != XGE_HAL_USE_BIOS_DEFAULT_LATENCY) {
 505                     if ((new_config->latency_timer < XGE_HAL_MIN_LATENCY_TIMER) ||
 506                 (new_config->latency_timer > XGE_HAL_MAX_LATENCY_TIMER)) {
 507                             return XGE_HAL_BADCFG_LATENCY_TIMER;
 508             }
 509         }
 510
 511         if (new_config->max_splits_trans != XGE_HAL_USE_BIOS_DEFAULT_SPLITS)  {
 512             if ((new_config->max_splits_trans <
 513                 XGE_HAL_ONE_SPLIT_TRANSACTION) ||
 514                 (new_config->max_splits_trans >
 515                 XGE_HAL_THIRTYTWO_SPLIT_TRANSACTION))
 516             return XGE_HAL_BADCFG_MAX_SPLITS_TRANS;
 517         }
 518
 519         if (new_config->mmrb_count != XGE_HAL_DEFAULT_BIOS_MMRB_COUNT)
 520         {
 521             if ((new_config->mmrb_count < XGE_HAL_MIN_MMRB_COUNT) ||
 522                 (new_config->mmrb_count > XGE_HAL_MAX_MMRB_COUNT)) {
 523                 return XGE_HAL_BADCFG_MMRB_COUNT;
 524             }
 525         }
 526
 527         if ((new_config->shared_splits < XGE_HAL_MIN_SHARED_SPLITS) ||
 528             (new_config->shared_splits > XGE_HAL_MAX_SHARED_SPLITS)) {
 529             return XGE_HAL_BADCFG_SHARED_SPLITS;
 530         }
 531
 532         if (new_config->stats_refresh_time_sec !=
 533                 XGE_HAL_STATS_REFRESH_DISABLE)  {
 534                 if ((new_config->stats_refresh_time_sec <
 535                             XGE_HAL_MIN_STATS_REFRESH_TIME) ||
 536                     (new_config->stats_refresh_time_sec >
 537                             XGE_HAL_MAX_STATS_REFRESH_TIME)) {
 538                     return XGE_HAL_BADCFG_STATS_REFRESH_TIME;
 539                 }
 540         }
 541
 542         if ((new_config->intr_mode != XGE_HAL_INTR_MODE_IRQLINE) &&
 543             (new_config->intr_mode != XGE_HAL_INTR_MODE_MSI) &&
 544             (new_config->intr_mode != XGE_HAL_INTR_MODE_MSIX)) {
 545             return XGE_HAL_BADCFG_INTR_MODE;
 546         }
 547
 548         if ((new_config->sched_timer_us < XGE_HAL_SCHED_TIMER_MIN) ||
 549             (new_config->sched_timer_us > XGE_HAL_SCHED_TIMER_MAX)) {
 550             return XGE_HAL_BADCFG_SCHED_TIMER_US;
 551         }
 552
 553         if ((new_config->sched_timer_one_shot !=
 554                 XGE_HAL_SCHED_TIMER_ON_SHOT_DISABLE)  &&
 555             (new_config->sched_timer_one_shot !=
 556                 XGE_HAL_SCHED_TIMER_ON_SHOT_ENABLE)) {
 557             return XGE_HAL_BADCFG_SCHED_TIMER_ON_SHOT;
 558         }
 559
 560         /*
 561          * Check adaptive schema parameters. Note that there are two
 562          * configuration variables needs to be enabled in ULD:
 563          *
 564          *   a) sched_timer_us should not be zero;
 565          *   b) rxufca_hi_lim should not be equal to rxufca_lo_lim.
 566          *
 567          * The code bellow checking for those conditions.
 568          */
 569         if (new_config->sched_timer_us &&
 570             new_config->rxufca_hi_lim != new_config->rxufca_lo_lim) {
 571             if ((new_config->rxufca_intr_thres <
 572                         XGE_HAL_RXUFCA_INTR_THRES_MIN) ||
 573                 (new_config->rxufca_intr_thres >
 574                         XGE_HAL_RXUFCA_INTR_THRES_MAX)) {
 575                 return XGE_HAL_BADCFG_RXUFCA_INTR_THRES;
 576             }
 577
 578             if ((new_config->rxufca_hi_lim < XGE_HAL_RXUFCA_HI_LIM_MIN) ||
 579                 (new_config->rxufca_hi_lim > XGE_HAL_RXUFCA_HI_LIM_MAX)) {
 580                 return XGE_HAL_BADCFG_RXUFCA_HI_LIM;
 581             }
 582
 583             if ((new_config->rxufca_lo_lim < XGE_HAL_RXUFCA_LO_LIM_MIN) ||
 584                 (new_config->rxufca_lo_lim > XGE_HAL_RXUFCA_LO_LIM_MAX) ||
 585                 (new_config->rxufca_lo_lim > new_config->rxufca_hi_lim)) {
 586                 return XGE_HAL_BADCFG_RXUFCA_LO_LIM;
 587             }
 588
 589             if ((new_config->rxufca_lbolt_period <
 590                         XGE_HAL_RXUFCA_LBOLT_PERIOD_MIN) ||
 591                 (new_config->rxufca_lbolt_period >
 592                         XGE_HAL_RXUFCA_LBOLT_PERIOD_MAX)) {
 593                 return XGE_HAL_BADCFG_RXUFCA_LBOLT_PERIOD;
 594             }
 595         }
 596
 597         if ((new_config->link_valid_cnt < XGE_HAL_LINK_VALID_CNT_MIN) ||
 598             (new_config->link_valid_cnt > XGE_HAL_LINK_VALID_CNT_MAX)) {
 599             return XGE_HAL_BADCFG_LINK_VALID_CNT;
 600         }
 601
 602         if ((new_config->link_retry_cnt < XGE_HAL_LINK_RETRY_CNT_MIN) ||
 603             (new_config->link_retry_cnt > XGE_HAL_LINK_RETRY_CNT_MAX)) {
 604             return XGE_HAL_BADCFG_LINK_RETRY_CNT;
 605         }
 606
 607         if (new_config->link_valid_cnt > new_config->link_retry_cnt)
 608             return XGE_HAL_BADCFG_LINK_VALID_CNT;
 609
 610         if (new_config->link_stability_period != XGE_HAL_DEFAULT_USE_HARDCODE) {
 611                 if ((new_config->link_stability_period <
 612                             XGE_HAL_MIN_LINK_STABILITY_PERIOD) ||
 613                     (new_config->link_stability_period >
 614                             XGE_HAL_MAX_LINK_STABILITY_PERIOD)) {
 615                     return XGE_HAL_BADCFG_LINK_STABILITY_PERIOD;
 616                 }
 617         }
 618
 619         if (new_config->device_poll_millis !=
 620                         XGE_HAL_DEFAULT_USE_HARDCODE)  {
 621                 if ((new_config->device_poll_millis <
 622                         XGE_HAL_MIN_DEVICE_POLL_MILLIS) ||
 623                     (new_config->device_poll_millis >
 624                         XGE_HAL_MAX_DEVICE_POLL_MILLIS)) {
 625                     return XGE_HAL_BADCFG_DEVICE_POLL_MILLIS;
 626                 }
 627             }
 628
 629         if ((new_config->rts_port_en < XGE_HAL_MIN_RING_RTS_PORT_EN) ||
 630             (new_config->rts_port_en > XGE_HAL_MAX_RING_RTS_PORT_EN)) {
 631             return XGE_HAL_BADCFG_RTS_PORT_EN;
 632         }
 633
 634         if ((new_config->rts_qos_en < XGE_HAL_RTS_QOS_DISABLE) ||
 635             (new_config->rts_qos_en > XGE_HAL_RTS_QOS_ENABLE)) {
 636             return XGE_HAL_BADCFG_RTS_QOS_EN;
 637         }
 638
 639 #if defined(XGE_HAL_CONFIG_LRO)
 640         if (new_config->lro_sg_size !=
 641                     XGE_HAL_DEFAULT_USE_HARDCODE)  {
 642             if ((new_config->lro_sg_size < XGE_HAL_LRO_MIN_SG_SIZE) ||
 643                 (new_config->lro_sg_size > XGE_HAL_LRO_MAX_SG_SIZE)) {
 644                 return XGE_HAL_BADCFG_LRO_SG_SIZE;
 645             }
 646         }
 647
 648         if (new_config->lro_frm_len !=
 649                     XGE_HAL_DEFAULT_USE_HARDCODE)  {
 650             if ((new_config->lro_frm_len < XGE_HAL_LRO_MIN_FRM_LEN) ||
 651                 (new_config->lro_frm_len > XGE_HAL_LRO_MAX_FRM_LEN)) {
 652                 return XGE_HAL_BADCFG_LRO_FRM_LEN;
 653             }
 654         }
 655 #endif
 656
 657         if ((status = __hal_ring_config_check(&new_config->ring))
 658                 != XGE_HAL_OK) {
 659             return status;
 660         }
 661
 662         if ((status = __hal_mac_config_check(&new_config->mac)) !=
 663             XGE_HAL_OK) {
 664             return status;
 665         }
 666
 667         if ((status = __hal_fifo_config_check(&new_config->fifo)) !=
 668             XGE_HAL_OK) {
 669             return status;
 670         }
 671
 672         return XGE_HAL_OK;
 673 }
 674
 675 /*
 676  * __hal_device_config_check_xena - Check Xframe-I configuration
 677  * @new_config: Device configuration.
 678  *
 679  * Check part of configuration that is relevant only to Xframe-I.
 680  *
 681  * Returns: XGE_HAL_OK - success,
 682  * otherwise one of the xge_hal_status_e{} enumerated error codes.
 683  *
 684  * See also: __hal_device_config_check_common().
 685  */
 686 xge_hal_status_e
 687 __hal_device_config_check_xena (xge_hal_device_config_t *new_config)
 688 {
 689         if ((new_config->pci_freq_mherz != XGE_HAL_PCI_FREQ_MHERZ_33) &&
 690             (new_config->pci_freq_mherz != XGE_HAL_PCI_FREQ_MHERZ_66) &&
 691             (new_config->pci_freq_mherz != XGE_HAL_PCI_FREQ_MHERZ_100) &&
 692             (new_config->pci_freq_mherz != XGE_HAL_PCI_FREQ_MHERZ_133) &&
 693             (new_config->pci_freq_mherz != XGE_HAL_PCI_FREQ_MHERZ_266) &&
 694             (new_config->pci_freq_mherz != XGE_HAL_DEFAULT_USE_HARDCODE)) {
 695             return XGE_HAL_BADCFG_PCI_FREQ_MHERZ;
 696         }
 697
 698         return XGE_HAL_OK;
 699 }
 700
 701 /*
 702  * __hal_device_config_check_herc - Check device configuration
 703  * @new_config: Device configuration.
 704  *
 705  * Check part of configuration that is relevant only to Xframe-II.
 706  *
 707  * Returns: XGE_HAL_OK - success,
 708  * otherwise one of the xge_hal_status_e{} enumerated error codes.
 709  *
 710  * See also: __hal_device_config_check_common().
 711  */
 712 xge_hal_status_e
 713 __hal_device_config_check_herc (xge_hal_device_config_t *new_config)
 714 {
 715         return XGE_HAL_OK;
 716 }
 717
 718
 719 /*
 720  * __hal_driver_config_check - Check HAL configuration
 721  * @new_config: Driver configuration information
 722  *
 723  * Returns: XGE_HAL_OK - success,
 724  * otherwise one of the xge_hal_status_e{} enumerated error codes.
 725  */
 726 xge_hal_status_e
 727 __hal_driver_config_check (xge_hal_driver_config_t *new_config)
 728 {
 729         if ((new_config->queue_size_initial <
 730                     XGE_HAL_MIN_QUEUE_SIZE_INITIAL) ||
 731             (new_config->queue_size_initial >
 732                     XGE_HAL_MAX_QUEUE_SIZE_INITIAL)) {
 733             return XGE_HAL_BADCFG_QUEUE_SIZE_INITIAL;
 734         }
 735
 736         if ((new_config->queue_size_max < XGE_HAL_MIN_QUEUE_SIZE_MAX) ||
 737             (new_config->queue_size_max > XGE_HAL_MAX_QUEUE_SIZE_MAX)) {
 738             return XGE_HAL_BADCFG_QUEUE_SIZE_MAX;
 739         }
 740
 741 #ifdef XGE_TRACE_INTO_CIRCULAR_ARR
 742         if ((new_config->tracebuf_size < XGE_HAL_MIN_CIRCULAR_ARR) ||
 743             (new_config->tracebuf_size > XGE_HAL_MAX_CIRCULAR_ARR)) {
 744             return XGE_HAL_BADCFG_TRACEBUF_SIZE;
 745         }
 746         if ((new_config->tracebuf_timestamp_en < XGE_HAL_MIN_TIMESTAMP_EN) ||
 747             (new_config->tracebuf_timestamp_en > XGE_HAL_MAX_TIMESTAMP_EN)) {
 748             return XGE_HAL_BADCFG_TRACEBUF_SIZE;
 749         }
 750 #endif
 751
 752         return XGE_HAL_OK;
 753 }