sys/dev/oce/oce_hw.h

   1 /*-
   2  * Copyright (C) 2013 Emulex
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright notice,
   9  *    this list of conditions and the following disclaimer.
  10  *
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * 3. Neither the name of the Emulex Corporation nor the names of its
  16  *    contributors may be used to endorse or promote products derived from
  17  *    this software without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  *
  31  * Contact Information:
  32  * freebsd-drivers@emulex.com
  33  *
  34  * Emulex
  35  * 3333 Susan Street
  36  * Costa Mesa, CA 92626
  37  */
  38
  39 /* $FreeBSD$ */
  40
  41 #include <sys/types.h>
  42
  43 #undef _BIG_ENDIAN /* TODO */
  44 #pragma pack(1)
  45
  46 #define OC_CNA_GEN2                     0x2
  47 #define OC_CNA_GEN3                     0x3
  48 #define DEVID_TIGERSHARK                0x700
  49 #define DEVID_TOMCAT                    0x710
  50
  51 /* PCI CSR offsets */
  52 #define PCICFG_F1_CSR                   0x0     /* F1 for NIC */
  53 #define PCICFG_SEMAPHORE                0xbc
  54 #define PCICFG_SOFT_RESET               0x5c
  55 #define PCICFG_UE_STATUS_HI_MASK        0xac
  56 #define PCICFG_UE_STATUS_LO_MASK        0xa8
  57 #define PCICFG_ONLINE0                  0xb0
  58 #define PCICFG_ONLINE1                  0xb4
  59 #define INTR_EN                         0x20000000
  60 #define IMAGE_TRANSFER_SIZE             (32 * 1024)     /* 32K at a time */
  61
  62
  63 /********* UE Status and Mask Registers ***/
  64 #define PCICFG_UE_STATUS_LOW                    0xA0
  65 #define PCICFG_UE_STATUS_HIGH                   0xA4
  66 #define PCICFG_UE_STATUS_LOW_MASK               0xA8
  67
  68 /* Lancer SLIPORT registers */
  69 #define SLIPORT_STATUS_OFFSET           0x404
  70 #define SLIPORT_CONTROL_OFFSET          0x408
  71 #define SLIPORT_ERROR1_OFFSET           0x40C
  72 #define SLIPORT_ERROR2_OFFSET           0x410
  73 #define PHYSDEV_CONTROL_OFFSET          0x414
  74
  75 #define SLIPORT_STATUS_ERR_MASK         0x80000000
  76 #define SLIPORT_STATUS_DIP_MASK         0x02000000
  77 #define SLIPORT_STATUS_RN_MASK          0x01000000
  78 #define SLIPORT_STATUS_RDY_MASK         0x00800000
  79 #define SLI_PORT_CONTROL_IP_MASK        0x08000000
  80 #define PHYSDEV_CONTROL_FW_RESET_MASK   0x00000002
  81 #define PHYSDEV_CONTROL_DD_MASK         0x00000004
  82 #define PHYSDEV_CONTROL_INP_MASK        0x40000000
  83
  84 #define SLIPORT_ERROR_NO_RESOURCE1      0x2
  85 #define SLIPORT_ERROR_NO_RESOURCE2      0x9
  86 /* CSR register offsets */
  87 #define MPU_EP_CONTROL                  0
  88 #define MPU_EP_SEMAPHORE_BE3            0xac
  89 #define MPU_EP_SEMAPHORE_XE201          0x400
  90 #define MPU_EP_SEMAPHORE_SH             0x94
  91 #define PCICFG_INTR_CTRL                0xfc
  92 #define HOSTINTR_MASK                   (1 << 29)
  93 #define HOSTINTR_PFUNC_SHIFT            26
  94 #define HOSTINTR_PFUNC_MASK             7
  95
  96 /* POST status reg struct */
  97 #define POST_STAGE_POWER_ON_RESET       0x00
  98 #define POST_STAGE_AWAITING_HOST_RDY    0x01
  99 #define POST_STAGE_HOST_RDY             0x02
 100 #define POST_STAGE_CHIP_RESET           0x03
 101 #define POST_STAGE_ARMFW_READY          0xc000
 102 #define POST_STAGE_ARMFW_UE             0xf000
 103
 104 /* DOORBELL registers */
 105 #define PD_RXULP_DB                     0x0100
 106 #define PD_TXULP_DB                     0x0060
 107 #define DB_RQ_ID_MASK                   0x3FF
 108
 109 #define PD_CQ_DB                        0x0120
 110 #define PD_EQ_DB                        PD_CQ_DB
 111 #define PD_MPU_MBOX_DB                  0x0160
 112 #define PD_MQ_DB                        0x0140
 113
 114 /* EQE completion types */
 115 #define EQ_MINOR_CODE_COMPLETION        0x00
 116 #define EQ_MINOR_CODE_OTHER             0x01
 117 #define EQ_MAJOR_CODE_COMPLETION        0x00
 118
 119 /* Link Status field values */
 120 #define PHY_LINK_FAULT_NONE             0x0
 121 #define PHY_LINK_FAULT_LOCAL            0x01
 122 #define PHY_LINK_FAULT_REMOTE           0x02
 123
 124 #define PHY_LINK_SPEED_ZERO             0x0     /* No link */
 125 #define PHY_LINK_SPEED_10MBPS           0x1     /* (10 Mbps) */
 126 #define PHY_LINK_SPEED_100MBPS          0x2     /* (100 Mbps) */
 127 #define PHY_LINK_SPEED_1GBPS            0x3     /* (1 Gbps) */
 128 #define PHY_LINK_SPEED_10GBPS           0x4     /* (10 Gbps) */
 129
 130 #define PHY_LINK_DUPLEX_NONE            0x0
 131 #define PHY_LINK_DUPLEX_HALF            0x1
 132 #define PHY_LINK_DUPLEX_FULL            0x2
 133
 134 #define NTWK_PORT_A                     0x0     /* (Port A) */
 135 #define NTWK_PORT_B                     0x1     /* (Port B) */
 136
 137 #define PHY_LINK_SPEED_ZERO                     0x0     /* (No link.) */
 138 #define PHY_LINK_SPEED_10MBPS           0x1     /* (10 Mbps) */
 139 #define PHY_LINK_SPEED_100MBPS          0x2     /* (100 Mbps) */
 140 #define PHY_LINK_SPEED_1GBPS            0x3     /* (1 Gbps) */
 141 #define PHY_LINK_SPEED_10GBPS           0x4     /* (10 Gbps) */
 142
 143 /* Hardware Address types */
 144 #define MAC_ADDRESS_TYPE_STORAGE        0x0     /* (Storage MAC Address) */
 145 #define MAC_ADDRESS_TYPE_NETWORK        0x1     /* (Network MAC Address) */
 146 #define MAC_ADDRESS_TYPE_PD             0x2     /* (Protection Domain MAC Addr) */
 147 #define MAC_ADDRESS_TYPE_MANAGEMENT     0x3     /* (Management MAC Address) */
 148 #define MAC_ADDRESS_TYPE_FCOE           0x4     /* (FCoE MAC Address) */
 149
 150 /* CREATE_IFACE capability and cap_en flags */
 151 #define MBX_RX_IFACE_FLAGS_RSS          0x4
 152 #define MBX_RX_IFACE_FLAGS_PROMISCUOUS  0x8
 153 #define MBX_RX_IFACE_FLAGS_BROADCAST    0x10
 154 #define MBX_RX_IFACE_FLAGS_UNTAGGED     0x20
 155 #define MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS     0x80
 156 #define MBX_RX_IFACE_FLAGS_VLAN         0x100
 157 #define MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS    0x200
 158 #define MBX_RX_IFACE_FLAGS_PASS_L2_ERR  0x400
 159 #define MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR        0x800
 160 #define MBX_RX_IFACE_FLAGS_MULTICAST    0x1000
 161 #define MBX_RX_IFACE_RX_FILTER_IF_MULTICAST_HASH 0x2000
 162 #define MBX_RX_IFACE_FLAGS_HDS          0x4000
 163 #define MBX_RX_IFACE_FLAGS_DIRECTED     0x8000
 164 #define MBX_RX_IFACE_FLAGS_VMQ          0x10000
 165 #define MBX_RX_IFACE_FLAGS_NETQ         0x20000
 166 #define MBX_RX_IFACE_FLAGS_QGROUPS      0x40000
 167 #define MBX_RX_IFACE_FLAGS_LSO          0x80000
 168 #define MBX_RX_IFACE_FLAGS_LRO          0x100000
 169
 170 #define MQ_RING_CONTEXT_SIZE_16         0x5     /* (16 entries) */
 171 #define MQ_RING_CONTEXT_SIZE_32         0x6     /* (32 entries) */
 172 #define MQ_RING_CONTEXT_SIZE_64         0x7     /* (64 entries) */
 173 #define MQ_RING_CONTEXT_SIZE_128        0x8     /* (128 entries) */
 174
 175 #define MBX_DB_READY_BIT                0x1
 176 #define MBX_DB_HI_BIT                   0x2
 177 #define ASYNC_EVENT_CODE_LINK_STATE     0x1
 178 #define ASYNC_EVENT_LINK_UP             0x1
 179 #define ASYNC_EVENT_LINK_DOWN           0x0
 180 #define ASYNC_EVENT_GRP5                0x5
 181 #define ASYNC_EVENT_CODE_DEBUG          0x6
 182 #define ASYNC_EVENT_PVID_STATE          0x3
 183 #define ASYNC_EVENT_DEBUG_QNQ           0x1
 184 #define ASYNC_EVENT_CODE_SLIPORT        0x11
 185 #define VLAN_VID_MASK                   0x0FFF
 186
 187 /* port link_status */
 188 #define ASYNC_EVENT_LOGICAL             0x02
 189
 190 /* Logical Link Status */
 191 #define NTWK_LOGICAL_LINK_DOWN          0
 192 #define NTWK_LOGICAL_LINK_UP            1
 193
 194 /* Rx filter bits */
 195 #define NTWK_RX_FILTER_IP_CKSUM         0x1
 196 #define NTWK_RX_FILTER_TCP_CKSUM        0x2
 197 #define NTWK_RX_FILTER_UDP_CKSUM        0x4
 198 #define NTWK_RX_FILTER_STRIP_CRC        0x8
 199
 200 /* max SGE per mbx */
 201 #define MAX_MBX_SGE                     19
 202
 203 /* Max multicast filter size*/
 204 #define OCE_MAX_MC_FILTER_SIZE          64
 205
 206 /* PCI SLI (Service Level Interface) capabilities register */
 207 #define OCE_INTF_REG_OFFSET             0x58
 208 #define OCE_INTF_VALID_SIG              6       /* register's signature */
 209 #define OCE_INTF_FUNC_RESET_REQD        1
 210 #define OCE_INTF_HINT1_NOHINT           0
 211 #define OCE_INTF_HINT1_SEMAINIT         1
 212 #define OCE_INTF_HINT1_STATCTRL         2
 213 #define OCE_INTF_IF_TYPE_0              0
 214 #define OCE_INTF_IF_TYPE_1              1
 215 #define OCE_INTF_IF_TYPE_2              2
 216 #define OCE_INTF_IF_TYPE_3              3
 217 #define OCE_INTF_SLI_REV3               3       /* not supported by driver */
 218 #define OCE_INTF_SLI_REV4               4       /* driver supports SLI-4 */
 219 #define OCE_INTF_PHYS_FUNC              0
 220 #define OCE_INTF_VIRT_FUNC              1
 221 #define OCE_INTF_FAMILY_BE2             0       /* not supported by driver */
 222 #define OCE_INTF_FAMILY_BE3             1       /* driver supports BE3 */
 223 #define OCE_INTF_FAMILY_A0_CHIP         0xA     /* Lancer A0 chip (supported) */
 224 #define OCE_INTF_FAMILY_B0_CHIP         0xB     /* Lancer B0 chip (future) */
 225
 226 #define NIC_WQE_SIZE    16
 227 #define NIC_UNICAST     0x00
 228 #define NIC_MULTICAST   0x01
 229 #define NIC_BROADCAST   0x02
 230
 231 #define NIC_HDS_NO_SPLIT        0x00
 232 #define NIC_HDS_SPLIT_L3PL      0x01
 233 #define NIC_HDS_SPLIT_L4PL      0x02
 234
 235 #define NIC_WQ_TYPE_FORWARDING          0x01
 236 #define NIC_WQ_TYPE_STANDARD            0x02
 237 #define NIC_WQ_TYPE_LOW_LATENCY         0x04
 238
 239 #define OCE_RESET_STATS         1
 240 #define OCE_RETAIN_STATS        0
 241 #define OCE_TXP_SW_SZ           48
 242
 243 typedef union pci_sli_intf_u {
 244         uint32_t dw0;
 245         struct {
 246 #ifdef _BIG_ENDIAN
 247                 uint32_t sli_valid:3;
 248                 uint32_t sli_hint2:5;
 249                 uint32_t sli_hint1:8;
 250                 uint32_t sli_if_type:4;
 251                 uint32_t sli_family:4;
 252                 uint32_t sli_rev:4;
 253                 uint32_t rsv0:3;
 254                 uint32_t sli_func_type:1;
 255 #else
 256                 uint32_t sli_func_type:1;
 257                 uint32_t rsv0:3;
 258                 uint32_t sli_rev:4;
 259                 uint32_t sli_family:4;
 260                 uint32_t sli_if_type:4;
 261                 uint32_t sli_hint1:8;
 262                 uint32_t sli_hint2:5;
 263                 uint32_t sli_valid:3;
 264 #endif
 265         } bits;
 266 } pci_sli_intf_t;
 267
 268
 269
 270 /* physical address structure to be used in MBX */
 271 struct phys_addr {
 272         /* dw0 */
 273         uint32_t lo;
 274         /* dw1 */
 275         uint32_t hi;
 276 };
 277
 278
 279
 280 typedef union pcicfg_intr_ctl_u {
 281         uint32_t dw0;
 282         struct {
 283 #ifdef _BIG_ENDIAN
 284                 uint32_t winselect:2;
 285                 uint32_t hostintr:1;
 286                 uint32_t pfnum:3;
 287                 uint32_t vf_cev_int_line_en:1;
 288                 uint32_t winaddr:23;
 289                 uint32_t membarwinen:1;
 290 #else
 291                 uint32_t membarwinen:1;
 292                 uint32_t winaddr:23;
 293                 uint32_t vf_cev_int_line_en:1;
 294                 uint32_t pfnum:3;
 295                 uint32_t hostintr:1;
 296                 uint32_t winselect:2;
 297 #endif
 298         } bits;
 299 } pcicfg_intr_ctl_t;
 300
 301
 302
 303
 304 typedef union pcicfg_semaphore_u {
 305         uint32_t dw0;
 306         struct {
 307 #ifdef _BIG_ENDIAN
 308                 uint32_t rsvd:31;
 309                 uint32_t lock:1;
 310 #else
 311                 uint32_t lock:1;
 312                 uint32_t rsvd:31;
 313 #endif
 314         } bits;
 315 } pcicfg_semaphore_t;
 316
 317
 318
 319
 320 typedef union pcicfg_soft_reset_u {
 321         uint32_t dw0;
 322         struct {
 323 #ifdef _BIG_ENDIAN
 324                 uint32_t nec_ll_rcvdetect:8;
 325                 uint32_t dbg_all_reqs_62_49:14;
 326                 uint32_t scratchpad0:1;
 327                 uint32_t exception_oe:1;
 328                 uint32_t soft_reset:1;
 329                 uint32_t rsvd0:7;
 330 #else
 331                 uint32_t rsvd0:7;
 332                 uint32_t soft_reset:1;
 333                 uint32_t exception_oe:1;
 334                 uint32_t scratchpad0:1;
 335                 uint32_t dbg_all_reqs_62_49:14;
 336                 uint32_t nec_ll_rcvdetect:8;
 337 #endif
 338         } bits;
 339 } pcicfg_soft_reset_t;
 340
 341
 342
 343
 344 typedef union pcicfg_online1_u {
 345         uint32_t dw0;
 346         struct {
 347 #ifdef _BIG_ENDIAN
 348                 uint32_t host8_online:1;
 349                 uint32_t host7_online:1;
 350                 uint32_t host6_online:1;
 351                 uint32_t host5_online:1;
 352                 uint32_t host4_online:1;
 353                 uint32_t host3_online:1;
 354                 uint32_t host2_online:1;
 355                 uint32_t ipc_online:1;
 356                 uint32_t arm_online:1;
 357                 uint32_t txp_online:1;
 358                 uint32_t xaui_online:1;
 359                 uint32_t rxpp_online:1;
 360                 uint32_t txpb_online:1;
 361                 uint32_t rr_online:1;
 362                 uint32_t pmem_online:1;
 363                 uint32_t pctl1_online:1;
 364                 uint32_t pctl0_online:1;
 365                 uint32_t pcs1online_online:1;
 366                 uint32_t mpu_iram_online:1;
 367                 uint32_t pcs0online_online:1;
 368                 uint32_t mgmt_mac_online:1;
 369                 uint32_t lpcmemhost_online:1;
 370 #else
 371                 uint32_t lpcmemhost_online:1;
 372                 uint32_t mgmt_mac_online:1;
 373                 uint32_t pcs0online_online:1;
 374                 uint32_t mpu_iram_online:1;
 375                 uint32_t pcs1online_online:1;
 376                 uint32_t pctl0_online:1;
 377                 uint32_t pctl1_online:1;
 378                 uint32_t pmem_online:1;
 379                 uint32_t rr_online:1;
 380                 uint32_t txpb_online:1;
 381                 uint32_t rxpp_online:1;
 382                 uint32_t xaui_online:1;
 383                 uint32_t txp_online:1;
 384                 uint32_t arm_online:1;
 385                 uint32_t ipc_online:1;
 386                 uint32_t host2_online:1;
 387                 uint32_t host3_online:1;
 388                 uint32_t host4_online:1;
 389                 uint32_t host5_online:1;
 390                 uint32_t host6_online:1;
 391                 uint32_t host7_online:1;
 392                 uint32_t host8_online:1;
 393 #endif
 394         } bits;
 395 } pcicfg_online1_t;
 396
 397
 398
 399 typedef union mpu_ep_semaphore_u {
 400         uint32_t dw0;
 401         struct {
 402 #ifdef _BIG_ENDIAN
 403                 uint32_t error:1;
 404                 uint32_t backup_fw:1;
 405                 uint32_t iscsi_no_ip:1;
 406                 uint32_t iscsi_ip_conflict:1;
 407                 uint32_t option_rom_installed:1;
 408                 uint32_t iscsi_drv_loaded:1;
 409                 uint32_t rsvd0:10;
 410                 uint32_t stage:16;
 411 #else
 412                 uint32_t stage:16;
 413                 uint32_t rsvd0:10;
 414                 uint32_t iscsi_drv_loaded:1;
 415                 uint32_t option_rom_installed:1;
 416                 uint32_t iscsi_ip_conflict:1;
 417                 uint32_t iscsi_no_ip:1;
 418                 uint32_t backup_fw:1;
 419                 uint32_t error:1;
 420 #endif
 421         } bits;
 422 } mpu_ep_semaphore_t;
 423
 424
 425
 426
 427 typedef union mpu_ep_control_u {
 428         uint32_t dw0;
 429         struct {
 430 #ifdef _BIG_ENDIAN
 431                 uint32_t cpu_reset:1;
 432                 uint32_t rsvd1:15;
 433                 uint32_t ep_ram_init_status:1;
 434                 uint32_t rsvd0:12;
 435                 uint32_t m2_rxpbuf:1;
 436                 uint32_t m1_rxpbuf:1;
 437                 uint32_t m0_rxpbuf:1;
 438 #else
 439                 uint32_t m0_rxpbuf:1;
 440                 uint32_t m1_rxpbuf:1;
 441                 uint32_t m2_rxpbuf:1;
 442                 uint32_t rsvd0:12;
 443                 uint32_t ep_ram_init_status:1;
 444                 uint32_t rsvd1:15;
 445                 uint32_t cpu_reset:1;
 446 #endif
 447         } bits;
 448 } mpu_ep_control_t;
 449
 450
 451
 452
 453 /* RX doorbell */
 454 typedef union pd_rxulp_db_u {
 455         uint32_t dw0;
 456         struct {
 457 #ifdef _BIG_ENDIAN
 458                 uint32_t num_posted:8;
 459                 uint32_t invalidate:1;
 460                 uint32_t rsvd1:13;
 461                 uint32_t qid:10;
 462 #else
 463                 uint32_t qid:10;
 464                 uint32_t rsvd1:13;
 465                 uint32_t invalidate:1;
 466                 uint32_t num_posted:8;
 467 #endif
 468         } bits;
 469 } pd_rxulp_db_t;
 470
 471
 472 /* TX doorbell */
 473 typedef union pd_txulp_db_u {
 474         uint32_t dw0;
 475         struct {
 476 #ifdef _BIG_ENDIAN
 477                 uint32_t rsvd1:2;
 478                 uint32_t num_posted:14;
 479                 uint32_t rsvd0:6;
 480                 uint32_t qid:10;
 481 #else
 482                 uint32_t qid:10;
 483                 uint32_t rsvd0:6;
 484                 uint32_t num_posted:14;
 485                 uint32_t rsvd1:2;
 486 #endif
 487         } bits;
 488 } pd_txulp_db_t;
 489
 490 /* CQ doorbell */
 491 typedef union cq_db_u {
 492         uint32_t dw0;
 493         struct {
 494 #ifdef _BIG_ENDIAN
 495                 uint32_t rsvd1:2;
 496                 uint32_t rearm:1;
 497                 uint32_t num_popped:13;
 498                 uint32_t rsvd0:5;
 499                 uint32_t event:1;
 500                 uint32_t qid:10;
 501 #else
 502                 uint32_t qid:10;
 503                 uint32_t event:1;
 504                 uint32_t rsvd0:5;
 505                 uint32_t num_popped:13;
 506                 uint32_t rearm:1;
 507                 uint32_t rsvd1:2;
 508 #endif
 509         } bits;
 510 } cq_db_t;
 511
 512 /* EQ doorbell */
 513 typedef union eq_db_u {
 514         uint32_t dw0;
 515         struct {
 516 #ifdef _BIG_ENDIAN
 517                 uint32_t rsvd1:2;
 518                 uint32_t rearm:1;
 519                 uint32_t num_popped:13;
 520                 uint32_t rsvd0:5;
 521                 uint32_t event:1;
 522                 uint32_t clrint:1;
 523                 uint32_t qid:9;
 524 #else
 525                 uint32_t qid:9;
 526                 uint32_t clrint:1;
 527                 uint32_t event:1;
 528                 uint32_t rsvd0:5;
 529                 uint32_t num_popped:13;
 530                 uint32_t rearm:1;
 531                 uint32_t rsvd1:2;
 532 #endif
 533         } bits;
 534 } eq_db_t;
 535
 536 /* bootstrap mbox doorbell */
 537 typedef union pd_mpu_mbox_db_u {
 538         uint32_t dw0;
 539         struct {
 540 #ifdef _BIG_ENDIAN
 541                 uint32_t address:30;
 542                 uint32_t hi:1;
 543                 uint32_t ready:1;
 544 #else
 545                 uint32_t ready:1;
 546                 uint32_t hi:1;
 547                 uint32_t address:30;
 548 #endif
 549         } bits;
 550 } pd_mpu_mbox_db_t;
 551
 552 /* MQ ring doorbell */
 553 typedef union pd_mq_db_u {
 554         uint32_t dw0;
 555         struct {
 556 #ifdef _BIG_ENDIAN
 557                 uint32_t rsvd1:2;
 558                 uint32_t num_posted:14;
 559                 uint32_t rsvd0:5;
 560                 uint32_t mq_id:11;
 561 #else
 562                 uint32_t mq_id:11;
 563                 uint32_t rsvd0:5;
 564                 uint32_t num_posted:14;
 565                 uint32_t rsvd1:2;
 566 #endif
 567         } bits;
 568 } pd_mq_db_t;
 569
 570 /*
 571  * Event Queue Entry
 572  */
 573 struct oce_eqe {
 574         uint32_t evnt;
 575 };
 576
 577 /* MQ scatter gather entry. Array of these make an SGL */
 578 struct oce_mq_sge {
 579         uint32_t pa_lo;
 580         uint32_t pa_hi;
 581         uint32_t length;
 582 };
 583
 584 /*
 585  * payload can contain an SGL or an embedded array of upto 59 dwords
 586  */
 587 struct oce_mbx_payload {
 588         union {
 589                 union {
 590                         struct oce_mq_sge sgl[MAX_MBX_SGE];
 591                         uint32_t embedded[59];
 592                 } u1;
 593                 uint32_t dw[59];
 594         } u0;
 595 };
 596
 597 /*
 598  * MQ MBX structure
 599  */
 600 struct oce_mbx {
 601         union {
 602                 struct {
 603 #ifdef _BIG_ENDIAN
 604                         uint32_t special:8;
 605                         uint32_t rsvd1:16;
 606                         uint32_t sge_count:5;
 607                         uint32_t rsvd0:2;
 608                         uint32_t embedded:1;
 609 #else
 610                         uint32_t embedded:1;
 611                         uint32_t rsvd0:2;
 612                         uint32_t sge_count:5;
 613                         uint32_t rsvd1:16;
 614                         uint32_t special:8;
 615 #endif
 616                 } s;
 617                 uint32_t dw0;
 618         } u0;
 619
 620         uint32_t payload_length;
 621         uint32_t tag[2];
 622         uint32_t rsvd2[1];
 623         struct oce_mbx_payload payload;
 624 };
 625
 626 /* completion queue entry for MQ */
 627 struct oce_mq_cqe {
 628         union {
 629                 struct {
 630 #ifdef _BIG_ENDIAN
 631                         /* dw0 */
 632                         uint32_t extended_status:16;
 633                         uint32_t completion_status:16;
 634                         /* dw1 dw2 */
 635                         uint32_t mq_tag[2];
 636                         /* dw3 */
 637                         uint32_t valid:1;
 638                         uint32_t async_event:1;
 639                         uint32_t hpi_buffer_cmpl:1;
 640                         uint32_t completed:1;
 641                         uint32_t consumed:1;
 642                         uint32_t rsvd0:3;
 643                         uint32_t async_type:8;
 644                         uint32_t event_type:8;
 645                         uint32_t rsvd1:8;
 646 #else
 647                         /* dw0 */
 648                         uint32_t completion_status:16;
 649                         uint32_t extended_status:16;
 650                         /* dw1 dw2 */
 651                         uint32_t mq_tag[2];
 652                         /* dw3 */
 653                         uint32_t rsvd1:8;
 654                         uint32_t event_type:8;
 655                         uint32_t async_type:8;
 656                         uint32_t rsvd0:3;
 657                         uint32_t consumed:1;
 658                         uint32_t completed:1;
 659                         uint32_t hpi_buffer_cmpl:1;
 660                         uint32_t async_event:1;
 661                         uint32_t valid:1;
 662 #endif
 663                 } s;
 664                 uint32_t dw[4];
 665         } u0;
 666 };
 667
 668 /* Mailbox Completion Status Codes */
 669 enum MBX_COMPLETION_STATUS {
 670         MBX_CQE_STATUS_SUCCESS = 0x00,
 671         MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES = 0x01,
 672         MBX_CQE_STATUS_INVALID_PARAMETER = 0x02,
 673         MBX_CQE_STATUS_INSUFFICIENT_RESOURCES = 0x03,
 674         MBX_CQE_STATUS_QUEUE_FLUSHING = 0x04,
 675         MBX_CQE_STATUS_DMA_FAILED = 0x05
 676 };
 677
 678 struct oce_async_cqe_link_state {
 679         union {
 680                 struct {
 681 #ifdef _BIG_ENDIAN
 682                         /* dw0 */
 683                         uint8_t speed;
 684                         uint8_t duplex;
 685                         uint8_t link_status;
 686                         uint8_t phy_port;
 687                         /* dw1 */
 688                         uint16_t qos_link_speed;
 689                         uint8_t rsvd0;
 690                         uint8_t fault;
 691                         /* dw2 */
 692                         uint32_t event_tag;
 693                         /* dw3 */
 694                         uint32_t valid:1;
 695                         uint32_t async_event:1;
 696                         uint32_t rsvd2:6;
 697                         uint32_t event_type:8;
 698                         uint32_t event_code:8;
 699                         uint32_t rsvd1:8;
 700 #else
 701                         /* dw0 */
 702                         uint8_t phy_port;
 703                         uint8_t link_status;
 704                         uint8_t duplex;
 705                         uint8_t speed;
 706                         /* dw1 */
 707                         uint8_t fault;
 708                         uint8_t rsvd0;
 709                         uint16_t qos_link_speed;
 710                         /* dw2 */
 711                         uint32_t event_tag;
 712                         /* dw3 */
 713                         uint32_t rsvd1:8;
 714                         uint32_t event_code:8;
 715                         uint32_t event_type:8;
 716                         uint32_t rsvd2:6;
 717                         uint32_t async_event:1;
 718                         uint32_t valid:1;
 719 #endif
 720                 } s;
 721                 uint32_t dw[4];
 722         } u0;
 723 };
 724
 725
 726 /* PVID aync event */
 727 struct oce_async_event_grp5_pvid_state {
 728         uint8_t enabled;
 729         uint8_t rsvd0;
 730         uint16_t tag;
 731         uint32_t event_tag;
 732         uint32_t rsvd1;
 733         uint32_t code;
 734 };
 735
 736 /* async event indicating outer VLAN tag in QnQ */
 737 struct oce_async_event_qnq {
 738         uint8_t valid;       /* Indicates if outer VLAN is valid */
 739         uint8_t rsvd0;
 740         uint16_t vlan_tag;
 741         uint32_t event_tag;
 742         uint8_t rsvd1[4];
 743         uint32_t code;
 744 } ;
 745
 746
 747 typedef union oce_mq_ext_ctx_u {
 748         uint32_t dw[6];
 749         struct {
 750                 #ifdef _BIG_ENDIAN
 751                 /* dw0 */
 752                 uint32_t dw4rsvd1:16;
 753                 uint32_t num_pages:16;
 754                 /* dw1 */
 755                 uint32_t async_evt_bitmap;
 756                 /* dw2 */
 757                 uint32_t cq_id:10;
 758                 uint32_t dw5rsvd2:2;
 759                 uint32_t ring_size:4;
 760                 uint32_t dw5rsvd1:16;
 761                 /* dw3 */
 762                 uint32_t valid:1;
 763                 uint32_t dw6rsvd1:31;
 764                 /* dw4 */
 765                 uint32_t dw7rsvd1:21;
 766                 uint32_t async_cq_id:10;
 767                 uint32_t async_cq_valid:1;
 768         #else
 769                 /* dw0 */
 770                 uint32_t num_pages:16;
 771                 uint32_t dw4rsvd1:16;
 772                 /* dw1 */
 773                 uint32_t async_evt_bitmap;
 774                 /* dw2 */
 775                 uint32_t dw5rsvd1:16;
 776                 uint32_t ring_size:4;
 777                 uint32_t dw5rsvd2:2;
 778                 uint32_t cq_id:10;
 779                 /* dw3 */
 780                 uint32_t dw6rsvd1:31;
 781                 uint32_t valid:1;
 782                 /* dw4 */
 783                 uint32_t async_cq_valid:1;
 784                 uint32_t async_cq_id:10;
 785                 uint32_t dw7rsvd1:21;
 786         #endif
 787                 /* dw5 */
 788                 uint32_t dw8rsvd1;
 789         } v0;
 790                 struct {
 791         #ifdef _BIG_ENDIAN
 792                 /* dw0 */
 793                 uint32_t cq_id:16;
 794                 uint32_t num_pages:16;
 795                 /* dw1 */
 796                 uint32_t async_evt_bitmap;
 797                 /* dw2 */
 798                 uint32_t dw5rsvd2:12;
 799                 uint32_t ring_size:4;
 800                 uint32_t async_cq_id:16;
 801                 /* dw3 */
 802                 uint32_t valid:1;
 803                 uint32_t dw6rsvd1:31;
 804                 /* dw4 */
 805                 uint32_t dw7rsvd1:31;
 806                 uint32_t async_cq_valid:1;
 807         #else
 808                 /* dw0 */
 809                 uint32_t num_pages:16;
 810                 uint32_t cq_id:16;
 811                 /* dw1 */
 812                 uint32_t async_evt_bitmap;
 813                 /* dw2 */
 814                 uint32_t async_cq_id:16;
 815                 uint32_t ring_size:4;
 816                 uint32_t dw5rsvd2:12;
 817                 /* dw3 */
 818                 uint32_t dw6rsvd1:31;
 819                 uint32_t valid:1;
 820                 /* dw4 */
 821                 uint32_t async_cq_valid:1;
 822                 uint32_t dw7rsvd1:31;
 823         #endif
 824                 /* dw5 */
 825                 uint32_t dw8rsvd1;
 826         } v1;
 827
 828 } oce_mq_ext_ctx_t;
 829
 830
 831 /* MQ mailbox structure */
 832 struct oce_bmbx {
 833         struct oce_mbx mbx;
 834         struct oce_mq_cqe cqe;
 835 };
 836
 837 /* ---[ MBXs start here ]---------------------------------------------- */
 838 /* MBXs sub system codes */
 839 enum MBX_SUBSYSTEM_CODES {
 840         MBX_SUBSYSTEM_RSVD = 0,
 841         MBX_SUBSYSTEM_COMMON = 1,
 842         MBX_SUBSYSTEM_COMMON_ISCSI = 2,
 843         MBX_SUBSYSTEM_NIC = 3,
 844         MBX_SUBSYSTEM_TOE = 4,
 845         MBX_SUBSYSTEM_PXE_UNDI = 5,
 846         MBX_SUBSYSTEM_ISCSI_INI = 6,
 847         MBX_SUBSYSTEM_ISCSI_TGT = 7,
 848         MBX_SUBSYSTEM_MILI_PTL = 8,
 849         MBX_SUBSYSTEM_MILI_TMD = 9,
 850         MBX_SUBSYSTEM_RDMA = 10,
 851         MBX_SUBSYSTEM_LOWLEVEL = 11,
 852         MBX_SUBSYSTEM_LRO = 13,
 853         IOCBMBX_SUBSYSTEM_DCBX = 15,
 854         IOCBMBX_SUBSYSTEM_DIAG = 16,
 855         IOCBMBX_SUBSYSTEM_VENDOR = 17
 856 };
 857
 858 /* common ioctl opcodes */
 859 enum COMMON_SUBSYSTEM_OPCODES {
 860 /* These opcodes are common to both networking and storage PCI functions
 861  * They are used to reserve resources and configure CNA. These opcodes
 862  * all use the MBX_SUBSYSTEM_COMMON subsystem code.
 863  */
 864         OPCODE_COMMON_QUERY_IFACE_MAC = 1,
 865         OPCODE_COMMON_SET_IFACE_MAC = 2,
 866         OPCODE_COMMON_SET_IFACE_MULTICAST = 3,
 867         OPCODE_COMMON_CONFIG_IFACE_VLAN = 4,
 868         OPCODE_COMMON_QUERY_LINK_CONFIG = 5,
 869         OPCODE_COMMON_READ_FLASHROM = 6,
 870         OPCODE_COMMON_WRITE_FLASHROM = 7,
 871         OPCODE_COMMON_QUERY_MAX_MBX_BUFFER_SIZE = 8,
 872         OPCODE_COMMON_CREATE_CQ = 12,
 873         OPCODE_COMMON_CREATE_EQ = 13,
 874         OPCODE_COMMON_CREATE_MQ = 21,
 875         OPCODE_COMMON_GET_QOS = 27,
 876         OPCODE_COMMON_SET_QOS = 28,
 877         OPCODE_COMMON_READ_EPROM = 30,
 878         OPCODE_COMMON_GET_CNTL_ATTRIBUTES = 32,
 879         OPCODE_COMMON_NOP = 33,
 880         OPCODE_COMMON_SET_IFACE_RX_FILTER = 34,
 881         OPCODE_COMMON_GET_FW_VERSION = 35,
 882         OPCODE_COMMON_SET_FLOW_CONTROL = 36,
 883         OPCODE_COMMON_GET_FLOW_CONTROL = 37,
 884         OPCODE_COMMON_SET_FRAME_SIZE = 39,
 885         OPCODE_COMMON_MODIFY_EQ_DELAY = 41,
 886         OPCODE_COMMON_CREATE_IFACE = 50,
 887         OPCODE_COMMON_DESTROY_IFACE = 51,
 888         OPCODE_COMMON_MODIFY_MSI_MESSAGES = 52,
 889         OPCODE_COMMON_DESTROY_MQ = 53,
 890         OPCODE_COMMON_DESTROY_CQ = 54,
 891         OPCODE_COMMON_DESTROY_EQ = 55,
 892         OPCODE_COMMON_UPLOAD_TCP = 56,
 893         OPCODE_COMMON_SET_NTWK_LINK_SPEED = 57,
 894         OPCODE_COMMON_QUERY_FIRMWARE_CONFIG = 58,
 895         OPCODE_COMMON_ADD_IFACE_MAC = 59,
 896         OPCODE_COMMON_DEL_IFACE_MAC = 60,
 897         OPCODE_COMMON_FUNCTION_RESET = 61,
 898         OPCODE_COMMON_SET_PHYSICAL_LINK_CONFIG = 62,
 899         OPCODE_COMMON_GET_BOOT_CONFIG = 66,
 900         OPCPDE_COMMON_SET_BOOT_CONFIG = 67,
 901         OPCODE_COMMON_SET_BEACON_CONFIG = 69,
 902         OPCODE_COMMON_GET_BEACON_CONFIG = 70,
 903         OPCODE_COMMON_GET_PHYSICAL_LINK_CONFIG = 71,
 904         OPCODE_COMMON_READ_TRANSRECEIVER_DATA = 73,
 905         OPCODE_COMMON_GET_OEM_ATTRIBUTES = 76,
 906         OPCODE_COMMON_GET_PORT_NAME = 77,
 907         OPCODE_COMMON_GET_CONFIG_SIGNATURE = 78,
 908         OPCODE_COMMON_SET_CONFIG_SIGNATURE = 79,
 909         OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG = 80,
 910         OPCODE_COMMON_GET_BE_CONFIGURATION_RESOURCES = 81,
 911         OPCODE_COMMON_SET_BE_CONFIGURATION_RESOURCES = 82,
 912         OPCODE_COMMON_GET_RESET_NEEDED = 84,
 913         OPCODE_COMMON_GET_SERIAL_NUMBER = 85,
 914         OPCODE_COMMON_GET_NCSI_CONFIG = 86,
 915         OPCODE_COMMON_SET_NCSI_CONFIG = 87,
 916         OPCODE_COMMON_CREATE_MQ_EXT = 90,
 917         OPCODE_COMMON_SET_FUNCTION_PRIVILEGES = 100,
 918         OPCODE_COMMON_SET_VF_PORT_TYPE = 101,
 919         OPCODE_COMMON_GET_PHY_CONFIG = 102,
 920         OPCODE_COMMON_SET_FUNCTIONAL_CAPS = 103,
 921         OPCODE_COMMON_GET_ADAPTER_ID = 110,
 922         OPCODE_COMMON_GET_UPGRADE_FEATURES = 111,
 923         OPCODE_COMMON_GET_INSTALLED_FEATURES = 112,
 924         OPCODE_COMMON_GET_AVAIL_PERSONALITIES = 113,
 925         OPCODE_COMMON_GET_CONFIG_PERSONALITIES = 114,
 926         OPCODE_COMMON_SEND_ACTIVATION = 115,
 927         OPCODE_COMMON_RESET_LICENSES = 116,
 928         OPCODE_COMMON_GET_CNTL_ADDL_ATTRIBUTES = 121,
 929         OPCODE_COMMON_QUERY_TCB = 144,
 930         OPCODE_COMMON_ADD_IFACE_QUEUE_FILTER = 145,
 931         OPCODE_COMMON_DEL_IFACE_QUEUE_FILTER = 146,
 932         OPCODE_COMMON_GET_IFACE_MAC_LIST = 147,
 933         OPCODE_COMMON_SET_IFACE_MAC_LIST = 148,
 934         OPCODE_COMMON_MODIFY_CQ = 149,
 935         OPCODE_COMMON_GET_IFACE_VLAN_LIST = 150,
 936         OPCODE_COMMON_SET_IFACE_VLAN_LIST = 151,
 937         OPCODE_COMMON_GET_HSW_CONFIG = 152,
 938         OPCODE_COMMON_SET_HSW_CONFIG = 153,
 939         OPCODE_COMMON_GET_RESOURCE_EXTENT_INFO = 154,
 940         OPCODE_COMMON_GET_ALLOCATED_RESOURCE_EXTENTS = 155,
 941         OPCODE_COMMON_ALLOC_RESOURCE_EXTENTS = 156,
 942         OPCODE_COMMON_DEALLOC_RESOURCE_EXTENTS = 157,
 943         OPCODE_COMMON_SET_DIAG_REGISTERS = 158,
 944         OPCODE_COMMON_GET_FUNCTION_CONFIG = 160,
 945         OPCODE_COMMON_GET_PROFILE_CAPACITIES = 161,
 946         OPCODE_COMMON_GET_MR_PROFILE_CAPACITIES = 162,
 947         OPCODE_COMMON_SET_MR_PROFILE_CAPACITIES = 163,
 948         OPCODE_COMMON_GET_PROFILE_CONFIG = 164,
 949         OPCODE_COMMON_SET_PROFILE_CONFIG = 165,
 950         OPCODE_COMMON_GET_PROFILE_LIST = 166,
 951         OPCODE_COMMON_GET_ACTIVE_PROFILE = 167,
 952         OPCODE_COMMON_SET_ACTIVE_PROFILE = 168,
 953         OPCODE_COMMON_GET_FUNCTION_PRIVILEGES = 170,
 954         OPCODE_COMMON_READ_OBJECT = 171,
 955         OPCODE_COMMON_WRITE_OBJECT = 172
 956 };
 957
 958 /* common ioctl header */
 959 #define OCE_MBX_VER_V2  0x0002          /* Version V2 mailbox command */
 960 #define OCE_MBX_VER_V1  0x0001          /* Version V1 mailbox command */
 961 #define OCE_MBX_VER_V0  0x0000          /* Version V0 mailbox command */
 962 struct mbx_hdr {
 963         union {
 964                 uint32_t dw[4];
 965                 struct {
 966                 #ifdef _BIG_ENDIAN
 967                         /* dw 0 */
 968                         uint32_t domain:8;
 969                         uint32_t port_number:8;
 970                         uint32_t subsystem:8;
 971                         uint32_t opcode:8;
 972                         /* dw 1 */
 973                         uint32_t timeout;
 974                         /* dw 2 */
 975                         uint32_t request_length;
 976                         /* dw 3 */
 977                         uint32_t rsvd0:24;
 978                         uint32_t version:8;
 979                 #else
 980                         /* dw 0 */
 981                         uint32_t opcode:8;
 982                         uint32_t subsystem:8;
 983                         uint32_t port_number:8;
 984                         uint32_t domain:8;
 985                         /* dw 1 */
 986                         uint32_t timeout;
 987                         /* dw 2 */
 988                         uint32_t request_length;
 989                         /* dw 3 */
 990                         uint32_t version:8;
 991                         uint32_t rsvd0:24;
 992                 #endif
 993                 } req;
 994                 struct {
 995                 #ifdef _BIG_ENDIAN
 996                         /* dw 0 */
 997                         uint32_t domain:8;
 998                         uint32_t rsvd0:8;
 999                         uint32_t subsystem:8;
1000                         uint32_t opcode:8;
1001                         /* dw 1 */
1002                         uint32_t rsvd1:16;
1003                         uint32_t additional_status:8;
1004                         uint32_t status:8;
1005                 #else
1006                         /* dw 0 */
1007                         uint32_t opcode:8;
1008                         uint32_t subsystem:8;
1009                         uint32_t rsvd0:8;
1010                         uint32_t domain:8;
1011                         /* dw 1 */
1012                         uint32_t status:8;
1013                         uint32_t additional_status:8;
1014                         uint32_t rsvd1:16;
1015                 #endif
1016                         uint32_t rsp_length;
1017                         uint32_t actual_rsp_length;
1018                 } rsp;
1019         } u0;
1020 };
1021 #define OCE_BMBX_RHDR_SZ 20
1022 #define OCE_MBX_RRHDR_SZ sizeof (struct mbx_hdr)
1023 #define OCE_MBX_ADDL_STATUS(_MHDR) ((_MHDR)->u0.rsp.additional_status)
1024 #define OCE_MBX_STATUS(_MHDR) ((_MHDR)->u0.rsp.status)
1025
1026 /* [05] OPCODE_COMMON_QUERY_LINK_CONFIG */
1027 struct mbx_query_common_link_config {
1028         struct mbx_hdr hdr;
1029         union {
1030                 struct {
1031                         uint32_t rsvd0;
1032                 } req;
1033
1034                 struct {
1035                         /* dw 0 */
1036                         uint8_t physical_port;
1037                         uint8_t mac_duplex;
1038                         uint8_t mac_speed;
1039                         uint8_t mac_fault;
1040                         /* dw 1 */
1041                         uint8_t mgmt_mac_duplex;
1042                         uint8_t mgmt_mac_speed;
1043                         uint16_t qos_link_speed;
1044                         uint32_t logical_link_status;
1045                 } rsp;
1046         } params;
1047 };
1048
1049 /* [57] OPCODE_COMMON_SET_LINK_SPEED */
1050 struct mbx_set_common_link_speed {
1051         struct mbx_hdr hdr;
1052         union {
1053                 struct {
1054 #ifdef _BIG_ENDIAN
1055                         uint8_t rsvd0;
1056                         uint8_t mac_speed;
1057                         uint8_t virtual_port;
1058                         uint8_t physical_port;
1059 #else
1060                         uint8_t physical_port;
1061                         uint8_t virtual_port;
1062                         uint8_t mac_speed;
1063                         uint8_t rsvd0;
1064 #endif
1065                 } req;
1066
1067                 struct {
1068                         uint32_t rsvd0;
1069                 } rsp;
1070
1071                 uint32_t dw;
1072         } params;
1073 };
1074
1075 struct mac_address_format {
1076         uint16_t size_of_struct;
1077         uint8_t mac_addr[6];
1078 };
1079
1080 /* [01] OPCODE_COMMON_QUERY_IFACE_MAC */
1081 struct mbx_query_common_iface_mac {
1082         struct mbx_hdr hdr;
1083         union {
1084                 struct {
1085 #ifdef _BIG_ENDIAN
1086                         uint16_t if_id;
1087                         uint8_t permanent;
1088                         uint8_t type;
1089 #else
1090                         uint8_t type;
1091                         uint8_t permanent;
1092                         uint16_t if_id;
1093 #endif
1094
1095                 } req;
1096
1097                 struct {
1098                         struct mac_address_format mac;
1099                 } rsp;
1100         } params;
1101 };
1102
1103 /* [02] OPCODE_COMMON_SET_IFACE_MAC */
1104 struct mbx_set_common_iface_mac {
1105         struct mbx_hdr hdr;
1106         union {
1107                 struct {
1108 #ifdef _BIG_ENDIAN
1109                         /* dw 0 */
1110                         uint16_t if_id;
1111                         uint8_t invalidate;
1112                         uint8_t type;
1113 #else
1114                         /* dw 0 */
1115                         uint8_t type;
1116                         uint8_t invalidate;
1117                         uint16_t if_id;
1118 #endif
1119                         /* dw 1 */
1120                         struct mac_address_format mac;
1121                 } req;
1122
1123                 struct {
1124                         uint32_t rsvd0;
1125                 } rsp;
1126
1127                 uint32_t dw[2];
1128         } params;
1129 };
1130
1131 /* [03] OPCODE_COMMON_SET_IFACE_MULTICAST */
1132 struct mbx_set_common_iface_multicast {
1133         struct mbx_hdr hdr;
1134         union {
1135                 struct {
1136                         /* dw 0 */
1137                         uint16_t num_mac;
1138                         uint8_t promiscuous;
1139                         uint8_t if_id;
1140                         /* dw 1-48 */
1141                         struct {
1142                                 uint8_t byte[6];
1143                         } mac[32];
1144
1145                 } req;
1146
1147                 struct {
1148                         uint32_t rsvd0;
1149                 } rsp;
1150
1151                 uint32_t dw[49];
1152         } params;
1153 };
1154
1155 struct qinq_vlan {
1156 #ifdef _BIG_ENDIAN
1157         uint16_t inner;
1158         uint16_t outer;
1159 #else
1160         uint16_t outer;
1161         uint16_t inner;
1162 #endif
1163 };
1164
1165 struct normal_vlan {
1166         uint16_t vtag;
1167 };
1168
1169 struct ntwk_if_vlan_tag {
1170         union {
1171                 struct normal_vlan normal;
1172                 struct qinq_vlan qinq;
1173         } u0;
1174 };
1175
1176 /* [50] OPCODE_COMMON_CREATE_IFACE */
1177 struct mbx_create_common_iface {
1178         struct mbx_hdr hdr;
1179         union {
1180                 struct {
1181                         uint32_t version;
1182                         uint32_t cap_flags;
1183                         uint32_t enable_flags;
1184                         uint8_t mac_addr[6];
1185                         uint8_t rsvd0;
1186                         uint8_t mac_invalid;
1187                         struct ntwk_if_vlan_tag vlan_tag;
1188                 } req;
1189
1190                 struct {
1191                         uint32_t if_id;
1192                         uint32_t pmac_id;
1193                 } rsp;
1194                 uint32_t dw[4];
1195         } params;
1196 };
1197
1198 /* [51] OPCODE_COMMON_DESTROY_IFACE */
1199 struct mbx_destroy_common_iface {
1200         struct mbx_hdr hdr;
1201         union {
1202                 struct {
1203                         uint32_t if_id;
1204                 } req;
1205
1206                 struct {
1207                         uint32_t rsvd0;
1208                 } rsp;
1209
1210                 uint32_t dw;
1211         } params;
1212 };
1213
1214 /* event queue context structure */
1215 struct oce_eq_ctx {
1216 #ifdef _BIG_ENDIAN
1217         uint32_t dw4rsvd1:16;
1218         uint32_t num_pages:16;
1219
1220         uint32_t size:1;
1221         uint32_t dw5rsvd2:1;
1222         uint32_t valid:1;
1223         uint32_t dw5rsvd1:29;
1224
1225         uint32_t armed:1;
1226         uint32_t dw6rsvd2:2;
1227         uint32_t count:3;
1228         uint32_t dw6rsvd1:26;
1229
1230         uint32_t dw7rsvd2:9;
1231         uint32_t delay_mult:10;
1232         uint32_t dw7rsvd1:13;
1233
1234         uint32_t dw8rsvd1;
1235 #else
1236         uint32_t num_pages:16;
1237         uint32_t dw4rsvd1:16;
1238
1239         uint32_t dw5rsvd1:29;
1240         uint32_t valid:1;
1241         uint32_t dw5rsvd2:1;
1242         uint32_t size:1;
1243
1244         uint32_t dw6rsvd1:26;
1245         uint32_t count:3;
1246         uint32_t dw6rsvd2:2;
1247         uint32_t armed:1;
1248
1249         uint32_t dw7rsvd1:13;
1250         uint32_t delay_mult:10;
1251         uint32_t dw7rsvd2:9;
1252
1253         uint32_t dw8rsvd1;
1254 #endif
1255 };
1256
1257 /* [13] OPCODE_COMMON_CREATE_EQ */
1258 struct mbx_create_common_eq {
1259         struct mbx_hdr hdr;
1260         union {
1261                 struct {
1262                         struct oce_eq_ctx ctx;
1263                         struct phys_addr pages[8];
1264                 } req;
1265
1266                 struct {
1267                         uint16_t eq_id;
1268                         uint16_t rsvd0;
1269                 } rsp;
1270         } params;
1271 };
1272
1273 /* [55] OPCODE_COMMON_DESTROY_EQ */
1274 struct mbx_destroy_common_eq {
1275         struct mbx_hdr hdr;
1276         union {
1277                 struct {
1278 #ifdef _BIG_ENDIAN
1279                         uint16_t rsvd0;
1280                         uint16_t id;
1281 #else
1282                         uint16_t id;
1283                         uint16_t rsvd0;
1284 #endif
1285                 } req;
1286
1287                 struct {
1288                         uint32_t rsvd0;
1289                 } rsp;
1290         } params;
1291 };
1292
1293 /* SLI-4 CQ context - use version V0 for B3, version V2 for Lancer */
1294 typedef union oce_cq_ctx_u {
1295         uint32_t dw[5];
1296         struct {
1297         #ifdef _BIG_ENDIAN
1298                 /* dw4 */
1299                 uint32_t dw4rsvd1:16;
1300                 uint32_t num_pages:16;
1301                 /* dw5 */
1302                 uint32_t eventable:1;
1303                 uint32_t dw5rsvd3:1;
1304                 uint32_t valid:1;
1305                 uint32_t count:2;
1306                 uint32_t dw5rsvd2:12;
1307                 uint32_t nodelay:1;
1308                 uint32_t coalesce_wm:2;
1309                 uint32_t dw5rsvd1:12;
1310                 /* dw6 */
1311                 uint32_t armed:1;
1312                 uint32_t dw6rsvd2:1;
1313                 uint32_t eq_id:8;
1314                 uint32_t dw6rsvd1:22;
1315         #else
1316                 /* dw4 */
1317                 uint32_t num_pages:16;
1318                 uint32_t dw4rsvd1:16;
1319                 /* dw5 */
1320                 uint32_t dw5rsvd1:12;
1321                 uint32_t coalesce_wm:2;
1322                 uint32_t nodelay:1;
1323                 uint32_t dw5rsvd2:12;
1324                 uint32_t count:2;
1325                 uint32_t valid:1;
1326                 uint32_t dw5rsvd3:1;
1327                 uint32_t eventable:1;
1328                 /* dw6 */
1329                 uint32_t dw6rsvd1:22;
1330                 uint32_t eq_id:8;
1331                 uint32_t dw6rsvd2:1;
1332                 uint32_t armed:1;
1333         #endif
1334                 /* dw7 */
1335                 uint32_t dw7rsvd1;
1336                 /* dw8 */
1337                 uint32_t dw8rsvd1;
1338         } v0;
1339         struct {
1340         #ifdef _BIG_ENDIAN
1341                 /* dw4 */
1342                 uint32_t dw4rsvd1:8;
1343                 uint32_t page_size:8;
1344                 uint32_t num_pages:16;
1345                 /* dw5 */
1346                 uint32_t eventable:1;
1347                 uint32_t dw5rsvd3:1;
1348                 uint32_t valid:1;
1349                 uint32_t count:2;
1350                 uint32_t dw5rsvd2:11;
1351                 uint32_t autovalid:1;
1352                 uint32_t nodelay:1;
1353                 uint32_t coalesce_wm:2;
1354                 uint32_t dw5rsvd1:12;
1355                 /* dw6 */
1356                 uint32_t armed:1;
1357                 uint32_t dw6rsvd1:15;
1358                 uint32_t eq_id:16;
1359                 /* dw7 */
1360                 uint32_t dw7rsvd1:16;
1361                 uint32_t cqe_count:16;
1362         #else
1363                 /* dw4 */
1364                 uint32_t num_pages:16;
1365                 uint32_t page_size:8;
1366                 uint32_t dw4rsvd1:8;
1367                 /* dw5 */
1368                 uint32_t dw5rsvd1:12;
1369                 uint32_t coalesce_wm:2;
1370                 uint32_t nodelay:1;
1371                 uint32_t autovalid:1;
1372                 uint32_t dw5rsvd2:11;
1373                 uint32_t count:2;
1374                 uint32_t valid:1;
1375                 uint32_t dw5rsvd3:1;
1376                 uint32_t eventable:1;
1377                 /* dw6 */
1378                 uint32_t eq_id:8;
1379                 uint32_t dw6rsvd1:15;
1380                 uint32_t armed:1;
1381                 /* dw7 */
1382                 uint32_t cqe_count:16;
1383                 uint32_t dw7rsvd1:16;
1384         #endif
1385                 /* dw8 */
1386                 uint32_t dw8rsvd1;
1387         } v2;
1388 } oce_cq_ctx_t;
1389
1390 /* [12] OPCODE_COMMON_CREATE_CQ */
1391 struct mbx_create_common_cq {
1392         struct mbx_hdr hdr;
1393         union {
1394                 struct {
1395                         oce_cq_ctx_t cq_ctx;
1396                         struct phys_addr pages[4];
1397                 } req;
1398
1399                 struct {
1400                         uint16_t cq_id;
1401                         uint16_t rsvd0;
1402                 } rsp;
1403         } params;
1404 };
1405
1406 /* [54] OPCODE_COMMON_DESTROY_CQ */
1407 struct mbx_destroy_common_cq {
1408         struct mbx_hdr hdr;
1409         union {
1410                 struct {
1411 #ifdef _BIG_ENDIAN
1412                         uint16_t rsvd0;
1413                         uint16_t id;
1414 #else
1415                         uint16_t id;
1416                         uint16_t rsvd0;
1417 #endif
1418                 } req;
1419
1420                 struct {
1421                         uint32_t rsvd0;
1422                 } rsp;
1423         } params;
1424 };
1425
1426 typedef union oce_mq_ctx_u {
1427         uint32_t dw[5];
1428         struct {
1429         #ifdef _BIG_ENDIAN
1430                 /* dw4 */
1431                 uint32_t dw4rsvd1:16;
1432                 uint32_t num_pages:16;
1433                 /* dw5 */
1434                 uint32_t cq_id:10;
1435                 uint32_t dw5rsvd2:2;
1436                 uint32_t ring_size:4;
1437                 uint32_t dw5rsvd1:16;
1438                 /* dw6 */
1439                 uint32_t valid:1;
1440                 uint32_t dw6rsvd1:31;
1441                 /* dw7 */
1442                 uint32_t dw7rsvd1:21;
1443                 uint32_t async_cq_id:10;
1444                 uint32_t async_cq_valid:1;
1445         #else
1446                 /* dw4 */
1447                 uint32_t num_pages:16;
1448                 uint32_t dw4rsvd1:16;
1449                 /* dw5 */
1450                 uint32_t dw5rsvd1:16;
1451                 uint32_t ring_size:4;
1452                 uint32_t dw5rsvd2:2;
1453                 uint32_t cq_id:10;
1454                 /* dw6 */
1455                 uint32_t dw6rsvd1:31;
1456                 uint32_t valid:1;
1457                 /* dw7 */
1458                 uint32_t async_cq_valid:1;
1459                 uint32_t async_cq_id:10;
1460                 uint32_t dw7rsvd1:21;
1461         #endif
1462                 /* dw8 */
1463                 uint32_t dw8rsvd1;
1464         } v0;
1465 } oce_mq_ctx_t;
1466
1467 /**
1468  * @brief [21] OPCODE_COMMON_CREATE_MQ
1469  * A MQ must be at least 16 entries deep (corresponding to 1 page) and
1470  * at most 128 entries deep (corresponding to 8 pages).
1471  */
1472 struct mbx_create_common_mq {
1473         struct mbx_hdr hdr;
1474         union {
1475                 struct {
1476                         oce_mq_ctx_t context;
1477                         struct phys_addr pages[8];
1478                 } req;
1479
1480                 struct {
1481                         uint32_t mq_id:16;
1482                         uint32_t rsvd0:16;
1483                 } rsp;
1484         } params;
1485 };
1486
1487 struct mbx_create_common_mq_ex {
1488         struct mbx_hdr hdr;
1489         union {
1490                 struct {
1491                         oce_mq_ext_ctx_t context;
1492                         struct phys_addr pages[8];
1493                 } req;
1494
1495                 struct {
1496                         uint32_t mq_id:16;
1497                         uint32_t rsvd0:16;
1498                 } rsp;
1499         } params;
1500 };
1501
1502
1503
1504 /* [53] OPCODE_COMMON_DESTROY_MQ */
1505 struct mbx_destroy_common_mq {
1506         struct mbx_hdr hdr;
1507         union {
1508                 struct {
1509 #ifdef _BIG_ENDIAN
1510                         uint16_t rsvd0;
1511                         uint16_t id;
1512 #else
1513                         uint16_t id;
1514                         uint16_t rsvd0;
1515 #endif
1516                 } req;
1517
1518                 struct {
1519                         uint32_t rsvd0;
1520                 } rsp;
1521         } params;
1522 };
1523
1524 /* [35] OPCODE_COMMON_GET_ FW_VERSION */
1525 struct mbx_get_common_fw_version {
1526         struct mbx_hdr hdr;
1527         union {
1528                 struct {
1529                         uint32_t rsvd0;
1530                 } req;
1531
1532                 struct {
1533                         uint8_t fw_ver_str[32];
1534                         uint8_t fw_on_flash_ver_str[32];
1535                 } rsp;
1536         } params;
1537 };
1538
1539 /* [52] OPCODE_COMMON_CEV_MODIFY_MSI_MESSAGES */
1540 struct mbx_common_cev_modify_msi_messages {
1541         struct mbx_hdr hdr;
1542         union {
1543                 struct {
1544                         uint32_t num_msi_msgs;
1545                 } req;
1546
1547                 struct {
1548                         uint32_t rsvd0;
1549                 } rsp;
1550         } params;
1551 };
1552
1553 /* [36] OPCODE_COMMON_SET_FLOW_CONTROL */
1554 /* [37] OPCODE_COMMON_GET_FLOW_CONTROL */
1555 struct mbx_common_get_set_flow_control {
1556         struct mbx_hdr hdr;
1557 #ifdef _BIG_ENDIAN
1558         uint16_t tx_flow_control;
1559         uint16_t rx_flow_control;
1560 #else
1561         uint16_t rx_flow_control;
1562         uint16_t tx_flow_control;
1563 #endif
1564 };
1565
1566 enum e_flash_opcode {
1567         MGMT_FLASHROM_OPCODE_FLASH = 1,
1568         MGMT_FLASHROM_OPCODE_SAVE = 2
1569 };
1570
1571 /* [06] OPCODE_READ_COMMON_FLASHROM */
1572 /* [07] OPCODE_WRITE_COMMON_FLASHROM */
1573
1574 struct mbx_common_read_write_flashrom {
1575         struct mbx_hdr hdr;
1576         uint32_t flash_op_code;
1577         uint32_t flash_op_type;
1578         uint32_t data_buffer_size;
1579         uint32_t data_offset;
1580         uint8_t  data_buffer[4];        /* + IMAGE_TRANSFER_SIZE */
1581 };
1582
1583 struct oce_phy_info {
1584         uint16_t phy_type;
1585         uint16_t interface_type;
1586         uint32_t misc_params;
1587         uint16_t ext_phy_details;
1588         uint16_t rsvd;
1589         uint16_t auto_speeds_supported;
1590         uint16_t fixed_speeds_supported;
1591         uint32_t future_use[2];
1592 };
1593
1594 struct mbx_common_phy_info {
1595         struct mbx_hdr hdr;
1596         union {
1597                 struct {
1598                         uint32_t rsvd0[4];
1599                 } req;
1600                 struct {
1601                         struct oce_phy_info phy_info;
1602                 } rsp;
1603         } params;
1604 };
1605
1606 /*Lancer firmware*/
1607
1608 struct mbx_lancer_common_write_object {
1609         union {
1610                 struct {
1611                         struct   mbx_hdr hdr;
1612                         uint32_t write_length: 24;
1613                         uint32_t rsvd: 7;
1614                         uint32_t eof: 1;
1615                         uint32_t write_offset;
1616                         uint8_t  object_name[104];
1617                         uint32_t descriptor_count;
1618                         uint32_t buffer_length;
1619                         uint32_t address_lower;
1620                         uint32_t address_upper;
1621                 } req;
1622                 struct {
1623                         uint8_t  opcode;
1624                         uint8_t  subsystem;
1625                         uint8_t  rsvd1[2];
1626                         uint8_t  status;
1627                         uint8_t  additional_status;
1628                         uint8_t  rsvd2[2];
1629                         uint32_t response_length;
1630                         uint32_t actual_response_length;
1631                         uint32_t actual_write_length;
1632                 } rsp;
1633         } params;
1634 };
1635
1636 /**
1637  * @brief MBX Common Quiery Firmaware Config
1638  * This command retrieves firmware configuration parameters and adapter
1639  * resources available to the driver originating the request. The firmware
1640  * configuration defines supported protocols by the installed adapter firmware.
1641  * This includes which ULP processors support the specified protocols and
1642  * the number of TCP connections allowed for that protocol.
1643  */
1644 struct mbx_common_query_fw_config {
1645         struct mbx_hdr hdr;
1646         union {
1647                 struct {
1648                         uint32_t rsvd0[30];
1649                 } req;
1650
1651                 struct {
1652                         uint32_t config_number;
1653                         uint32_t asic_revision;
1654                         uint32_t port_id;       /* used for stats retrieval */
1655                         uint32_t function_mode;
1656                         struct {
1657
1658                                 uint32_t ulp_mode;
1659                                 uint32_t nic_wqid_base;
1660                                 uint32_t nic_wq_tot;
1661                                 uint32_t toe_wqid_base;
1662                                 uint32_t toe_wq_tot;
1663                                 uint32_t toe_rqid_base;
1664                                 uint32_t toe_rqid_tot;
1665                                 uint32_t toe_defrqid_base;
1666                                 uint32_t toe_defrqid_count;
1667                                 uint32_t lro_rqid_base;
1668                                 uint32_t lro_rqid_tot;
1669                                 uint32_t iscsi_icd_base;
1670                                 uint32_t iscsi_icd_count;
1671                         } ulp[2];
1672                         uint32_t function_caps;
1673                         uint32_t cqid_base;
1674                         uint32_t cqid_tot;
1675                         uint32_t eqid_base;
1676                         uint32_t eqid_tot;
1677                 } rsp;
1678         } params;
1679 };
1680
1681 enum CQFW_CONFIG_NUMBER {
1682         FCN_NIC_ISCSI_Initiator = 0x0,
1683         FCN_ISCSI_Target = 0x3,
1684         FCN_FCoE = 0x7,
1685         FCN_ISCSI_Initiator_Target = 0x9,
1686         FCN_NIC_RDMA_TOE = 0xA,
1687         FCN_NIC_RDMA_FCoE = 0xB,
1688         FCN_NIC_RDMA_iSCSI = 0xC,
1689         FCN_NIC_iSCSI_FCoE = 0xD
1690 };
1691
1692 /**
1693  * @brief Function Capabilites
1694  * This field contains the flags indicating the capabilities of
1695  * the SLI Host’s PCI function.
1696  */
1697 enum CQFW_FUNCTION_CAPABILITIES {
1698         FNC_UNCLASSIFIED_STATS = 0x1,
1699         FNC_RSS = 0x2,
1700         FNC_PROMISCUOUS = 0x4,
1701         FNC_LEGACY_MODE = 0x8,
1702         FNC_HDS = 0x4000,
1703         FNC_VMQ = 0x10000,
1704         FNC_NETQ = 0x20000,
1705         FNC_QGROUPS = 0x40000,
1706         FNC_LRO = 0x100000,
1707         FNC_VLAN_OFFLOAD = 0x800000
1708 };
1709
1710 enum CQFW_ULP_MODES_SUPPORTED {
1711         ULP_TOE_MODE = 0x1,
1712         ULP_NIC_MODE = 0x2,
1713         ULP_RDMA_MODE = 0x4,
1714         ULP_ISCSI_INI_MODE = 0x10,
1715         ULP_ISCSI_TGT_MODE = 0x20,
1716         ULP_FCOE_INI_MODE = 0x40,
1717         ULP_FCOE_TGT_MODE = 0x80,
1718         ULP_DAL_MODE = 0x100,
1719         ULP_LRO_MODE = 0x200
1720 };
1721
1722 /**
1723  * @brief Function Modes Supported
1724  * Valid function modes (or protocol-types) supported on the SLI-Host’s
1725  * PCIe function.  This field is a logical OR of the following values:
1726  */
1727 enum CQFW_FUNCTION_MODES_SUPPORTED {
1728         FNM_TOE_MODE = 0x1,             /* TCP offload supported */
1729         FNM_NIC_MODE = 0x2,             /* Raw Ethernet supported */
1730         FNM_RDMA_MODE = 0x4,            /* RDMA protocol supported */
1731         FNM_VM_MODE = 0x8,              /* Virtual Machines supported  */
1732         FNM_ISCSI_INI_MODE = 0x10,      /* iSCSI initiator supported */
1733         FNM_ISCSI_TGT_MODE = 0x20,      /* iSCSI target plus initiator */
1734         FNM_FCOE_INI_MODE = 0x40,       /* FCoE Initiator supported */
1735         FNM_FCOE_TGT_MODE = 0x80,       /* FCoE target supported */
1736         FNM_DAL_MODE = 0x100,           /* DAL supported */
1737         FNM_LRO_MODE = 0x200,           /* LRO supported */
1738         FNM_FLEX10_MODE = 0x400,        /* QinQ, FLEX-10 or VNIC */
1739         FNM_NCSI_MODE = 0x800,          /* NCSI supported */
1740         FNM_IPV6_MODE = 0x1000,         /* IPV6 stack enabled */
1741         FNM_BE2_COMPAT_MODE = 0x2000,   /* BE2 compatibility (BE3 disable)*/
1742         FNM_INVALID_MODE = 0x8000,      /* Invalid */
1743         FNM_BE3_COMPAT_MODE = 0x10000,  /* BE3 features */
1744         FNM_VNIC_MODE = 0x20000,        /* Set when IBM vNIC mode is set */
1745         FNM_VNTAG_MODE = 0x40000,       /* Set when VNTAG mode is set */
1746         FNM_UMC_MODE = 0x1000000,       /* Set when UMC mode is set */
1747         FNM_UMC_DEF_EN = 0x100000,      /* Set when UMC Default is set */
1748         FNM_ONE_GB_EN = 0x200000,       /* Set when 1GB Default is set */
1749         FNM_VNIC_DEF_VALID = 0x400000,  /* Set when VNIC_DEF_EN is valid */
1750         FNM_VNIC_DEF_EN = 0x800000      /* Set when VNIC Default enabled */
1751 };
1752
1753
1754 struct mbx_common_config_vlan {
1755         struct mbx_hdr hdr;
1756         union {
1757                 struct {
1758 #ifdef _BIG_ENDIAN
1759                         uint8_t num_vlans;
1760                         uint8_t untagged;
1761                         uint8_t promisc;
1762                         uint8_t if_id;
1763 #else
1764                         uint8_t if_id;
1765                         uint8_t promisc;
1766                         uint8_t untagged;
1767                         uint8_t num_vlans;
1768 #endif
1769                         union {
1770                                 struct normal_vlan normal_vlans[64];
1771                                 struct qinq_vlan qinq_vlans[32];
1772                         } tags;
1773                 } req;
1774
1775                 struct {
1776                         uint32_t rsvd;
1777                 } rsp;
1778         } params;
1779 };
1780
1781 typedef struct iface_rx_filter_ctx {
1782         uint32_t global_flags_mask;
1783         uint32_t global_flags;
1784         uint32_t iface_flags_mask;
1785         uint32_t iface_flags;
1786         uint32_t if_id;
1787         #define IFACE_RX_NUM_MCAST_MAX          64
1788         uint32_t num_mcast;
1789         struct mbx_mcast_addr {
1790                 uint8_t byte[6];
1791         } mac[IFACE_RX_NUM_MCAST_MAX];
1792 } iface_rx_filter_ctx_t;
1793
1794 /* [34] OPCODE_COMMON_SET_IFACE_RX_FILTER */
1795 struct mbx_set_common_iface_rx_filter {
1796         struct mbx_hdr hdr;
1797         union {
1798                 iface_rx_filter_ctx_t req;
1799                 iface_rx_filter_ctx_t rsp;
1800         } params;
1801 };
1802
1803 struct be_set_eqd {
1804         uint32_t eq_id;
1805         uint32_t phase;
1806         uint32_t dm;
1807 };
1808
1809 /* [41] OPCODE_COMMON_MODIFY_EQ_DELAY */
1810 struct mbx_modify_common_eq_delay {
1811         struct mbx_hdr hdr;
1812         union {
1813                 struct {
1814                         uint32_t num_eq;
1815                         struct {
1816                                 uint32_t eq_id;
1817                                 uint32_t phase;
1818                                 uint32_t dm;
1819                         } delay[8];
1820                 } req;
1821
1822                 struct {
1823                         uint32_t rsvd0;
1824                 } rsp;
1825         } params;
1826 };
1827
1828 /* [32] OPCODE_COMMON_GET_CNTL_ATTRIBUTES */
1829
1830 struct mgmt_hba_attr {
1831         int8_t   flashrom_ver_str[32];
1832         int8_t   manufac_name[32];
1833         uint32_t supp_modes;
1834         int8_t   seeprom_ver_lo;
1835         int8_t   seeprom_ver_hi;
1836         int8_t   rsvd0[2];
1837         uint32_t ioctl_data_struct_ver;
1838         uint32_t ep_fw_data_struct_ver;
1839         uint8_t  ncsi_ver_str[12];
1840         uint32_t def_ext_to;
1841         int8_t   cntl_mod_num[32];
1842         int8_t   cntl_desc[64];
1843         int8_t   cntl_ser_num[32];
1844         int8_t   ip_ver_str[32];
1845         int8_t   fw_ver_str[32];
1846         int8_t   bios_ver_str[32];
1847         int8_t   redboot_ver_str[32];
1848         int8_t   drv_ver_str[32];
1849         int8_t   fw_on_flash_ver_str[32];
1850         uint32_t funcs_supp;
1851         uint16_t max_cdblen;
1852         uint8_t  asic_rev;
1853         uint8_t  gen_guid[16];
1854         uint8_t  hba_port_count;
1855         uint16_t default_link_down_timeout;
1856         uint8_t  iscsi_ver_min_max;
1857         uint8_t  multifunc_dev;
1858         uint8_t  cache_valid;
1859         uint8_t  hba_status;
1860         uint8_t  max_domains_supp;
1861         uint8_t  phy_port;
1862         uint32_t fw_post_status;
1863         uint32_t hba_mtu[8];
1864         uint8_t  iSCSI_feat;
1865         uint8_t  asic_gen;
1866         uint8_t  future_u8[2];
1867         uint32_t future_u32[3];
1868 };
1869
1870 struct mgmt_cntl_attr {
1871         struct    mgmt_hba_attr hba_attr;
1872         uint16_t  pci_vendor_id;
1873         uint16_t  pci_device_id;
1874         uint16_t  pci_sub_vendor_id;
1875         uint16_t  pci_sub_system_id;
1876         uint8_t   pci_bus_num;
1877         uint8_t   pci_dev_num;
1878         uint8_t   pci_func_num;
1879         uint8_t   interface_type;
1880         uint64_t  unique_id;
1881         uint8_t   netfilters;
1882         uint8_t   rsvd0[3];
1883         uint32_t  future_u32[4];
1884 };
1885
1886 struct mbx_common_get_cntl_attr {
1887         struct mbx_hdr hdr;
1888         union {
1889                 struct {
1890                         uint32_t rsvd0;
1891                 } req;
1892                 struct {
1893                         struct mgmt_cntl_attr cntl_attr_info;
1894                 } rsp;
1895         } params;
1896 };
1897
1898 /* [59] OPCODE_ADD_COMMON_IFACE_MAC */
1899 struct mbx_add_common_iface_mac {
1900         struct mbx_hdr hdr;
1901         union {
1902                 struct {
1903                         uint32_t if_id;
1904                         uint8_t mac_address[6];
1905                         uint8_t rsvd0[2];
1906                 } req;
1907                 struct {
1908                         uint32_t pmac_id;
1909                 } rsp;
1910         } params;
1911 };
1912
1913 /* [60] OPCODE_DEL_COMMON_IFACE_MAC */
1914 struct mbx_del_common_iface_mac {
1915         struct mbx_hdr hdr;
1916         union {
1917                 struct {
1918                         uint32_t if_id;
1919                         uint32_t pmac_id;
1920                 } req;
1921                 struct {
1922                         uint32_t rsvd0;
1923                 } rsp;
1924         } params;
1925 };
1926
1927 /* [8] OPCODE_QUERY_COMMON_MAX_MBX_BUFFER_SIZE */
1928 struct mbx_query_common_max_mbx_buffer_size {
1929         struct mbx_hdr hdr;
1930         struct {
1931                 uint32_t max_ioctl_bufsz;
1932         } rsp;
1933 };
1934
1935 /* [61] OPCODE_COMMON_FUNCTION_RESET */
1936 struct ioctl_common_function_reset {
1937         struct mbx_hdr hdr;
1938 };
1939
1940 /* [73] OPCODE_COMMON_READ_TRANSRECEIVER_DATA */
1941 struct mbx_read_common_transrecv_data {
1942         struct mbx_hdr hdr;
1943         union {
1944                 struct {
1945                         uint32_t    page_num;
1946                         uint32_t    port;
1947                 } req;
1948                 struct {
1949                         uint32_t    page_num;
1950                         uint32_t    port;
1951                         uint32_t    page_data[32];
1952                 } rsp;
1953         } params;
1954
1955 };
1956
1957 /* [80] OPCODE_COMMON_FUNCTION_LINK_CONFIG */
1958 struct mbx_common_func_link_cfg {
1959         struct mbx_hdr hdr;
1960         union {
1961                 struct {
1962                         uint32_t enable;
1963                 } req;
1964                 struct {
1965                         uint32_t rsvd0;
1966                 } rsp;
1967         } params;
1968 };
1969
1970 /* [103] OPCODE_COMMON_SET_FUNCTIONAL_CAPS */
1971 #define CAP_SW_TIMESTAMPS       2
1972 #define CAP_BE3_NATIVE_ERX_API  4
1973
1974 struct mbx_common_set_function_cap {
1975         struct mbx_hdr hdr;
1976         union {
1977                 struct {
1978                         uint32_t valid_capability_flags;
1979                         uint32_t capability_flags;
1980                         uint8_t  sbz[212];
1981                 } req;
1982                 struct {
1983                         uint32_t valid_capability_flags;
1984                         uint32_t capability_flags;
1985                         uint8_t  sbz[212];
1986                 } rsp;
1987         } params;
1988 };
1989 struct mbx_lowlevel_test_loopback_mode {
1990         struct mbx_hdr hdr;
1991         union {
1992                 struct {
1993                         uint32_t loopback_type;
1994                         uint32_t num_pkts;
1995                         uint64_t pattern;
1996                         uint32_t src_port;
1997                         uint32_t dest_port;
1998                         uint32_t pkt_size;
1999                 }req;
2000                 struct {
2001                         uint32_t    status;
2002                         uint32_t    num_txfer;
2003                         uint32_t    num_rx;
2004                         uint32_t    miscomp_off;
2005                         uint32_t    ticks_compl;
2006                 }rsp;
2007         } params;
2008 };
2009
2010 struct mbx_lowlevel_set_loopback_mode {
2011         struct mbx_hdr hdr;
2012         union {
2013                 struct {
2014                         uint8_t src_port;
2015                         uint8_t dest_port;
2016                         uint8_t loopback_type;
2017                         uint8_t loopback_state;
2018                 } req;
2019                 struct {
2020                         uint8_t rsvd0[4];
2021                 } rsp;
2022         } params;
2023 };
2024 #define MAX_RESC_DESC                           256
2025 #define RESC_DESC_SIZE                          88
2026 #define ACTIVE_PROFILE                          2
2027 #define NIC_RESC_DESC_TYPE_V0                   0x41
2028 #define NIC_RESC_DESC_TYPE_V1                   0x51
2029 /* OPCODE_COMMON_GET_FUNCTION_CONFIG */
2030 struct mbx_common_get_func_config {
2031         struct mbx_hdr hdr;
2032         union {
2033                 struct {
2034                         uint8_t rsvd;
2035                         uint8_t type;
2036                         uint16_t rsvd1;
2037                 } req;
2038                 struct {
2039                         uint32_t desc_count;
2040                         uint8_t resources[MAX_RESC_DESC * RESC_DESC_SIZE];
2041                 } rsp;
2042         } params;
2043 };
2044
2045
2046 /* OPCODE_COMMON_GET_PROFILE_CONFIG */
2047
2048 struct mbx_common_get_profile_config {
2049         struct mbx_hdr hdr;
2050         union {
2051                 struct {
2052                         uint8_t rsvd;
2053                         uint8_t type;
2054                         uint16_t rsvd1;
2055                 } req;
2056                 struct {
2057                         uint32_t desc_count;
2058                         uint8_t resources[MAX_RESC_DESC * RESC_DESC_SIZE];
2059                 } rsp;
2060         } params;
2061 };
2062
2063 struct oce_nic_resc_desc {
2064         uint8_t desc_type;
2065         uint8_t desc_len;
2066         uint8_t rsvd1;
2067         uint8_t flags;
2068         uint8_t vf_num;
2069         uint8_t rsvd2;
2070         uint8_t pf_num;
2071         uint8_t rsvd3;
2072         uint16_t unicast_mac_count;
2073         uint8_t rsvd4[6];
2074         uint16_t mcc_count;
2075         uint16_t vlan_count;
2076         uint16_t mcast_mac_count;
2077         uint16_t txq_count;
2078         uint16_t rq_count;
2079         uint16_t rssq_count;
2080         uint16_t lro_count;
2081         uint16_t cq_count;
2082         uint16_t toe_conn_count;
2083         uint16_t eq_count;
2084         uint32_t rsvd5;
2085         uint32_t cap_flags;
2086         uint8_t link_param;
2087         uint8_t rsvd6[3];
2088         uint32_t bw_min;
2089         uint32_t bw_max;
2090         uint8_t acpi_params;
2091         uint8_t wol_param;
2092         uint16_t rsvd7;
2093         uint32_t rsvd8[7];
2094
2095 };
2096
2097
2098 struct flash_file_hdr {
2099         uint8_t  sign[52];
2100         uint8_t  ufi_version[4];
2101         uint32_t file_len;
2102         uint32_t cksum;
2103         uint32_t antidote;
2104         uint32_t num_imgs;
2105         uint8_t  build[24];
2106         uint8_t  asic_type_rev;
2107         uint8_t  rsvd[31];
2108 };
2109
2110 struct image_hdr {
2111         uint32_t imageid;
2112         uint32_t imageoffset;
2113         uint32_t imagelength;
2114         uint32_t image_checksum;
2115         uint8_t  image_version[32];
2116 };
2117
2118 struct flash_section_hdr {
2119         uint32_t format_rev;
2120         uint32_t cksum;
2121         uint32_t antidote;
2122         uint32_t num_images;
2123         uint8_t  id_string[128];
2124         uint32_t rsvd[4];
2125 };
2126
2127 struct flash_section_entry {
2128         uint32_t type;
2129         uint32_t offset;
2130         uint32_t pad_size;
2131         uint32_t image_size;
2132         uint32_t cksum;
2133         uint32_t entry_point;
2134         uint32_t rsvd0;
2135         uint32_t rsvd1;
2136         uint8_t  ver_data[32];
2137 };
2138
2139 struct flash_sec_info {
2140         uint8_t cookie[32];
2141         struct  flash_section_hdr fsec_hdr;
2142         struct  flash_section_entry fsec_entry[32];
2143 };
2144
2145
2146 enum LOWLEVEL_SUBSYSTEM_OPCODES {
2147 /* Opcodes used for lowlevel functions common to many subystems.
2148  * Some of these opcodes are used for diagnostic functions only.
2149  * These opcodes use the MBX_SUBSYSTEM_LOWLEVEL subsystem code.
2150  */
2151         OPCODE_LOWLEVEL_TEST_LOOPBACK = 18,
2152         OPCODE_LOWLEVEL_SET_LOOPBACK_MODE = 19,
2153         OPCODE_LOWLEVEL_GET_LOOPBACK_MODE = 20
2154 };
2155
2156 enum LLDP_SUBSYSTEM_OPCODES {
2157 /* Opcodes used for LLDP susbsytem for configuring the LLDP state machines. */
2158         OPCODE_LLDP_GET_CFG = 1,
2159         OPCODE_LLDP_SET_CFG = 2,
2160         OPCODE_LLDP_GET_STATS = 3
2161 };
2162
2163 enum DCBX_SUBSYSTEM_OPCODES {
2164 /* Opcodes used for DCBX. */
2165         OPCODE_DCBX_GET_CFG = 1,
2166         OPCODE_DCBX_SET_CFG = 2,
2167         OPCODE_DCBX_GET_MIB_INFO = 3,
2168         OPCODE_DCBX_GET_DCBX_MODE = 4,
2169         OPCODE_DCBX_SET_MODE = 5
2170 };
2171
2172 enum DMTF_SUBSYSTEM_OPCODES {
2173 /* Opcodes used for DCBX subsystem. */
2174         OPCODE_DMTF_EXEC_CLP_CMD = 1
2175 };
2176
2177 enum DIAG_SUBSYSTEM_OPCODES {
2178 /* Opcodes used for diag functions common to many subsystems. */
2179         OPCODE_DIAG_RUN_DMA_TEST = 1,
2180         OPCODE_DIAG_RUN_MDIO_TEST = 2,
2181         OPCODE_DIAG_RUN_NLB_TEST = 3,
2182         OPCODE_DIAG_RUN_ARM_TIMER_TEST = 4,
2183         OPCODE_DIAG_GET_MAC = 5
2184 };
2185
2186 enum VENDOR_SUBSYSTEM_OPCODES {
2187 /* Opcodes used for Vendor subsystem. */
2188         OPCODE_VENDOR_SLI = 1
2189 };
2190
2191 /* Management Status Codes */
2192 enum MGMT_STATUS_SUCCESS {
2193         MGMT_SUCCESS = 0,
2194         MGMT_FAILED = 1,
2195         MGMT_ILLEGAL_REQUEST = 2,
2196         MGMT_ILLEGAL_FIELD = 3,
2197         MGMT_INSUFFICIENT_BUFFER = 4,
2198         MGMT_UNAUTHORIZED_REQUEST = 5,
2199         MGMT_INVALID_ISNS_ADDRESS = 10,
2200         MGMT_INVALID_IPADDR = 11,
2201         MGMT_INVALID_GATEWAY = 12,
2202         MGMT_INVALID_SUBNETMASK = 13,
2203         MGMT_INVALID_TARGET_IPADDR = 16,
2204         MGMT_TGTTBL_FULL = 20,
2205         MGMT_FLASHROM_SAVE_FAILED = 23,
2206         MGMT_IOCTLHANDLE_ALLOC_FAILED = 27,
2207         MGMT_INVALID_SESSION = 31,
2208         MGMT_INVALID_CONNECTION = 32,
2209         MGMT_BTL_PATH_EXCEEDS_OSM_LIMIT = 33,
2210         MGMT_BTL_TGTID_EXCEEDS_OSM_LIMIT = 34,
2211         MGMT_BTL_PATH_TGTID_OCCUPIED = 35,
2212         MGMT_BTL_NO_FREE_SLOT_PATH = 36,
2213         MGMT_BTL_NO_FREE_SLOT_TGTID = 37,
2214         MGMT_POLL_IOCTL_TIMEOUT = 40,
2215         MGMT_ERROR_ACITISCSI = 41,
2216         MGMT_BUFFER_SIZE_EXCEED_OSM_OR_OS_LIMIT = 43,
2217         MGMT_REBOOT_REQUIRED = 44,
2218         MGMT_INSUFFICIENT_TIMEOUT = 45,
2219         MGMT_IPADDR_NOT_SET = 46,
2220         MGMT_IPADDR_DUP_DETECTED = 47,
2221         MGMT_CANT_REMOVE_LAST_CONNECTION = 48,
2222         MGMT_TARGET_BUSY = 49,
2223         MGMT_TGT_ERR_LISTEN_SOCKET = 50,
2224         MGMT_TGT_ERR_BIND_SOCKET = 51,
2225         MGMT_TGT_ERR_NO_SOCKET = 52,
2226         MGMT_TGT_ERR_ISNS_COMM_FAILED = 55,
2227         MGMT_CANNOT_DELETE_BOOT_TARGET = 56,
2228         MGMT_TGT_PORTAL_MODE_IN_LISTEN = 57,
2229         MGMT_FCF_IN_USE = 58 ,
2230         MGMT_NO_CQE = 59,
2231         MGMT_TARGET_NOT_FOUND = 65,
2232         MGMT_NOT_SUPPORTED = 66,
2233         MGMT_NO_FCF_RECORDS = 67,
2234         MGMT_FEATURE_NOT_SUPPORTED = 68,
2235         MGMT_VPD_FUNCTION_OUT_OF_RANGE = 69,
2236         MGMT_VPD_FUNCTION_TYPE_INCORRECT = 70,
2237         MGMT_INVALID_NON_EMBEDDED_WRB = 71,
2238         MGMT_OOR = 100,
2239         MGMT_INVALID_PD = 101,
2240         MGMT_STATUS_PD_INUSE = 102,
2241         MGMT_INVALID_CQ = 103,
2242         MGMT_INVALID_QP = 104,
2243         MGMT_INVALID_STAG = 105,
2244         MGMT_ORD_EXCEEDS = 106,
2245         MGMT_IRD_EXCEEDS = 107,
2246         MGMT_SENDQ_WQE_EXCEEDS = 108,
2247         MGMT_RECVQ_RQE_EXCEEDS = 109,
2248         MGMT_SGE_SEND_EXCEEDS = 110,
2249         MGMT_SGE_WRITE_EXCEEDS = 111,
2250         MGMT_SGE_RECV_EXCEEDS = 112,
2251         MGMT_INVALID_STATE_CHANGE = 113,
2252         MGMT_MW_BOUND = 114,
2253         MGMT_INVALID_VA = 115,
2254         MGMT_INVALID_LENGTH = 116,
2255         MGMT_INVALID_FBO = 117,
2256         MGMT_INVALID_ACC_RIGHTS = 118,
2257         MGMT_INVALID_PBE_SIZE = 119,
2258         MGMT_INVALID_PBL_ENTRY = 120,
2259         MGMT_INVALID_PBL_OFFSET = 121,
2260         MGMT_ADDR_NON_EXIST = 122,
2261         MGMT_INVALID_VLANID = 123,
2262         MGMT_INVALID_MTU = 124,
2263         MGMT_INVALID_BACKLOG = 125,
2264         MGMT_CONNECTION_INPROGRESS = 126,
2265         MGMT_INVALID_RQE_SIZE = 127,
2266         MGMT_INVALID_RQE_ENTRY = 128
2267 };
2268
2269 /* Additional Management Status Codes */
2270 enum MGMT_ADDI_STATUS {
2271         MGMT_ADDI_NO_STATUS = 0,
2272         MGMT_ADDI_INVALID_IPTYPE = 1,
2273         MGMT_ADDI_TARGET_HANDLE_NOT_FOUND = 9,
2274         MGMT_ADDI_SESSION_HANDLE_NOT_FOUND = 10,
2275         MGMT_ADDI_CONNECTION_HANDLE_NOT_FOUND = 11,
2276         MGMT_ADDI_ACTIVE_SESSIONS_PRESENT = 16,
2277         MGMT_ADDI_SESSION_ALREADY_OPENED = 17,
2278         MGMT_ADDI_SESSION_ALREADY_CLOSED = 18,
2279         MGMT_ADDI_DEST_HOST_UNREACHABLE = 19,
2280         MGMT_ADDI_LOGIN_IN_PROGRESS = 20,
2281         MGMT_ADDI_TCP_CONNECT_FAILED = 21,
2282         MGMT_ADDI_INSUFFICIENT_RESOURCES = 22,
2283         MGMT_ADDI_LINK_DOWN = 23,
2284         MGMT_ADDI_DHCP_ERROR = 24,
2285         MGMT_ADDI_CONNECTION_OFFLOADED = 25,
2286         MGMT_ADDI_CONNECTION_NOT_OFFLOADED = 26,
2287         MGMT_ADDI_CONNECTION_UPLOAD_IN_PROGRESS = 27,
2288         MGMT_ADDI_REQUEST_REJECTED = 28,
2289         MGMT_ADDI_INVALID_SUBSYSTEM = 29,
2290         MGMT_ADDI_INVALID_OPCODE = 30,
2291         MGMT_ADDI_INVALID_MAXCONNECTION_PARAM = 31,
2292         MGMT_ADDI_INVALID_KEY = 32,
2293         MGMT_ADDI_INVALID_DOMAIN = 35,
2294         MGMT_ADDI_LOGIN_INITIATOR_ERROR = 43,
2295         MGMT_ADDI_LOGIN_AUTHENTICATION_ERROR = 44,
2296         MGMT_ADDI_LOGIN_AUTHORIZATION_ERROR = 45,
2297         MGMT_ADDI_LOGIN_NOT_FOUND = 46,
2298         MGMT_ADDI_LOGIN_TARGET_REMOVED = 47,
2299         MGMT_ADDI_LOGIN_UNSUPPORTED_VERSION = 48,
2300         MGMT_ADDI_LOGIN_TOO_MANY_CONNECTIONS = 49,
2301         MGMT_ADDI_LOGIN_MISSING_PARAMETER = 50,
2302         MGMT_ADDI_LOGIN_NO_SESSION_SPANNING = 51,
2303         MGMT_ADDI_LOGIN_SESSION_TYPE_NOT_SUPPORTED = 52,
2304         MGMT_ADDI_LOGIN_SESSION_DOES_NOT_EXIST = 53,
2305         MGMT_ADDI_LOGIN_INVALID_DURING_LOGIN = 54,
2306         MGMT_ADDI_LOGIN_TARGET_ERROR = 55,
2307         MGMT_ADDI_LOGIN_SERVICE_UNAVAILABLE = 56,
2308         MGMT_ADDI_LOGIN_OUT_OF_RESOURCES = 57,
2309         MGMT_ADDI_SAME_CHAP_SECRET = 58,
2310         MGMT_ADDI_INVALID_SECRET_LENGTH = 59,
2311         MGMT_ADDI_DUPLICATE_ENTRY = 60,
2312         MGMT_ADDI_SETTINGS_MODIFIED_REBOOT_REQD = 63,
2313         MGMT_ADDI_INVALID_EXTENDED_TIMEOUT = 64,
2314         MGMT_ADDI_INVALID_INTERFACE_HANDLE = 65,
2315         MGMT_ADDI_ERR_VLAN_ON_DEF_INTERFACE = 66,
2316         MGMT_ADDI_INTERFACE_DOES_NOT_EXIST = 67,
2317         MGMT_ADDI_INTERFACE_ALREADY_EXISTS = 68,
2318         MGMT_ADDI_INVALID_VLAN_RANGE = 69,
2319         MGMT_ADDI_ERR_SET_VLAN = 70,
2320         MGMT_ADDI_ERR_DEL_VLAN = 71,
2321         MGMT_ADDI_CANNOT_DEL_DEF_INTERFACE = 72,
2322         MGMT_ADDI_DHCP_REQ_ALREADY_PENDING = 73,
2323         MGMT_ADDI_TOO_MANY_INTERFACES = 74,
2324         MGMT_ADDI_INVALID_REQUEST = 75
2325 };
2326
2327 enum NIC_SUBSYSTEM_OPCODES {
2328 /**
2329  * @brief NIC Subsystem Opcodes (see Network SLI-4 manual >= Rev4, v21-2)
2330  * These opcodes are used for configuring the Ethernet interfaces.
2331  * These opcodes all use the MBX_SUBSYSTEM_NIC subsystem code.
2332  */
2333         NIC_CONFIG_RSS = 1,
2334         NIC_CONFIG_ACPI = 2,
2335         NIC_CONFIG_PROMISCUOUS = 3,
2336         NIC_GET_STATS = 4,
2337         NIC_CREATE_WQ = 7,
2338         NIC_CREATE_RQ = 8,
2339         NIC_DELETE_WQ = 9,
2340         NIC_DELETE_RQ = 10,
2341         NIC_CONFIG_ACPI_WOL_MAGIC = 12,
2342         NIC_GET_NETWORK_STATS = 13,
2343         NIC_CREATE_HDS_RQ = 16,
2344         NIC_DELETE_HDS_RQ = 17,
2345         NIC_GET_PPORT_STATS = 18,
2346         NIC_GET_VPORT_STATS = 19,
2347         NIC_GET_QUEUE_STATS = 20
2348 };
2349
2350 /* Hash option flags for RSS enable */
2351 enum RSS_ENABLE_FLAGS {
2352         RSS_ENABLE_NONE         = 0x0,  /* (No RSS) */
2353         RSS_ENABLE_IPV4         = 0x1,  /* (IPV4 HASH enabled ) */
2354         RSS_ENABLE_TCP_IPV4     = 0x2,  /* (TCP IPV4 Hash enabled) */
2355         RSS_ENABLE_IPV6         = 0x4,  /* (IPV6 HASH enabled) */
2356         RSS_ENABLE_TCP_IPV6     = 0x8,  /* (TCP IPV6 HASH */
2357         RSS_ENABLE_UDP_IPV4     = 0x10, /* UDP IPV4 HASH */
2358         RSS_ENABLE_UDP_IPV6     = 0x20  /* UDP IPV6 HASH */
2359 };
2360 #define RSS_ENABLE (RSS_ENABLE_IPV4 | RSS_ENABLE_TCP_IPV4)
2361 #define RSS_DISABLE RSS_ENABLE_NONE
2362
2363 /* NIC header WQE */
2364 struct oce_nic_hdr_wqe {
2365         union {
2366                 struct {
2367 #ifdef _BIG_ENDIAN
2368                         /* dw0 */
2369                         uint32_t rsvd0;
2370
2371                         /* dw1 */
2372                         uint32_t last_seg_udp_len:14;
2373                         uint32_t rsvd1:18;
2374
2375                         /* dw2 */
2376                         uint32_t lso_mss:14;
2377                         uint32_t num_wqe:5;
2378                         uint32_t rsvd4:2;
2379                         uint32_t vlan:1;
2380                         uint32_t lso:1;
2381                         uint32_t tcpcs:1;
2382                         uint32_t udpcs:1;
2383                         uint32_t ipcs:1;
2384                         uint32_t rsvd3:1;
2385                         uint32_t rsvd2:1;
2386                         uint32_t forward:1;
2387                         uint32_t crc:1;
2388                         uint32_t event:1;
2389                         uint32_t complete:1;
2390
2391                         /* dw3 */
2392                         uint32_t vlan_tag:16;
2393                         uint32_t total_length:16;
2394 #else
2395                         /* dw0 */
2396                         uint32_t rsvd0;
2397
2398                         /* dw1 */
2399                         uint32_t rsvd1:18;
2400                         uint32_t last_seg_udp_len:14;
2401
2402                         /* dw2 */
2403                         uint32_t complete:1;
2404                         uint32_t event:1;
2405                         uint32_t crc:1;
2406                         uint32_t forward:1;
2407                         uint32_t rsvd2:1;
2408                         uint32_t rsvd3:1;
2409                         uint32_t ipcs:1;
2410                         uint32_t udpcs:1;
2411                         uint32_t tcpcs:1;
2412                         uint32_t lso:1;
2413                         uint32_t vlan:1;
2414                         uint32_t rsvd4:2;
2415                         uint32_t num_wqe:5;
2416                         uint32_t lso_mss:14;
2417
2418                         /* dw3 */
2419                         uint32_t total_length:16;
2420                         uint32_t vlan_tag:16;
2421 #endif
2422                 } s;
2423                 uint32_t dw[4];
2424         } u0;
2425 };
2426
2427 /* NIC fragment WQE */
2428 struct oce_nic_frag_wqe {
2429         union {
2430                 struct {
2431                         /* dw0 */
2432                         uint32_t frag_pa_hi;
2433                         /* dw1 */
2434                         uint32_t frag_pa_lo;
2435                         /* dw2 */
2436                         uint32_t rsvd0;
2437                         uint32_t frag_len;
2438                 } s;
2439                 uint32_t dw[4];
2440         } u0;
2441 };
2442
2443 /* Ethernet Tx Completion Descriptor */
2444 struct oce_nic_tx_cqe {
2445         union {
2446                 struct {
2447 #ifdef _BIG_ENDIAN
2448                         /* dw 0 */
2449                         uint32_t status:4;
2450                         uint32_t rsvd0:8;
2451                         uint32_t port:2;
2452                         uint32_t ct:2;
2453                         uint32_t wqe_index:16;
2454
2455                         /* dw 1 */
2456                         uint32_t rsvd1:5;
2457                         uint32_t cast_enc:2;
2458                         uint32_t lso:1;
2459                         uint32_t nwh_bytes:8;
2460                         uint32_t user_bytes:16;
2461
2462                         /* dw 2 */
2463                         uint32_t rsvd2;
2464
2465                         /* dw 3 */
2466                         uint32_t valid:1;
2467                         uint32_t rsvd3:4;
2468                         uint32_t wq_id:11;
2469                         uint32_t num_pkts:16;
2470 #else
2471                         /* dw 0 */
2472                         uint32_t wqe_index:16;
2473                         uint32_t ct:2;
2474                         uint32_t port:2;
2475                         uint32_t rsvd0:8;
2476                         uint32_t status:4;
2477
2478                         /* dw 1 */
2479                         uint32_t user_bytes:16;
2480                         uint32_t nwh_bytes:8;
2481                         uint32_t lso:1;
2482                         uint32_t cast_enc:2;
2483                         uint32_t rsvd1:5;
2484                         /* dw 2 */
2485                         uint32_t rsvd2;
2486
2487                         /* dw 3 */
2488                         uint32_t num_pkts:16;
2489                         uint32_t wq_id:11;
2490                         uint32_t rsvd3:4;
2491                         uint32_t valid:1;
2492 #endif
2493                 } s;
2494                 uint32_t dw[4];
2495         } u0;
2496 };
2497 #define WQ_CQE_VALID(_cqe)  (_cqe->u0.dw[3])
2498 #define WQ_CQE_INVALIDATE(_cqe)  (_cqe->u0.dw[3] = 0)
2499
2500 /* Receive Queue Entry (RQE) */
2501 struct oce_nic_rqe {
2502         union {
2503                 struct {
2504                         uint32_t frag_pa_hi;
2505                         uint32_t frag_pa_lo;
2506                 } s;
2507                 uint32_t dw[2];
2508         } u0;
2509 };
2510
2511 /* NIC Receive CQE */
2512 struct oce_nic_rx_cqe {
2513         union {
2514                 struct {
2515 #ifdef _BIG_ENDIAN
2516                         /* dw 0 */
2517                         uint32_t ip_options:1;
2518                         uint32_t port:1;
2519                         uint32_t pkt_size:14;
2520                         uint32_t vlan_tag:16;
2521
2522                         /* dw 1 */
2523                         uint32_t num_fragments:3;
2524                         uint32_t switched:1;
2525                         uint32_t ct:2;
2526                         uint32_t frag_index:10;
2527                         uint32_t rsvd0:1;
2528                         uint32_t vlan_tag_present:1;
2529                         uint32_t mac_dst:6;
2530                         uint32_t ip_ver:1;
2531                         uint32_t l4_cksum_pass:1;
2532                         uint32_t ip_cksum_pass:1;
2533                         uint32_t udpframe:1;
2534                         uint32_t tcpframe:1;
2535                         uint32_t ipframe:1;
2536                         uint32_t rss_hp:1;
2537                         uint32_t error:1;
2538
2539                         /* dw 2 */
2540                         uint32_t valid:1;
2541                         uint32_t hds_type:2;
2542                         uint32_t lro_pkt:1;
2543                         uint32_t rsvd4:1;
2544                         uint32_t hds_hdr_size:12;
2545                         uint32_t hds_hdr_frag_index:10;
2546                         uint32_t rss_bank:1;
2547                         uint32_t qnq:1;
2548                         uint32_t pkt_type:2;
2549                         uint32_t rss_flush:1;
2550
2551                         /* dw 3 */
2552                         uint32_t rss_hash_value;
2553 #else
2554                         /* dw 0 */
2555                         uint32_t vlan_tag:16;
2556                         uint32_t pkt_size:14;
2557                         uint32_t port:1;
2558                         uint32_t ip_options:1;
2559                         /* dw 1 */
2560                         uint32_t error:1;
2561                         uint32_t rss_hp:1;
2562                         uint32_t ipframe:1;
2563                         uint32_t tcpframe:1;
2564                         uint32_t udpframe:1;
2565                         uint32_t ip_cksum_pass:1;
2566                         uint32_t l4_cksum_pass:1;
2567                         uint32_t ip_ver:1;
2568                         uint32_t mac_dst:6;
2569                         uint32_t vlan_tag_present:1;
2570                         uint32_t rsvd0:1;
2571                         uint32_t frag_index:10;
2572                         uint32_t ct:2;
2573                         uint32_t switched:1;
2574                         uint32_t num_fragments:3;
2575
2576                         /* dw 2 */
2577                         uint32_t rss_flush:1;
2578                         uint32_t pkt_type:2;
2579                         uint32_t qnq:1;
2580                         uint32_t rss_bank:1;
2581                         uint32_t hds_hdr_frag_index:10;
2582                         uint32_t hds_hdr_size:12;
2583                         uint32_t rsvd4:1;
2584                         uint32_t lro_pkt:1;
2585                         uint32_t hds_type:2;
2586                         uint32_t valid:1;
2587                         /* dw 3 */
2588                         uint32_t rss_hash_value;
2589 #endif
2590                 } s;
2591                 uint32_t dw[4];
2592         } u0;
2593 };
2594 /* NIC Receive CQE_v1 */
2595 struct oce_nic_rx_cqe_v1 {
2596         union {
2597                 struct {
2598 #ifdef _BIG_ENDIAN
2599                         /* dw 0 */
2600                         uint32_t ip_options:1;
2601                         uint32_t vlan_tag_present:1;
2602                         uint32_t pkt_size:14;
2603                         uint32_t vlan_tag:16;
2604
2605                         /* dw 1 */
2606                         uint32_t num_fragments:3;
2607                         uint32_t switched:1;
2608                         uint32_t ct:2;
2609                         uint32_t frag_index:10;
2610                         uint32_t rsvd0:1;
2611                         uint32_t mac_dst:7;
2612                         uint32_t ip_ver:1;
2613                         uint32_t l4_cksum_pass:1;
2614                         uint32_t ip_cksum_pass:1;
2615                         uint32_t udpframe:1;
2616                         uint32_t tcpframe:1;
2617                         uint32_t ipframe:1;
2618                         uint32_t rss_hp:1;
2619                         uint32_t error:1;
2620
2621                         /* dw 2 */
2622                         uint32_t valid:1;
2623                         uint32_t rsvd4:13;
2624                         uint32_t hds_hdr_size:
2625                         uint32_t hds_hdr_frag_index:8;
2626                         uint32_t vlantag:1;
2627                         uint32_t port:2;
2628                         uint32_t rss_bank:1;
2629                         uint32_t qnq:1;
2630                         uint32_t pkt_type:2;
2631                         uint32_t rss_flush:1;
2632
2633                         /* dw 3 */
2634                         uint32_t rss_hash_value;
2635         #else
2636                         /* dw 0 */
2637                         uint32_t vlan_tag:16;
2638                         uint32_t pkt_size:14;
2639                         uint32_t vlan_tag_present:1;
2640                         uint32_t ip_options:1;
2641                         /* dw 1 */
2642                         uint32_t error:1;
2643                         uint32_t rss_hp:1;
2644                         uint32_t ipframe:1;
2645                         uint32_t tcpframe:1;
2646                         uint32_t udpframe:1;
2647                         uint32_t ip_cksum_pass:1;
2648                         uint32_t l4_cksum_pass:1;
2649                         uint32_t ip_ver:1;
2650                         uint32_t mac_dst:7;
2651                         uint32_t rsvd0:1;
2652                         uint32_t frag_index:10;
2653                         uint32_t ct:2;
2654                         uint32_t switched:1;
2655                         uint32_t num_fragments:3;
2656
2657                         /* dw 2 */
2658                         uint32_t rss_flush:1;
2659                         uint32_t pkt_type:2;
2660                         uint32_t qnq:1;
2661                         uint32_t rss_bank:1;
2662                         uint32_t port:2;
2663                         uint32_t vlantag:1;
2664                         uint32_t hds_hdr_frag_index:8;
2665                         uint32_t hds_hdr_size:2;
2666                         uint32_t rsvd4:13;
2667                         uint32_t valid:1;
2668                         /* dw 3 */
2669                         uint32_t rss_hash_value;
2670 #endif
2671                 } s;
2672                 uint32_t dw[4];
2673         } u0;
2674 };
2675
2676 #define RQ_CQE_VALID_MASK  0x80
2677 #define RQ_CQE_VALID(_cqe) (_cqe->u0.dw[2])
2678 #define RQ_CQE_INVALIDATE(_cqe) (_cqe->u0.dw[2] = 0)
2679
2680 struct mbx_config_nic_promiscuous {
2681         struct mbx_hdr hdr;
2682         union {
2683                 struct {
2684 #ifdef _BIG_ENDIAN
2685                         uint16_t rsvd0;
2686                         uint8_t port1_promisc;
2687                         uint8_t port0_promisc;
2688 #else
2689                         uint8_t port0_promisc;
2690                         uint8_t port1_promisc;
2691                         uint16_t rsvd0;
2692 #endif
2693                 } req;
2694
2695                 struct {
2696                         uint32_t rsvd0;
2697                 } rsp;
2698         } params;
2699 };
2700
2701 typedef union oce_wq_ctx_u {
2702                 uint32_t dw[17];
2703                 struct {
2704 #ifdef _BIG_ENDIAN
2705                         /* dw4 */
2706                         uint32_t dw4rsvd2:8;
2707                         uint32_t nic_wq_type:8;
2708                         uint32_t dw4rsvd1:8;
2709                         uint32_t num_pages:8;
2710                         /* dw5 */
2711                         uint32_t dw5rsvd2:12;
2712                         uint32_t wq_size:4;
2713                         uint32_t dw5rsvd1:16;
2714                         /* dw6 */
2715                         uint32_t valid:1;
2716                         uint32_t dw6rsvd1:31;
2717                         /* dw7 */
2718                         uint32_t dw7rsvd1:16;
2719                         uint32_t cq_id:16;
2720 #else
2721                         /* dw4 */
2722                         uint32_t num_pages:8;
2723 #if 0
2724                         uint32_t dw4rsvd1:8;
2725 #else
2726 /* PSP: this workaround is not documented: fill 0x01 for ulp_mask */
2727                         uint32_t ulp_mask:8;
2728 #endif
2729                         uint32_t nic_wq_type:8;
2730                         uint32_t dw4rsvd2:8;
2731                         /* dw5 */
2732                         uint32_t dw5rsvd1:16;
2733                         uint32_t wq_size:4;
2734                         uint32_t dw5rsvd2:12;
2735                         /* dw6 */
2736                         uint32_t dw6rsvd1:31;
2737                         uint32_t valid:1;
2738                         /* dw7 */
2739                         uint32_t cq_id:16;
2740                         uint32_t dw7rsvd1:16;
2741 #endif
2742                         /* dw8 - dw20 */
2743                         uint32_t dw8_20rsvd1[13];
2744                 } v0;
2745                 struct {
2746 #ifdef _BIG_ENDIAN
2747                         /* dw4 */
2748                         uint32_t dw4rsvd2:8;
2749                         uint32_t nic_wq_type:8;
2750                         uint32_t dw4rsvd1:8;
2751                         uint32_t num_pages:8;
2752                         /* dw5 */
2753                         uint32_t dw5rsvd2:12;
2754                         uint32_t wq_size:4;
2755                         uint32_t iface_id:16;
2756                         /* dw6 */
2757                         uint32_t valid:1;
2758                         uint32_t dw6rsvd1:31;
2759                         /* dw7 */
2760                         uint32_t dw7rsvd1:16;
2761                         uint32_t cq_id:16;
2762 #else
2763                         /* dw4 */
2764                         uint32_t num_pages:8;
2765                         uint32_t dw4rsvd1:8;
2766                         uint32_t nic_wq_type:8;
2767                         uint32_t dw4rsvd2:8;
2768                         /* dw5 */
2769                         uint32_t iface_id:16;
2770                         uint32_t wq_size:4;
2771                         uint32_t dw5rsvd2:12;
2772                         /* dw6 */
2773                         uint32_t dw6rsvd1:31;
2774                         uint32_t valid:1;
2775                         /* dw7 */
2776                         uint32_t cq_id:16;
2777                         uint32_t dw7rsvd1:16;
2778 #endif
2779                         /* dw8 - dw20 */
2780                         uint32_t dw8_20rsvd1[13];
2781                 } v1;
2782 } oce_wq_ctx_t;
2783
2784 /**
2785  * @brief [07] NIC_CREATE_WQ
2786  * @note
2787  * Lancer requires an InterfaceID to be specified with every WQ. This
2788  * is the basis for NIC IOV where the Interface maps to a vPort and maps
2789  * to both Tx and Rx sides.
2790  */
2791 #define OCE_WQ_TYPE_FORWARDING  0x1     /* wq forwards pkts to TOE */
2792 #define OCE_WQ_TYPE_STANDARD    0x2     /* wq sends network pkts */
2793 struct mbx_create_nic_wq {
2794         struct mbx_hdr hdr;
2795         union {
2796                 struct {
2797                         uint8_t num_pages;
2798                         uint8_t ulp_num;
2799                         uint16_t nic_wq_type;
2800                         uint16_t if_id;
2801                         uint8_t wq_size;
2802                         uint8_t rsvd1;
2803                         uint32_t rsvd2;
2804                         uint16_t cq_id;
2805                         uint16_t rsvd3;
2806                         uint32_t rsvd4[13];
2807                         struct phys_addr pages[8];
2808
2809                 } req;
2810
2811                 struct {
2812                         uint16_t wq_id;
2813                         uint16_t rid;
2814                         uint32_t db_offset;
2815                         uint8_t tc_id;
2816                         uint8_t rsvd0[3];
2817                 } rsp;
2818         } params;
2819 };
2820
2821 /* [09] NIC_DELETE_WQ */
2822 struct mbx_delete_nic_wq {
2823         /* dw0 - dw3 */
2824         struct mbx_hdr hdr;
2825         union {
2826                 struct {
2827 #ifdef _BIG_ENDIAN
2828                         /* dw4 */
2829                         uint16_t rsvd0;
2830                         uint16_t wq_id;
2831 #else
2832                         /* dw4 */
2833                         uint16_t wq_id;
2834                         uint16_t rsvd0;
2835 #endif
2836                 } req;
2837                 struct {
2838                         uint32_t rsvd0;
2839                 } rsp;
2840         } params;
2841 };
2842
2843
2844
2845 struct mbx_create_nic_rq {
2846         struct mbx_hdr hdr;
2847         union {
2848                 struct {
2849                         uint16_t cq_id;
2850                         uint8_t frag_size;
2851                         uint8_t num_pages;
2852                         struct phys_addr pages[2];
2853                         uint32_t if_id;
2854                         uint16_t max_frame_size;
2855                         uint16_t page_size;
2856                         uint32_t is_rss_queue;
2857                 } req;
2858
2859                 struct {
2860                         uint16_t rq_id;
2861                         uint8_t rss_cpuid;
2862                         uint8_t rsvd0;
2863                 } rsp;
2864
2865         } params;
2866 };
2867
2868
2869
2870 /* [10] NIC_DELETE_RQ */
2871 struct mbx_delete_nic_rq {
2872         /* dw0 - dw3 */
2873         struct mbx_hdr hdr;
2874         union {
2875                 struct {
2876 #ifdef _BIG_ENDIAN
2877                         /* dw4 */
2878                         uint16_t bypass_flush;
2879                         uint16_t rq_id;
2880 #else
2881                         /* dw4 */
2882                         uint16_t rq_id;
2883                         uint16_t bypass_flush;
2884 #endif
2885                 } req;
2886
2887                 struct {
2888                         /* dw4 */
2889                         uint32_t rsvd0;
2890                 } rsp;
2891         } params;
2892 };
2893
2894
2895
2896
2897 struct oce_port_rxf_stats_v0 {
2898         uint32_t rx_bytes_lsd;                  /* dword 0*/
2899         uint32_t rx_bytes_msd;                  /* dword 1*/
2900         uint32_t rx_total_frames;               /* dword 2*/
2901         uint32_t rx_unicast_frames;             /* dword 3*/
2902         uint32_t rx_multicast_frames;           /* dword 4*/
2903         uint32_t rx_broadcast_frames;           /* dword 5*/
2904         uint32_t rx_crc_errors;                 /* dword 6*/
2905         uint32_t rx_alignment_symbol_errors;    /* dword 7*/
2906         uint32_t rx_pause_frames;               /* dword 8*/
2907         uint32_t rx_control_frames;             /* dword 9*/
2908         uint32_t rx_in_range_errors;            /* dword 10*/
2909         uint32_t rx_out_range_errors;           /* dword 11*/
2910         uint32_t rx_frame_too_long;             /* dword 12*/
2911         uint32_t rx_address_match_errors;       /* dword 13*/
2912         uint32_t rx_vlan_mismatch;              /* dword 14*/
2913         uint32_t rx_dropped_too_small;          /* dword 15*/
2914         uint32_t rx_dropped_too_short;          /* dword 16*/
2915         uint32_t rx_dropped_header_too_small;   /* dword 17*/
2916         uint32_t rx_dropped_tcp_length;         /* dword 18*/
2917         uint32_t rx_dropped_runt;               /* dword 19*/
2918         uint32_t rx_64_byte_packets;            /* dword 20*/
2919         uint32_t rx_65_127_byte_packets;        /* dword 21*/
2920         uint32_t rx_128_256_byte_packets;       /* dword 22*/
2921         uint32_t rx_256_511_byte_packets;       /* dword 23*/
2922         uint32_t rx_512_1023_byte_packets;      /* dword 24*/
2923         uint32_t rx_1024_1518_byte_packets;     /* dword 25*/
2924         uint32_t rx_1519_2047_byte_packets;     /* dword 26*/
2925         uint32_t rx_2048_4095_byte_packets;     /* dword 27*/
2926         uint32_t rx_4096_8191_byte_packets;     /* dword 28*/
2927         uint32_t rx_8192_9216_byte_packets;     /* dword 29*/
2928         uint32_t rx_ip_checksum_errs;           /* dword 30*/
2929         uint32_t rx_tcp_checksum_errs;          /* dword 31*/
2930         uint32_t rx_udp_checksum_errs;          /* dword 32*/
2931         uint32_t rx_non_rss_packets;            /* dword 33*/
2932         uint32_t rx_ipv4_packets;               /* dword 34*/
2933         uint32_t rx_ipv6_packets;               /* dword 35*/
2934         uint32_t rx_ipv4_bytes_lsd;             /* dword 36*/
2935         uint32_t rx_ipv4_bytes_msd;             /* dword 37*/
2936         uint32_t rx_ipv6_bytes_lsd;             /* dword 38*/
2937         uint32_t rx_ipv6_bytes_msd;             /* dword 39*/
2938         uint32_t rx_chute1_packets;             /* dword 40*/
2939         uint32_t rx_chute2_packets;             /* dword 41*/
2940         uint32_t rx_chute3_packets;             /* dword 42*/
2941         uint32_t rx_management_packets;         /* dword 43*/
2942         uint32_t rx_switched_unicast_packets;   /* dword 44*/
2943         uint32_t rx_switched_multicast_packets; /* dword 45*/
2944         uint32_t rx_switched_broadcast_packets; /* dword 46*/
2945         uint32_t tx_bytes_lsd;                  /* dword 47*/
2946         uint32_t tx_bytes_msd;                  /* dword 48*/
2947         uint32_t tx_unicastframes;              /* dword 49*/
2948         uint32_t tx_multicastframes;            /* dword 50*/
2949         uint32_t tx_broadcastframes;            /* dword 51*/
2950         uint32_t tx_pauseframes;                /* dword 52*/
2951         uint32_t tx_controlframes;              /* dword 53*/
2952         uint32_t tx_64_byte_packets;            /* dword 54*/
2953         uint32_t tx_65_127_byte_packets;        /* dword 55*/
2954         uint32_t tx_128_256_byte_packets;       /* dword 56*/
2955         uint32_t tx_256_511_byte_packets;       /* dword 57*/
2956         uint32_t tx_512_1023_byte_packets;      /* dword 58*/
2957         uint32_t tx_1024_1518_byte_packets;     /* dword 59*/
2958         uint32_t tx_1519_2047_byte_packets;     /* dword 60*/
2959         uint32_t tx_2048_4095_byte_packets;     /* dword 61*/
2960         uint32_t tx_4096_8191_byte_packets;     /* dword 62*/
2961         uint32_t tx_8192_9216_byte_packets;     /* dword 63*/
2962         uint32_t rxpp_fifo_overflow_drop;       /* dword 64*/
2963         uint32_t rx_input_fifo_overflow_drop;   /* dword 65*/
2964 };
2965
2966
2967 struct oce_rxf_stats_v0 {
2968         struct oce_port_rxf_stats_v0 port[2];
2969         uint32_t rx_drops_no_pbuf;              /* dword 132*/
2970         uint32_t rx_drops_no_txpb;              /* dword 133*/
2971         uint32_t rx_drops_no_erx_descr;         /* dword 134*/
2972         uint32_t rx_drops_no_tpre_descr;        /* dword 135*/
2973         uint32_t management_rx_port_packets;    /* dword 136*/
2974         uint32_t management_rx_port_bytes;      /* dword 137*/
2975         uint32_t management_rx_port_pause_frames;/* dword 138*/
2976         uint32_t management_rx_port_errors;     /* dword 139*/
2977         uint32_t management_tx_port_packets;    /* dword 140*/
2978         uint32_t management_tx_port_bytes;      /* dword 141*/
2979         uint32_t management_tx_port_pause;      /* dword 142*/
2980         uint32_t management_rx_port_rxfifo_overflow; /* dword 143*/
2981         uint32_t rx_drops_too_many_frags;       /* dword 144*/
2982         uint32_t rx_drops_invalid_ring;         /* dword 145*/
2983         uint32_t forwarded_packets;             /* dword 146*/
2984         uint32_t rx_drops_mtu;                  /* dword 147*/
2985         uint32_t rsvd0[7];
2986         uint32_t port0_jabber_events;
2987         uint32_t port1_jabber_events;
2988         uint32_t rsvd1[6];
2989 };
2990
2991 struct oce_port_rxf_stats_v1 {
2992         uint32_t rsvd0[12];
2993         uint32_t rx_crc_errors;
2994         uint32_t rx_alignment_symbol_errors;
2995         uint32_t rx_pause_frames;
2996         uint32_t rx_priority_pause_frames;
2997         uint32_t rx_control_frames;
2998         uint32_t rx_in_range_errors;
2999         uint32_t rx_out_range_errors;
3000         uint32_t rx_frame_too_long;
3001         uint32_t rx_address_match_errors;
3002         uint32_t rx_dropped_too_small;
3003         uint32_t rx_dropped_too_short;
3004         uint32_t rx_dropped_header_too_small;
3005         uint32_t rx_dropped_tcp_length;
3006         uint32_t rx_dropped_runt;
3007         uint32_t rsvd1[10];
3008         uint32_t rx_ip_checksum_errs;
3009         uint32_t rx_tcp_checksum_errs;
3010         uint32_t rx_udp_checksum_errs;
3011         uint32_t rsvd2[7];
3012         uint32_t rx_switched_unicast_packets;
3013         uint32_t rx_switched_multicast_packets;
3014         uint32_t rx_switched_broadcast_packets;
3015         uint32_t rsvd3[3];
3016         uint32_t tx_pauseframes;
3017         uint32_t tx_priority_pauseframes;
3018         uint32_t tx_controlframes;
3019         uint32_t rsvd4[10];
3020         uint32_t rxpp_fifo_overflow_drop;
3021         uint32_t rx_input_fifo_overflow_drop;
3022         uint32_t pmem_fifo_overflow_drop;
3023         uint32_t jabber_events;
3024         uint32_t rsvd5[3];
3025 };
3026
3027
3028 struct oce_rxf_stats_v1 {
3029         struct oce_port_rxf_stats_v1 port[4];
3030         uint32_t rsvd0[2];
3031         uint32_t rx_drops_no_pbuf;
3032         uint32_t rx_drops_no_txpb;
3033         uint32_t rx_drops_no_erx_descr;
3034         uint32_t rx_drops_no_tpre_descr;
3035         uint32_t rsvd1[6];
3036         uint32_t rx_drops_too_many_frags;
3037         uint32_t rx_drops_invalid_ring;
3038         uint32_t forwarded_packets;
3039         uint32_t rx_drops_mtu;
3040         uint32_t rsvd2[14];
3041 };
3042
3043 struct oce_erx_stats_v1 {
3044         uint32_t rx_drops_no_fragments[68];
3045         uint32_t rsvd[4];
3046 };
3047
3048
3049 struct oce_erx_stats_v0 {
3050         uint32_t rx_drops_no_fragments[44];
3051         uint32_t rsvd[4];
3052 };
3053
3054 struct oce_pmem_stats {
3055         uint32_t eth_red_drops;
3056         uint32_t rsvd[5];
3057 };
3058
3059 struct oce_hw_stats_v1 {
3060         struct oce_rxf_stats_v1 rxf;
3061         uint32_t rsvd0[OCE_TXP_SW_SZ];
3062         struct oce_erx_stats_v1 erx;
3063         struct oce_pmem_stats pmem;
3064         uint32_t rsvd1[18];
3065 };
3066
3067 struct oce_hw_stats_v0 {
3068         struct oce_rxf_stats_v0 rxf;
3069         uint32_t rsvd[48];
3070         struct oce_erx_stats_v0 erx;
3071         struct oce_pmem_stats pmem;
3072 };
3073
3074 struct mbx_get_nic_stats_v0 {
3075         struct mbx_hdr hdr;
3076         union {
3077                 struct {
3078                         uint32_t rsvd0;
3079                 } req;
3080
3081                 union {
3082                         struct oce_hw_stats_v0 stats;
3083                 } rsp;
3084         } params;
3085 };
3086
3087 struct mbx_get_nic_stats {
3088         struct mbx_hdr hdr;
3089         union {
3090                 struct {
3091                         uint32_t rsvd0;
3092                 } req;
3093
3094                 struct {
3095                         struct oce_hw_stats_v1 stats;
3096                 } rsp;
3097         } params;
3098 };
3099
3100
3101 /* [18(0x12)] NIC_GET_PPORT_STATS */
3102 struct pport_stats {
3103         uint64_t tx_pkts;
3104         uint64_t tx_unicast_pkts;
3105         uint64_t tx_multicast_pkts;
3106         uint64_t tx_broadcast_pkts;
3107         uint64_t tx_bytes;
3108         uint64_t tx_unicast_bytes;
3109         uint64_t tx_multicast_bytes;
3110         uint64_t tx_broadcast_bytes;
3111         uint64_t tx_discards;
3112         uint64_t tx_errors;
3113         uint64_t tx_pause_frames;
3114         uint64_t tx_pause_on_frames;
3115         uint64_t tx_pause_off_frames;
3116         uint64_t tx_internal_mac_errors;
3117         uint64_t tx_control_frames;
3118         uint64_t tx_pkts_64_bytes;
3119         uint64_t tx_pkts_65_to_127_bytes;
3120         uint64_t tx_pkts_128_to_255_bytes;
3121         uint64_t tx_pkts_256_to_511_bytes;
3122         uint64_t tx_pkts_512_to_1023_bytes;
3123         uint64_t tx_pkts_1024_to_1518_bytes;
3124         uint64_t tx_pkts_1519_to_2047_bytes;
3125         uint64_t tx_pkts_2048_to_4095_bytes;
3126         uint64_t tx_pkts_4096_to_8191_bytes;
3127         uint64_t tx_pkts_8192_to_9216_bytes;
3128         uint64_t tx_lso_pkts;
3129         uint64_t rx_pkts;
3130         uint64_t rx_unicast_pkts;
3131         uint64_t rx_multicast_pkts;
3132         uint64_t rx_broadcast_pkts;
3133         uint64_t rx_bytes;
3134         uint64_t rx_unicast_bytes;
3135         uint64_t rx_multicast_bytes;
3136         uint64_t rx_broadcast_bytes;
3137         uint32_t rx_unknown_protos;
3138         uint32_t reserved_word69;
3139         uint64_t rx_discards;
3140         uint64_t rx_errors;
3141         uint64_t rx_crc_errors;
3142         uint64_t rx_alignment_errors;
3143         uint64_t rx_symbol_errors;
3144         uint64_t rx_pause_frames;
3145         uint64_t rx_pause_on_frames;
3146         uint64_t rx_pause_off_frames;
3147         uint64_t rx_frames_too_long;
3148         uint64_t rx_internal_mac_errors;
3149         uint32_t rx_undersize_pkts;
3150         uint32_t rx_oversize_pkts;
3151         uint32_t rx_fragment_pkts;
3152         uint32_t rx_jabbers;
3153         uint64_t rx_control_frames;
3154         uint64_t rx_control_frames_unknown_opcode;
3155         uint32_t rx_in_range_errors;
3156         uint32_t rx_out_of_range_errors;
3157         uint32_t rx_address_match_errors;
3158         uint32_t rx_vlan_mismatch_errors;
3159         uint32_t rx_dropped_too_small;
3160         uint32_t rx_dropped_too_short;
3161         uint32_t rx_dropped_header_too_small;
3162         uint32_t rx_dropped_invalid_tcp_length;
3163         uint32_t rx_dropped_runt;
3164         uint32_t rx_ip_checksum_errors;
3165         uint32_t rx_tcp_checksum_errors;
3166         uint32_t rx_udp_checksum_errors;
3167         uint32_t rx_non_rss_pkts;
3168         uint64_t reserved_word111;
3169         uint64_t rx_ipv4_pkts;
3170         uint64_t rx_ipv6_pkts;
3171         uint64_t rx_ipv4_bytes;
3172         uint64_t rx_ipv6_bytes;
3173         uint64_t rx_nic_pkts;
3174         uint64_t rx_tcp_pkts;
3175         uint64_t rx_iscsi_pkts;
3176         uint64_t rx_management_pkts;
3177         uint64_t rx_switched_unicast_pkts;
3178         uint64_t rx_switched_multicast_pkts;
3179         uint64_t rx_switched_broadcast_pkts;
3180         uint64_t num_forwards;
3181         uint32_t rx_fifo_overflow;
3182         uint32_t rx_input_fifo_overflow;
3183         uint64_t rx_drops_too_many_frags;
3184         uint32_t rx_drops_invalid_queue;
3185         uint32_t reserved_word141;
3186         uint64_t rx_drops_mtu;
3187         uint64_t rx_pkts_64_bytes;
3188         uint64_t rx_pkts_65_to_127_bytes;
3189         uint64_t rx_pkts_128_to_255_bytes;
3190         uint64_t rx_pkts_256_to_511_bytes;
3191         uint64_t rx_pkts_512_to_1023_bytes;
3192         uint64_t rx_pkts_1024_to_1518_bytes;
3193         uint64_t rx_pkts_1519_to_2047_bytes;
3194         uint64_t rx_pkts_2048_to_4095_bytes;
3195         uint64_t rx_pkts_4096_to_8191_bytes;
3196         uint64_t rx_pkts_8192_to_9216_bytes;
3197 };
3198
3199 struct mbx_get_pport_stats {
3200         /* dw0 - dw3 */
3201         struct mbx_hdr hdr;
3202         union {
3203                 struct {
3204                         /* dw4 */
3205 #ifdef _BIG_ENDIAN
3206                         uint32_t reset_stats:8;
3207                         uint32_t rsvd0:8;
3208                         uint32_t port_number:16;
3209 #else
3210                         uint32_t port_number:16;
3211                         uint32_t rsvd0:8;
3212                         uint32_t reset_stats:8;
3213 #endif
3214                 } req;
3215
3216                 union {
3217                         struct pport_stats pps;
3218                         uint32_t pport_stats[164 - 4 + 1];
3219                 } rsp;
3220         } params;
3221 };
3222
3223 /* [19(0x13)] NIC_GET_VPORT_STATS */
3224 struct vport_stats {
3225         uint64_t tx_pkts;
3226         uint64_t tx_unicast_pkts;
3227         uint64_t tx_multicast_pkts;
3228         uint64_t tx_broadcast_pkts;
3229         uint64_t tx_bytes;
3230         uint64_t tx_unicast_bytes;
3231         uint64_t tx_multicast_bytes;
3232         uint64_t tx_broadcast_bytes;
3233         uint64_t tx_discards;
3234         uint64_t tx_errors;
3235         uint64_t tx_pkts_64_bytes;
3236         uint64_t tx_pkts_65_to_127_bytes;
3237         uint64_t tx_pkts_128_to_255_bytes;
3238         uint64_t tx_pkts_256_to_511_bytes;
3239         uint64_t tx_pkts_512_to_1023_bytes;
3240         uint64_t tx_pkts_1024_to_1518_bytes;
3241         uint64_t tx_pkts_1519_to_9699_bytes;
3242         uint64_t tx_pkts_over_9699_bytes;
3243         uint64_t rx_pkts;
3244         uint64_t rx_unicast_pkts;
3245         uint64_t rx_multicast_pkts;
3246         uint64_t rx_broadcast_pkts;
3247         uint64_t rx_bytes;
3248         uint64_t rx_unicast_bytes;
3249         uint64_t rx_multicast_bytes;
3250         uint64_t rx_broadcast_bytes;
3251         uint64_t rx_discards;
3252         uint64_t rx_errors;
3253         uint64_t rx_pkts_64_bytes;
3254         uint64_t rx_pkts_65_to_127_bytes;
3255         uint64_t rx_pkts_128_to_255_bytes;
3256         uint64_t rx_pkts_256_to_511_bytes;
3257         uint64_t rx_pkts_512_to_1023_bytes;
3258         uint64_t rx_pkts_1024_to_1518_bytes;
3259         uint64_t rx_pkts_1519_to_9699_bytes;
3260         uint64_t rx_pkts_gt_9699_bytes;
3261 };
3262 struct mbx_get_vport_stats {
3263         /* dw0 - dw3 */
3264         struct mbx_hdr hdr;
3265         union {
3266                 struct {
3267                         /* dw4 */
3268 #ifdef _BIG_ENDIAN
3269                         uint32_t reset_stats:8;
3270                         uint32_t rsvd0:8;
3271                         uint32_t vport_number:16;
3272 #else
3273                         uint32_t vport_number:16;
3274                         uint32_t rsvd0:8;
3275                         uint32_t reset_stats:8;
3276 #endif
3277                 } req;
3278
3279                 union {
3280                         struct vport_stats vps;
3281                         uint32_t vport_stats[75 - 4 + 1];
3282                 } rsp;
3283         } params;
3284 };
3285
3286 /**
3287  * @brief       [20(0x14)] NIC_GET_QUEUE_STATS
3288  * The significant difference between vPort and Queue statistics is
3289  * the packet byte counters.
3290  */
3291 struct queue_stats {
3292         uint64_t packets;
3293         uint64_t bytes;
3294         uint64_t errors;
3295         uint64_t drops;
3296         uint64_t buffer_errors;         /* rsvd when tx */
3297 };
3298
3299 #define QUEUE_TYPE_WQ           0
3300 #define QUEUE_TYPE_RQ           1
3301 #define QUEUE_TYPE_HDS_RQ       1       /* same as RQ */
3302
3303 struct mbx_get_queue_stats {
3304         /* dw0 - dw3 */
3305         struct mbx_hdr hdr;
3306         union {
3307                 struct {
3308                         /* dw4 */
3309 #ifdef _BIG_ENDIAN
3310                         uint32_t reset_stats:8;
3311                         uint32_t queue_type:8;
3312                         uint32_t queue_id:16;
3313 #else
3314                         uint32_t queue_id:16;
3315                         uint32_t queue_type:8;
3316                         uint32_t reset_stats:8;
3317 #endif
3318                 } req;
3319
3320                 union {
3321                         struct queue_stats qs;
3322                         uint32_t queue_stats[13 - 4 + 1];
3323                 } rsp;
3324         } params;
3325 };
3326
3327
3328 /* [01] NIC_CONFIG_RSS */
3329 #define OCE_HASH_TBL_SZ 10
3330 #define OCE_CPU_TBL_SZ  128
3331 #define OCE_FLUSH       1       /* RSS flush completion per CQ port */
3332 struct mbx_config_nic_rss {
3333         struct mbx_hdr hdr;
3334         union {
3335                 struct {
3336 #ifdef _BIG_ENDIAN
3337                         uint32_t if_id;
3338                         uint16_t cpu_tbl_sz_log2;
3339                         uint16_t enable_rss;
3340                         uint32_t hash[OCE_HASH_TBL_SZ];
3341                         uint8_t cputable[OCE_CPU_TBL_SZ];
3342                         uint8_t rsvd[3];
3343                         uint8_t flush;
3344 #else
3345                         uint32_t if_id;
3346                         uint16_t enable_rss;
3347                         uint16_t cpu_tbl_sz_log2;
3348                         uint32_t hash[OCE_HASH_TBL_SZ];
3349                         uint8_t cputable[OCE_CPU_TBL_SZ];
3350                         uint8_t flush;
3351                         uint8_t rsvd[3];
3352 #endif
3353                 } req;
3354                 struct {
3355                         uint8_t rsvd[3];
3356                         uint8_t rss_bank;
3357                 } rsp;
3358         } params;
3359 };
3360
3361
3362 #pragma pack()
3363
3364
3365 typedef uint32_t oce_stat_t;            /* statistic counter */
3366
3367 enum OCE_RXF_PORT_STATS {
3368         RXF_RX_BYTES_LSD,
3369         RXF_RX_BYTES_MSD,
3370         RXF_RX_TOTAL_FRAMES,
3371         RXF_RX_UNICAST_FRAMES,
3372         RXF_RX_MULTICAST_FRAMES,
3373         RXF_RX_BROADCAST_FRAMES,
3374         RXF_RX_CRC_ERRORS,
3375         RXF_RX_ALIGNMENT_SYMBOL_ERRORS,
3376         RXF_RX_PAUSE_FRAMES,
3377         RXF_RX_CONTROL_FRAMES,
3378         RXF_RX_IN_RANGE_ERRORS,
3379         RXF_RX_OUT_RANGE_ERRORS,
3380         RXF_RX_FRAME_TOO_LONG,
3381         RXF_RX_ADDRESS_MATCH_ERRORS,
3382         RXF_RX_VLAN_MISMATCH,
3383         RXF_RX_DROPPED_TOO_SMALL,
3384         RXF_RX_DROPPED_TOO_SHORT,
3385         RXF_RX_DROPPED_HEADER_TOO_SMALL,
3386         RXF_RX_DROPPED_TCP_LENGTH,
3387         RXF_RX_DROPPED_RUNT,
3388         RXF_RX_64_BYTE_PACKETS,
3389         RXF_RX_65_127_BYTE_PACKETS,
3390         RXF_RX_128_256_BYTE_PACKETS,
3391         RXF_RX_256_511_BYTE_PACKETS,
3392         RXF_RX_512_1023_BYTE_PACKETS,
3393         RXF_RX_1024_1518_BYTE_PACKETS,
3394         RXF_RX_1519_2047_BYTE_PACKETS,
3395         RXF_RX_2048_4095_BYTE_PACKETS,
3396         RXF_RX_4096_8191_BYTE_PACKETS,
3397         RXF_RX_8192_9216_BYTE_PACKETS,
3398         RXF_RX_IP_CHECKSUM_ERRS,
3399         RXF_RX_TCP_CHECKSUM_ERRS,
3400         RXF_RX_UDP_CHECKSUM_ERRS,
3401         RXF_RX_NON_RSS_PACKETS,
3402         RXF_RX_IPV4_PACKETS,
3403         RXF_RX_IPV6_PACKETS,
3404         RXF_RX_IPV4_BYTES_LSD,
3405         RXF_RX_IPV4_BYTES_MSD,
3406         RXF_RX_IPV6_BYTES_LSD,
3407         RXF_RX_IPV6_BYTES_MSD,
3408         RXF_RX_CHUTE1_PACKETS,
3409         RXF_RX_CHUTE2_PACKETS,
3410         RXF_RX_CHUTE3_PACKETS,
3411         RXF_RX_MANAGEMENT_PACKETS,
3412         RXF_RX_SWITCHED_UNICAST_PACKETS,
3413         RXF_RX_SWITCHED_MULTICAST_PACKETS,
3414         RXF_RX_SWITCHED_BROADCAST_PACKETS,
3415         RXF_TX_BYTES_LSD,
3416         RXF_TX_BYTES_MSD,
3417         RXF_TX_UNICAST_FRAMES,
3418         RXF_TX_MULTICAST_FRAMES,
3419         RXF_TX_BROADCAST_FRAMES,
3420         RXF_TX_PAUSE_FRAMES,
3421         RXF_TX_CONTROL_FRAMES,
3422         RXF_TX_64_BYTE_PACKETS,
3423         RXF_TX_65_127_BYTE_PACKETS,
3424         RXF_TX_128_256_BYTE_PACKETS,
3425         RXF_TX_256_511_BYTE_PACKETS,
3426         RXF_TX_512_1023_BYTE_PACKETS,
3427         RXF_TX_1024_1518_BYTE_PACKETS,
3428         RXF_TX_1519_2047_BYTE_PACKETS,
3429         RXF_TX_2048_4095_BYTE_PACKETS,
3430         RXF_TX_4096_8191_BYTE_PACKETS,
3431         RXF_TX_8192_9216_BYTE_PACKETS,
3432         RXF_RX_FIFO_OVERFLOW,
3433         RXF_RX_INPUT_FIFO_OVERFLOW,
3434         RXF_PORT_STATS_N_WORDS
3435 };
3436
3437 enum OCE_RXF_ADDL_STATS {
3438         RXF_RX_DROPS_NO_PBUF,
3439         RXF_RX_DROPS_NO_TXPB,
3440         RXF_RX_DROPS_NO_ERX_DESCR,
3441         RXF_RX_DROPS_NO_TPRE_DESCR,
3442         RXF_MANAGEMENT_RX_PORT_PACKETS,
3443         RXF_MANAGEMENT_RX_PORT_BYTES,
3444         RXF_MANAGEMENT_RX_PORT_PAUSE_FRAMES,
3445         RXF_MANAGEMENT_RX_PORT_ERRORS,
3446         RXF_MANAGEMENT_TX_PORT_PACKETS,
3447         RXF_MANAGEMENT_TX_PORT_BYTES,
3448         RXF_MANAGEMENT_TX_PORT_PAUSE,
3449         RXF_MANAGEMENT_RX_PORT_RXFIFO_OVERFLOW,
3450         RXF_RX_DROPS_TOO_MANY_FRAGS,
3451         RXF_RX_DROPS_INVALID_RING,
3452         RXF_FORWARDED_PACKETS,
3453         RXF_RX_DROPS_MTU,
3454         RXF_ADDL_STATS_N_WORDS
3455 };
3456
3457 enum OCE_TX_CHUTE_PORT_STATS {
3458         CTPT_XMT_IPV4_PKTS,
3459         CTPT_XMT_IPV4_LSD,
3460         CTPT_XMT_IPV4_MSD,
3461         CTPT_XMT_IPV6_PKTS,
3462         CTPT_XMT_IPV6_LSD,
3463         CTPT_XMT_IPV6_MSD,
3464         CTPT_REXMT_IPV4_PKTs,
3465         CTPT_REXMT_IPV4_LSD,
3466         CTPT_REXMT_IPV4_MSD,
3467         CTPT_REXMT_IPV6_PKTs,
3468         CTPT_REXMT_IPV6_LSD,
3469         CTPT_REXMT_IPV6_MSD,
3470         CTPT_N_WORDS,
3471 };
3472
3473 enum OCE_RX_ERR_STATS {
3474         RX_DROPS_NO_FRAGMENTS_0,
3475         RX_DROPS_NO_FRAGMENTS_1,
3476         RX_DROPS_NO_FRAGMENTS_2,
3477         RX_DROPS_NO_FRAGMENTS_3,
3478         RX_DROPS_NO_FRAGMENTS_4,
3479         RX_DROPS_NO_FRAGMENTS_5,
3480         RX_DROPS_NO_FRAGMENTS_6,
3481         RX_DROPS_NO_FRAGMENTS_7,
3482         RX_DROPS_NO_FRAGMENTS_8,
3483         RX_DROPS_NO_FRAGMENTS_9,
3484         RX_DROPS_NO_FRAGMENTS_10,
3485         RX_DROPS_NO_FRAGMENTS_11,
3486         RX_DROPS_NO_FRAGMENTS_12,
3487         RX_DROPS_NO_FRAGMENTS_13,
3488         RX_DROPS_NO_FRAGMENTS_14,
3489         RX_DROPS_NO_FRAGMENTS_15,
3490         RX_DROPS_NO_FRAGMENTS_16,
3491         RX_DROPS_NO_FRAGMENTS_17,
3492         RX_DROPS_NO_FRAGMENTS_18,
3493         RX_DROPS_NO_FRAGMENTS_19,
3494         RX_DROPS_NO_FRAGMENTS_20,
3495         RX_DROPS_NO_FRAGMENTS_21,
3496         RX_DROPS_NO_FRAGMENTS_22,
3497         RX_DROPS_NO_FRAGMENTS_23,
3498         RX_DROPS_NO_FRAGMENTS_24,
3499         RX_DROPS_NO_FRAGMENTS_25,
3500         RX_DROPS_NO_FRAGMENTS_26,
3501         RX_DROPS_NO_FRAGMENTS_27,
3502         RX_DROPS_NO_FRAGMENTS_28,
3503         RX_DROPS_NO_FRAGMENTS_29,
3504         RX_DROPS_NO_FRAGMENTS_30,
3505         RX_DROPS_NO_FRAGMENTS_31,
3506         RX_DROPS_NO_FRAGMENTS_32,
3507         RX_DROPS_NO_FRAGMENTS_33,
3508         RX_DROPS_NO_FRAGMENTS_34,
3509         RX_DROPS_NO_FRAGMENTS_35,
3510         RX_DROPS_NO_FRAGMENTS_36,
3511         RX_DROPS_NO_FRAGMENTS_37,
3512         RX_DROPS_NO_FRAGMENTS_38,
3513         RX_DROPS_NO_FRAGMENTS_39,
3514         RX_DROPS_NO_FRAGMENTS_40,
3515         RX_DROPS_NO_FRAGMENTS_41,
3516         RX_DROPS_NO_FRAGMENTS_42,
3517         RX_DROPS_NO_FRAGMENTS_43,
3518         RX_DEBUG_WDMA_SENT_HOLD,
3519         RX_DEBUG_WDMA_PBFREE_SENT_HOLD,
3520         RX_DEBUG_WDMA_0B_PBFREE_SENT_HOLD,
3521         RX_DEBUG_PMEM_PBUF_DEALLOC,
3522         RX_ERRORS_N_WORDS
3523 };
3524
3525 enum OCE_PMEM_ERR_STATS {
3526         PMEM_ETH_RED_DROPS,
3527         PMEM_LRO_RED_DROPS,
3528         PMEM_ULP0_RED_DROPS,
3529         PMEM_ULP1_RED_DROPS,
3530         PMEM_GLOBAL_RED_DROPS,
3531         PMEM_ERRORS_N_WORDS
3532 };
3533
3534 /**
3535  * @brief Statistics for a given Physical Port
3536  * These satisfy all the required BE2 statistics and also the
3537  * following MIB objects:
3538  *
3539  * RFC 2863 - The Interfaces Group MIB
3540  * RFC 2819 - Remote Network Monitoring Management Information Base (RMON)
3541  * RFC 3635 - Managed Objects for the Ethernet-like Interface Types
3542  * RFC 4502 - Remote Network Monitoring Mgmt Information Base Ver-2 (RMON2)
3543  *
3544  */
3545 enum OCE_PPORT_STATS {
3546         PPORT_TX_PKTS = 0,
3547         PPORT_TX_UNICAST_PKTS = 2,
3548         PPORT_TX_MULTICAST_PKTS = 4,
3549         PPORT_TX_BROADCAST_PKTS = 6,
3550         PPORT_TX_BYTES = 8,
3551         PPORT_TX_UNICAST_BYTES = 10,
3552         PPORT_TX_MULTICAST_BYTES = 12,
3553         PPORT_TX_BROADCAST_BYTES = 14,
3554         PPORT_TX_DISCARDS = 16,
3555         PPORT_TX_ERRORS = 18,
3556         PPORT_TX_PAUSE_FRAMES = 20,
3557         PPORT_TX_PAUSE_ON_FRAMES = 22,
3558         PPORT_TX_PAUSE_OFF_FRAMES = 24,
3559         PPORT_TX_INTERNAL_MAC_ERRORS = 26,
3560         PPORT_TX_CONTROL_FRAMES = 28,
3561         PPORT_TX_PKTS_64_BYTES = 30,
3562         PPORT_TX_PKTS_65_TO_127_BYTES = 32,
3563         PPORT_TX_PKTS_128_TO_255_BYTES = 34,
3564         PPORT_TX_PKTS_256_TO_511_BYTES = 36,
3565         PPORT_TX_PKTS_512_TO_1023_BYTES = 38,
3566         PPORT_TX_PKTS_1024_TO_1518_BYTES = 40,
3567         PPORT_TX_PKTS_1519_TO_2047_BYTES = 42,
3568         PPORT_TX_PKTS_2048_TO_4095_BYTES = 44,
3569         PPORT_TX_PKTS_4096_TO_8191_BYTES = 46,
3570         PPORT_TX_PKTS_8192_TO_9216_BYTES = 48,
3571         PPORT_TX_LSO_PKTS = 50,
3572         PPORT_RX_PKTS = 52,
3573         PPORT_RX_UNICAST_PKTS = 54,
3574         PPORT_RX_MULTICAST_PKTS = 56,
3575         PPORT_RX_BROADCAST_PKTS = 58,
3576         PPORT_RX_BYTES = 60,
3577         PPORT_RX_UNICAST_BYTES = 62,
3578         PPORT_RX_MULTICAST_BYTES = 64,
3579         PPORT_RX_BROADCAST_BYTES = 66,
3580         PPORT_RX_UNKNOWN_PROTOS = 68,
3581         PPORT_RESERVED_WORD69 = 69,
3582         PPORT_RX_DISCARDS = 70,
3583         PPORT_RX_ERRORS = 72,
3584         PPORT_RX_CRC_ERRORS = 74,
3585         PPORT_RX_ALIGNMENT_ERRORS = 76,
3586         PPORT_RX_SYMBOL_ERRORS = 78,
3587         PPORT_RX_PAUSE_FRAMES = 80,
3588         PPORT_RX_PAUSE_ON_FRAMES = 82,
3589         PPORT_RX_PAUSE_OFF_FRAMES = 84,
3590         PPORT_RX_FRAMES_TOO_LONG = 86,
3591         PPORT_RX_INTERNAL_MAC_ERRORS = 88,
3592         PPORT_RX_UNDERSIZE_PKTS = 90,
3593         PPORT_RX_OVERSIZE_PKTS = 91,
3594         PPORT_RX_FRAGMENT_PKTS = 92,
3595         PPORT_RX_JABBERS = 93,
3596         PPORT_RX_CONTROL_FRAMES = 94,
3597         PPORT_RX_CONTROL_FRAMES_UNK_OPCODE = 96,
3598         PPORT_RX_IN_RANGE_ERRORS = 98,
3599         PPORT_RX_OUT_OF_RANGE_ERRORS = 99,
3600         PPORT_RX_ADDRESS_MATCH_ERRORS = 100,
3601         PPORT_RX_VLAN_MISMATCH_ERRORS = 101,
3602         PPORT_RX_DROPPED_TOO_SMALL = 102,
3603         PPORT_RX_DROPPED_TOO_SHORT = 103,
3604         PPORT_RX_DROPPED_HEADER_TOO_SMALL = 104,
3605         PPORT_RX_DROPPED_INVALID_TCP_LENGTH = 105,
3606         PPORT_RX_DROPPED_RUNT = 106,
3607         PPORT_RX_IP_CHECKSUM_ERRORS = 107,
3608         PPORT_RX_TCP_CHECKSUM_ERRORS = 108,
3609         PPORT_RX_UDP_CHECKSUM_ERRORS = 109,
3610         PPORT_RX_NON_RSS_PKTS = 110,
3611         PPORT_RESERVED_WORD111 = 111,
3612         PPORT_RX_IPV4_PKTS = 112,
3613         PPORT_RX_IPV6_PKTS = 114,
3614         PPORT_RX_IPV4_BYTES = 116,
3615         PPORT_RX_IPV6_BYTES = 118,
3616         PPORT_RX_NIC_PKTS = 120,
3617         PPORT_RX_TCP_PKTS = 122,
3618         PPORT_RX_ISCSI_PKTS = 124,
3619         PPORT_RX_MANAGEMENT_PKTS = 126,
3620         PPORT_RX_SWITCHED_UNICAST_PKTS = 128,
3621         PPORT_RX_SWITCHED_MULTICAST_PKTS = 130,
3622         PPORT_RX_SWITCHED_BROADCAST_PKTS = 132,
3623         PPORT_NUM_FORWARDS = 134,
3624         PPORT_RX_FIFO_OVERFLOW = 136,
3625         PPORT_RX_INPUT_FIFO_OVERFLOW = 137,
3626         PPORT_RX_DROPS_TOO_MANY_FRAGS = 138,
3627         PPORT_RX_DROPS_INVALID_QUEUE = 140,
3628         PPORT_RESERVED_WORD141 = 141,
3629         PPORT_RX_DROPS_MTU = 142,
3630         PPORT_RX_PKTS_64_BYTES = 144,
3631         PPORT_RX_PKTS_65_TO_127_BYTES = 146,
3632         PPORT_RX_PKTS_128_TO_255_BYTES = 148,
3633         PPORT_RX_PKTS_256_TO_511_BYTES = 150,
3634         PPORT_RX_PKTS_512_TO_1023_BYTES = 152,
3635         PPORT_RX_PKTS_1024_TO_1518_BYTES = 154,
3636         PPORT_RX_PKTS_1519_TO_2047_BYTES = 156,
3637         PPORT_RX_PKTS_2048_TO_4095_BYTES = 158,
3638         PPORT_RX_PKTS_4096_TO_8191_BYTES = 160,
3639         PPORT_RX_PKTS_8192_TO_9216_BYTES = 162,
3640         PPORT_N_WORDS = 164
3641 };
3642
3643 /**
3644  * @brief Statistics for a given Virtual Port (vPort)
3645  * The following describes the vPort statistics satisfying
3646  * requirements of Linux/VMWare netdev statistics and
3647  * Microsoft Windows Statistics along with other Operating Systems.
3648  */
3649 enum OCE_VPORT_STATS {
3650         VPORT_TX_PKTS = 0,
3651         VPORT_TX_UNICAST_PKTS = 2,
3652         VPORT_TX_MULTICAST_PKTS = 4,
3653         VPORT_TX_BROADCAST_PKTS = 6,
3654         VPORT_TX_BYTES = 8,
3655         VPORT_TX_UNICAST_BYTES = 10,
3656         VPORT_TX_MULTICAST_BYTES = 12,
3657         VPORT_TX_BROADCAST_BYTES = 14,
3658         VPORT_TX_DISCARDS = 16,
3659         VPORT_TX_ERRORS = 18,
3660         VPORT_TX_PKTS_64_BYTES = 20,
3661         VPORT_TX_PKTS_65_TO_127_BYTES = 22,
3662         VPORT_TX_PKTS_128_TO_255_BYTES = 24,
3663         VPORT_TX_PKTS_256_TO_511_BYTES = 26,
3664         VPORT_TX_PKTS_512_TO_1023_BYTEs = 28,
3665         VPORT_TX_PKTS_1024_TO_1518_BYTEs = 30,
3666         VPORT_TX_PKTS_1519_TO_9699_BYTEs = 32,
3667         VPORT_TX_PKTS_OVER_9699_BYTES = 34,
3668         VPORT_RX_PKTS = 36,
3669         VPORT_RX_UNICAST_PKTS = 38,
3670         VPORT_RX_MULTICAST_PKTS = 40,
3671         VPORT_RX_BROADCAST_PKTS = 42,
3672         VPORT_RX_BYTES = 44,
3673         VPORT_RX_UNICAST_BYTES = 46,
3674         VPORT_RX_MULTICAST_BYTES = 48,
3675         VPORT_RX_BROADCAST_BYTES = 50,
3676         VPORT_RX_DISCARDS = 52,
3677         VPORT_RX_ERRORS = 54,
3678         VPORT_RX_PKTS_64_BYTES = 56,
3679         VPORT_RX_PKTS_65_TO_127_BYTES = 58,
3680         VPORT_RX_PKTS_128_TO_255_BYTES = 60,
3681         VPORT_RX_PKTS_256_TO_511_BYTES = 62,
3682         VPORT_RX_PKTS_512_TO_1023_BYTEs = 64,
3683         VPORT_RX_PKTS_1024_TO_1518_BYTEs = 66,
3684         VPORT_RX_PKTS_1519_TO_9699_BYTEs = 68,
3685         VPORT_RX_PKTS_OVER_9699_BYTES = 70,
3686         VPORT_N_WORDS = 72
3687 };
3688
3689 /**
3690  * @brief Statistics for a given queue (NIC WQ, RQ, or HDS RQ)
3691  * This set satisfies requirements of VMQare NetQueue and Microsoft VMQ
3692  */
3693 enum OCE_QUEUE_TX_STATS {
3694         QUEUE_TX_PKTS = 0,
3695         QUEUE_TX_BYTES = 2,
3696         QUEUE_TX_ERRORS = 4,
3697         QUEUE_TX_DROPS = 6,
3698         QUEUE_TX_N_WORDS = 8
3699 };
3700
3701 enum OCE_QUEUE_RX_STATS {
3702         QUEUE_RX_PKTS = 0,
3703         QUEUE_RX_BYTES = 2,
3704         QUEUE_RX_ERRORS = 4,
3705         QUEUE_RX_DROPS = 6,
3706         QUEUE_RX_BUFFER_ERRORS = 8,
3707         QUEUE_RX_N_WORDS = 10
3708 };