2 * Copyright (c) 2013-2014 Qlogic Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
31 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
37 * PCIe Registers; Direct Mapped; Offsets from BAR0
41 * Register offsets for QLE8030
45 * Firmware Mailbox Registers
46 * 0 thru 511; offsets 0x800 thru 0xFFC; 32bits each
48 #define Q8_FW_MBOX0 0x00000800
49 #define Q8_FW_MBOX511 0x00000FFC
52 * Host Mailbox Registers
53 * 0 thru 511; offsets 0x000 thru 0x7FC; 32bits each
55 #define Q8_HOST_MBOX0 0x00000000
56 #define Q8_HOST_MBOX511 0x000007FC
58 #define Q8_MBOX_INT_ENABLE 0x00001000
59 #define Q8_MBOX_INT_MASK_MSIX 0x00001200
60 #define Q8_MBOX_INT_LEGACY 0x00003010
62 #define Q8_HOST_MBOX_CNTRL 0x00003038
63 #define Q8_FW_MBOX_CNTRL 0x0000303C
65 #define Q8_PEG_HALT_STATUS1 0x000034A8
66 #define Q8_PEG_HALT_STATUS2 0x000034AC
67 #define Q8_FIRMWARE_HEARTBEAT 0x000034B0
69 #define Q8_FLASH_LOCK_ID 0x00003500
70 #define Q8_DRIVER_LOCK_ID 0x00003504
71 #define Q8_FW_CAPABILITIES 0x00003528
73 #define Q8_FW_VER_MAJOR 0x00003550
74 #define Q8_FW_VER_MINOR 0x00003554
75 #define Q8_FW_VER_SUB 0x00003558
77 #define Q8_BOOTLD_ADDR 0x0000355C
78 #define Q8_BOOTLD_SIZE 0x00003560
80 #define Q8_FW_IMAGE_ADDR 0x00003564
81 #define Q8_FW_BUILD_NUMBER 0x00003568
82 #define Q8_FW_IMAGE_VALID 0x000035FC
84 #define Q8_CMDPEG_STATE 0x00003650
86 #define Q8_LINK_STATE 0x00003698
87 #define Q8_LINK_STATE_2 0x0000369C
89 #define Q8_LINK_SPEED_0 0x000036E0
90 #define Q8_LINK_SPEED_1 0x000036E4
91 #define Q8_LINK_SPEED_2 0x000036E8
92 #define Q8_LINK_SPEED_3 0x000036EC
94 #define Q8_MAX_LINK_SPEED_0 0x000036F0
95 #define Q8_MAX_LINK_SPEED_1 0x000036F4
96 #define Q8_MAX_LINK_SPEED_2 0x000036F8
97 #define Q8_MAX_LINK_SPEED_3 0x000036FC
99 #define Q8_ASIC_TEMPERATURE 0x000037B4
102 * CRB Window Registers
103 * 0 thru 15; offsets 0x3800 thru 0x383C; 32bits each
105 #define Q8_CRB_WINDOW_PF0 0x00003800
106 #define Q8_CRB_WINDOW_PF15 0x0000383C
108 #define Q8_FLASH_LOCK 0x00003850
109 #define Q8_FLASH_UNLOCK 0x00003854
111 #define Q8_DRIVER_LOCK 0x00003868
112 #define Q8_DRIVER_UNLOCK 0x0000386C
114 #define Q8_LEGACY_INT_PTR 0x000038C0
115 #define Q8_LEGACY_INT_TRIG 0x000038C4
116 #define Q8_LEGACY_INT_MASK 0x000038C8
118 #define Q8_WILD_CARD 0x000038F0
119 #define Q8_INFORMANT 0x000038FC
122 * Ethernet Interface Specific Registers
124 #define Q8_DRIVER_OP_MODE 0x00003570
125 #define Q8_API_VERSION 0x0000356C
126 #define Q8_NPAR_STATE 0x0000359C
129 * End of PCIe Registers; Direct Mapped; Offsets from BAR0
135 #define Q8_LED_DUAL_0 0x28084C80
136 #define Q8_LED_SINGLE_0 0x28084C90
138 #define Q8_LED_DUAL_1 0x28084CA0
139 #define Q8_LED_SINGLE_1 0x28084CB0
141 #define Q8_LED_DUAL_2 0x28084CC0
142 #define Q8_LED_SINGLE_2 0x28084CD0
144 #define Q8_LED_DUAL_3 0x28084CE0
145 #define Q8_LED_SINGLE_3 0x28084CF0
147 #define Q8_GPIO_1 0x28084D00
148 #define Q8_GPIO_2 0x28084D10
149 #define Q8_GPIO_3 0x28084D20
150 #define Q8_GPIO_4 0x28084D40
151 #define Q8_GPIO_5 0x28084D50
152 #define Q8_GPIO_6 0x28084D60
153 #define Q8_GPIO_7 0x42100060
154 #define Q8_GPIO_8 0x42100064
156 #define Q8_FLASH_SPI_STATUS 0x2808E010
157 #define Q8_FLASH_SPI_CONTROL 0x2808E014
159 #define Q8_FLASH_STATUS 0x42100004
160 #define Q8_FLASH_CONTROL 0x42110004
161 #define Q8_FLASH_ADDRESS 0x42110008
162 #define Q8_FLASH_WR_DATA 0x4211000C
163 #define Q8_FLASH_RD_DATA 0x42110018
165 #define Q8_FLASH_DIRECT_WINDOW 0x42110030
166 #define Q8_FLASH_DIRECT_DATA 0x42150000
168 #define Q8_MS_CNTRL 0x41000090
170 #define Q8_MS_ADDR_LO 0x41000094
171 #define Q8_MS_ADDR_HI 0x41000098
173 #define Q8_MS_WR_DATA_0_31 0x410000A0
174 #define Q8_MS_WR_DATA_32_63 0x410000A4
175 #define Q8_MS_WR_DATA_64_95 0x410000B0
176 #define Q8_MS_WR_DATA_96_127 0x410000B4
178 #define Q8_MS_RD_DATA_0_31 0x410000A8
179 #define Q8_MS_RD_DATA_32_63 0x410000AC
180 #define Q8_MS_RD_DATA_64_95 0x410000B8
181 #define Q8_MS_RD_DATA_96_127 0x410000BC
183 #define Q8_CRB_PEG_0 0x3400003c
184 #define Q8_CRB_PEG_1 0x3410003c
185 #define Q8_CRB_PEG_2 0x3420003c
186 #define Q8_CRB_PEG_3 0x3430003c
187 #define Q8_CRB_PEG_4 0x34B0003c
190 * Macros for reading and writing registers
193 #if defined(__i386__) || defined(__amd64__)
194 #define Q8_MB() __asm volatile("mfence" ::: "memory")
195 #define Q8_WMB() __asm volatile("sfence" ::: "memory")
196 #define Q8_RMB() __asm volatile("lfence" ::: "memory")
203 #define READ_REG32(ha, reg) bus_read_4((ha->pci_reg), reg)
205 #define WRITE_REG32(ha, reg, val) \
207 bus_write_4((ha->pci_reg), reg, val);\
208 bus_read_4((ha->pci_reg), reg);\
211 #define Q8_NUM_MBOX 512
213 #define Q8_MAX_NUM_MULTICAST_ADDRS 1023
214 #define Q8_MAC_ADDR_LEN 6
221 * Command Response Interface - Commands
224 #define Q8_MBX_CONFIG_IP_ADDRESS 0x0001
225 #define Q8_MBX_CONFIG_INTR 0x0002
226 #define Q8_MBX_MAP_INTR_SRC 0x0003
227 #define Q8_MBX_MAP_SDS_TO_RDS 0x0006
228 #define Q8_MBX_CREATE_RX_CNTXT 0x0007
229 #define Q8_MBX_DESTROY_RX_CNTXT 0x0008
230 #define Q8_MBX_CREATE_TX_CNTXT 0x0009
231 #define Q8_MBX_DESTROY_TX_CNTXT 0x000A
232 #define Q8_MBX_ADD_RX_RINGS 0x000B
233 #define Q8_MBX_CONFIG_LRO_FLOW 0x000C
234 #define Q8_MBX_CONFIG_MAC_LEARNING 0x000D
235 #define Q8_MBX_GET_STATS 0x000F
236 #define Q8_MBX_GENERATE_INTR 0x0011
237 #define Q8_MBX_SET_MAX_MTU 0x0012
238 #define Q8_MBX_MAC_ADDR_CNTRL 0x001F
239 #define Q8_MBX_GET_PCI_CONFIG 0x0020
240 #define Q8_MBX_GET_NIC_PARTITION 0x0021
241 #define Q8_MBX_SET_NIC_PARTITION 0x0022
242 #define Q8_MBX_QUERY_WOL_CAP 0x002C
243 #define Q8_MBX_SET_WOL_CONFIG 0x002D
244 #define Q8_MBX_GET_MINIDUMP_TMPLT_SIZE 0x002F
245 #define Q8_MBX_GET_MINIDUMP_TMPLT 0x0030
246 #define Q8_MBX_GET_FW_DCBX_CAPS 0x0034
247 #define Q8_MBX_QUERY_DCBX_SETTINGS 0x0035
248 #define Q8_MBX_CONFIG_RSS 0x0041
249 #define Q8_MBX_CONFIG_RSS_TABLE 0x0042
250 #define Q8_MBX_CONFIG_INTR_COALESCE 0x0043
251 #define Q8_MBX_CONFIG_LED 0x0044
252 #define Q8_MBX_CONFIG_MAC_ADDR 0x0045
253 #define Q8_MBX_CONFIG_STATISTICS 0x0046
254 #define Q8_MBX_CONFIG_LOOPBACK 0x0047
255 #define Q8_MBX_LINK_EVENT_REQ 0x0048
256 #define Q8_MBX_CONFIG_MAC_RX_MODE 0x0049
257 #define Q8_MBX_CONFIG_FW_LRO 0x004A
258 #define Q8_MBX_INIT_NIC_FUNC 0x0060
259 #define Q8_MBX_STOP_NIC_FUNC 0x0061
260 #define Q8_MBX_SET_PORT_CONFIG 0x0066
261 #define Q8_MBX_GET_PORT_CONFIG 0x0067
262 #define Q8_MBX_GET_LINK_STATUS 0x0068
267 * Mailbox Command Response
269 #define Q8_MBX_RSP_SUCCESS 0x0001
270 #define Q8_MBX_RSP_RESPONSE_FAILURE 0x0002
271 #define Q8_MBX_RSP_NO_CARD_CRB 0x0003
272 #define Q8_MBX_RSP_NO_CARD_MEM 0x0004
273 #define Q8_MBX_RSP_NO_CARD_RSRC 0x0005
274 #define Q8_MBX_RSP_INVALID_ARGS 0x0006
275 #define Q8_MBX_RSP_INVALID_ACTION 0x0007
276 #define Q8_MBX_RSP_INVALID_STATE 0x0008
277 #define Q8_MBX_RSP_NOT_SUPPORTED 0x0009
278 #define Q8_MBX_RSP_NOT_PERMITTED 0x000A
279 #define Q8_MBX_RSP_NOT_READY 0x000B
280 #define Q8_MBX_RSP_DOES_NOT_EXIST 0x000C
281 #define Q8_MBX_RSP_ALREADY_EXISTS 0x000D
282 #define Q8_MBX_RSP_BAD_SIGNATURE 0x000E
283 #define Q8_MBX_RSP_CMD_NOT_IMPLEMENTED 0x000F
284 #define Q8_MBX_RSP_CMD_INVALID 0x0010
285 #define Q8_MBX_RSP_TIMEOUT 0x0011
286 #define Q8_MBX_RSP_CMD_FAILED 0x0012
287 #define Q8_MBX_RSP_FATAL_TEMP 0x0013
288 #define Q8_MBX_RSP_MAX_EXCEEDED 0x0014
289 #define Q8_MBX_RSP_UNSPECIFIED 0x0015
290 #define Q8_MBX_RSP_INTR_CREATE_FAILED 0x0017
291 #define Q8_MBX_RSP_INTR_DELETE_FAILED 0x0018
292 #define Q8_MBX_RSP_INTR_INVALID_OP 0x0019
293 #define Q8_MBX_RSP_IDC_INTRMD_RSP 0x001A
295 #define Q8_MBX_CMD_VERSION (0x2 << 13)
296 #define Q8_MBX_RSP_STATUS(x) (((!(x >> 9)) || ((x >> 9) == 1)) ? 0: (x >> 9))
298 * Configure IP Address
300 typedef struct _q80_config_ip_addr {
302 uint16_t count_version;
305 #define Q8_MBX_CONFIG_IP_ADD_IP 0x1
306 #define Q8_MBX_CONFIG_IP_DEL_IP 0x2
309 #define Q8_MBX_CONFIG_IP_V4 0x0
310 #define Q8_MBX_CONFIG_IP_V6 0x1
318 uint8_t ipv6_addr[16];
320 } __packed q80_config_ip_addr_t;
322 typedef struct _q80_config_ip_addr_rsp {
324 uint16_t regcnt_status;
325 } __packed q80_config_ip_addr_rsp_t;
328 * Configure Interrupt Command
330 typedef struct _q80_intr {
332 #define Q8_MBX_CONFIG_INTR_CREATE 0x1
333 #define Q8_MBX_CONFIG_INTR_DELETE 0x2
334 #define Q8_MBX_CONFIG_INTR_TYPE_LINE (0x1 << 4)
335 #define Q8_MBX_CONFIG_INTR_TYPE_MSI_X (0x3 << 4)
339 } __packed q80_intr_t;
341 #define Q8_MAX_INTR_VECTORS 16
342 typedef struct _q80_config_intr {
344 uint16_t count_version;
347 q80_intr_t intr[Q8_MAX_INTR_VECTORS];
348 } __packed q80_config_intr_t;
350 typedef struct _q80_intr_rsp {
357 typedef struct _q80_config_intr_rsp {
359 uint16_t regcnt_status;
362 q80_intr_rsp_t intr[Q8_MAX_INTR_VECTORS];
363 } __packed q80_config_intr_rsp_t;
366 * Configure LRO Flow Command
368 typedef struct _q80_config_lro_flow {
370 uint16_t count_version;
373 #define Q8_MBX_CONFIG_LRO_FLOW_ADD 0x01
374 #define Q8_MBX_CONFIG_LRO_FLOW_DELETE 0x02
377 #define Q8_MBX_CONFIG_LRO_FLOW_IPV4 0x00
378 #define Q8_MBX_CONFIG_LRO_FLOW_IPV6 0x01
379 #define Q8_MBX_CONFIG_LRO_FLOW_TS_ABSENT 0x00
380 #define Q8_MBX_CONFIG_LRO_FLOW_TS_PRESENT 0x02
388 uint8_t ipv6_addr[16];
395 uint8_t ipv6_addr[16];
399 } __packed q80_config_lro_flow_t;
401 typedef struct _q80_config_lro_flow_rsp {
403 uint16_t regcnt_status;
404 } __packed q80_config_lro_flow_rsp_t;
406 typedef struct _q80_set_max_mtu {
408 uint16_t count_version;
411 } __packed q80_set_max_mtu_t;
413 typedef struct _q80_set_max_mtu_rsp {
415 uint16_t regcnt_status;
416 } __packed q80_set_max_mtu_rsp_t;
421 typedef struct _q80_config_rss {
423 uint16_t count_version;
429 #define Q8_MBX_RSS_HASH_TYPE_IPV4_TCP_IP (0x3 << 4)
430 #define Q8_MBX_RSS_HASH_TYPE_IPV6_TCP_IP (0x3 << 6)
433 #define Q8_MBX_RSS_FLAGS_ENABLE_RSS (0x1)
434 #define Q8_MBX_RSS_FLAGS_USE_IND_TABLE (0x2)
435 #define Q8_MBX_RSS_FLAGS_TYPE_CRSS (0x4)
437 uint16_t indtbl_mask;
438 #define Q8_MBX_RSS_INDTBL_MASK 0x7F
439 #define Q8_MBX_RSS_FLAGS_MULTI_RSS_VALID 0x8000
442 #define Q8_MBX_RSS_MULTI_RSS_ENGINE_ASSIGN BIT_30
443 #define Q8_MBX_RSS_USE_MULTI_RSS_ENGINES BIT_31
446 } __packed q80_config_rss_t;
448 typedef struct _q80_config_rss_rsp {
450 uint16_t regcnt_status;
451 } __packed q80_config_rss_rsp_t;
454 * Configure RSS Indirection Table
456 #define Q8_RSS_IND_TBL_SIZE 40
457 #define Q8_RSS_IND_TBL_MIN_IDX 0
458 #define Q8_RSS_IND_TBL_MAX_IDX 127
460 typedef struct _q80_config_rss_ind_table {
462 uint16_t count_version;
466 uint8_t ind_table[40];
467 } __packed q80_config_rss_ind_table_t;
469 typedef struct _q80_config_rss_ind_table_rsp {
471 uint16_t regcnt_status;
472 } __packed q80_config_rss_ind_table_rsp_t;
475 * Configure Interrupt Coalescing and Generation
477 typedef struct _q80_config_intr_coalesc {
479 uint16_t count_version;
481 #define Q8_MBX_INTRC_FLAGS_RCV 1
482 #define Q8_MBX_INTRC_FLAGS_XMT 2
483 #define Q8_MBX_INTRC_FLAGS_PERIODIC (1 << 3)
489 #define Q8_MBX_INTRC_TIMER_NONE 0
490 #define Q8_MBX_INTRC_TIMER_SINGLE 1
491 #define Q8_MBX_INTRC_TIMER_PERIODIC 2
493 uint16_t sds_ring_mask;
497 } __packed q80_config_intr_coalesc_t;
499 typedef struct _q80_config_intr_coalesc_rsp {
501 uint16_t regcnt_status;
502 } __packed q80_config_intr_coalesc_rsp_t;
505 * Configure MAC Address
507 typedef struct _q80_mac_addr {
510 } __packed q80_mac_addr_t;
512 #define Q8_MAX_MAC_ADDRS 64
514 typedef struct _q80_config_mac_addr {
516 uint16_t count_version;
518 #define Q8_MBX_CMAC_CMD_ADD_MAC_ADDR 1
519 #define Q8_MBX_CMAC_CMD_DEL_MAC_ADDR 2
521 #define Q8_MBX_CMAC_CMD_CAM_BOTH (0x0 << 6)
522 #define Q8_MBX_CMAC_CMD_CAM_INGRESS (0x1 << 6)
523 #define Q8_MBX_CMAC_CMD_CAM_EGRESS (0x2 << 6)
525 uint8_t nmac_entries;
527 q80_mac_addr_t mac_addr[Q8_MAX_MAC_ADDRS];
528 } __packed q80_config_mac_addr_t;
530 typedef struct _q80_config_mac_addr_rsp {
532 uint16_t regcnt_status;
534 uint8_t nmac_entries;
536 uint32_t status[Q8_MAX_MAC_ADDRS];
537 } __packed q80_config_mac_addr_rsp_t;
540 * Configure MAC Receive Mode
542 typedef struct _q80_config_mac_rcv_mode {
544 uint16_t count_version;
547 #define Q8_MBX_MAC_RCV_PROMISC_ENABLE 0x1
548 #define Q8_MBX_MAC_ALL_MULTI_ENABLE 0x2
552 } __packed q80_config_mac_rcv_mode_t;
554 typedef struct _q80_config_mac_rcv_mode_rsp {
556 uint16_t regcnt_status;
557 } __packed q80_config_mac_rcv_mode_rsp_t;
560 * Configure Firmware Controlled LRO
562 typedef struct _q80_config_fw_lro {
564 uint16_t count_version;
567 #define Q8_MBX_FW_LRO_IPV4 0x1
568 #define Q8_MBX_FW_LRO_IPV6 0x2
569 #define Q8_MBX_FW_LRO_IPV4_WO_DST_IP_CHK 0x4
570 #define Q8_MBX_FW_LRO_IPV6_WO_DST_IP_CHK 0x8
571 #define Q8_MBX_FW_LRO_LOW_THRESHOLD 0x10
576 uint16_t low_threshold;
578 } __packed q80_config_fw_lro_t;
580 typedef struct _q80_config_fw_lro_rsp {
582 uint16_t regcnt_status;
583 } __packed q80_config_fw_lro_rsp_t;
586 * Minidump mailbox commands
588 typedef struct _q80_config_md_templ_size {
590 uint16_t count_version;
591 } __packed q80_config_md_templ_size_t;
593 typedef struct _q80_config_md_templ_size_rsp {
595 uint16_t regcnt_status;
598 uint32_t templ_version;
599 } __packed q80_config_md_templ_size_rsp_t;
601 typedef struct _q80_config_md_templ_cmd {
603 uint16_t count_version;
604 uint64_t buf_addr; /* physical address of buffer */
607 } __packed q80_config_md_templ_cmd_t;
609 typedef struct _q80_config_md_templ_cmd_rsp {
611 uint16_t regcnt_status;
616 } __packed q80_config_md_templ_cmd_rsp_t;
619 * Link Event Request Command
621 typedef struct _q80_link_event {
623 uint16_t count_version;
625 #define Q8_LINK_EVENT_CMD_STOP_PERIODIC 0
626 #define Q8_LINK_EVENT_CMD_ENABLE_ASYNC 1
629 #define Q8_LINK_EVENT_FLAGS_SEND_RSP 1
632 } __packed q80_link_event_t;
634 typedef struct _q80_link_event_rsp {
636 uint16_t regcnt_status;
637 } __packed q80_link_event_rsp_t;
640 * Get Statistics Command
642 typedef struct _q80_rcv_stats {
643 uint64_t total_bytes;
645 uint64_t lro_pkt_count;
646 uint64_t sw_pkt_count;
647 uint64_t ip_chksum_err;
648 uint64_t pkts_wo_acntxts;
649 uint64_t pkts_dropped_no_sds_card;
650 uint64_t pkts_dropped_no_sds_host;
651 uint64_t oversized_pkts;
652 uint64_t pkts_dropped_no_rds;
653 uint64_t unxpctd_mcast_pkts;
654 uint64_t re1_fbq_error;
655 uint64_t invalid_mac_addr;
656 uint64_t rds_prime_trys;
657 uint64_t rds_prime_success;
658 uint64_t lro_flows_added;
659 uint64_t lro_flows_deleted;
660 uint64_t lro_flows_active;
661 uint64_t pkts_droped_unknown;
662 } __packed q80_rcv_stats_t;
664 typedef struct _q80_xmt_stats {
665 uint64_t total_bytes;
668 uint64_t pkts_dropped;
669 uint64_t switch_pkts;
670 uint64_t num_buffers;
671 } __packed q80_xmt_stats_t;
673 typedef struct _q80_mac_stats {
676 uint64_t xmt_mcast_pkts;
677 uint64_t xmt_bcast_pkts;
678 uint64_t xmt_pause_frames;
679 uint64_t xmt_cntrl_pkts;
680 uint64_t xmt_pkt_lt_64bytes;
681 uint64_t xmt_pkt_lt_127bytes;
682 uint64_t xmt_pkt_lt_255bytes;
683 uint64_t xmt_pkt_lt_511bytes;
684 uint64_t xmt_pkt_lt_1023bytes;
685 uint64_t xmt_pkt_lt_1518bytes;
686 uint64_t xmt_pkt_gt_1518bytes;
690 uint64_t rcv_mcast_pkts;
691 uint64_t rcv_bcast_pkts;
692 uint64_t rcv_pause_frames;
693 uint64_t rcv_cntrl_pkts;
694 uint64_t rcv_pkt_lt_64bytes;
695 uint64_t rcv_pkt_lt_127bytes;
696 uint64_t rcv_pkt_lt_255bytes;
697 uint64_t rcv_pkt_lt_511bytes;
698 uint64_t rcv_pkt_lt_1023bytes;
699 uint64_t rcv_pkt_lt_1518bytes;
700 uint64_t rcv_pkt_gt_1518bytes;
702 uint64_t rcv_len_error;
703 uint64_t rcv_len_small;
704 uint64_t rcv_len_large;
706 uint64_t rcv_dropped;
708 uint64_t align_error;
709 } __packed q80_mac_stats_t;
711 typedef struct _q80_get_stats {
713 uint16_t count_version;
716 #define Q8_GET_STATS_CMD_CLEAR 0x01
717 #define Q8_GET_STATS_CMD_RCV 0x00
718 #define Q8_GET_STATS_CMD_XMT 0x02
719 #define Q8_GET_STATS_CMD_TYPE_CNTXT 0x00
720 #define Q8_GET_STATS_CMD_TYPE_MAC 0x04
721 #define Q8_GET_STATS_CMD_TYPE_FUNC 0x08
722 #define Q8_GET_STATS_CMD_TYPE_VPORT 0x0C
724 } __packed q80_get_stats_t;
726 typedef struct _q80_get_stats_rsp {
728 uint16_t regcnt_status;
735 } __packed q80_get_stats_rsp_t;
739 * Used to Register DCBX Configuration Change AEN
741 typedef struct _q80_init_nic_func {
743 uint16_t count_version;
746 #define Q8_INIT_NIC_REG_DCBX_CHNG_AEN 0x02
747 #define Q8_INIT_NIC_REG_SFP_CHNG_AEN 0x04
749 } __packed q80_init_nic_func_t;
751 typedef struct _q80_init_nic_func_rsp {
753 uint16_t regcnt_status;
754 } __packed q80_init_nic_func_rsp_t;
758 * Used to DeRegister DCBX Configuration Change AEN
760 typedef struct _q80_stop_nic_func {
762 uint16_t count_version;
765 #define Q8_STOP_NIC_DEREG_DCBX_CHNG_AEN 0x02
766 #define Q8_STOP_NIC_DEREG_SFP_CHNG_AEN 0x04
768 } __packed q80_stop_nic_func_t;
770 typedef struct _q80_stop_nic_func_rsp {
772 uint16_t regcnt_status;
773 } __packed q80_stop_nic_func_rsp_t;
776 * Query Firmware DCBX Capabilities
778 typedef struct _q80_query_fw_dcbx_caps {
780 uint16_t count_version;
781 } __packed q80_query_fw_dcbx_caps_t;
783 typedef struct _q80_query_fw_dcbx_caps_rsp {
785 uint16_t regcnt_status;
788 #define Q8_QUERY_FW_DCBX_CAPS_TSA 0x00000001
789 #define Q8_QUERY_FW_DCBX_CAPS_ETS 0x00000002
790 #define Q8_QUERY_FW_DCBX_CAPS_DCBX_CEE_1_01 0x00000004
791 #define Q8_QUERY_FW_DCBX_CAPS_DCBX_IEEE_1_0 0x00000008
792 #define Q8_QUERY_FW_DCBX_MAX_TC_MASK 0x00F00000
793 #define Q8_QUERY_FW_DCBX_MAX_ETS_TC_MASK 0x0F000000
794 #define Q8_QUERY_FW_DCBX_MAX_PFC_TC_MASK 0xF0000000
796 } __packed q80_query_fw_dcbx_caps_rsp_t;
799 * Set Port Configuration command
800 * Used to set Ethernet Standard Pause values
803 typedef struct _q80_set_port_cfg {
805 uint16_t count_version;
809 #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_MASK (0x7 << 1)
810 #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_NONE (0x0 << 1)
811 #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_HSS (0x2 << 1)
812 #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_PHY (0x3 << 1)
813 #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_EXT (0x4 << 1)
815 #define Q8_VALID_LOOPBACK_MODE(mode) \
816 (((mode) == Q8_PORT_CFG_BITS_LOOPBACK_MODE_NONE) || \
817 (((mode) >= Q8_PORT_CFG_BITS_LOOPBACK_MODE_HSS) && \
818 ((mode) <= Q8_PORT_CFG_BITS_LOOPBACK_MODE_EXT)))
820 #define Q8_PORT_CFG_BITS_DCBX_ENABLE BIT_4
822 #define Q8_PORT_CFG_BITS_PAUSE_CFG_MASK (0x3 << 5)
823 #define Q8_PORT_CFG_BITS_PAUSE_DISABLED (0x0 << 5)
824 #define Q8_PORT_CFG_BITS_PAUSE_STD (0x1 << 5)
825 #define Q8_PORT_CFG_BITS_PAUSE_PPM (0x2 << 5)
827 #define Q8_PORT_CFG_BITS_LNKCAP_10MB BIT_8
828 #define Q8_PORT_CFG_BITS_LNKCAP_100MB BIT_9
829 #define Q8_PORT_CFG_BITS_LNKCAP_1GB BIT_10
830 #define Q8_PORT_CFG_BITS_LNKCAP_10GB BIT_11
832 #define Q8_PORT_CFG_BITS_AUTONEG BIT_15
833 #define Q8_PORT_CFG_BITS_XMT_DISABLE BIT_17
834 #define Q8_PORT_CFG_BITS_FEC_RQSTD BIT_18
835 #define Q8_PORT_CFG_BITS_EEE_RQSTD BIT_19
837 #define Q8_PORT_CFG_BITS_STDPAUSE_DIR_MASK (0x3 << 20)
838 #define Q8_PORT_CFG_BITS_STDPAUSE_XMT_RCV (0x0 << 20)
839 #define Q8_PORT_CFG_BITS_STDPAUSE_XMT (0x1 << 20)
840 #define Q8_PORT_CFG_BITS_STDPAUSE_RCV (0x2 << 20)
842 } __packed q80_set_port_cfg_t;
844 typedef struct _q80_set_port_cfg_rsp {
846 uint16_t regcnt_status;
847 } __packed q80_set_port_cfg_rsp_t;
850 * Get Port Configuration Command
853 typedef struct _q80_get_port_cfg {
855 uint16_t count_version;
856 } __packed q80_get_port_cfg_t;
858 typedef struct _q80_get_port_cfg_rsp {
860 uint16_t regcnt_status;
862 uint32_t cfg_bits; /* same as in q80_set_port_cfg_t */
864 uint8_t phys_port_type;
866 } __packed q80_get_port_cfg_rsp_t;
869 * Get Link Status Command
870 * Used to get current PAUSE values for the port
873 typedef struct _q80_get_link_status {
875 uint16_t count_version;
876 } __packed q80_get_link_status_t;
878 typedef struct _q80_get_link_status_rsp {
880 uint16_t regcnt_status;
883 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_UP BIT_0
885 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_MASK (0x7 << 3)
886 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_UNKNOWN (0x0 << 3)
887 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_10MB (0x1 << 3)
888 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_100MB (0x2 << 3)
889 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_1GB (0x3 << 3)
890 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_10GB (0x4 << 3)
892 #define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_MASK (0x3 << 6)
893 #define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_DISABLE (0x0 << 6)
894 #define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_STD (0x1 << 6)
895 #define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_PPM (0x2 << 6)
897 #define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_MASK (0x7 << 8)
898 #define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_NONE (0x0 << 6)
899 #define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_HSS (0x2 << 6)
900 #define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_PHY (0x3 << 6)
902 #define Q8_GET_LINK_STAT_CFG_BITS_FEC_ENABLED BIT_12
903 #define Q8_GET_LINK_STAT_CFG_BITS_EEE_ENABLED BIT_13
905 #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_DIR_MASK (0x3 << 20)
906 #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_NONE (0x0 << 20)
907 #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_XMT (0x1 << 20)
908 #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_RCV (0x2 << 20)
909 #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_XMT_RCV (0x3 << 20)
912 #define Q8_GET_LINK_STAT_LOSS_OF_SIGNAL BIT_0
913 #define Q8_GET_LINK_STAT_PORT_RST_DONE BIT_3
914 #define Q8_GET_LINK_STAT_PHY_LINK_DOWN BIT_4
915 #define Q8_GET_LINK_STAT_PCS_LINK_DOWN BIT_5
916 #define Q8_GET_LINK_STAT_MAC_LOCAL_FAULT BIT_6
917 #define Q8_GET_LINK_STAT_MAC_REMOTE_FAULT BIT_7
918 #define Q8_GET_LINK_STAT_XMT_DISABLED BIT_9
919 #define Q8_GET_LINK_STAT_SFP_XMT_FAULT BIT_10
922 #define Q8_GET_LINK_STAT_SFP_TRNCVR_MASK 0x3
923 #define Q8_GET_LINK_STAT_SFP_TRNCVR_NOT_EXPECTED 0x0
924 #define Q8_GET_LINK_STAT_SFP_TRNCVR_NONE 0x1
925 #define Q8_GET_LINK_STAT_SFP_TRNCVR_INVALID 0x2
926 #define Q8_GET_LINK_STAT_SFP_TRNCVR_VALID 0x3
928 #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_MASK (0x3 << 2)
929 #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_UNREC_TRSVR (0x0 << 2)
930 #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_NOT_QLOGIC (0x1 << 2)
931 #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_SPEED_FAILED (0x2 << 2)
932 #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_ACCESS_ERROR (0x3 << 2)
934 #define Q8_GET_LINK_STAT_SFP_MOD_TYPE_MASK (0x1F << 4)
935 #define Q8_GET_LINK_STAT_SFP_MOD_NONE (0x00 << 4)
936 #define Q8_GET_LINK_STAT_SFP_MOD_10GBLRM (0x01 << 4)
937 #define Q8_GET_LINK_STAT_SFP_MOD_10GBLR (0x02 << 4)
938 #define Q8_GET_LINK_STAT_SFP_MOD_10GBSR (0x03 << 4)
939 #define Q8_GET_LINK_STAT_SFP_MOD_10GBC_P (0x04 << 4)
940 #define Q8_GET_LINK_STAT_SFP_MOD_10GBC_AL (0x05 << 4)
941 #define Q8_GET_LINK_STAT_SFP_MOD_10GBC_PL (0x06 << 4)
942 #define Q8_GET_LINK_STAT_SFP_MOD_1GBSX (0x07 << 4)
943 #define Q8_GET_LINK_STAT_SFP_MOD_1GBLX (0x08 << 4)
944 #define Q8_GET_LINK_STAT_SFP_MOD_1GBCX (0x09 << 4)
945 #define Q8_GET_LINK_STAT_SFP_MOD_1GBT (0x0A << 4)
946 #define Q8_GET_LINK_STAT_SFP_MOD_1GBC_PL (0x0B << 4)
947 #define Q8_GET_LINK_STAT_SFP_MOD_UNKNOWN (0x0F << 4)
949 #define Q8_GET_LINK_STAT_SFP_MULTI_RATE_MOD BIT_9
950 #define Q8_GET_LINK_STAT_SFP_XMT_FAULT BIT_10
951 #define Q8_GET_LINK_STAT_SFP_COPPER_CBL_LENGTH_MASK (0xFF << 16)
953 } __packed q80_get_link_status_rsp_t;
957 * Transmit Related Definitions
959 /* Max# of TX Rings per Tx Create Cntxt Mbx Cmd*/
960 #define MAX_TCNTXT_RINGS 8
963 * Transmit Context - Q8_CMD_CREATE_TX_CNTXT Command Configuration Data
966 typedef struct _q80_rq_tx_ring {
968 uint64_t tx_consumer;
971 uint8_t intr_src_bit;
973 } __packed q80_rq_tx_ring_t;
975 typedef struct _q80_rq_tx_cntxt {
977 uint16_t count_version;
980 #define Q8_TX_CNTXT_CAP0_BASEFW (1 << 0)
981 #define Q8_TX_CNTXT_CAP0_LSO (1 << 6)
982 #define Q8_TX_CNTXT_CAP0_TC (1 << 25)
988 uint8_t traffic_class; /* bits 8-10; others reserved */
990 q80_rq_tx_ring_t tx_ring[MAX_TCNTXT_RINGS];
991 } __packed q80_rq_tx_cntxt_t;
993 typedef struct _q80_rsp_tx_ring {
1000 typedef struct _q80_rsp_tx_cntxt {
1002 uint16_t regcnt_status;
1007 q80_rsp_tx_ring_t tx_ring[MAX_TCNTXT_RINGS];
1008 } __packed q80_rsp_tx_cntxt_t;
1010 typedef struct _q80_tx_cntxt_destroy {
1012 uint16_t count_version;
1014 } __packed q80_tx_cntxt_destroy_t;
1016 typedef struct _q80_tx_cntxt_destroy_rsp {
1018 uint16_t regcnt_status;
1019 } __packed q80_tx_cntxt_destroy_rsp_t;
1022 * Transmit Command Descriptor
1023 * These commands are issued on the Transmit Ring associated with a Transmit
1026 typedef struct _q80_tx_cmd {
1027 uint8_t tcp_hdr_off; /* TCP Header Offset */
1028 uint8_t ip_hdr_off; /* IP Header Offset */
1029 uint16_t flags_opcode; /* Bits 0-6: flags; 7-12: opcode */
1032 #define Q8_TX_CMD_FLAGS_MULTICAST 0x01
1033 #define Q8_TX_CMD_FLAGS_LSO_TSO 0x02
1034 #define Q8_TX_CMD_FLAGS_VLAN_TAGGED 0x10
1035 #define Q8_TX_CMD_FLAGS_HW_VLAN_ID 0x40
1038 #define Q8_TX_CMD_OP_XMT_UDP_CHKSUM_IPV6 (0xC << 7)
1039 #define Q8_TX_CMD_OP_XMT_TCP_CHKSUM_IPV6 (0xB << 7)
1040 #define Q8_TX_CMD_OP_XMT_TCP_LSO_IPV6 (0x6 << 7)
1041 #define Q8_TX_CMD_OP_XMT_TCP_LSO (0x5 << 7)
1042 #define Q8_TX_CMD_OP_XMT_UDP_CHKSUM (0x3 << 7)
1043 #define Q8_TX_CMD_OP_XMT_TCP_CHKSUM (0x2 << 7)
1044 #define Q8_TX_CMD_OP_XMT_ETHER (0x1 << 7)
1046 uint8_t n_bufs; /* # of data segs in data buffer */
1047 uint8_t data_len_lo; /* data length lower 8 bits */
1048 uint16_t data_len_hi; /* data length upper 16 bits */
1050 uint64_t buf2_addr; /* buffer 2 address */
1053 uint16_t mss; /* MSS for this packet */
1054 uint8_t cntxtid; /* Bits 7-4: ContextId; 3-0: reserved */
1056 #define Q8_TX_CMD_PORT_CNXTID(c_id) ((c_id & 0xF) << 4)
1058 uint8_t total_hdr_len; /* MAC+IP+TCP Header Length for LSO */
1061 uint64_t buf3_addr; /* buffer 3 address */
1062 uint64_t buf1_addr; /* buffer 1 address */
1064 uint16_t buf1_len; /* length of buffer 1 */
1065 uint16_t buf2_len; /* length of buffer 2 */
1066 uint16_t buf3_len; /* length of buffer 3 */
1067 uint16_t buf4_len; /* length of buffer 4 */
1069 uint64_t buf4_addr; /* buffer 4 address */
1073 uint16_t vlan_tci; /* VLAN TCI when hw tagging is enabled*/
1075 } __packed q80_tx_cmd_t; /* 64 bytes */
1077 #define Q8_TX_CMD_MAX_SEGMENTS 4
1078 #define Q8_TX_CMD_TSO_ALIGN 2
1079 #define Q8_TX_MAX_NON_TSO_SEGS 62
1083 * Receive Related Definitions
1085 #define MAX_RDS_RING_SETS 8 /* Max# of Receive Descriptor Rings */
1086 #define MAX_SDS_RINGS 4 /* Max# of Status Descriptor Rings */
1088 typedef struct _q80_rq_sds_ring {
1089 uint64_t paddr; /* physical addr of status ring in system memory */
1090 uint64_t hdr_split1;
1091 uint64_t hdr_split2;
1092 uint16_t size; /* number of entries in status ring */
1093 uint16_t hdr_split1_size;
1094 uint16_t hdr_split2_size;
1095 uint16_t hdr_split_count;
1097 uint8_t intr_src_bit;
1099 } __packed q80_rq_sds_ring_t; /* 10 32bit words */
1101 typedef struct _q80_rq_rds_ring {
1102 uint64_t paddr_std; /* physical addr of rcv ring in system memory */
1103 uint64_t paddr_jumbo; /* physical addr of rcv ring in system memory */
1105 uint16_t std_nentries;
1106 uint16_t jumbo_bsize;
1107 uint16_t jumbo_nentries;
1108 } __packed q80_rq_rds_ring_t; /* 6 32bit words */
1110 #define MAX_RCNTXT_SDS_RINGS 8
1112 typedef struct _q80_rq_rcv_cntxt {
1114 uint16_t count_version;
1116 #define Q8_RCV_CNTXT_CAP0_BASEFW (1 << 0)
1117 #define Q8_RCV_CNTXT_CAP0_MULTI_RDS (1 << 1)
1118 #define Q8_RCV_CNTXT_CAP0_LRO (1 << 5)
1119 #define Q8_RCV_CNTXT_CAP0_HW_LRO (1 << 10)
1120 #define Q8_RCV_CNTXT_CAP0_VLAN_ALIGN (1 << 14)
1121 #define Q8_RCV_CNTXT_CAP0_RSS (1 << 15)
1122 #define Q8_RCV_CNTXT_CAP0_MSFT_RSS (1 << 16)
1123 #define Q8_RCV_CNTXT_CAP0_SGL_JUMBO (1 << 18)
1124 #define Q8_RCV_CNTXT_CAP0_SGL_LRO (1 << 19)
1129 uint8_t nrds_sets_rings;
1131 uint16_t rds_producer_mode;
1132 #define Q8_RCV_CNTXT_RDS_PROD_MODE_UNIQUE 0
1133 #define Q8_RCV_CNTXT_RDS_PROD_MODE_SHARED 1
1138 q80_rq_sds_ring_t sds[MAX_RCNTXT_SDS_RINGS];
1139 q80_rq_rds_ring_t rds[MAX_RDS_RING_SETS];
1140 } __packed q80_rq_rcv_cntxt_t;
1142 typedef struct _q80_rsp_rds_ring {
1144 uint32_t prod_jumbo;
1145 } __packed q80_rsp_rds_ring_t; /* 8 bytes */
1147 typedef struct _q80_rsp_rcv_cntxt {
1149 uint16_t regcnt_status;
1150 uint8_t nrds_sets_rings;
1157 uint32_t sds_cons[MAX_RCNTXT_SDS_RINGS];
1158 q80_rsp_rds_ring_t rds[MAX_RDS_RING_SETS];
1159 } __packed q80_rsp_rcv_cntxt_t;
1161 typedef struct _q80_rcv_cntxt_destroy {
1163 uint16_t count_version;
1165 } __packed q80_rcv_cntxt_destroy_t;
1167 typedef struct _q80_rcv_cntxt_destroy_rsp {
1169 uint16_t regcnt_status;
1170 } __packed q80_rcv_cntxt_destroy_rsp_t;
1176 typedef struct _q80_rq_add_rcv_rings {
1178 uint16_t count_version;
1179 uint8_t nrds_sets_rings;
1182 q80_rq_sds_ring_t sds[MAX_RCNTXT_SDS_RINGS];
1183 q80_rq_rds_ring_t rds[MAX_RDS_RING_SETS];
1184 } __packed q80_rq_add_rcv_rings_t;
1186 typedef struct _q80_rsp_add_rcv_rings {
1188 uint16_t regcnt_status;
1189 uint8_t nrds_sets_rings;
1192 uint32_t sds_cons[MAX_RCNTXT_SDS_RINGS];
1193 q80_rsp_rds_ring_t rds[MAX_RDS_RING_SETS];
1194 } __packed q80_rsp_add_rcv_rings_t;
1197 * Map Status Ring to Receive Descriptor Set
1200 #define MAX_SDS_TO_RDS_MAP 16
1202 typedef struct _q80_sds_rds_map_e {
1207 } __packed q80_sds_rds_map_e_t;
1209 typedef struct _q80_rq_map_sds_to_rds {
1211 uint16_t count_version;
1214 q80_sds_rds_map_e_t sds_rds[MAX_SDS_TO_RDS_MAP];
1215 } __packed q80_rq_map_sds_to_rds_t;
1218 typedef struct _q80_rsp_map_sds_to_rds {
1220 uint16_t regcnt_status;
1223 q80_sds_rds_map_e_t sds_rds[MAX_SDS_TO_RDS_MAP];
1224 } __packed q80_rsp_map_sds_to_rds_t;
1228 * Receive Descriptor corresponding to each entry in the receive ring
1230 typedef struct _q80_rcv_desc {
1233 uint32_t buf_size; /* buffer size in bytes */
1234 uint64_t buf_addr; /* physical address of buffer */
1235 } __packed q80_recv_desc_t;
1238 * Status Descriptor corresponding to each entry in the Status ring
1240 typedef struct _q80_stat_desc {
1242 } __packed q80_stat_desc_t;
1245 * definitions for data[0] field of Status Descriptor
1247 #define Q8_STAT_DESC_RSS_HASH(data) (data & 0xFFFFFFFF)
1248 #define Q8_STAT_DESC_TOTAL_LENGTH(data) ((data >> 32) & 0x3FFF)
1249 #define Q8_STAT_DESC_TOTAL_LENGTH_SGL_RCV(data) ((data >> 32) & 0xFFFF)
1250 #define Q8_STAT_DESC_HANDLE(data) ((data >> 48) & 0xFFFF)
1252 * definitions for data[1] field of Status Descriptor
1255 #define Q8_STAT_DESC_OPCODE(data) ((data >> 42) & 0xF)
1256 #define Q8_STAT_DESC_OPCODE_RCV_PKT 0x01
1257 #define Q8_STAT_DESC_OPCODE_LRO_PKT 0x02
1258 #define Q8_STAT_DESC_OPCODE_SGL_LRO 0x04
1259 #define Q8_STAT_DESC_OPCODE_SGL_RCV 0x05
1260 #define Q8_STAT_DESC_OPCODE_CONT 0x06
1263 * definitions for data[1] field of Status Descriptor for standard frames
1264 * status descriptor opcode equals 0x04
1266 #define Q8_STAT_DESC_STATUS(data) ((data >> 39) & 0x0007)
1267 #define Q8_STAT_DESC_STATUS_CHKSUM_NOT_DONE 0x00
1268 #define Q8_STAT_DESC_STATUS_NO_CHKSUM 0x01
1269 #define Q8_STAT_DESC_STATUS_CHKSUM_OK 0x02
1270 #define Q8_STAT_DESC_STATUS_CHKSUM_ERR 0x03
1272 #define Q8_STAT_DESC_VLAN(data) ((data >> 47) & 1)
1273 #define Q8_STAT_DESC_VLAN_ID(data) ((data >> 48) & 0xFFFF)
1275 #define Q8_STAT_DESC_PROTOCOL(data) ((data >> 44) & 0x000F)
1276 #define Q8_STAT_DESC_L2_OFFSET(data) ((data >> 48) & 0x001F)
1277 #define Q8_STAT_DESC_COUNT(data) ((data >> 37) & 0x0007)
1280 * definitions for data[0-1] fields of Status Descriptor for LRO
1281 * status descriptor opcode equals 0x04
1284 /* definitions for data[1] field */
1285 #define Q8_LRO_STAT_DESC_SEQ_NUM(data) (uint32_t)(data)
1288 * definitions specific to opcode 0x04 data[1]
1290 #define Q8_STAT_DESC_COUNT_SGL_LRO(data) ((data >> 13) & 0x0007)
1291 #define Q8_SGL_LRO_STAT_L2_OFFSET(data) ((data >> 16) & 0xFF)
1292 #define Q8_SGL_LRO_STAT_L4_OFFSET(data) ((data >> 24) & 0xFF)
1293 #define Q8_SGL_LRO_STAT_TS(data) ((data >> 40) & 0x1)
1294 #define Q8_SGL_LRO_STAT_PUSH_BIT(data) ((data >> 41) & 0x1)
1298 * definitions specific to opcode 0x05 data[1]
1300 #define Q8_STAT_DESC_COUNT_SGL_RCV(data) ((data >> 37) & 0x0003)
1303 * definitions for opcode 0x06
1305 /* definitions for data[0] field */
1306 #define Q8_SGL_STAT_DESC_HANDLE1(data) (data & 0xFFFF)
1307 #define Q8_SGL_STAT_DESC_HANDLE2(data) ((data >> 16) & 0xFFFF)
1308 #define Q8_SGL_STAT_DESC_HANDLE3(data) ((data >> 32) & 0xFFFF)
1309 #define Q8_SGL_STAT_DESC_HANDLE4(data) ((data >> 48) & 0xFFFF)
1311 /* definitions for data[1] field */
1312 #define Q8_SGL_STAT_DESC_HANDLE5(data) (data & 0xFFFF)
1313 #define Q8_SGL_STAT_DESC_HANDLE6(data) ((data >> 16) & 0xFFFF)
1314 #define Q8_SGL_STAT_DESC_NUM_HANDLES(data) ((data >> 32) & 0x7)
1315 #define Q8_SGL_STAT_DESC_HANDLE7(data) ((data >> 48) & 0xFFFF)
1317 /** Driver Related Definitions Begin **/
1319 #define TX_SMALL_PKT_SIZE 128 /* size in bytes of small packets */
1321 /* The number of descriptors should be a power of 2 */
1322 #define NUM_TX_DESCRIPTORS 1024
1323 #define NUM_STATUS_DESCRIPTORS 1024
1326 #define NUM_RX_DESCRIPTORS 2048
1327 #define MAX_RDS_RINGS MAX_SDS_RINGS /* Max# of Rcv Descriptor Rings */
1330 * structure describing various dma buffers
1333 typedef struct qla_dmabuf {
1335 uint32_t tx_ring :1,
1342 qla_dma_t rds_ring[MAX_RDS_RINGS];
1343 qla_dma_t sds_ring[MAX_SDS_RINGS];
1347 typedef struct _qla_sds {
1348 q80_stat_desc_t *sds_ring_base; /* start of sds ring */
1349 uint32_t sdsr_next; /* next entry in SDS ring to process */
1350 struct lro_ctrl lro;
1353 volatile uint32_t rcv_active;
1354 uint32_t sds_consumer;
1355 uint64_t intr_count;
1358 #define Q8_MAX_LRO_CONT_DESC 7
1359 #define Q8_MAX_HANDLES_LRO (1 + (Q8_MAX_LRO_CONT_DESC * 7))
1360 #define Q8_MAX_HANDLES_NON_LRO 8
1362 typedef struct _qla_sgl_rcv {
1363 uint16_t pkt_length;
1364 uint16_t num_handles;
1365 uint16_t chksum_status;
1367 uint16_t rss_hash_flags;
1369 uint16_t handle[Q8_MAX_HANDLES_NON_LRO];
1372 typedef struct _qla_sgl_lro {
1374 #define Q8_LRO_COMP_TS 0x1
1375 #define Q8_LRO_COMP_PUSH_BIT 0x2
1379 uint16_t payload_length;
1380 uint16_t num_handles;
1382 uint16_t rss_hash_flags;
1384 uint16_t handle[Q8_MAX_HANDLES_LRO];
1392 #define QL_FRAME_HDR_SIZE (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +\
1393 sizeof (struct ip6_hdr) + sizeof (struct tcphdr) + 16)
1395 typedef struct _qla_hw_tx_cntxt {
1396 q80_tx_cmd_t *tx_ring_base;
1397 bus_addr_t tx_ring_paddr;
1399 volatile uint32_t *tx_cons; /* tx consumer shadow reg */
1400 bus_addr_t tx_cons_paddr;
1402 volatile uint32_t txr_free; /* # of free entries in tx ring */
1403 volatile uint32_t txr_next; /* # next available tx ring entry */
1404 volatile uint32_t txr_comp; /* index of last tx entry completed */
1406 uint32_t tx_prod_reg;
1407 uint16_t tx_cntxt_id;
1408 uint8_t frame_hdr[QL_FRAME_HDR_SIZE];
1410 } qla_hw_tx_cntxt_t;
1412 typedef struct _qla_mcast {
1415 } __packed qla_mcast_t;
1417 typedef struct _qla_rdesc {
1418 volatile uint32_t prod_std;
1419 volatile uint32_t prod_jumbo;
1420 volatile uint32_t rx_next; /* next standard rcv ring to arm fw */
1421 volatile int32_t rx_in; /* next standard rcv ring to add mbufs */
1422 volatile uint64_t count;
1425 typedef struct _qla_flash_desc_table {
1426 uint32_t flash_valid;
1429 uint16_t flash_cksum;
1430 uint16_t flash_unused;
1431 uint8_t flash_model[16];
1432 uint16_t flash_manuf;
1436 uint8_t alt_erase_cmd;
1437 uint8_t write_enable_cmd;
1438 uint8_t write_enable_bits;
1439 uint8_t write_statusreg_cmd;
1440 uint8_t unprotected_sec_cmd;
1441 uint8_t read_manuf_cmd;
1442 uint32_t block_size;
1443 uint32_t alt_block_size;
1444 uint32_t flash_size;
1445 uint32_t write_enable_data;
1446 uint8_t readid_addr_len;
1447 uint8_t write_disable_bits;
1448 uint8_t read_dev_id_len;
1449 uint8_t chip_erase_cmd;
1450 uint16_t read_timeo;
1451 uint8_t protected_sec_cmd;
1453 } __packed qla_flash_desc_table_t;
1455 #define NUM_TX_RINGS 4
1458 * struct for storing hardware specific information for a given interface
1460 typedef struct _qla_hw {
1475 uint16_t link_speed;
1476 uint16_t cable_length;
1479 uint8_t module_type;
1480 uint8_t link_faults;
1482 uint8_t mac_rcv_mode;
1486 uint8_t mac_addr[ETHER_ADDR_LEN];
1488 uint32_t num_sds_rings;
1489 uint32_t num_rds_rings;
1490 uint32_t num_tx_rings;
1492 qla_dmabuf_t dma_buf;
1496 qla_hw_tx_cntxt_t tx_cntxt[NUM_TX_RINGS];
1500 uint16_t rcv_cntxt_id;
1502 uint32_t mbx_intr_mask_offset;
1504 uint16_t intr_id[MAX_SDS_RINGS];
1505 uint32_t intr_src[MAX_SDS_RINGS];
1507 qla_sds_t sds[MAX_SDS_RINGS];
1508 uint32_t mbox[Q8_NUM_MBOX];
1509 qla_rdesc_t rds[MAX_RDS_RINGS];
1511 uint32_t rds_pidx_thres;
1512 uint32_t sds_cidx_thres;
1514 /* multicast address list */
1516 qla_mcast_t mcast[Q8_MAX_NUM_MULTICAST_ADDRS];
1518 /* reset sequence */
1519 #define Q8_MAX_RESET_SEQ_IDX 16
1520 uint32_t rst_seq[Q8_MAX_RESET_SEQ_IDX];
1521 uint32_t rst_seq_idx;
1523 /* heart beat register value */
1524 uint32_t hbeat_value;
1525 uint32_t health_count;
1527 uint32_t max_tx_segs;
1528 uint32_t min_lro_pkt_size;
1530 /* Flash Descriptor Table */
1531 qla_flash_desc_table_t fdt;
1533 /* Minidump Related */
1534 uint32_t mdump_init;
1535 uint32_t mdump_start;
1536 uint32_t mdump_active;
1537 uint32_t mdump_start_seq_index;
1540 #define QL_UPDATE_RDS_PRODUCER_INDEX(ha, prod_reg, val) \
1541 bus_write_4((ha->pci_reg), prod_reg, val);
1543 #define QL_UPDATE_TX_PRODUCER_INDEX(ha, val, i) \
1544 WRITE_REG32(ha, ha->hw.tx_cntxt[i].tx_prod_reg, val)
1546 #define QL_UPDATE_SDS_CONSUMER_INDEX(ha, i, val) \
1547 bus_write_4((ha->pci_reg), (ha->hw.sds[i].sds_consumer), val);
1549 #define QL_ENABLE_INTERRUPTS(ha, i) \
1550 bus_write_4((ha->pci_reg), (ha->hw.intr_src[i]), 0);
1552 #define QL_BUFFER_ALIGN 16
1556 * Flash Configuration
1558 #define Q8_BOARD_CONFIG_OFFSET 0x370000
1559 #define Q8_BOARD_CONFIG_LENGTH 0x2000
1561 #define Q8_BOARD_CONFIG_MAC0_LO 0x400
1563 #define Q8_FDT_LOCK_MAGIC_ID 0x00FD00FD
1564 #define Q8_FDT_FLASH_ADDR_VAL 0xFD009F
1565 #define Q8_FDT_FLASH_CTRL_VAL 0x3F
1566 #define Q8_FDT_MASK_VAL 0xFF
1568 #define Q8_WR_ENABLE_FL_ADDR 0xFD0100
1569 #define Q8_WR_ENABLE_FL_CTRL 0x5
1571 #define Q8_ERASE_LOCK_MAGIC_ID 0x00EF00EF
1572 #define Q8_ERASE_FL_ADDR_MASK 0xFD0300
1573 #define Q8_ERASE_FL_CTRL_MASK 0x3D
1575 #define Q8_WR_FL_LOCK_MAGIC_ID 0xABCDABCD
1576 #define Q8_WR_FL_ADDR_MASK 0x800000
1577 #define Q8_WR_FL_CTRL_MASK 0x3D
1579 #define QL_FDT_OFFSET 0x3F0000
1580 #define Q8_FLASH_SECTOR_SIZE 0x10000
1583 * Off Chip Memory Access
1586 typedef struct _q80_offchip_mem_val {
1591 } q80_offchip_mem_val_t;
1593 #endif /* #ifndef _QL_HW_H_ */