sys/dev/qlxge/qls_dump.c

   1 /*
   2  * Copyright (c) 2013-2014 Qlogic Corporation
   3  * All rights reserved.
   4  *
   5  *  Redistribution and use in source and binary forms, with or without
   6  *  modification, are permitted provided that the following conditions
   7  *  are met:
   8  *
   9  *  1. Redistributions of source code must retain the above copyright
  10  *     notice, this list of conditions and the following disclaimer.
  11  *  2. Redistributions in binary form must reproduce the above copyright
  12  *     notice, this list of conditions and the following disclaimer in the
  13  *     documentation and/or other materials provided with the distribution.
  14  *
  15  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  16  *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  19  *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  20  *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  21  *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  22  *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  23  *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  24  *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  25  *  POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 /*
  29  * File: qls_dump.c
  30  */
  31 #include <sys/cdefs.h>
  32 __FBSDID("$FreeBSD$");
  33
  34
  35 #include "qls_os.h"
  36 #include "qls_hw.h"
  37 #include "qls_def.h"
  38 #include "qls_glbl.h"
  39 #include "qls_dump.h"
  40
  41 qls_mpi_coredump_t ql_mpi_coredump;
  42
  43 #define Q81_CORE_SEG_NUM              1
  44 #define Q81_TEST_LOGIC_SEG_NUM        2
  45 #define Q81_RMII_SEG_NUM              3
  46 #define Q81_FCMAC1_SEG_NUM            4
  47 #define Q81_FCMAC2_SEG_NUM            5
  48 #define Q81_FC1_MBOX_SEG_NUM          6
  49 #define Q81_IDE_SEG_NUM               7
  50 #define Q81_NIC1_MBOX_SEG_NUM         8
  51 #define Q81_SMBUS_SEG_NUM             9
  52 #define Q81_FC2_MBOX_SEG_NUM          10
  53 #define Q81_NIC2_MBOX_SEG_NUM         11
  54 #define Q81_I2C_SEG_NUM               12
  55 #define Q81_MEMC_SEG_NUM              13
  56 #define Q81_PBUS_SEG_NUM              14
  57 #define Q81_MDE_SEG_NUM               15
  58 #define Q81_NIC1_CONTROL_SEG_NUM      16
  59 #define Q81_NIC2_CONTROL_SEG_NUM      17
  60 #define Q81_NIC1_XGMAC_SEG_NUM        18
  61 #define Q81_NIC2_XGMAC_SEG_NUM        19
  62 #define Q81_WCS_RAM_SEG_NUM           20
  63 #define Q81_MEMC_RAM_SEG_NUM          21
  64 #define Q81_XAUI1_AN_SEG_NUM          22
  65 #define Q81_XAUI1_HSS_PCS_SEG_NUM     23
  66 #define Q81_XFI1_AN_SEG_NUM           24
  67 #define Q81_XFI1_TRAIN_SEG_NUM        25
  68 #define Q81_XFI1_HSS_PCS_SEG_NUM      26
  69 #define Q81_XFI1_HSS_TX_SEG_NUM       27
  70 #define Q81_XFI1_HSS_RX_SEG_NUM       28
  71 #define Q81_XFI1_HSS_PLL_SEG_NUM      29
  72 #define Q81_INTR_STATES_SEG_NUM       31
  73 #define Q81_ETS_SEG_NUM               34
  74 #define Q81_PROBE_DUMP_SEG_NUM        35
  75 #define Q81_ROUTING_INDEX_SEG_NUM     36
  76 #define Q81_MAC_PROTOCOL_SEG_NUM      37
  77 #define Q81_XAUI2_AN_SEG_NUM          38
  78 #define Q81_XAUI2_HSS_PCS_SEG_NUM     39
  79 #define Q81_XFI2_AN_SEG_NUM           40
  80 #define Q81_XFI2_TRAIN_SEG_NUM        41
  81 #define Q81_XFI2_HSS_PCS_SEG_NUM      42
  82 #define Q81_XFI2_HSS_TX_SEG_NUM       43
  83 #define Q81_XFI2_HSS_RX_SEG_NUM       44
  84 #define Q81_XFI2_HSS_PLL_SEG_NUM      45
  85 #define Q81_WQC1_SEG_NUM              46
  86 #define Q81_CQC1_SEG_NUM              47
  87 #define Q81_WQC2_SEG_NUM              48
  88 #define Q81_CQC2_SEG_NUM              49
  89 #define Q81_SEM_REGS_SEG_NUM          50
  90
  91 enum
  92 {
  93         Q81_PAUSE_SRC_LO               = 0x00000100,
  94         Q81_PAUSE_SRC_HI               = 0x00000104,
  95         Q81_GLOBAL_CFG                 = 0x00000108,
  96         Q81_GLOBAL_CFG_RESET           = (1 << 0),    /*Control*/
  97         Q81_GLOBAL_CFG_JUMBO           = (1 << 6),    /*Control*/
  98         Q81_GLOBAL_CFG_TX_STAT_EN      = (1 << 10),   /*Control*/
  99         Q81_GLOBAL_CFG_RX_STAT_EN      = (1 << 11),   /*Control*/
 100         Q81_TX_CFG                     = 0x0000010c,
 101         Q81_TX_CFG_RESET               = (1 << 0),    /*Control*/
 102         Q81_TX_CFG_EN                  = (1 << 1),    /*Control*/
 103         Q81_TX_CFG_PREAM               = (1 << 2),    /*Control*/
 104         Q81_RX_CFG                     = 0x00000110,
 105         Q81_RX_CFG_RESET               = (1 << 0),    /*Control*/
 106         Q81_RX_CFG_EN                  = (1 << 1),    /*Control*/
 107         Q81_RX_CFG_PREAM               = (1 << 2),    /*Control*/
 108         Q81_FLOW_CTL                   = 0x0000011c,
 109         Q81_PAUSE_OPCODE               = 0x00000120,
 110         Q81_PAUSE_TIMER                = 0x00000124,
 111         Q81_PAUSE_FRM_DEST_LO          = 0x00000128,
 112         Q81_PAUSE_FRM_DEST_HI          = 0x0000012c,
 113         Q81_MAC_TX_PARAMS              = 0x00000134,
 114         Q81_MAC_TX_PARAMS_JUMBO        = (1 << 31),   /*Control*/
 115         Q81_MAC_TX_PARAMS_SIZE_SHIFT   = 16,          /*Control*/
 116         Q81_MAC_RX_PARAMS              = 0x00000138,
 117         Q81_MAC_SYS_INT                = 0x00000144,
 118         Q81_MAC_SYS_INT_MASK           = 0x00000148,
 119         Q81_MAC_MGMT_INT               = 0x0000014c,
 120         Q81_MAC_MGMT_IN_MASK           = 0x00000150,
 121         Q81_EXT_ARB_MODE               = 0x000001fc,
 122         Q81_TX_PKTS                    = 0x00000200,
 123         Q81_TX_PKTS_LO                 = 0x00000204,
 124         Q81_TX_BYTES                   = 0x00000208,
 125         Q81_TX_BYTES_LO                = 0x0000020C,
 126         Q81_TX_MCAST_PKTS              = 0x00000210,
 127         Q81_TX_MCAST_PKTS_LO           = 0x00000214,
 128         Q81_TX_BCAST_PKTS              = 0x00000218,
 129         Q81_TX_BCAST_PKTS_LO           = 0x0000021C,
 130         Q81_TX_UCAST_PKTS              = 0x00000220,
 131         Q81_TX_UCAST_PKTS_LO           = 0x00000224,
 132         Q81_TX_CTL_PKTS                = 0x00000228,
 133         Q81_TX_CTL_PKTS_LO             = 0x0000022c,
 134         Q81_TX_PAUSE_PKTS              = 0x00000230,
 135         Q81_TX_PAUSE_PKTS_LO           = 0x00000234,
 136         Q81_TX_64_PKT                  = 0x00000238,
 137         Q81_TX_64_PKT_LO               = 0x0000023c,
 138         Q81_TX_65_TO_127_PKT           = 0x00000240,
 139         Q81_TX_65_TO_127_PKT_LO        = 0x00000244,
 140         Q81_TX_128_TO_255_PKT          = 0x00000248,
 141         Q81_TX_128_TO_255_PKT_LO       = 0x0000024c,
 142         Q81_TX_256_511_PKT             = 0x00000250,
 143         Q81_TX_256_511_PKT_LO          = 0x00000254,
 144         Q81_TX_512_TO_1023_PKT         = 0x00000258,
 145         Q81_TX_512_TO_1023_PKT_LO      = 0x0000025c,
 146         Q81_TX_1024_TO_1518_PKT        = 0x00000260,
 147         Q81_TX_1024_TO_1518_PKT_LO     = 0x00000264,
 148         Q81_TX_1519_TO_MAX_PKT         = 0x00000268,
 149         Q81_TX_1519_TO_MAX_PKT_LO      = 0x0000026c,
 150         Q81_TX_UNDERSIZE_PKT           = 0x00000270,
 151         Q81_TX_UNDERSIZE_PKT_LO        = 0x00000274,
 152         Q81_TX_OVERSIZE_PKT            = 0x00000278,
 153         Q81_TX_OVERSIZE_PKT_LO         = 0x0000027c,
 154         Q81_RX_HALF_FULL_DET           = 0x000002a0,
 155         Q81_TX_HALF_FULL_DET_LO        = 0x000002a4,
 156         Q81_RX_OVERFLOW_DET            = 0x000002a8,
 157         Q81_TX_OVERFLOW_DET_LO         = 0x000002ac,
 158         Q81_RX_HALF_FULL_MASK          = 0x000002b0,
 159         Q81_TX_HALF_FULL_MASK_LO       = 0x000002b4,
 160         Q81_RX_OVERFLOW_MASK           = 0x000002b8,
 161         Q81_TX_OVERFLOW_MASK_LO        = 0x000002bc,
 162         Q81_STAT_CNT_CTL               = 0x000002c0,
 163         Q81_STAT_CNT_CTL_CLEAR_TX      = (1 << 0),   /*Control*/
 164         Q81_STAT_CNT_CTL_CLEAR_RX      = (1 << 1),   /*Control*/
 165         Q81_AUX_RX_HALF_FULL_DET       = 0x000002d0,
 166         Q81_AUX_TX_HALF_FULL_DET       = 0x000002d4,
 167         Q81_AUX_RX_OVERFLOW_DET        = 0x000002d8,
 168         Q81_AUX_TX_OVERFLOW_DET        = 0x000002dc,
 169         Q81_AUX_RX_HALF_FULL_MASK      = 0x000002f0,
 170         Q81_AUX_TX_HALF_FULL_MASK      = 0x000002f4,
 171         Q81_AUX_RX_OVERFLOW_MASK       = 0x000002f8,
 172         Q81_AUX_TX_OVERFLOW_MASK       = 0x000002fc,
 173         Q81_RX_BYTES                   = 0x00000300,
 174         Q81_RX_BYTES_LO                = 0x00000304,
 175         Q81_RX_BYTES_OK                = 0x00000308,
 176         Q81_RX_BYTES_OK_LO             = 0x0000030c,
 177         Q81_RX_PKTS                    = 0x00000310,
 178         Q81_RX_PKTS_LO                 = 0x00000314,
 179         Q81_RX_PKTS_OK                 = 0x00000318,
 180         Q81_RX_PKTS_OK_LO              = 0x0000031c,
 181         Q81_RX_BCAST_PKTS              = 0x00000320,
 182         Q81_RX_BCAST_PKTS_LO           = 0x00000324,
 183         Q81_RX_MCAST_PKTS              = 0x00000328,
 184         Q81_RX_MCAST_PKTS_LO           = 0x0000032c,
 185         Q81_RX_UCAST_PKTS              = 0x00000330,
 186         Q81_RX_UCAST_PKTS_LO           = 0x00000334,
 187         Q81_RX_UNDERSIZE_PKTS          = 0x00000338,
 188         Q81_RX_UNDERSIZE_PKTS_LO       = 0x0000033c,
 189         Q81_RX_OVERSIZE_PKTS           = 0x00000340,
 190         Q81_RX_OVERSIZE_PKTS_LO        = 0x00000344,
 191         Q81_RX_JABBER_PKTS             = 0x00000348,
 192         Q81_RX_JABBER_PKTS_LO          = 0x0000034c,
 193         Q81_RX_UNDERSIZE_FCERR_PKTS    = 0x00000350,
 194         Q81_RX_UNDERSIZE_FCERR_PKTS_LO = 0x00000354,
 195         Q81_RX_DROP_EVENTS             = 0x00000358,
 196         Q81_RX_DROP_EVENTS_LO          = 0x0000035c,
 197         Q81_RX_FCERR_PKTS              = 0x00000360,
 198         Q81_RX_FCERR_PKTS_LO           = 0x00000364,
 199         Q81_RX_ALIGN_ERR               = 0x00000368,
 200         Q81_RX_ALIGN_ERR_LO            = 0x0000036c,
 201         Q81_RX_SYMBOL_ERR              = 0x00000370,
 202         Q81_RX_SYMBOL_ERR_LO           = 0x00000374,
 203         Q81_RX_MAC_ERR                 = 0x00000378,
 204         Q81_RX_MAC_ERR_LO              = 0x0000037c,
 205         Q81_RX_CTL_PKTS                = 0x00000380,
 206         Q81_RX_CTL_PKTS_LO             = 0x00000384,
 207         Q81_RX_PAUSE_PKTS              = 0x00000388,
 208         Q81_RX_PAUSE_PKTS_LO           = 0x0000038c,
 209         Q81_RX_64_PKTS                 = 0x00000390,
 210         Q81_RX_64_PKTS_LO              = 0x00000394,
 211         Q81_RX_65_TO_127_PKTS          = 0x00000398,
 212         Q81_RX_65_TO_127_PKTS_LO       = 0x0000039c,
 213         Q81_RX_128_255_PKTS            = 0x000003a0,
 214         Q81_RX_128_255_PKTS_LO         = 0x000003a4,
 215         Q81_RX_256_511_PKTS            = 0x000003a8,
 216         Q81_RX_256_511_PKTS_LO         = 0x000003ac,
 217         Q81_RX_512_TO_1023_PKTS        = 0x000003b0,
 218         Q81_RX_512_TO_1023_PKTS_LO     = 0x000003b4,
 219         Q81_RX_1024_TO_1518_PKTS       = 0x000003b8,
 220         Q81_RX_1024_TO_1518_PKTS_LO    = 0x000003bc,
 221         Q81_RX_1519_TO_MAX_PKTS        = 0x000003c0,
 222         Q81_RX_1519_TO_MAX_PKTS_LO     = 0x000003c4,
 223         Q81_RX_LEN_ERR_PKTS            = 0x000003c8,
 224         Q81_RX_LEN_ERR_PKTS_LO         = 0x000003cc,
 225         Q81_MDIO_TX_DATA               = 0x00000400,
 226         Q81_MDIO_RX_DATA               = 0x00000410,
 227         Q81_MDIO_CMD                   = 0x00000420,
 228         Q81_MDIO_PHY_ADDR              = 0x00000430,
 229         Q81_MDIO_PORT                  = 0x00000440,
 230         Q81_MDIO_STATUS                = 0x00000450,
 231         Q81_TX_CBFC_PAUSE_FRAMES0      = 0x00000500,
 232         Q81_TX_CBFC_PAUSE_FRAMES0_LO   = 0x00000504,
 233         Q81_TX_CBFC_PAUSE_FRAMES1      = 0x00000508,
 234         Q81_TX_CBFC_PAUSE_FRAMES1_LO   = 0x0000050C,
 235         Q81_TX_CBFC_PAUSE_FRAMES2      = 0x00000510,
 236         Q81_TX_CBFC_PAUSE_FRAMES2_LO   = 0x00000514,
 237         Q81_TX_CBFC_PAUSE_FRAMES3      = 0x00000518,
 238         Q81_TX_CBFC_PAUSE_FRAMES3_LO   = 0x0000051C,
 239         Q81_TX_CBFC_PAUSE_FRAMES4      = 0x00000520,
 240         Q81_TX_CBFC_PAUSE_FRAMES4_LO   = 0x00000524,
 241         Q81_TX_CBFC_PAUSE_FRAMES5      = 0x00000528,
 242         Q81_TX_CBFC_PAUSE_FRAMES5_LO   = 0x0000052C,
 243         Q81_TX_CBFC_PAUSE_FRAMES6      = 0x00000530,
 244         Q81_TX_CBFC_PAUSE_FRAMES6_LO   = 0x00000534,
 245         Q81_TX_CBFC_PAUSE_FRAMES7      = 0x00000538,
 246         Q81_TX_CBFC_PAUSE_FRAMES7_LO   = 0x0000053C,
 247         Q81_TX_FCOE_PKTS               = 0x00000540,
 248         Q81_TX_FCOE_PKTS_LO            = 0x00000544,
 249         Q81_TX_MGMT_PKTS               = 0x00000548,
 250         Q81_TX_MGMT_PKTS_LO            = 0x0000054C,
 251         Q81_RX_CBFC_PAUSE_FRAMES0      = 0x00000568,
 252         Q81_RX_CBFC_PAUSE_FRAMES0_LO   = 0x0000056C,
 253         Q81_RX_CBFC_PAUSE_FRAMES1      = 0x00000570,
 254         Q81_RX_CBFC_PAUSE_FRAMES1_LO   = 0x00000574,
 255         Q81_RX_CBFC_PAUSE_FRAMES2      = 0x00000578,
 256         Q81_RX_CBFC_PAUSE_FRAMES2_LO   = 0x0000057C,
 257         Q81_RX_CBFC_PAUSE_FRAMES3      = 0x00000580,
 258         Q81_RX_CBFC_PAUSE_FRAMES3_LO   = 0x00000584,
 259         Q81_RX_CBFC_PAUSE_FRAMES4      = 0x00000588,
 260         Q81_RX_CBFC_PAUSE_FRAMES4_LO   = 0x0000058C,
 261         Q81_RX_CBFC_PAUSE_FRAMES5      = 0x00000590,
 262         Q81_RX_CBFC_PAUSE_FRAMES5_LO   = 0x00000594,
 263         Q81_RX_CBFC_PAUSE_FRAMES6      = 0x00000598,
 264         Q81_RX_CBFC_PAUSE_FRAMES6_LO   = 0x0000059C,
 265         Q81_RX_CBFC_PAUSE_FRAMES7      = 0x000005A0,
 266         Q81_RX_CBFC_PAUSE_FRAMES7_LO   = 0x000005A4,
 267         Q81_RX_FCOE_PKTS               = 0x000005A8,
 268         Q81_RX_FCOE_PKTS_LO            = 0x000005AC,
 269         Q81_RX_MGMT_PKTS               = 0x000005B0,
 270         Q81_RX_MGMT_PKTS_LO            = 0x000005B4,
 271         Q81_RX_NIC_FIFO_DROP           = 0x000005B8,
 272         Q81_RX_NIC_FIFO_DROP_LO        = 0x000005BC,
 273         Q81_RX_FCOE_FIFO_DROP          = 0x000005C0,
 274         Q81_RX_FCOE_FIFO_DROP_LO       = 0x000005C4,
 275         Q81_RX_MGMT_FIFO_DROP          = 0x000005C8,
 276         Q81_RX_MGMT_FIFO_DROP_LO       = 0x000005CC,
 277         Q81_RX_PKTS_PRIORITY0          = 0x00000600,
 278         Q81_RX_PKTS_PRIORITY0_LO       = 0x00000604,
 279         Q81_RX_PKTS_PRIORITY1          = 0x00000608,
 280         Q81_RX_PKTS_PRIORITY1_LO       = 0x0000060C,
 281         Q81_RX_PKTS_PRIORITY2          = 0x00000610,
 282         Q81_RX_PKTS_PRIORITY2_LO       = 0x00000614,
 283         Q81_RX_PKTS_PRIORITY3          = 0x00000618,
 284         Q81_RX_PKTS_PRIORITY3_LO       = 0x0000061C,
 285         Q81_RX_PKTS_PRIORITY4          = 0x00000620,
 286         Q81_RX_PKTS_PRIORITY4_LO       = 0x00000624,
 287         Q81_RX_PKTS_PRIORITY5          = 0x00000628,
 288         Q81_RX_PKTS_PRIORITY5_LO       = 0x0000062C,
 289         Q81_RX_PKTS_PRIORITY6          = 0x00000630,
 290         Q81_RX_PKTS_PRIORITY6_LO       = 0x00000634,
 291         Q81_RX_PKTS_PRIORITY7          = 0x00000638,
 292         Q81_RX_PKTS_PRIORITY7_LO       = 0x0000063C,
 293         Q81_RX_OCTETS_PRIORITY0        = 0x00000640,
 294         Q81_RX_OCTETS_PRIORITY0_LO     = 0x00000644,
 295         Q81_RX_OCTETS_PRIORITY1        = 0x00000648,
 296         Q81_RX_OCTETS_PRIORITY1_LO     = 0x0000064C,
 297         Q81_RX_OCTETS_PRIORITY2        = 0x00000650,
 298         Q81_RX_OCTETS_PRIORITY2_LO     = 0x00000654,
 299         Q81_RX_OCTETS_PRIORITY3        = 0x00000658,
 300         Q81_RX_OCTETS_PRIORITY3_LO     = 0x0000065C,
 301         Q81_RX_OCTETS_PRIORITY4        = 0x00000660,
 302         Q81_RX_OCTETS_PRIORITY4_LO     = 0x00000664,
 303         Q81_RX_OCTETS_PRIORITY5        = 0x00000668,
 304         Q81_RX_OCTETS_PRIORITY5_LO     = 0x0000066C,
 305         Q81_RX_OCTETS_PRIORITY6        = 0x00000670,
 306         Q81_RX_OCTETS_PRIORITY6_LO     = 0x00000674,
 307         Q81_RX_OCTETS_PRIORITY7        = 0x00000678,
 308         Q81_RX_OCTETS_PRIORITY7_LO     = 0x0000067C,
 309         Q81_TX_PKTS_PRIORITY0          = 0x00000680,
 310         Q81_TX_PKTS_PRIORITY0_LO       = 0x00000684,
 311         Q81_TX_PKTS_PRIORITY1          = 0x00000688,
 312         Q81_TX_PKTS_PRIORITY1_LO       = 0x0000068C,
 313         Q81_TX_PKTS_PRIORITY2          = 0x00000690,
 314         Q81_TX_PKTS_PRIORITY2_LO       = 0x00000694,
 315         Q81_TX_PKTS_PRIORITY3          = 0x00000698,
 316         Q81_TX_PKTS_PRIORITY3_LO       = 0x0000069C,
 317         Q81_TX_PKTS_PRIORITY4          = 0x000006A0,
 318         Q81_TX_PKTS_PRIORITY4_LO       = 0x000006A4,
 319         Q81_TX_PKTS_PRIORITY5          = 0x000006A8,
 320         Q81_TX_PKTS_PRIORITY5_LO       = 0x000006AC,
 321         Q81_TX_PKTS_PRIORITY6          = 0x000006B0,
 322         Q81_TX_PKTS_PRIORITY6_LO       = 0x000006B4,
 323         Q81_TX_PKTS_PRIORITY7          = 0x000006B8,
 324         Q81_TX_PKTS_PRIORITY7_LO       = 0x000006BC,
 325         Q81_TX_OCTETS_PRIORITY0        = 0x000006C0,
 326         Q81_TX_OCTETS_PRIORITY0_LO     = 0x000006C4,
 327         Q81_TX_OCTETS_PRIORITY1        = 0x000006C8,
 328         Q81_TX_OCTETS_PRIORITY1_LO     = 0x000006CC,
 329         Q81_TX_OCTETS_PRIORITY2        = 0x000006D0,
 330         Q81_TX_OCTETS_PRIORITY2_LO     = 0x000006D4,
 331         Q81_TX_OCTETS_PRIORITY3        = 0x000006D8,
 332         Q81_TX_OCTETS_PRIORITY3_LO     = 0x000006DC,
 333         Q81_TX_OCTETS_PRIORITY4        = 0x000006E0,
 334         Q81_TX_OCTETS_PRIORITY4_LO     = 0x000006E4,
 335         Q81_TX_OCTETS_PRIORITY5        = 0x000006E8,
 336         Q81_TX_OCTETS_PRIORITY5_LO     = 0x000006EC,
 337         Q81_TX_OCTETS_PRIORITY6        = 0x000006F0,
 338         Q81_TX_OCTETS_PRIORITY6_LO     = 0x000006F4,
 339         Q81_TX_OCTETS_PRIORITY7        = 0x000006F8,
 340         Q81_TX_OCTETS_PRIORITY7_LO     = 0x000006FC,
 341         Q81_RX_DISCARD_PRIORITY0       = 0x00000700,
 342         Q81_RX_DISCARD_PRIORITY0_LO    = 0x00000704,
 343         Q81_RX_DISCARD_PRIORITY1       = 0x00000708,
 344         Q81_RX_DISCARD_PRIORITY1_LO    = 0x0000070C,
 345         Q81_RX_DISCARD_PRIORITY2       = 0x00000710,
 346         Q81_RX_DISCARD_PRIORITY2_LO    = 0x00000714,
 347         Q81_RX_DISCARD_PRIORITY3       = 0x00000718,
 348         Q81_RX_DISCARD_PRIORITY3_LO    = 0x0000071C,
 349         Q81_RX_DISCARD_PRIORITY4       = 0x00000720,
 350         Q81_RX_DISCARD_PRIORITY4_LO    = 0x00000724,
 351         Q81_RX_DISCARD_PRIORITY5       = 0x00000728,
 352         Q81_RX_DISCARD_PRIORITY5_LO    = 0x0000072C,
 353         Q81_RX_DISCARD_PRIORITY6       = 0x00000730,
 354         Q81_RX_DISCARD_PRIORITY6_LO    = 0x00000734,
 355         Q81_RX_DISCARD_PRIORITY7       = 0x00000738,
 356         Q81_RX_DISCARD_PRIORITY7_LO    = 0x0000073C
 357 };
 358
 359 static void
 360 qls_mpid_seg_hdr(qls_mpid_seg_hdr_t *seg_hdr, uint32_t seg_num,
 361         uint32_t seg_size, unsigned char *desc)
 362 {
 363         memset(seg_hdr, 0, sizeof(qls_mpid_seg_hdr_t));
 364
 365         seg_hdr->cookie = Q81_MPID_COOKIE;
 366         seg_hdr->seg_num = seg_num;
 367         seg_hdr->seg_size = seg_size;
 368
 369         memcpy(seg_hdr->desc, desc, (sizeof(seg_hdr->desc))-1);
 370
 371         return;
 372 }
 373
 374 static int
 375 qls_wait_reg_rdy(qla_host_t *ha , uint32_t reg, uint32_t bit, uint32_t err_bit)
 376 {
 377         uint32_t data;
 378         int count = 10;
 379
 380         while (count) {
 381
 382                 data = READ_REG32(ha, reg);
 383
 384                 if (data & err_bit)
 385                         return (-1);
 386                 else if (data & bit)
 387                         return (0);
 388
 389                 qls_mdelay(__func__, 10);
 390                 count--;
 391         }
 392         return (-1);
 393 }
 394
 395 static int
 396 qls_rd_mpi_reg(qla_host_t *ha, uint32_t reg, uint32_t *data)
 397 {
 398         int ret;
 399
 400         ret = qls_wait_reg_rdy(ha, Q81_CTL_PROC_ADDR, Q81_CTL_PROC_ADDR_RDY,
 401                         Q81_CTL_PROC_ADDR_ERR);
 402
 403         if (ret)
 404                 goto exit_qls_rd_mpi_reg;
 405
 406         WRITE_REG32(ha, Q81_CTL_PROC_ADDR, reg | Q81_CTL_PROC_ADDR_READ);
 407
 408         ret = qls_wait_reg_rdy(ha, Q81_CTL_PROC_ADDR, Q81_CTL_PROC_ADDR_RDY,
 409                         Q81_CTL_PROC_ADDR_ERR);
 410
 411         if (ret)
 412                 goto exit_qls_rd_mpi_reg;
 413
 414         *data = READ_REG32(ha, Q81_CTL_PROC_DATA);
 415
 416 exit_qls_rd_mpi_reg:
 417         return (ret);
 418 }
 419
 420 static int
 421 qls_wr_mpi_reg(qla_host_t *ha, uint32_t reg, uint32_t data)
 422 {
 423         int ret = 0;
 424
 425         ret = qls_wait_reg_rdy(ha, Q81_CTL_PROC_ADDR, Q81_CTL_PROC_ADDR_RDY,
 426                         Q81_CTL_PROC_ADDR_ERR);
 427         if (ret)
 428                 goto exit_qls_wr_mpi_reg;
 429
 430         WRITE_REG32(ha, Q81_CTL_PROC_DATA, data);
 431
 432         WRITE_REG32(ha, Q81_CTL_PROC_ADDR, reg);
 433
 434         ret = qls_wait_reg_rdy(ha, Q81_CTL_PROC_ADDR, Q81_CTL_PROC_ADDR_RDY,
 435                         Q81_CTL_PROC_ADDR_ERR);
 436 exit_qls_wr_mpi_reg:
 437         return (ret);
 438 }
 439
 440
 441 #define Q81_TEST_LOGIC_FUNC_PORT_CONFIG 0x1002
 442 #define Q81_INVALID_NUM         0xFFFFFFFF
 443
 444 #define Q81_NIC1_FUNC_ENABLE    0x00000001
 445 #define Q81_NIC1_FUNC_MASK      0x0000000e
 446 #define Q81_NIC1_FUNC_SHIFT     1
 447 #define Q81_NIC2_FUNC_ENABLE    0x00000010
 448 #define Q81_NIC2_FUNC_MASK      0x000000e0
 449 #define Q81_NIC2_FUNC_SHIFT     5
 450 #define Q81_FUNCTION_SHIFT      6
 451
 452 static uint32_t
 453 qls_get_other_fnum(qla_host_t *ha)
 454 {
 455         int             ret;
 456         uint32_t        o_func;
 457         uint32_t        test_logic;
 458         uint32_t        nic1_fnum = Q81_INVALID_NUM;
 459         uint32_t        nic2_fnum = Q81_INVALID_NUM;
 460
 461         ret = qls_rd_mpi_reg(ha, Q81_TEST_LOGIC_FUNC_PORT_CONFIG, &test_logic);
 462         if (ret)
 463                 return(Q81_INVALID_NUM);
 464
 465         if (test_logic & Q81_NIC1_FUNC_ENABLE)
 466                 nic1_fnum = (test_logic & Q81_NIC1_FUNC_MASK) >>
 467                                         Q81_NIC1_FUNC_SHIFT;
 468
 469         if (test_logic & Q81_NIC2_FUNC_ENABLE)
 470                 nic2_fnum = (test_logic & Q81_NIC2_FUNC_MASK) >>
 471                                         Q81_NIC2_FUNC_SHIFT;
 472
 473         if (ha->pci_func == 0)
 474                 o_func = nic2_fnum;
 475         else
 476                 o_func = nic1_fnum;
 477
 478         return(o_func);
 479 }
 480
 481 static uint32_t
 482 qls_rd_ofunc_reg(qla_host_t *ha, uint32_t reg)
 483 {
 484         uint32_t        ofunc;
 485         uint32_t        data;
 486         int             ret = 0;
 487
 488         ofunc = qls_get_other_fnum(ha);
 489
 490         if (ofunc == Q81_INVALID_NUM)
 491                 return(Q81_INVALID_NUM);
 492
 493         reg = Q81_CTL_PROC_ADDR_REG_BLOCK | (ofunc << Q81_FUNCTION_SHIFT) | reg;
 494
 495         ret = qls_rd_mpi_reg(ha, reg, &data);
 496
 497         if (ret != 0)
 498                 return(Q81_INVALID_NUM);
 499
 500         return(data);
 501 }
 502
 503 static void
 504 qls_wr_ofunc_reg(qla_host_t *ha, uint32_t reg, uint32_t value)
 505 {
 506         uint32_t ofunc;
 507         int ret = 0;
 508
 509         ofunc = qls_get_other_fnum(ha);
 510
 511         if (ofunc == Q81_INVALID_NUM)
 512                 return;
 513
 514         reg = Q81_CTL_PROC_ADDR_REG_BLOCK | (ofunc << Q81_FUNCTION_SHIFT) | reg;
 515
 516         ret = qls_wr_mpi_reg(ha, reg, value);
 517
 518         return;
 519 }
 520
 521 static int
 522 qls_wait_ofunc_reg_rdy(qla_host_t *ha , uint32_t reg, uint32_t bit,
 523         uint32_t err_bit)
 524 {
 525         uint32_t data;
 526         int count = 10;
 527
 528         while (count) {
 529
 530                 data = qls_rd_ofunc_reg(ha, reg);
 531
 532                 if (data & err_bit)
 533                         return (-1);
 534                 else if (data & bit)
 535                         return (0);
 536
 537                 qls_mdelay(__func__, 10);
 538                 count--;
 539         }
 540         return (-1);
 541 }
 542
 543 #define Q81_XG_SERDES_ADDR_RDY  BIT_31
 544 #define Q81_XG_SERDES_ADDR_READ BIT_30
 545
 546 static int
 547 qls_rd_ofunc_serdes_reg(qla_host_t *ha, uint32_t reg, uint32_t *data)
 548 {
 549         int ret;
 550
 551         /* wait for reg to come ready */
 552         ret = qls_wait_ofunc_reg_rdy(ha, (Q81_CTL_XG_SERDES_ADDR >> 2),
 553                         Q81_XG_SERDES_ADDR_RDY, 0);
 554         if (ret)
 555                 goto exit_qls_rd_ofunc_serdes_reg;
 556
 557         /* set up for reg read */
 558         qls_wr_ofunc_reg(ha, (Q81_CTL_XG_SERDES_ADDR >> 2),
 559                 (reg | Q81_XG_SERDES_ADDR_READ));
 560
 561         /* wait for reg to come ready */
 562         ret = qls_wait_ofunc_reg_rdy(ha, (Q81_CTL_XG_SERDES_ADDR >> 2),
 563                         Q81_XG_SERDES_ADDR_RDY, 0);
 564         if (ret)
 565                 goto exit_qls_rd_ofunc_serdes_reg;
 566
 567         /* get the data */
 568         *data = qls_rd_ofunc_reg(ha, (Q81_CTL_XG_SERDES_DATA >> 2));
 569
 570 exit_qls_rd_ofunc_serdes_reg:
 571         return ret;
 572 }
 573
 574 #define Q81_XGMAC_ADDR_RDY      BIT_31
 575 #define Q81_XGMAC_ADDR_R        BIT_30
 576 #define Q81_XGMAC_ADDR_XME      BIT_29
 577
 578 static int
 579 qls_rd_ofunc_xgmac_reg(qla_host_t *ha, uint32_t reg, uint32_t *data)
 580 {
 581         int ret = 0;
 582
 583         ret = qls_wait_ofunc_reg_rdy(ha, (Q81_CTL_XGMAC_ADDR >> 2),
 584                         Q81_XGMAC_ADDR_RDY, Q81_XGMAC_ADDR_XME);
 585
 586         if (ret)
 587                 goto exit_qls_rd_ofunc_xgmac_reg;
 588
 589         qls_wr_ofunc_reg(ha, (Q81_XGMAC_ADDR_RDY >> 2),
 590                 (reg | Q81_XGMAC_ADDR_R));
 591
 592         ret = qls_wait_ofunc_reg_rdy(ha, (Q81_CTL_XGMAC_ADDR >> 2),
 593                         Q81_XGMAC_ADDR_RDY, Q81_XGMAC_ADDR_XME);
 594         if (ret)
 595                 goto exit_qls_rd_ofunc_xgmac_reg;
 596
 597         *data = qls_rd_ofunc_reg(ha, Q81_CTL_XGMAC_DATA);
 598
 599 exit_qls_rd_ofunc_xgmac_reg:
 600         return ret;
 601 }
 602
 603 static int
 604 qls_rd_serdes_reg(qla_host_t *ha, uint32_t reg, uint32_t *data)
 605 {
 606         int ret;
 607
 608         ret = qls_wait_reg_rdy(ha, Q81_CTL_XG_SERDES_ADDR,
 609                         Q81_XG_SERDES_ADDR_RDY, 0);
 610
 611         if (ret)
 612                 goto exit_qls_rd_serdes_reg;
 613
 614         WRITE_REG32(ha, Q81_CTL_XG_SERDES_ADDR, \
 615                 (reg | Q81_XG_SERDES_ADDR_READ));
 616
 617         ret = qls_wait_reg_rdy(ha, Q81_CTL_XG_SERDES_ADDR,
 618                         Q81_XG_SERDES_ADDR_RDY, 0);
 619
 620         if (ret)
 621                 goto exit_qls_rd_serdes_reg;
 622
 623         *data = READ_REG32(ha, Q81_CTL_XG_SERDES_DATA);
 624
 625 exit_qls_rd_serdes_reg:
 626
 627         return ret;
 628 }
 629
 630 static void
 631 qls_get_both_serdes(qla_host_t *ha, uint32_t addr, uint32_t *dptr,
 632         uint32_t *ind_ptr, uint32_t dvalid, uint32_t ind_valid)
 633 {
 634         int ret = -1;
 635
 636         if (dvalid)
 637                 ret = qls_rd_serdes_reg(ha, addr, dptr);
 638
 639         if (ret)
 640                 *dptr = Q81_BAD_DATA;
 641
 642         ret = -1;
 643
 644         if(ind_valid)
 645                 ret = qls_rd_ofunc_serdes_reg(ha, addr, ind_ptr);
 646
 647         if (ret)
 648                 *ind_ptr = Q81_BAD_DATA;
 649 }
 650
 651 #define Q81_XFI1_POWERED_UP 0x00000005
 652 #define Q81_XFI2_POWERED_UP 0x0000000A
 653 #define Q81_XAUI_POWERED_UP 0x00000001
 654
 655 static int
 656 qls_rd_serdes_regs(qla_host_t *ha, qls_mpi_coredump_t *mpi_dump)
 657 {
 658         int ret;
 659         uint32_t xfi_d_valid, xfi_ind_valid, xaui_d_valid, xaui_ind_valid;
 660         uint32_t temp, xaui_reg, i;
 661         uint32_t *dptr, *indptr;
 662
 663         xfi_d_valid = xfi_ind_valid = xaui_d_valid = xaui_ind_valid = 0;
 664
 665         xaui_reg = 0x800;
 666
 667         ret = qls_rd_ofunc_serdes_reg(ha, xaui_reg, &temp);
 668         if (ret)
 669                 temp = 0;
 670
 671         if ((temp & Q81_XAUI_POWERED_UP) == Q81_XAUI_POWERED_UP)
 672                 xaui_ind_valid = 1;
 673
 674         ret = qls_rd_serdes_reg(ha, xaui_reg, &temp);
 675         if (ret)
 676                 temp = 0;
 677
 678         if ((temp & Q81_XAUI_POWERED_UP) == Q81_XAUI_POWERED_UP)
 679                 xaui_d_valid = 1;
 680
 681         ret = qls_rd_serdes_reg(ha, 0x1E06, &temp);
 682         if (ret)
 683                 temp = 0;
 684
 685         if ((temp & Q81_XFI1_POWERED_UP) == Q81_XFI1_POWERED_UP) {
 686
 687                 if (ha->pci_func & 1)
 688                         xfi_ind_valid = 1; /* NIC 2, so the indirect
 689                                                  (NIC1) xfi is up*/
 690                 else
 691                         xfi_d_valid = 1;
 692         }
 693
 694         if((temp & Q81_XFI2_POWERED_UP) == Q81_XFI2_POWERED_UP) {
 695
 696                 if(ha->pci_func & 1)
 697                         xfi_d_valid = 1; /* NIC 2, so the indirect (NIC1)
 698                                                 xfi is up */
 699                 else
 700                         xfi_ind_valid = 1;
 701         }
 702
 703         if (ha->pci_func & 1) {
 704                 dptr = (uint32_t *)(&mpi_dump->serdes2_xaui_an);
 705                 indptr = (uint32_t *)(&mpi_dump->serdes1_xaui_an);
 706         } else {
 707                 dptr = (uint32_t *)(&mpi_dump->serdes1_xaui_an);
 708                 indptr = (uint32_t *)(&mpi_dump->serdes2_xaui_an);
 709         }
 710
 711         for (i = 0; i <= 0x000000034; i += 4, dptr ++, indptr ++) {
 712                 qls_get_both_serdes(ha, i, dptr, indptr,
 713                         xaui_d_valid, xaui_ind_valid);
 714         }
 715
 716         if (ha->pci_func & 1) {
 717                 dptr = (uint32_t *)(&mpi_dump->serdes2_xaui_hss_pcs);
 718                 indptr = (uint32_t *)(&mpi_dump->serdes1_xaui_hss_pcs);
 719         } else {
 720                 dptr = (uint32_t *)(&mpi_dump->serdes1_xaui_hss_pcs);
 721                 indptr = (uint32_t *)(&mpi_dump->serdes2_xaui_hss_pcs);
 722         }
 723
 724         for (i = 0x800; i <= 0x880; i += 4, dptr ++, indptr ++) {
 725                 qls_get_both_serdes(ha, i, dptr, indptr,
 726                         xaui_d_valid, xaui_ind_valid);
 727         }
 728
 729         if (ha->pci_func & 1) {
 730                 dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_an);
 731                 indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_an);
 732         } else {
 733                 dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_an);
 734                 indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_an);
 735         }
 736
 737         for (i = 0x1000; i <= 0x1034; i += 4, dptr ++, indptr ++) {
 738                 qls_get_both_serdes(ha, i, dptr, indptr,
 739                         xfi_d_valid, xfi_ind_valid);
 740         }
 741
 742         if (ha->pci_func & 1) {
 743                 dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_train);
 744                 indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_train);
 745         } else {
 746                 dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_train);
 747                 indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_train);
 748         }
 749
 750         for (i = 0x1050; i <= 0x107c; i += 4, dptr ++, indptr ++) {
 751                 qls_get_both_serdes(ha, i, dptr, indptr,
 752                         xfi_d_valid, xfi_ind_valid);
 753         }
 754
 755         if (ha->pci_func & 1) {
 756                 dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_pcs);
 757                 indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_pcs);
 758         } else {
 759                 dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_pcs);
 760                 indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_pcs);
 761         }
 762
 763         for (i = 0x1800; i <= 0x1838; i += 4, dptr++, indptr ++) {
 764                 qls_get_both_serdes(ha, i, dptr, indptr,
 765                         xfi_d_valid, xfi_ind_valid);
 766         }
 767
 768         if (ha->pci_func & 1) {
 769                 dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_tx);
 770                 indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_tx);
 771         } else {
 772                 dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_tx);
 773                 indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_tx);
 774         }
 775
 776         for (i = 0x1c00; i <= 0x1c1f; i++, dptr ++, indptr ++) {
 777                 qls_get_both_serdes(ha, i, dptr, indptr,
 778                         xfi_d_valid, xfi_ind_valid);
 779         }
 780
 781         if (ha->pci_func & 1) {
 782                 dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_rx);
 783                 indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_rx);
 784         } else {
 785                 dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_rx);
 786                 indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_rx);
 787         }
 788
 789         for (i = 0x1c40; i <= 0x1c5f; i++, dptr ++, indptr ++) {
 790                 qls_get_both_serdes(ha, i, dptr, indptr,
 791                         xfi_d_valid, xfi_ind_valid);
 792         }
 793
 794         if (ha->pci_func & 1) {
 795                 dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_pll);
 796                 indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_pll);
 797         } else {
 798                 dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_pll);
 799                 indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_pll);
 800         }
 801
 802         for (i = 0x1e00; i <= 0x1e1f; i++, dptr ++, indptr ++) {
 803                 qls_get_both_serdes(ha, i, dptr, indptr,
 804                         xfi_d_valid, xfi_ind_valid);
 805         }
 806
 807         return(0);
 808 }
 809
 810 static int
 811 qls_unpause_mpi_risc(qla_host_t *ha)
 812 {
 813         uint32_t data;
 814
 815         data = READ_REG32(ha, Q81_CTL_HOST_CMD_STATUS);
 816
 817         if (!(data & Q81_CTL_HCS_RISC_PAUSED))
 818                 return -1;
 819
 820         WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS, \
 821                 Q81_CTL_HCS_CMD_CLR_RISC_PAUSE);
 822
 823         return 0;
 824 }
 825
 826 static int
 827 qls_pause_mpi_risc(qla_host_t *ha)
 828 {
 829         uint32_t data;
 830         int count = 10;
 831
 832         WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS, \
 833                 Q81_CTL_HCS_CMD_SET_RISC_PAUSE);
 834
 835         do {
 836                 data = READ_REG32(ha, Q81_CTL_HOST_CMD_STATUS);
 837
 838                 if (data & Q81_CTL_HCS_RISC_PAUSED)
 839                         break;
 840
 841                 qls_mdelay(__func__, 10);
 842
 843                 count--;
 844
 845         } while (count);
 846
 847         return ((count == 0) ? -1 : 0);
 848 }
 849
 850 static void
 851 qls_get_intr_states(qla_host_t *ha, uint32_t *buf)
 852 {
 853         int i;
 854
 855         for (i = 0; i < MAX_RX_RINGS; i++, buf++) {
 856
 857                 WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, (0x037f0300 + i));
 858
 859                 *buf = READ_REG32(ha, Q81_CTL_INTR_ENABLE);
 860         }
 861 }
 862
 863 static int
 864 qls_rd_xgmac_reg(qla_host_t *ha, uint32_t reg, uint32_t*data)
 865 {
 866         int ret = 0;
 867
 868         ret = qls_wait_reg_rdy(ha, Q81_CTL_XGMAC_ADDR, Q81_XGMAC_ADDR_RDY,
 869                         Q81_XGMAC_ADDR_XME);
 870         if (ret)
 871                 goto exit_qls_rd_xgmac_reg;
 872
 873         WRITE_REG32(ha, Q81_CTL_XGMAC_ADDR, (reg | Q81_XGMAC_ADDR_R));
 874
 875         ret = qls_wait_reg_rdy(ha, Q81_CTL_XGMAC_ADDR, Q81_XGMAC_ADDR_RDY,
 876                         Q81_XGMAC_ADDR_XME);
 877         if (ret)
 878                 goto exit_qls_rd_xgmac_reg;
 879
 880         *data = READ_REG32(ha, Q81_CTL_XGMAC_DATA);
 881
 882 exit_qls_rd_xgmac_reg:
 883         return ret;
 884 }
 885
 886 static int
 887 qls_rd_xgmac_regs(qla_host_t *ha, uint32_t *buf, uint32_t o_func)
 888 {
 889         int ret = 0;
 890         int i;
 891
 892         for (i = 0; i < Q81_XGMAC_REGISTER_END; i += 4, buf ++) {
 893
 894                 switch (i) {
 895                 case  Q81_PAUSE_SRC_LO               :
 896                 case  Q81_PAUSE_SRC_HI               :
 897                 case  Q81_GLOBAL_CFG                 :
 898                 case  Q81_TX_CFG                     :
 899                 case  Q81_RX_CFG                     :
 900                 case  Q81_FLOW_CTL                   :
 901                 case  Q81_PAUSE_OPCODE               :
 902                 case  Q81_PAUSE_TIMER                :
 903                 case  Q81_PAUSE_FRM_DEST_LO          :
 904                 case  Q81_PAUSE_FRM_DEST_HI          :
 905                 case  Q81_MAC_TX_PARAMS              :
 906                 case  Q81_MAC_RX_PARAMS              :
 907                 case  Q81_MAC_SYS_INT                :
 908                 case  Q81_MAC_SYS_INT_MASK           :
 909                 case  Q81_MAC_MGMT_INT               :
 910                 case  Q81_MAC_MGMT_IN_MASK           :
 911                 case  Q81_EXT_ARB_MODE               :
 912                 case  Q81_TX_PKTS                    :
 913                 case  Q81_TX_PKTS_LO                 :
 914                 case  Q81_TX_BYTES                   :
 915                 case  Q81_TX_BYTES_LO                :
 916                 case  Q81_TX_MCAST_PKTS              :
 917                 case  Q81_TX_MCAST_PKTS_LO           :
 918                 case  Q81_TX_BCAST_PKTS              :
 919                 case  Q81_TX_BCAST_PKTS_LO           :
 920                 case  Q81_TX_UCAST_PKTS              :
 921                 case  Q81_TX_UCAST_PKTS_LO           :
 922                 case  Q81_TX_CTL_PKTS                :
 923                 case  Q81_TX_CTL_PKTS_LO             :
 924                 case  Q81_TX_PAUSE_PKTS              :
 925                 case  Q81_TX_PAUSE_PKTS_LO           :
 926                 case  Q81_TX_64_PKT                  :
 927                 case  Q81_TX_64_PKT_LO               :
 928                 case  Q81_TX_65_TO_127_PKT           :
 929                 case  Q81_TX_65_TO_127_PKT_LO        :
 930                 case  Q81_TX_128_TO_255_PKT          :
 931                 case  Q81_TX_128_TO_255_PKT_LO       :
 932                 case  Q81_TX_256_511_PKT             :
 933                 case  Q81_TX_256_511_PKT_LO          :
 934                 case  Q81_TX_512_TO_1023_PKT         :
 935                 case  Q81_TX_512_TO_1023_PKT_LO      :
 936                 case  Q81_TX_1024_TO_1518_PKT        :
 937                 case  Q81_TX_1024_TO_1518_PKT_LO     :
 938                 case  Q81_TX_1519_TO_MAX_PKT         :
 939                 case  Q81_TX_1519_TO_MAX_PKT_LO      :
 940                 case  Q81_TX_UNDERSIZE_PKT           :
 941                 case  Q81_TX_UNDERSIZE_PKT_LO        :
 942                 case  Q81_TX_OVERSIZE_PKT            :
 943                 case  Q81_TX_OVERSIZE_PKT_LO         :
 944                 case  Q81_RX_HALF_FULL_DET           :
 945                 case  Q81_TX_HALF_FULL_DET_LO        :
 946                 case  Q81_RX_OVERFLOW_DET            :
 947                 case  Q81_TX_OVERFLOW_DET_LO         :
 948                 case  Q81_RX_HALF_FULL_MASK          :
 949                 case  Q81_TX_HALF_FULL_MASK_LO       :
 950                 case  Q81_RX_OVERFLOW_MASK           :
 951                 case  Q81_TX_OVERFLOW_MASK_LO        :
 952                 case  Q81_STAT_CNT_CTL               :
 953                 case  Q81_AUX_RX_HALF_FULL_DET       :
 954                 case  Q81_AUX_TX_HALF_FULL_DET       :
 955                 case  Q81_AUX_RX_OVERFLOW_DET        :
 956                 case  Q81_AUX_TX_OVERFLOW_DET        :
 957                 case  Q81_AUX_RX_HALF_FULL_MASK      :
 958                 case  Q81_AUX_TX_HALF_FULL_MASK      :
 959                 case  Q81_AUX_RX_OVERFLOW_MASK       :
 960                 case  Q81_AUX_TX_OVERFLOW_MASK       :
 961                 case  Q81_RX_BYTES                   :
 962                 case  Q81_RX_BYTES_LO                :
 963                 case  Q81_RX_BYTES_OK                :
 964                 case  Q81_RX_BYTES_OK_LO             :
 965                 case  Q81_RX_PKTS                    :
 966                 case  Q81_RX_PKTS_LO                 :
 967                 case  Q81_RX_PKTS_OK                 :
 968                 case  Q81_RX_PKTS_OK_LO              :
 969                 case  Q81_RX_BCAST_PKTS              :
 970                 case  Q81_RX_BCAST_PKTS_LO           :
 971                 case  Q81_RX_MCAST_PKTS              :
 972                 case  Q81_RX_MCAST_PKTS_LO           :
 973                 case  Q81_RX_UCAST_PKTS              :
 974                 case  Q81_RX_UCAST_PKTS_LO           :
 975                 case  Q81_RX_UNDERSIZE_PKTS          :
 976                 case  Q81_RX_UNDERSIZE_PKTS_LO       :
 977                 case  Q81_RX_OVERSIZE_PKTS           :
 978                 case  Q81_RX_OVERSIZE_PKTS_LO        :
 979                 case  Q81_RX_JABBER_PKTS             :
 980                 case  Q81_RX_JABBER_PKTS_LO          :
 981                 case  Q81_RX_UNDERSIZE_FCERR_PKTS    :
 982                 case  Q81_RX_UNDERSIZE_FCERR_PKTS_LO :
 983                 case  Q81_RX_DROP_EVENTS             :
 984                 case  Q81_RX_DROP_EVENTS_LO          :
 985                 case  Q81_RX_FCERR_PKTS              :
 986                 case  Q81_RX_FCERR_PKTS_LO           :
 987                 case  Q81_RX_ALIGN_ERR               :
 988                 case  Q81_RX_ALIGN_ERR_LO            :
 989                 case  Q81_RX_SYMBOL_ERR              :
 990                 case  Q81_RX_SYMBOL_ERR_LO           :
 991                 case  Q81_RX_MAC_ERR                 :
 992                 case  Q81_RX_MAC_ERR_LO              :
 993                 case  Q81_RX_CTL_PKTS                :
 994                 case  Q81_RX_CTL_PKTS_LO             :
 995                 case  Q81_RX_PAUSE_PKTS              :
 996                 case  Q81_RX_PAUSE_PKTS_LO           :
 997                 case  Q81_RX_64_PKTS                 :
 998                 case  Q81_RX_64_PKTS_LO              :
 999                 case  Q81_RX_65_TO_127_PKTS          :
1000                 case  Q81_RX_65_TO_127_PKTS_LO       :
1001                 case  Q81_RX_128_255_PKTS            :
1002                 case  Q81_RX_128_255_PKTS_LO         :
1003                 case  Q81_RX_256_511_PKTS            :
1004                 case  Q81_RX_256_511_PKTS_LO         :
1005                 case  Q81_RX_512_TO_1023_PKTS        :
1006                 case  Q81_RX_512_TO_1023_PKTS_LO     :
1007                 case  Q81_RX_1024_TO_1518_PKTS       :
1008                 case  Q81_RX_1024_TO_1518_PKTS_LO    :
1009                 case  Q81_RX_1519_TO_MAX_PKTS        :
1010                 case  Q81_RX_1519_TO_MAX_PKTS_LO     :
1011                 case  Q81_RX_LEN_ERR_PKTS            :
1012                 case  Q81_RX_LEN_ERR_PKTS_LO         :
1013                 case  Q81_MDIO_TX_DATA               :
1014                 case  Q81_MDIO_RX_DATA               :
1015                 case  Q81_MDIO_CMD                   :
1016                 case  Q81_MDIO_PHY_ADDR              :
1017                 case  Q81_MDIO_PORT                  :
1018                 case  Q81_MDIO_STATUS                :
1019                 case  Q81_TX_CBFC_PAUSE_FRAMES0      :
1020                 case  Q81_TX_CBFC_PAUSE_FRAMES0_LO   :
1021                 case  Q81_TX_CBFC_PAUSE_FRAMES1      :
1022                 case  Q81_TX_CBFC_PAUSE_FRAMES1_LO   :
1023                 case  Q81_TX_CBFC_PAUSE_FRAMES2      :
1024                 case  Q81_TX_CBFC_PAUSE_FRAMES2_LO   :
1025                 case  Q81_TX_CBFC_PAUSE_FRAMES3      :
1026                 case  Q81_TX_CBFC_PAUSE_FRAMES3_LO   :
1027                 case  Q81_TX_CBFC_PAUSE_FRAMES4      :
1028                 case  Q81_TX_CBFC_PAUSE_FRAMES4_LO   :
1029                 case  Q81_TX_CBFC_PAUSE_FRAMES5      :
1030                 case  Q81_TX_CBFC_PAUSE_FRAMES5_LO   :
1031                 case  Q81_TX_CBFC_PAUSE_FRAMES6      :
1032                 case  Q81_TX_CBFC_PAUSE_FRAMES6_LO   :
1033                 case  Q81_TX_CBFC_PAUSE_FRAMES7      :
1034                 case  Q81_TX_CBFC_PAUSE_FRAMES7_LO   :
1035                 case  Q81_TX_FCOE_PKTS               :
1036                 case  Q81_TX_FCOE_PKTS_LO            :
1037                 case  Q81_TX_MGMT_PKTS               :
1038                 case  Q81_TX_MGMT_PKTS_LO            :
1039                 case  Q81_RX_CBFC_PAUSE_FRAMES0      :
1040                 case  Q81_RX_CBFC_PAUSE_FRAMES0_LO   :
1041                 case  Q81_RX_CBFC_PAUSE_FRAMES1      :
1042                 case  Q81_RX_CBFC_PAUSE_FRAMES1_LO   :
1043                 case  Q81_RX_CBFC_PAUSE_FRAMES2      :
1044                 case  Q81_RX_CBFC_PAUSE_FRAMES2_LO   :
1045                 case  Q81_RX_CBFC_PAUSE_FRAMES3      :
1046                 case  Q81_RX_CBFC_PAUSE_FRAMES3_LO   :
1047                 case  Q81_RX_CBFC_PAUSE_FRAMES4      :
1048                 case  Q81_RX_CBFC_PAUSE_FRAMES4_LO   :
1049                 case  Q81_RX_CBFC_PAUSE_FRAMES5      :
1050                 case  Q81_RX_CBFC_PAUSE_FRAMES5_LO   :
1051                 case  Q81_RX_CBFC_PAUSE_FRAMES6      :
1052                 case  Q81_RX_CBFC_PAUSE_FRAMES6_LO   :
1053                 case  Q81_RX_CBFC_PAUSE_FRAMES7      :
1054                 case  Q81_RX_CBFC_PAUSE_FRAMES7_LO   :
1055                 case  Q81_RX_FCOE_PKTS               :
1056                 case  Q81_RX_FCOE_PKTS_LO            :
1057                 case  Q81_RX_MGMT_PKTS               :
1058                 case  Q81_RX_MGMT_PKTS_LO            :
1059                 case  Q81_RX_NIC_FIFO_DROP           :
1060                 case  Q81_RX_NIC_FIFO_DROP_LO        :
1061                 case  Q81_RX_FCOE_FIFO_DROP          :
1062                 case  Q81_RX_FCOE_FIFO_DROP_LO       :
1063                 case  Q81_RX_MGMT_FIFO_DROP          :
1064                 case  Q81_RX_MGMT_FIFO_DROP_LO       :
1065                 case  Q81_RX_PKTS_PRIORITY0          :
1066                 case  Q81_RX_PKTS_PRIORITY0_LO       :
1067                 case  Q81_RX_PKTS_PRIORITY1          :
1068                 case  Q81_RX_PKTS_PRIORITY1_LO       :
1069                 case  Q81_RX_PKTS_PRIORITY2          :
1070                 case  Q81_RX_PKTS_PRIORITY2_LO       :
1071                 case  Q81_RX_PKTS_PRIORITY3          :
1072                 case  Q81_RX_PKTS_PRIORITY3_LO       :
1073                 case  Q81_RX_PKTS_PRIORITY4          :
1074                 case  Q81_RX_PKTS_PRIORITY4_LO       :
1075                 case  Q81_RX_PKTS_PRIORITY5          :
1076                 case  Q81_RX_PKTS_PRIORITY5_LO       :
1077                 case  Q81_RX_PKTS_PRIORITY6          :
1078                 case  Q81_RX_PKTS_PRIORITY6_LO       :
1079                 case  Q81_RX_PKTS_PRIORITY7          :
1080                 case  Q81_RX_PKTS_PRIORITY7_LO       :
1081                 case  Q81_RX_OCTETS_PRIORITY0        :
1082                 case  Q81_RX_OCTETS_PRIORITY0_LO     :
1083                 case  Q81_RX_OCTETS_PRIORITY1        :
1084                 case  Q81_RX_OCTETS_PRIORITY1_LO     :
1085                 case  Q81_RX_OCTETS_PRIORITY2        :
1086                 case  Q81_RX_OCTETS_PRIORITY2_LO     :
1087                 case  Q81_RX_OCTETS_PRIORITY3        :
1088                 case  Q81_RX_OCTETS_PRIORITY3_LO     :
1089                 case  Q81_RX_OCTETS_PRIORITY4        :
1090                 case  Q81_RX_OCTETS_PRIORITY4_LO     :
1091                 case  Q81_RX_OCTETS_PRIORITY5        :
1092                 case  Q81_RX_OCTETS_PRIORITY5_LO     :
1093                 case  Q81_RX_OCTETS_PRIORITY6        :
1094                 case  Q81_RX_OCTETS_PRIORITY6_LO     :
1095                 case  Q81_RX_OCTETS_PRIORITY7        :
1096                 case  Q81_RX_OCTETS_PRIORITY7_LO     :
1097                 case  Q81_TX_PKTS_PRIORITY0          :
1098                 case  Q81_TX_PKTS_PRIORITY0_LO       :
1099                 case  Q81_TX_PKTS_PRIORITY1          :
1100                 case  Q81_TX_PKTS_PRIORITY1_LO       :
1101                 case  Q81_TX_PKTS_PRIORITY2          :
1102                 case  Q81_TX_PKTS_PRIORITY2_LO       :
1103                 case  Q81_TX_PKTS_PRIORITY3          :
1104                 case  Q81_TX_PKTS_PRIORITY3_LO       :
1105                 case  Q81_TX_PKTS_PRIORITY4          :
1106                 case  Q81_TX_PKTS_PRIORITY4_LO       :
1107                 case  Q81_TX_PKTS_PRIORITY5          :
1108                 case  Q81_TX_PKTS_PRIORITY5_LO       :
1109                 case  Q81_TX_PKTS_PRIORITY6          :
1110                 case  Q81_TX_PKTS_PRIORITY6_LO       :
1111                 case  Q81_TX_PKTS_PRIORITY7          :
1112                 case  Q81_TX_PKTS_PRIORITY7_LO       :
1113                 case  Q81_TX_OCTETS_PRIORITY0        :
1114                 case  Q81_TX_OCTETS_PRIORITY0_LO     :
1115                 case  Q81_TX_OCTETS_PRIORITY1        :
1116                 case  Q81_TX_OCTETS_PRIORITY1_LO     :
1117                 case  Q81_TX_OCTETS_PRIORITY2        :
1118                 case  Q81_TX_OCTETS_PRIORITY2_LO     :
1119                 case  Q81_TX_OCTETS_PRIORITY3        :
1120                 case  Q81_TX_OCTETS_PRIORITY3_LO     :
1121                 case  Q81_TX_OCTETS_PRIORITY4        :
1122                 case  Q81_TX_OCTETS_PRIORITY4_LO     :
1123                 case  Q81_TX_OCTETS_PRIORITY5        :
1124                 case  Q81_TX_OCTETS_PRIORITY5_LO     :
1125                 case  Q81_TX_OCTETS_PRIORITY6        :
1126                 case  Q81_TX_OCTETS_PRIORITY6_LO     :
1127                 case  Q81_TX_OCTETS_PRIORITY7        :
1128                 case  Q81_TX_OCTETS_PRIORITY7_LO     :
1129                 case  Q81_RX_DISCARD_PRIORITY0       :
1130                 case  Q81_RX_DISCARD_PRIORITY0_LO    :
1131                 case  Q81_RX_DISCARD_PRIORITY1       :
1132                 case  Q81_RX_DISCARD_PRIORITY1_LO    :
1133                 case  Q81_RX_DISCARD_PRIORITY2       :
1134                 case  Q81_RX_DISCARD_PRIORITY2_LO    :
1135                 case  Q81_RX_DISCARD_PRIORITY3       :
1136                 case  Q81_RX_DISCARD_PRIORITY3_LO    :
1137                 case  Q81_RX_DISCARD_PRIORITY4       :
1138                 case  Q81_RX_DISCARD_PRIORITY4_LO    :
1139                 case  Q81_RX_DISCARD_PRIORITY5       :
1140                 case  Q81_RX_DISCARD_PRIORITY5_LO    :
1141                 case  Q81_RX_DISCARD_PRIORITY6       :
1142                 case  Q81_RX_DISCARD_PRIORITY6_LO    :
1143                 case  Q81_RX_DISCARD_PRIORITY7       :
1144                 case  Q81_RX_DISCARD_PRIORITY7_LO    :
1145
1146                         if (o_func)
1147                                 ret = qls_rd_ofunc_xgmac_reg(ha,
1148                                                 i, buf);
1149                         else
1150                                 ret = qls_rd_xgmac_reg(ha, i, buf);
1151
1152                         if (ret)
1153                                 *buf = Q81_BAD_DATA;
1154
1155                         break;
1156
1157                 default:
1158                         break;
1159
1160                 }
1161         }
1162         return 0;
1163 }
1164
1165 static int
1166 qls_get_mpi_regs(qla_host_t *ha, uint32_t *buf, uint32_t offset, uint32_t count)
1167 {
1168         int i, ret = 0;
1169
1170         for (i = 0; i < count; i++, buf++) {
1171
1172                 ret = qls_rd_mpi_reg(ha, (offset + i), buf);
1173
1174                 if (ret)
1175                         return ret;
1176         }
1177
1178         return (ret);
1179 }
1180
1181 static int
1182 qls_get_mpi_shadow_regs(qla_host_t *ha, uint32_t *buf)
1183 {
1184         uint32_t        i;
1185         int             ret;
1186
1187 #define Q81_RISC_124 0x0000007c
1188 #define Q81_RISC_127 0x0000007f
1189 #define Q81_SHADOW_OFFSET 0xb0000000
1190
1191         for (i = 0; i < Q81_MPI_CORE_SH_REGS_CNT; i++, buf++) {
1192
1193                 ret = qls_wr_mpi_reg(ha,
1194                                 (Q81_CTL_PROC_ADDR_RISC_INT_REG | Q81_RISC_124),
1195                                 (Q81_SHADOW_OFFSET | i << 20));
1196                 if (ret)
1197                         goto exit_qls_get_mpi_shadow_regs;
1198
1199                 ret = qls_mpi_risc_rd_reg(ha,
1200                                 (Q81_CTL_PROC_ADDR_RISC_INT_REG | Q81_RISC_127),
1201                                  buf);
1202                 if (ret)
1203                         goto exit_qls_get_mpi_shadow_regs;
1204         }
1205
1206 exit_qls_get_mpi_shadow_regs:
1207         return ret;
1208 }
1209
1210 #define SYS_CLOCK (0x00)
1211 #define PCI_CLOCK (0x80)
1212 #define FC_CLOCK  (0x140)
1213 #define XGM_CLOCK (0x180)
1214
1215 #define Q81_ADDRESS_REGISTER_ENABLE 0x00010000
1216 #define Q81_UP                      0x00008000
1217 #define Q81_MAX_MUX                 0x40
1218 #define Q81_MAX_MODULES             0x1F
1219
1220 static uint32_t *
1221 qls_get_probe(qla_host_t *ha, uint32_t clock, uint8_t *valid, uint32_t *buf)
1222 {
1223         uint32_t module, mux_sel, probe, lo_val, hi_val;
1224
1225         for (module = 0; module < Q81_MAX_MODULES; module ++) {
1226
1227                 if (valid[module]) {
1228
1229                         for (mux_sel = 0; mux_sel < Q81_MAX_MUX; mux_sel++) {
1230
1231                                 probe = clock | Q81_ADDRESS_REGISTER_ENABLE |
1232                                                 mux_sel | (module << 9);
1233                                 WRITE_REG32(ha, Q81_CTL_XG_PROBE_MUX_ADDR,\
1234                                         probe);
1235
1236                                 lo_val = READ_REG32(ha,\
1237                                                 Q81_CTL_XG_PROBE_MUX_DATA);
1238
1239                                 if (mux_sel == 0) {
1240                                         *buf = probe;
1241                                         buf ++;
1242                                 }
1243
1244                                 probe |= Q81_UP;
1245
1246                                 WRITE_REG32(ha, Q81_CTL_XG_PROBE_MUX_ADDR,\
1247                                         probe);
1248                                 hi_val = READ_REG32(ha,\
1249                                                 Q81_CTL_XG_PROBE_MUX_DATA);
1250
1251                                 *buf = lo_val;
1252                                 buf++;
1253                                 *buf = hi_val;
1254                                 buf++;
1255                         }
1256                 }
1257         }
1258
1259         return(buf);
1260 }
1261
1262 static int
1263 qls_get_probe_dump(qla_host_t *ha, uint32_t *buf)
1264 {
1265
1266         uint8_t sys_clock_valid_modules[0x20] = {
1267                 1,   // 0x00
1268                 1,   // 0x01
1269                 1,   // 0x02
1270                 0,   // 0x03
1271                 1,   // 0x04
1272                 1,   // 0x05
1273                 1,   // 0x06
1274                 1,   // 0x07
1275                 1,   // 0x08
1276                 1,   // 0x09
1277                 1,   // 0x0A
1278                 1,   // 0x0B
1279                 1,   // 0x0C
1280                 1,   // 0x0D
1281                 1,   // 0x0E
1282                 0,   // 0x0F
1283                 1,   // 0x10
1284                 1,   // 0x11
1285                 1,   // 0x12
1286                 1,   // 0x13
1287                 0,   // 0x14
1288                 0,   // 0x15
1289                 0,   // 0x16
1290                 0,   // 0x17
1291                 0,   // 0x18
1292                 0,   // 0x19
1293                 0,   // 0x1A
1294                 0,   // 0x1B
1295                 0,   // 0x1C
1296                 0,   // 0x1D
1297                 0,   // 0x1E
1298                 0    // 0x1F
1299         };
1300
1301
1302         uint8_t pci_clock_valid_modules[0x20] = {
1303                 1,   // 0x00
1304                 0,   // 0x01
1305                 0,   // 0x02
1306                 0,   // 0x03
1307                 0,   // 0x04
1308                 0,   // 0x05
1309                 1,   // 0x06
1310                 1,   // 0x07
1311                 0,   // 0x08
1312                 0,   // 0x09
1313                 0,   // 0x0A
1314                 0,   // 0x0B
1315                 0,   // 0x0C
1316                 0,   // 0x0D
1317                 1,   // 0x0E
1318                 0,   // 0x0F
1319                 0,   // 0x10
1320                 0,   // 0x11
1321                 0,   // 0x12
1322                 0,   // 0x13
1323                 0,   // 0x14
1324                 0,   // 0x15
1325                 0,   // 0x16
1326                 0,   // 0x17
1327                 0,   // 0x18
1328                 0,   // 0x19
1329                 0,   // 0x1A
1330                 0,   // 0x1B
1331                 0,   // 0x1C
1332                 0,   // 0x1D
1333                 0,   // 0x1E
1334                 0    // 0x1F
1335         };
1336
1337
1338         uint8_t xgm_clock_valid_modules[0x20] = {
1339                 1,   // 0x00
1340                 0,   // 0x01
1341                 0,   // 0x02
1342                 1,   // 0x03
1343                 0,   // 0x04
1344                 0,   // 0x05
1345                 0,   // 0x06
1346                 0,   // 0x07
1347                 1,   // 0x08
1348                 1,   // 0x09
1349                 0,   // 0x0A
1350                 0,   // 0x0B
1351                 1,   // 0x0C
1352                 1,   // 0x0D
1353                 1,   // 0x0E
1354                 0,   // 0x0F
1355                 1,   // 0x10
1356                 1,   // 0x11
1357                 0,   // 0x12
1358                 0,   // 0x13
1359                 0,   // 0x14
1360                 0,   // 0x15
1361                 0,   // 0x16
1362                 0,   // 0x17
1363                 0,   // 0x18
1364                 0,   // 0x19
1365                 0,   // 0x1A
1366                 0,   // 0x1B
1367                 0,   // 0x1C
1368                 0,   // 0x1D
1369                 0,   // 0x1E
1370                 0    // 0x1F
1371         };
1372
1373         uint8_t fc_clock_valid_modules[0x20] = {
1374                 1,   // 0x00
1375                 0,   // 0x01
1376                 0,   // 0x02
1377                 0,   // 0x03
1378                 0,   // 0x04
1379                 0,   // 0x05
1380                 0,   // 0x06
1381                 0,   // 0x07
1382                 0,   // 0x08
1383                 0,   // 0x09
1384                 0,   // 0x0A
1385                 0,   // 0x0B
1386                 1,   // 0x0C
1387                 1,   // 0x0D
1388                 0,   // 0x0E
1389                 0,   // 0x0F
1390                 0,   // 0x10
1391                 0,   // 0x11
1392                 0,   // 0x12
1393                 0,   // 0x13
1394                 0,   // 0x14
1395                 0,   // 0x15
1396                 0,   // 0x16
1397                 0,   // 0x17
1398                 0,   // 0x18
1399                 0,   // 0x19
1400                 0,   // 0x1A
1401                 0,   // 0x1B
1402                 0,   // 0x1C
1403                 0,   // 0x1D
1404                 0,   // 0x1E
1405                 0    // 0x1F
1406         };
1407
1408         qls_wr_mpi_reg(ha, 0x100e, 0x18a20000);
1409
1410         buf = qls_get_probe(ha, SYS_CLOCK, sys_clock_valid_modules, buf);
1411
1412         buf = qls_get_probe(ha, PCI_CLOCK, pci_clock_valid_modules, buf);
1413
1414         buf = qls_get_probe(ha, XGM_CLOCK, xgm_clock_valid_modules, buf);
1415
1416         buf = qls_get_probe(ha, FC_CLOCK, fc_clock_valid_modules, buf);
1417
1418         return(0);
1419 }
1420
1421 static void
1422 qls_get_ridx_registers(qla_host_t *ha, uint32_t *buf)
1423 {
1424         uint32_t type, idx, idx_max;
1425         uint32_t r_idx;
1426         uint32_t r_data;
1427         uint32_t val;
1428
1429         for (type = 0; type < 4; type ++) {
1430                 if (type < 2)
1431                         idx_max = 8;
1432                 else
1433                         idx_max = 16;
1434
1435                 for (idx = 0; idx < idx_max; idx ++) {
1436
1437                         val = 0x04000000 | (type << 16) | (idx << 8);
1438                         WRITE_REG32(ha, Q81_CTL_ROUTING_INDEX, val);
1439
1440                         r_idx = 0;
1441                         while ((r_idx & 0x40000000) == 0)
1442                                 r_idx = READ_REG32(ha, Q81_CTL_ROUTING_INDEX);
1443
1444                         r_data = READ_REG32(ha, Q81_CTL_ROUTING_DATA);
1445
1446                         *buf = type;
1447                         buf ++;
1448                         *buf = idx;
1449                         buf ++;
1450                         *buf = r_idx;
1451                         buf ++;
1452                         *buf = r_data;
1453                         buf ++;
1454                 }
1455         }
1456 }
1457
1458 static void
1459 qls_get_mac_proto_regs(qla_host_t *ha, uint32_t* buf)
1460 {
1461
1462 #define Q81_RS_AND_ADR 0x06000000
1463 #define Q81_RS_ONLY    0x04000000
1464 #define Q81_NUM_TYPES  10
1465
1466         uint32_t result_index, result_data;
1467         uint32_t type;
1468         uint32_t index;
1469         uint32_t offset;
1470         uint32_t val;
1471         uint32_t initial_val;
1472         uint32_t max_index;
1473         uint32_t max_offset;
1474
1475         for (type = 0; type < Q81_NUM_TYPES; type ++) {
1476                 switch (type) {
1477
1478                 case 0: // CAM
1479                         initial_val = Q81_RS_AND_ADR;
1480                         max_index = 512;
1481                         max_offset = 3;
1482                         break;
1483
1484                 case 1: // Multicast MAC Address
1485                         initial_val = Q81_RS_ONLY;
1486                         max_index = 32;
1487                         max_offset = 2;
1488                         break;
1489
1490                 case 2: // VLAN filter mask
1491                 case 3: // MC filter mask
1492                         initial_val = Q81_RS_ONLY;
1493                         max_index = 4096;
1494                         max_offset = 1;
1495                         break;
1496
1497                 case 4: // FC MAC addresses
1498                         initial_val = Q81_RS_ONLY;
1499                         max_index = 4;
1500                         max_offset = 2;
1501                         break;
1502
1503                 case 5: // Mgmt MAC addresses
1504                         initial_val = Q81_RS_ONLY;
1505                         max_index = 8;
1506                         max_offset = 2;
1507                         break;
1508
1509                 case 6: // Mgmt VLAN addresses
1510                         initial_val = Q81_RS_ONLY;
1511                         max_index = 16;
1512                         max_offset = 1;
1513                         break;
1514
1515                 case 7: // Mgmt IPv4 address
1516                         initial_val = Q81_RS_ONLY;
1517                         max_index = 4;
1518                         max_offset = 1;
1519                         break;
1520
1521                 case 8: // Mgmt IPv6 address
1522                         initial_val = Q81_RS_ONLY;
1523                         max_index = 4;
1524                         max_offset = 4;
1525                         break;
1526
1527                 case 9: // Mgmt TCP/UDP Dest port
1528                         initial_val = Q81_RS_ONLY;
1529                         max_index = 4;
1530                         max_offset = 1;
1531                         break;
1532
1533                 default:
1534                         printf("Bad type!!! 0x%08x\n", type);
1535                         max_index = 0;
1536                         max_offset = 0;
1537                         break;
1538                 }
1539
1540                 for (index = 0; index < max_index; index ++) {
1541
1542                         for (offset = 0; offset < max_offset; offset ++) {
1543
1544                                 val = initial_val | (type << 16) |
1545                                         (index << 4) | (offset);
1546
1547                                 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX,\
1548                                         val);
1549
1550                                 result_index = 0;
1551
1552                                 while ((result_index & 0x40000000) == 0)
1553                                         result_index =
1554                                                 READ_REG32(ha, \
1555                                                 Q81_CTL_MAC_PROTO_ADDR_INDEX);
1556
1557                                 result_data = READ_REG32(ha,\
1558                                                 Q81_CTL_MAC_PROTO_ADDR_DATA);
1559
1560                                 *buf = result_index;
1561                                 buf ++;
1562
1563                                 *buf = result_data;
1564                                 buf ++;
1565                         }
1566                 }
1567         }
1568 }
1569
1570 static int
1571 qls_get_ets_regs(qla_host_t *ha, uint32_t *buf)
1572 {
1573         int ret = 0;
1574         int i;
1575
1576         for(i = 0; i < 8; i ++, buf ++) {
1577                 WRITE_REG32(ha, Q81_CTL_NIC_ENH_TX_SCHD, \
1578                         ((i << 29) | 0x08000000));
1579                 *buf = READ_REG32(ha, Q81_CTL_NIC_ENH_TX_SCHD);
1580         }
1581
1582         for(i = 0; i < 2; i ++, buf ++) {
1583                 WRITE_REG32(ha, Q81_CTL_CNA_ENH_TX_SCHD, \
1584                         ((i << 29) | 0x08000000));
1585                 *buf = READ_REG32(ha, Q81_CTL_CNA_ENH_TX_SCHD);
1586         }
1587
1588         return ret;
1589 }
1590
1591 int
1592 qls_mpi_core_dump(qla_host_t *ha)
1593 {
1594         int ret;
1595         int i;
1596         uint32_t reg, reg_val;
1597
1598         qls_mpi_coredump_t *mpi_dump = &ql_mpi_coredump;
1599
1600         ret = qls_pause_mpi_risc(ha);
1601         if (ret) {
1602                 printf("Failed RISC pause. Status = 0x%.08x\n",ret);
1603                 return(-1);
1604         }
1605
1606         memset(&(mpi_dump->mpi_global_header), 0,
1607                         sizeof(qls_mpid_glbl_hdr_t));
1608
1609         mpi_dump->mpi_global_header.cookie = Q81_MPID_COOKIE;
1610         mpi_dump->mpi_global_header.hdr_size =
1611                 sizeof(qls_mpid_glbl_hdr_t);
1612         mpi_dump->mpi_global_header.img_size =
1613                 sizeof(qls_mpi_coredump_t);
1614
1615         memcpy(mpi_dump->mpi_global_header.id, "MPI Coredump",
1616                 sizeof(mpi_dump->mpi_global_header.id));
1617
1618         qls_mpid_seg_hdr(&mpi_dump->nic1_regs_seg_hdr,
1619                 Q81_NIC1_CONTROL_SEG_NUM,
1620                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->nic1_regs)),
1621                 "NIC1 Registers");
1622
1623         qls_mpid_seg_hdr(&mpi_dump->nic2_regs_seg_hdr,
1624                 Q81_NIC2_CONTROL_SEG_NUM,
1625                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->nic2_regs)),
1626                 "NIC2 Registers");
1627
1628         qls_mpid_seg_hdr(&mpi_dump->xgmac1_seg_hdr,
1629                 Q81_NIC1_XGMAC_SEG_NUM,
1630                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->xgmac1)),
1631                 "NIC1 XGMac Registers");
1632
1633         qls_mpid_seg_hdr(&mpi_dump->xgmac2_seg_hdr,
1634                 Q81_NIC2_XGMAC_SEG_NUM,
1635                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->xgmac2)),
1636                 "NIC2 XGMac Registers");
1637
1638         if (ha->pci_func & 1) {
1639                 for (i = 0; i < 64; i++)
1640                         mpi_dump->nic2_regs[i] =
1641                                 READ_REG32(ha, i * sizeof(uint32_t));
1642
1643                 for (i = 0; i < 64; i++)
1644                         mpi_dump->nic1_regs[i] =
1645                                 qls_rd_ofunc_reg(ha,
1646                                         (i * sizeof(uint32_t)) / 4);
1647
1648                 qls_rd_xgmac_regs(ha, &mpi_dump->xgmac2[0], 0);
1649                 qls_rd_xgmac_regs(ha, &mpi_dump->xgmac1[0], 1);
1650         } else {
1651                 for (i = 0; i < 64; i++)
1652                         mpi_dump->nic1_regs[i] =
1653                                 READ_REG32(ha, i * sizeof(uint32_t));
1654
1655                 for (i = 0; i < 64; i++)
1656                         mpi_dump->nic2_regs[i] =
1657                                 qls_rd_ofunc_reg(ha,
1658                                         (i * sizeof(uint32_t)) / 4);
1659
1660                 qls_rd_xgmac_regs(ha, &mpi_dump->xgmac1[0], 0);
1661                 qls_rd_xgmac_regs(ha, &mpi_dump->xgmac2[0], 1);
1662         }
1663
1664
1665         qls_mpid_seg_hdr(&mpi_dump->xaui1_an_hdr,
1666                 Q81_XAUI1_AN_SEG_NUM,
1667                 (sizeof(qls_mpid_seg_hdr_t) +
1668                         sizeof(mpi_dump->serdes1_xaui_an)),
1669                 "XAUI1 AN Registers");
1670
1671         qls_mpid_seg_hdr(&mpi_dump->xaui1_hss_pcs_hdr,
1672                 Q81_XAUI1_HSS_PCS_SEG_NUM,
1673                 (sizeof(qls_mpid_seg_hdr_t) +
1674                         sizeof(mpi_dump->serdes1_xaui_hss_pcs)),
1675                 "XAUI1 HSS PCS Registers");
1676
1677         qls_mpid_seg_hdr(&mpi_dump->xfi1_an_hdr,
1678                 Q81_XFI1_AN_SEG_NUM,
1679                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->serdes1_xfi_an)),
1680                 "XFI1 AN Registers");
1681
1682         qls_mpid_seg_hdr(&mpi_dump->xfi1_train_hdr,
1683                 Q81_XFI1_TRAIN_SEG_NUM,
1684                 (sizeof(qls_mpid_seg_hdr_t) +
1685                         sizeof(mpi_dump->serdes1_xfi_train)),
1686                 "XFI1 TRAIN Registers");
1687
1688         qls_mpid_seg_hdr(&mpi_dump->xfi1_hss_pcs_hdr,
1689                 Q81_XFI1_HSS_PCS_SEG_NUM,
1690                 (sizeof(qls_mpid_seg_hdr_t) +
1691                         sizeof(mpi_dump->serdes1_xfi_hss_pcs)),
1692                 "XFI1 HSS PCS Registers");
1693
1694         qls_mpid_seg_hdr(&mpi_dump->xfi1_hss_tx_hdr,
1695                 Q81_XFI1_HSS_TX_SEG_NUM,
1696                 (sizeof(qls_mpid_seg_hdr_t) +
1697                         sizeof(mpi_dump->serdes1_xfi_hss_tx)),
1698                 "XFI1 HSS TX Registers");
1699
1700         qls_mpid_seg_hdr(&mpi_dump->xfi1_hss_rx_hdr,
1701                 Q81_XFI1_HSS_RX_SEG_NUM,
1702                 (sizeof(qls_mpid_seg_hdr_t) +
1703                         sizeof(mpi_dump->serdes1_xfi_hss_rx)),
1704                 "XFI1 HSS RX Registers");
1705
1706         qls_mpid_seg_hdr(&mpi_dump->xfi1_hss_pll_hdr,
1707                 Q81_XFI1_HSS_PLL_SEG_NUM,
1708                 (sizeof(qls_mpid_seg_hdr_t) +
1709                         sizeof(mpi_dump->serdes1_xfi_hss_pll)),
1710                 "XFI1 HSS PLL Registers");
1711
1712         qls_mpid_seg_hdr(&mpi_dump->xaui2_an_hdr,
1713                 Q81_XAUI2_AN_SEG_NUM,
1714                 (sizeof(qls_mpid_seg_hdr_t) +
1715                         sizeof(mpi_dump->serdes2_xaui_an)),
1716                 "XAUI2 AN Registers");
1717
1718         qls_mpid_seg_hdr(&mpi_dump->xaui2_hss_pcs_hdr,
1719                 Q81_XAUI2_HSS_PCS_SEG_NUM,
1720                 (sizeof(qls_mpid_seg_hdr_t) +
1721                         sizeof(mpi_dump->serdes2_xaui_hss_pcs)),
1722                 "XAUI2 HSS PCS Registers");
1723
1724         qls_mpid_seg_hdr(&mpi_dump->xfi2_an_hdr,
1725                 Q81_XFI2_AN_SEG_NUM,
1726                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->serdes2_xfi_an)),
1727                 "XFI2 AN Registers");
1728
1729         qls_mpid_seg_hdr(&mpi_dump->xfi2_train_hdr,
1730                 Q81_XFI2_TRAIN_SEG_NUM,
1731                 (sizeof(qls_mpid_seg_hdr_t) +
1732                         sizeof(mpi_dump->serdes2_xfi_train)),
1733                 "XFI2 TRAIN Registers");
1734
1735         qls_mpid_seg_hdr(&mpi_dump->xfi2_hss_pcs_hdr,
1736                 Q81_XFI2_HSS_PCS_SEG_NUM,
1737                 (sizeof(qls_mpid_seg_hdr_t) +
1738                         sizeof(mpi_dump->serdes2_xfi_hss_pcs)),
1739                 "XFI2 HSS PCS Registers");
1740
1741         qls_mpid_seg_hdr(&mpi_dump->xfi2_hss_tx_hdr,
1742                 Q81_XFI2_HSS_TX_SEG_NUM,
1743                 (sizeof(qls_mpid_seg_hdr_t) +
1744                         sizeof(mpi_dump->serdes2_xfi_hss_tx)),
1745                 "XFI2 HSS TX Registers");
1746
1747         qls_mpid_seg_hdr(&mpi_dump->xfi2_hss_rx_hdr,
1748                 Q81_XFI2_HSS_RX_SEG_NUM,
1749                 (sizeof(qls_mpid_seg_hdr_t) +
1750                         sizeof(mpi_dump->serdes2_xfi_hss_rx)),
1751                 "XFI2 HSS RX Registers");
1752
1753         qls_mpid_seg_hdr(&mpi_dump->xfi2_hss_pll_hdr,
1754                 Q81_XFI2_HSS_PLL_SEG_NUM,
1755                 (sizeof(qls_mpid_seg_hdr_t) +
1756                         sizeof(mpi_dump->serdes2_xfi_hss_pll)),
1757                 "XFI2 HSS PLL Registers");
1758
1759         qls_rd_serdes_regs(ha, mpi_dump);
1760
1761         qls_mpid_seg_hdr(&mpi_dump->core_regs_seg_hdr,
1762                 Q81_CORE_SEG_NUM,
1763                 (sizeof(mpi_dump->core_regs_seg_hdr) +
1764                  sizeof(mpi_dump->mpi_core_regs) +
1765                  sizeof(mpi_dump->mpi_core_sh_regs)),
1766                 "Core Registers");
1767
1768         ret = qls_get_mpi_regs(ha, &mpi_dump->mpi_core_regs[0],
1769                         Q81_MPI_CORE_REGS_ADDR, Q81_MPI_CORE_REGS_CNT);
1770
1771         ret = qls_get_mpi_shadow_regs(ha,
1772                         &mpi_dump->mpi_core_sh_regs[0]);
1773
1774         qls_mpid_seg_hdr(&mpi_dump->test_logic_regs_seg_hdr,
1775                 Q81_TEST_LOGIC_SEG_NUM,
1776                 (sizeof(qls_mpid_seg_hdr_t) +
1777                         sizeof(mpi_dump->test_logic_regs)),
1778                 "Test Logic Regs");
1779
1780         ret = qls_get_mpi_regs(ha, &mpi_dump->test_logic_regs[0],
1781                             Q81_TEST_REGS_ADDR, Q81_TEST_REGS_CNT);
1782
1783         qls_mpid_seg_hdr(&mpi_dump->rmii_regs_seg_hdr,
1784                 Q81_RMII_SEG_NUM,
1785                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->rmii_regs)),
1786                 "RMII Registers");
1787
1788         ret = qls_get_mpi_regs(ha, &mpi_dump->rmii_regs[0],
1789                             Q81_RMII_REGS_ADDR, Q81_RMII_REGS_CNT);
1790
1791         qls_mpid_seg_hdr(&mpi_dump->fcmac1_regs_seg_hdr,
1792                 Q81_FCMAC1_SEG_NUM,
1793                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->fcmac1_regs)),
1794                 "FCMAC1 Registers");
1795
1796         ret = qls_get_mpi_regs(ha, &mpi_dump->fcmac1_regs[0],
1797                             Q81_FCMAC1_REGS_ADDR, Q81_FCMAC_REGS_CNT);
1798
1799         qls_mpid_seg_hdr(&mpi_dump->fcmac2_regs_seg_hdr,
1800                 Q81_FCMAC2_SEG_NUM,
1801                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->fcmac2_regs)),
1802                 "FCMAC2 Registers");
1803
1804         ret = qls_get_mpi_regs(ha, &mpi_dump->fcmac2_regs[0],
1805                             Q81_FCMAC2_REGS_ADDR, Q81_FCMAC_REGS_CNT);
1806
1807         qls_mpid_seg_hdr(&mpi_dump->fc1_mbx_regs_seg_hdr,
1808                 Q81_FC1_MBOX_SEG_NUM,
1809                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->fc1_mbx_regs)),
1810                 "FC1 MBox Regs");
1811
1812         ret = qls_get_mpi_regs(ha, &mpi_dump->fc1_mbx_regs[0],
1813                             Q81_FC1_MBX_REGS_ADDR, Q81_FC_MBX_REGS_CNT);
1814
1815         qls_mpid_seg_hdr(&mpi_dump->ide_regs_seg_hdr,
1816                 Q81_IDE_SEG_NUM,
1817                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->ide_regs)),
1818                 "IDE Registers");
1819
1820         ret = qls_get_mpi_regs(ha, &mpi_dump->ide_regs[0],
1821                             Q81_IDE_REGS_ADDR, Q81_IDE_REGS_CNT);
1822
1823         qls_mpid_seg_hdr(&mpi_dump->nic1_mbx_regs_seg_hdr,
1824                 Q81_NIC1_MBOX_SEG_NUM,
1825                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->nic1_mbx_regs)),
1826                 "NIC1 MBox Regs");
1827
1828         ret = qls_get_mpi_regs(ha, &mpi_dump->nic1_mbx_regs[0],
1829                             Q81_NIC1_MBX_REGS_ADDR, Q81_NIC_MBX_REGS_CNT);
1830
1831         qls_mpid_seg_hdr(&mpi_dump->smbus_regs_seg_hdr,
1832                 Q81_SMBUS_SEG_NUM,
1833                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->smbus_regs)),
1834                 "SMBus Registers");
1835
1836         ret = qls_get_mpi_regs(ha, &mpi_dump->smbus_regs[0],
1837                             Q81_SMBUS_REGS_ADDR, Q81_SMBUS_REGS_CNT);
1838
1839         qls_mpid_seg_hdr(&mpi_dump->fc2_mbx_regs_seg_hdr,
1840                 Q81_FC2_MBOX_SEG_NUM,
1841                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->fc2_mbx_regs)),
1842                 "FC2 MBox Regs");
1843
1844         ret = qls_get_mpi_regs(ha, &mpi_dump->fc2_mbx_regs[0],
1845                             Q81_FC2_MBX_REGS_ADDR, Q81_FC_MBX_REGS_CNT);
1846
1847         qls_mpid_seg_hdr(&mpi_dump->nic2_mbx_regs_seg_hdr,
1848                 Q81_NIC2_MBOX_SEG_NUM,
1849                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->nic2_mbx_regs)),
1850                 "NIC2 MBox Regs");
1851
1852         ret = qls_get_mpi_regs(ha, &mpi_dump->nic2_mbx_regs[0],
1853                             Q81_NIC2_MBX_REGS_ADDR, Q81_NIC_MBX_REGS_CNT);
1854
1855         qls_mpid_seg_hdr(&mpi_dump->i2c_regs_seg_hdr,
1856                 Q81_I2C_SEG_NUM,
1857                 (sizeof(qls_mpid_seg_hdr_t) +
1858                         sizeof(mpi_dump->i2c_regs)),
1859                 "I2C Registers");
1860
1861         ret = qls_get_mpi_regs(ha, &mpi_dump->i2c_regs[0],
1862                             Q81_I2C_REGS_ADDR, Q81_I2C_REGS_CNT);
1863
1864         qls_mpid_seg_hdr(&mpi_dump->memc_regs_seg_hdr,
1865                 Q81_MEMC_SEG_NUM,
1866                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->memc_regs)),
1867                 "MEMC Registers");
1868
1869         ret = qls_get_mpi_regs(ha, &mpi_dump->memc_regs[0],
1870                             Q81_MEMC_REGS_ADDR, Q81_MEMC_REGS_CNT);
1871
1872         qls_mpid_seg_hdr(&mpi_dump->pbus_regs_seg_hdr,
1873                 Q81_PBUS_SEG_NUM,
1874                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->pbus_regs)),
1875                 "PBUS Registers");
1876
1877         ret = qls_get_mpi_regs(ha, &mpi_dump->pbus_regs[0],
1878                             Q81_PBUS_REGS_ADDR, Q81_PBUS_REGS_CNT);
1879
1880         qls_mpid_seg_hdr(&mpi_dump->mde_regs_seg_hdr,
1881                 Q81_MDE_SEG_NUM,
1882                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->mde_regs)),
1883                 "MDE Registers");
1884
1885         ret = qls_get_mpi_regs(ha, &mpi_dump->mde_regs[0],
1886                             Q81_MDE_REGS_ADDR, Q81_MDE_REGS_CNT);
1887
1888         qls_mpid_seg_hdr(&mpi_dump->intr_states_seg_hdr,
1889                 Q81_INTR_STATES_SEG_NUM,
1890                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->intr_states)),
1891                 "INTR States");
1892
1893         qls_get_intr_states(ha, &mpi_dump->intr_states[0]);
1894
1895         qls_mpid_seg_hdr(&mpi_dump->probe_dump_seg_hdr,
1896                 Q81_PROBE_DUMP_SEG_NUM,
1897                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->probe_dump)),
1898                 "Probe Dump");
1899
1900         qls_get_probe_dump(ha, &mpi_dump->probe_dump[0]);
1901
1902         qls_mpid_seg_hdr(&mpi_dump->routing_reg_seg_hdr,
1903                 Q81_ROUTING_INDEX_SEG_NUM,
1904                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->routing_regs)),
1905                 "Routing Regs");
1906
1907         qls_get_ridx_registers(ha, &mpi_dump->routing_regs[0]);
1908
1909         qls_mpid_seg_hdr(&mpi_dump->mac_prot_reg_seg_hdr,
1910                 Q81_MAC_PROTOCOL_SEG_NUM,
1911                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->mac_prot_regs)),
1912                 "MAC Prot Regs");
1913
1914         qls_get_mac_proto_regs(ha, &mpi_dump->mac_prot_regs[0]);
1915
1916         qls_mpid_seg_hdr(&mpi_dump->ets_seg_hdr,
1917                 Q81_ETS_SEG_NUM,
1918                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->ets)),
1919                 "ETS Registers");
1920
1921         ret = qls_get_ets_regs(ha, &mpi_dump->ets[0]);
1922
1923         qls_mpid_seg_hdr(&mpi_dump->sem_regs_seg_hdr,
1924                 Q81_SEM_REGS_SEG_NUM,
1925                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->sem_regs)),
1926                 "Sem Registers");
1927
1928         for(i = 0; i < Q81_MAX_SEMAPHORE_FUNCTIONS ; i ++) {
1929
1930                 reg = Q81_CTL_PROC_ADDR_REG_BLOCK | (i << Q81_FUNCTION_SHIFT) |
1931                                 (Q81_CTL_SEMAPHORE >> 2);
1932
1933                 ret = qls_mpi_risc_rd_reg(ha, reg, &reg_val);
1934                 mpi_dump->sem_regs[i] = reg_val;
1935
1936                 if (ret != 0)
1937                         mpi_dump->sem_regs[i] = Q81_BAD_DATA;
1938         }
1939
1940         ret = qls_unpause_mpi_risc(ha);
1941         if (ret)
1942                 printf("Failed RISC unpause. Status = 0x%.08x\n",ret);
1943
1944         ret = qls_mpi_reset(ha);
1945         if (ret)
1946                 printf("Failed RISC reset. Status = 0x%.08x\n",ret);
1947
1948         WRITE_REG32(ha, Q81_CTL_FUNC_SPECIFIC, 0x80008000);
1949
1950         qls_mpid_seg_hdr(&mpi_dump->memc_ram_seg_hdr,
1951                 Q81_MEMC_RAM_SEG_NUM,
1952                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->memc_ram)),
1953                 "MEMC RAM");
1954
1955         ret = qls_mbx_dump_risc_ram(ha, &mpi_dump->memc_ram[0],
1956                         Q81_MEMC_RAM_ADDR, Q81_MEMC_RAM_CNT);
1957         if (ret)
1958                 printf("Failed Dump of MEMC RAM. Status = 0x%.08x\n",ret);
1959
1960         qls_mpid_seg_hdr(&mpi_dump->code_ram_seg_hdr,
1961                 Q81_WCS_RAM_SEG_NUM,
1962                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->code_ram)),
1963                 "WCS RAM");
1964
1965         ret = qls_mbx_dump_risc_ram(ha, &mpi_dump->memc_ram[0],
1966                         Q81_CODE_RAM_ADDR, Q81_CODE_RAM_CNT);
1967         if (ret)
1968                 printf("Failed Dump of CODE RAM. Status = 0x%.08x\n",ret);
1969
1970         qls_mpid_seg_hdr(&mpi_dump->wqc1_seg_hdr,
1971                 Q81_WQC1_SEG_NUM,
1972                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->wqc1)),
1973                 "WQC 1");
1974
1975         qls_mpid_seg_hdr(&mpi_dump->wqc2_seg_hdr,
1976                 Q81_WQC2_SEG_NUM,
1977                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->wqc2)),
1978                 "WQC 2");
1979
1980         qls_mpid_seg_hdr(&mpi_dump->cqc1_seg_hdr,
1981                 Q81_CQC1_SEG_NUM,
1982                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->cqc1)),
1983                 "CQC 1");
1984
1985         qls_mpid_seg_hdr(&mpi_dump->cqc2_seg_hdr,
1986                 Q81_CQC2_SEG_NUM,
1987                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->cqc2)),
1988                 "CQC 2");
1989
1990         return 0;
1991 }
1992