2 * Copyright (c) 1998 Joachim Kuebart <joachim.kuebart@gmx.net>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 /* This supports the ENSONIQ AudioPCI board based on the ES1370. */
34 #define ES1370_REG_CONTROL 0x00
35 #define ES1370_REG_STATUS 0x04
36 #define ES1370_REG_UART_DATA 0x08
37 #define ES1370_REG_UART_STATUS 0x09
38 #define ES1370_REG_UART_CONTROL 0x09
39 #define ES1370_REG_UART_TEST 0x0a
40 #define ES1370_REG_MEMPAGE 0x0c
41 #define ES1370_REG_CODEC 0x10
42 #define CODEC_INDEX_SHIFT 8
43 #define ES1370_REG_SERIAL_CONTROL 0x20
44 #define ES1370_REG_DAC1_SCOUNT 0x24
45 #define ES1370_REG_DAC2_SCOUNT 0x28
46 #define ES1370_REG_ADC_SCOUNT 0x2c
48 #define ES1370_REG_DAC1_FRAMEADR 0xc30
49 #define ES1370_REG_DAC1_FRAMECNT 0xc34
50 #define ES1370_REG_DAC2_FRAMEADR 0xc38
51 #define ES1370_REG_DAC2_FRAMECNT 0xc3c
52 #define ES1370_REG_ADC_FRAMEADR 0xd30
53 #define ES1370_REG_ADC_FRAMECNT 0xd34
55 #define DAC2_SRTODIV(x) (((1411200 + (x) / 2) / (x) - 2) & 0x1fff)
56 #define DAC2_DIVTOSR(x) (1411200 / ((x) + 2))
58 #define CTRL_ADC_STOP 0x80000000 /* 1 = ADC stopped */
59 #define CTRL_XCTL1 0x40000000 /* SERR pin if enabled */
60 #define CTRL_OPEN 0x20000000 /* no function, can be read and
62 #define CTRL_PCLKDIV 0x1fff0000 /* ADC/DAC2 clock divider */
63 #define CTRL_SH_PCLKDIV 16
64 #define CTRL_MSFMTSEL 0x00008000 /* MPEG serial data fmt: 0 = Sony, 1
66 #define CTRL_M_SBB 0x00004000 /* DAC2 clock: 0 = PCLKDIV, 1 = MPEG */
67 #define CTRL_WTSRSEL 0x00003000 /* DAC1 clock freq: 0=5512, 1=11025,
69 #define CTRL_SH_WTSRSEL 12
70 #define CTRL_DAC_SYNC 0x00000800 /* 1 = DAC2 runs off DAC1 clock */
71 #define CTRL_CCB_INTRM 0x00000400 /* 1 = CCB "voice" ints enabled */
72 #define CTRL_M_CB 0x00000200 /* recording source: 0 = ADC, 1 =
74 #define CTRL_XCTL0 0x00000100 /* 0 = Line in, 1 = Line out */
75 #define CTRL_BREQ 0x00000080 /* 1 = test mode (internal mem test) */
76 #define CTRL_DAC1_EN 0x00000040 /* enable DAC1 */
77 #define CTRL_DAC2_EN 0x00000020 /* enable DAC2 */
78 #define CTRL_ADC_EN 0x00000010 /* enable ADC */
79 #define CTRL_UART_EN 0x00000008 /* enable MIDI uart */
80 #define CTRL_JYSTK_EN 0x00000004 /* enable Joystick port (presumably
81 * at address 0x200) */
82 #define CTRL_CDC_EN 0x00000002 /* enable serial (CODEC) interface */
83 #define CTRL_SERR_DIS 0x00000001 /* 1 = disable PCI SERR signal */
85 #define SCTRL_P2ENDINC 0x00380000 /* */
86 #define SCTRL_SH_P2ENDINC 19
87 #define SCTRL_P2STINC 0x00070000 /* */
88 #define SCTRL_SH_P2STINC 16
89 #define SCTRL_R1LOOPSEL 0x00008000 /* 0 = loop mode */
90 #define SCTRL_P2LOOPSEL 0x00004000 /* 0 = loop mode */
91 #define SCTRL_P1LOOPSEL 0x00002000 /* 0 = loop mode */
92 #define SCTRL_P2PAUSE 0x00001000 /* 1 = pause mode */
93 #define SCTRL_P1PAUSE 0x00000800 /* 1 = pause mode */
94 #define SCTRL_R1INTEN 0x00000400 /* enable interrupt */
95 #define SCTRL_P2INTEN 0x00000200 /* enable interrupt */
96 #define SCTRL_P1INTEN 0x00000100 /* enable interrupt */
97 #define SCTRL_P1SCTRLD 0x00000080 /* reload sample count register for
99 #define SCTRL_P2DACSEN 0x00000040 /* 1 = DAC2 play back last sample
101 #define SCTRL_R1SEB 0x00000020 /* 1 = 16bit */
102 #define SCTRL_R1SMB 0x00000010 /* 1 = stereo */
103 #define SCTRL_R1FMT 0x00000030 /* format mask */
104 #define SCTRL_SH_R1FMT 4
105 #define SCTRL_P2SEB 0x00000008 /* 1 = 16bit */
106 #define SCTRL_P2SMB 0x00000004 /* 1 = stereo */
107 #define SCTRL_P2FMT 0x0000000c /* format mask */
108 #define SCTRL_SH_P2FMT 2
109 #define SCTRL_P1SEB 0x00000002 /* 1 = 16bit */
110 #define SCTRL_P1SMB 0x00000001 /* 1 = stereo */
111 #define SCTRL_P1FMT 0x00000003 /* format mask */
112 #define SCTRL_SH_P1FMT 0
114 #define STAT_INTR 0x80000000 /* wired or of all interrupt bits */
115 #define STAT_CSTAT 0x00000400 /* 1 = codec busy or codec write in
117 #define STAT_CBUSY 0x00000200 /* 1 = codec busy */
118 #define STAT_CWRIP 0x00000100 /* 1 = codec write in progress */
119 #define STAT_VC 0x00000060 /* CCB int source, 0=DAC1, 1=DAC2,
122 #define STAT_MCCB 0x00000010 /* CCB int pending */
123 #define STAT_UART 0x00000008 /* UART int pending */
124 #define STAT_DAC1 0x00000004 /* DAC1 int pending */
125 #define STAT_DAC2 0x00000002 /* DAC2 int pending */
126 #define STAT_ADC 0x00000001 /* ADC int pending */
128 #define CODEC_OMIX1 0x10
129 #define CODEC_OMIX2 0x11
130 #define CODEC_LIMIX1 0x12
131 #define CODEC_RIMIX1 0x13
132 #define CODEC_LIMIX2 0x14
133 #define CODEC_RIMIX2 0x15
134 #define CODEC_RES_PD 0x16
135 #define CODEC_CSEL 0x17
136 #define CODEC_ADSEL 0x18
137 #define CODEC_MGAIN 0x19
139 /* ES1371 specific */
141 #define CODEC_ID_SESHIFT 10
142 #define CODEC_ID_SEMASK 0x1f
144 #define CODEC_PIRD 0x00800000 /* 0 = write AC97 register */
145 #define CODEC_PIADD_MASK 0x007f0000
146 #define CODEC_PIADD_SHIFT 16
147 #define CODEC_PIDAT_MASK 0x0000ffff
148 #define CODEC_PIDAT_SHIFT 0
150 #define CODEC_PORD 0x00800000 /* 0 = write AC97 register */
151 #define CODEC_POADD_MASK 0x007f0000
152 #define CODEC_POADD_SHIFT 16
153 #define CODEC_PODAT_MASK 0x0000ffff
154 #define CODEC_PODAT_SHIFT 0
156 #define CODEC_RDY 0x80000000 /* AC97 read data valid */
157 #define CODEC_WIP 0x40000000 /* AC97 write in progress */
159 #define ES1370_REG_CONTROL 0x00
160 #define ES1370_REG_SERIAL_CONTROL 0x20
161 #define ES1371_REG_CODEC 0x14
162 #define ES1371_REG_LEGACY 0x18 /* W/R: Legacy control/status register */
163 #define ES1371_REG_SMPRATE 0x10 /* W/R: Codec rate converter interface register */
165 #define ES1371_SYNC_RES (1<<14) /* Warm AC97 reset */
166 #define ES1371_DIS_R1 (1<<19) /* record channel accumulator update disable */
167 #define ES1371_DIS_P2 (1<<20) /* playback channel 2 accumulator update disable */
168 #define ES1371_DIS_P1 (1<<21) /* playback channel 1 accumulator update disable */
169 #define ES1371_DIS_SRC (1<<22) /* sample rate converter disable */
170 #define ES1371_SRC_RAM_BUSY (1<<23) /* R/O: sample rate memory is busy */
171 #define ES1371_SRC_RAM_WE (1<<24) /* R/W: read/write control for sample rate converter */
172 #define ES1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25) /* address of the sample rate converter */
173 #define ES1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0) /* current value of the sample rate converter */
174 #define ES1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff) /* current value of the sample rate converter */
180 /* Use ES1370_REG_CONTROL */
181 #define RECEN_B 0x08000000 /* Used to control mixing of analog with digital data */
182 #define SPDIFEN_B 0x04000000 /* Reset to switch digital output mux to "THRU" mode */
183 /* Use ES1370_REG_STATUS */
184 #define ENABLE_SPDIF 0x00040000 /* Used to enable the S/PDIF circuitry */
185 #define TEST_SPDIF 0x00020000 /* Used to put the S/PDIF module in "test mode" */
188 * Sample rate converter addresses
191 #define ES_SMPREG_DAC1 0x70
192 #define ES_SMPREG_DAC2 0x74
193 #define ES_SMPREG_ADC 0x78
194 #define ES_SMPREG_TRUNC_N 0x00
195 #define ES_SMPREG_INT_REGS 0x01
196 #define ES_SMPREG_VFREQ_FRAC 0x03
197 #define ES_SMPREG_VOL_ADC 0x6c
198 #define ES_SMPREG_VOL_DAC1 0x7c
199 #define ES_SMPREG_VOL_DAC2 0x7e