sys/dev/sound/pci/hda/hdac.c

   1 /*-
   2  * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>
   3  * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org>
   4  * Copyright (c) 2008-2012 Alexander Motin <mav@FreeBSD.org>
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 /*
  30  * Intel High Definition Audio (Controller) driver for FreeBSD.
  31  */
  32
  33 #ifdef HAVE_KERNEL_OPTION_HEADERS
  34 #include "opt_snd.h"
  35 #endif
  36
  37 #include <dev/sound/pcm/sound.h>
  38 #include <dev/pci/pcireg.h>
  39 #include <dev/pci/pcivar.h>
  40
  41 #include <sys/ctype.h>
  42 #include <sys/taskqueue.h>
  43
  44 #include <dev/sound/pci/hda/hdac_private.h>
  45 #include <dev/sound/pci/hda/hdac_reg.h>
  46 #include <dev/sound/pci/hda/hda_reg.h>
  47 #include <dev/sound/pci/hda/hdac.h>
  48
  49 #define HDA_DRV_TEST_REV        "20120126_0002"
  50
  51 SND_DECLARE_FILE("$FreeBSD$");
  52
  53 #define hdac_lock(sc)           snd_mtxlock((sc)->lock)
  54 #define hdac_unlock(sc)         snd_mtxunlock((sc)->lock)
  55 #define hdac_lockassert(sc)     snd_mtxassert((sc)->lock)
  56 #define hdac_lockowned(sc)      mtx_owned((sc)->lock)
  57
  58 #define HDAC_QUIRK_64BIT        (1 << 0)
  59 #define HDAC_QUIRK_DMAPOS       (1 << 1)
  60 #define HDAC_QUIRK_MSI          (1 << 2)
  61
  62 static const struct {
  63         char *key;
  64         uint32_t value;
  65 } hdac_quirks_tab[] = {
  66         { "64bit", HDAC_QUIRK_DMAPOS },
  67         { "dmapos", HDAC_QUIRK_DMAPOS },
  68         { "msi", HDAC_QUIRK_MSI },
  69 };
  70 #define HDAC_QUIRKS_TAB_LEN     \
  71                 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0]))
  72
  73 MALLOC_DEFINE(M_HDAC, "hdac", "HDA Controller");
  74
  75 static const struct {
  76         uint32_t        model;
  77         char            *desc;
  78         char            quirks_on;
  79         char            quirks_off;
  80 } hdac_devices[] = {
  81         { HDA_INTEL_CPT,     "Intel Cougar Point",      0, 0 },
  82         { HDA_INTEL_PATSBURG,"Intel Patsburg",  0, 0 },
  83         { HDA_INTEL_PPT1,    "Intel Panther Point",     0, 0 },
  84         { HDA_INTEL_LPT1,    "Intel Lynx Point",        0, 0 },
  85         { HDA_INTEL_LPT2,    "Intel Lynx Point",        0, 0 },
  86         { HDA_INTEL_82801F,  "Intel 82801F",    0, 0 },
  87         { HDA_INTEL_63XXESB, "Intel 631x/632xESB",      0, 0 },
  88         { HDA_INTEL_82801G,  "Intel 82801G",    0, 0 },
  89         { HDA_INTEL_82801H,  "Intel 82801H",    0, 0 },
  90         { HDA_INTEL_82801I,  "Intel 82801I",    0, 0 },
  91         { HDA_INTEL_82801JI, "Intel 82801JI",   0, 0 },
  92         { HDA_INTEL_82801JD, "Intel 82801JD",   0, 0 },
  93         { HDA_INTEL_PCH,     "Intel 5 Series/3400 Series",      0, 0 },
  94         { HDA_INTEL_PCH2,    "Intel 5 Series/3400 Series",      0, 0 },
  95         { HDA_INTEL_SCH,     "Intel SCH",       0, 0 },
  96         { HDA_NVIDIA_MCP51,  "NVIDIA MCP51",    0, HDAC_QUIRK_MSI },
  97         { HDA_NVIDIA_MCP55,  "NVIDIA MCP55",    0, HDAC_QUIRK_MSI },
  98         { HDA_NVIDIA_MCP61_1, "NVIDIA MCP61",   0, 0 },
  99         { HDA_NVIDIA_MCP61_2, "NVIDIA MCP61",   0, 0 },
 100         { HDA_NVIDIA_MCP65_1, "NVIDIA MCP65",   0, 0 },
 101         { HDA_NVIDIA_MCP65_2, "NVIDIA MCP65",   0, 0 },
 102         { HDA_NVIDIA_MCP67_1, "NVIDIA MCP67",   0, 0 },
 103         { HDA_NVIDIA_MCP67_2, "NVIDIA MCP67",   0, 0 },
 104         { HDA_NVIDIA_MCP73_1, "NVIDIA MCP73",   0, 0 },
 105         { HDA_NVIDIA_MCP73_2, "NVIDIA MCP73",   0, 0 },
 106         { HDA_NVIDIA_MCP78_1, "NVIDIA MCP78",   0, HDAC_QUIRK_64BIT },
 107         { HDA_NVIDIA_MCP78_2, "NVIDIA MCP78",   0, HDAC_QUIRK_64BIT },
 108         { HDA_NVIDIA_MCP78_3, "NVIDIA MCP78",   0, HDAC_QUIRK_64BIT },
 109         { HDA_NVIDIA_MCP78_4, "NVIDIA MCP78",   0, HDAC_QUIRK_64BIT },
 110         { HDA_NVIDIA_MCP79_1, "NVIDIA MCP79",   0, 0 },
 111         { HDA_NVIDIA_MCP79_2, "NVIDIA MCP79",   0, 0 },
 112         { HDA_NVIDIA_MCP79_3, "NVIDIA MCP79",   0, 0 },
 113         { HDA_NVIDIA_MCP79_4, "NVIDIA MCP79",   0, 0 },
 114         { HDA_NVIDIA_MCP89_1, "NVIDIA MCP89",   0, 0 },
 115         { HDA_NVIDIA_MCP89_2, "NVIDIA MCP89",   0, 0 },
 116         { HDA_NVIDIA_MCP89_3, "NVIDIA MCP89",   0, 0 },
 117         { HDA_NVIDIA_MCP89_4, "NVIDIA MCP89",   0, 0 },
 118         { HDA_NVIDIA_0BE2,   "NVIDIA (0x0be2)", 0, HDAC_QUIRK_MSI },
 119         { HDA_NVIDIA_0BE3,   "NVIDIA (0x0be3)", 0, HDAC_QUIRK_MSI },
 120         { HDA_NVIDIA_0BE4,   "NVIDIA (0x0be4)", 0, HDAC_QUIRK_MSI },
 121         { HDA_NVIDIA_GT100,  "NVIDIA GT100",    0, HDAC_QUIRK_MSI },
 122         { HDA_NVIDIA_GT104,  "NVIDIA GT104",    0, HDAC_QUIRK_MSI },
 123         { HDA_NVIDIA_GT106,  "NVIDIA GT106",    0, HDAC_QUIRK_MSI },
 124         { HDA_NVIDIA_GT108,  "NVIDIA GT108",    0, HDAC_QUIRK_MSI },
 125         { HDA_NVIDIA_GT116,  "NVIDIA GT116",    0, HDAC_QUIRK_MSI },
 126         { HDA_NVIDIA_GF119,  "NVIDIA GF119",    0, 0 },
 127         { HDA_NVIDIA_GF110_1, "NVIDIA GF110",   0, HDAC_QUIRK_MSI },
 128         { HDA_NVIDIA_GF110_2, "NVIDIA GF110",   0, HDAC_QUIRK_MSI },
 129         { HDA_ATI_SB450,     "ATI SB450",       0, 0 },
 130         { HDA_ATI_SB600,     "ATI SB600",       0, 0 },
 131         { HDA_ATI_RS600,     "ATI RS600",       0, 0 },
 132         { HDA_ATI_RS690,     "ATI RS690",       0, 0 },
 133         { HDA_ATI_RS780,     "ATI RS780",       0, 0 },
 134         { HDA_ATI_R600,      "ATI R600",        0, 0 },
 135         { HDA_ATI_RV610,     "ATI RV610",       0, 0 },
 136         { HDA_ATI_RV620,     "ATI RV620",       0, 0 },
 137         { HDA_ATI_RV630,     "ATI RV630",       0, 0 },
 138         { HDA_ATI_RV635,     "ATI RV635",       0, 0 },
 139         { HDA_ATI_RV710,     "ATI RV710",       0, 0 },
 140         { HDA_ATI_RV730,     "ATI RV730",       0, 0 },
 141         { HDA_ATI_RV740,     "ATI RV740",       0, 0 },
 142         { HDA_ATI_RV770,     "ATI RV770",       0, 0 },
 143         { HDA_ATI_RV810,     "ATI RV810",       0, 0 },
 144         { HDA_ATI_RV830,     "ATI RV830",       0, 0 },
 145         { HDA_ATI_RV840,     "ATI RV840",       0, 0 },
 146         { HDA_ATI_RV870,     "ATI RV870",       0, 0 },
 147         { HDA_ATI_RV910,     "ATI RV910",       0, 0 },
 148         { HDA_ATI_RV930,     "ATI RV930",       0, 0 },
 149         { HDA_ATI_RV940,     "ATI RV940",       0, 0 },
 150         { HDA_ATI_RV970,     "ATI RV970",       0, 0 },
 151         { HDA_ATI_R1000,     "ATI R1000",       0, 0 },
 152         { HDA_RDC_M3010,     "RDC M3010",       0, 0 },
 153         { HDA_VIA_VT82XX,    "VIA VT8251/8237A",0, 0 },
 154         { HDA_SIS_966,       "SiS 966",         0, 0 },
 155         { HDA_ULI_M5461,     "ULI M5461",       0, 0 },
 156         /* Unknown */
 157         { HDA_INTEL_ALL,  "Intel",              0, 0 },
 158         { HDA_NVIDIA_ALL, "NVIDIA",             0, 0 },
 159         { HDA_ATI_ALL,    "ATI",                0, 0 },
 160         { HDA_VIA_ALL,    "VIA",                0, 0 },
 161         { HDA_SIS_ALL,    "SiS",                0, 0 },
 162         { HDA_ULI_ALL,    "ULI",                0, 0 },
 163 };
 164 #define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0]))
 165
 166 static const struct {
 167         uint16_t vendor;
 168         uint8_t reg;
 169         uint8_t mask;
 170         uint8_t enable;
 171 } hdac_pcie_snoop[] = {
 172         {  INTEL_VENDORID, 0x00, 0x00, 0x00 },
 173         {    ATI_VENDORID, 0x42, 0xf8, 0x02 },
 174         { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f },
 175 };
 176 #define HDAC_PCIESNOOP_LEN      \
 177                         (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0]))
 178
 179 /****************************************************************************
 180  * Function prototypes
 181  ****************************************************************************/
 182 static void     hdac_intr_handler(void *);
 183 static int      hdac_reset(struct hdac_softc *, int);
 184 static int      hdac_get_capabilities(struct hdac_softc *);
 185 static void     hdac_dma_cb(void *, bus_dma_segment_t *, int, int);
 186 static int      hdac_dma_alloc(struct hdac_softc *,
 187                                         struct hdac_dma *, bus_size_t);
 188 static void     hdac_dma_free(struct hdac_softc *, struct hdac_dma *);
 189 static int      hdac_mem_alloc(struct hdac_softc *);
 190 static void     hdac_mem_free(struct hdac_softc *);
 191 static int      hdac_irq_alloc(struct hdac_softc *);
 192 static void     hdac_irq_free(struct hdac_softc *);
 193 static void     hdac_corb_init(struct hdac_softc *);
 194 static void     hdac_rirb_init(struct hdac_softc *);
 195 static void     hdac_corb_start(struct hdac_softc *);
 196 static void     hdac_rirb_start(struct hdac_softc *);
 197
 198 static void     hdac_attach2(void *);
 199
 200 static uint32_t hdac_send_command(struct hdac_softc *, nid_t, uint32_t);
 201
 202 static int      hdac_probe(device_t);
 203 static int      hdac_attach(device_t);
 204 static int      hdac_detach(device_t);
 205 static int      hdac_suspend(device_t);
 206 static int      hdac_resume(device_t);
 207
 208 static int      hdac_rirb_flush(struct hdac_softc *sc);
 209 static int      hdac_unsolq_flush(struct hdac_softc *sc);
 210
 211 #define hdac_command(a1, a2, a3)        \
 212                 hdac_send_command(a1, a3, a2)
 213
 214 /* This function surely going to make its way into upper level someday. */
 215 static void
 216 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off)
 217 {
 218         const char *res = NULL;
 219         int i = 0, j, k, len, inv;
 220
 221         if (resource_string_value(device_get_name(sc->dev),
 222             device_get_unit(sc->dev), "config", &res) != 0)
 223                 return;
 224         if (!(res != NULL && strlen(res) > 0))
 225                 return;
 226         HDA_BOOTVERBOSE(
 227                 device_printf(sc->dev, "Config options:");
 228         );
 229         for (;;) {
 230                 while (res[i] != '\0' &&
 231                     (res[i] == ',' || isspace(res[i]) != 0))
 232                         i++;
 233                 if (res[i] == '\0') {
 234                         HDA_BOOTVERBOSE(
 235                                 printf("\n");
 236                         );
 237                         return;
 238                 }
 239                 j = i;
 240                 while (res[j] != '\0' &&
 241                     !(res[j] == ',' || isspace(res[j]) != 0))
 242                         j++;
 243                 len = j - i;
 244                 if (len > 2 && strncmp(res + i, "no", 2) == 0)
 245                         inv = 2;
 246                 else
 247                         inv = 0;
 248                 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) {
 249                         if (strncmp(res + i + inv,
 250                             hdac_quirks_tab[k].key, len - inv) != 0)
 251                                 continue;
 252                         if (len - inv != strlen(hdac_quirks_tab[k].key))
 253                                 continue;
 254                         HDA_BOOTVERBOSE(
 255                                 printf(" %s%s", (inv != 0) ? "no" : "",
 256                                     hdac_quirks_tab[k].key);
 257                         );
 258                         if (inv == 0) {
 259                                 *on |= hdac_quirks_tab[k].value;
 260                                 *on &= ~hdac_quirks_tab[k].value;
 261                         } else if (inv != 0) {
 262                                 *off |= hdac_quirks_tab[k].value;
 263                                 *off &= ~hdac_quirks_tab[k].value;
 264                         }
 265                         break;
 266                 }
 267                 i = j;
 268         }
 269 }
 270
 271 /****************************************************************************
 272  * void hdac_intr_handler(void *)
 273  *
 274  * Interrupt handler. Processes interrupts received from the hdac.
 275  ****************************************************************************/
 276 static void
 277 hdac_intr_handler(void *context)
 278 {
 279         struct hdac_softc *sc;
 280         device_t dev;
 281         uint32_t intsts;
 282         uint8_t rirbsts;
 283         int i;
 284
 285         sc = (struct hdac_softc *)context;
 286         hdac_lock(sc);
 287
 288         /* Do we have anything to do? */
 289         intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS);
 290         if ((intsts & HDAC_INTSTS_GIS) == 0) {
 291                 hdac_unlock(sc);
 292                 return;
 293         }
 294
 295         /* Was this a controller interrupt? */
 296         if (intsts & HDAC_INTSTS_CIS) {
 297                 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
 298                 /* Get as many responses that we can */
 299                 while (rirbsts & HDAC_RIRBSTS_RINTFL) {
 300                         HDAC_WRITE_1(&sc->mem,
 301                             HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL);
 302                         hdac_rirb_flush(sc);
 303                         rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
 304                 }
 305                 if (sc->unsolq_rp != sc->unsolq_wp)
 306                         taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task);
 307         }
 308
 309         if (intsts & HDAC_INTSTS_SIS_MASK) {
 310                 for (i = 0; i < sc->num_ss; i++) {
 311                         if ((intsts & (1 << i)) == 0)
 312                                 continue;
 313                         HDAC_WRITE_1(&sc->mem, (i << 5) + HDAC_SDSTS,
 314                             HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS );
 315                         if ((dev = sc->streams[i].dev) != NULL) {
 316                                 HDAC_STREAM_INTR(dev,
 317                                     sc->streams[i].dir, sc->streams[i].stream);
 318                         }
 319                 }
 320         }
 321
 322         HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts);
 323         hdac_unlock(sc);
 324 }
 325
 326 static void
 327 hdac_poll_callback(void *arg)
 328 {
 329         struct hdac_softc *sc = arg;
 330
 331         if (sc == NULL)
 332                 return;
 333
 334         hdac_lock(sc);
 335         if (sc->polling == 0) {
 336                 hdac_unlock(sc);
 337                 return;
 338         }
 339         callout_reset(&sc->poll_callout, sc->poll_ival,
 340             hdac_poll_callback, sc);
 341         hdac_unlock(sc);
 342
 343         hdac_intr_handler(sc);
 344 }
 345
 346 /****************************************************************************
 347  * int hdac_reset(hdac_softc *, int)
 348  *
 349  * Reset the hdac to a quiescent and known state.
 350  ****************************************************************************/
 351 static int
 352 hdac_reset(struct hdac_softc *sc, int wakeup)
 353 {
 354         uint32_t gctl;
 355         int count, i;
 356
 357         /*
 358          * Stop all Streams DMA engine
 359          */
 360         for (i = 0; i < sc->num_iss; i++)
 361                 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0);
 362         for (i = 0; i < sc->num_oss; i++)
 363                 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0);
 364         for (i = 0; i < sc->num_bss; i++)
 365                 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0);
 366
 367         /*
 368          * Stop Control DMA engines.
 369          */
 370         HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0);
 371         HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0);
 372
 373         /*
 374          * Reset DMA position buffer.
 375          */
 376         HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0);
 377         HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0);
 378
 379         /*
 380          * Reset the controller. The reset must remain asserted for
 381          * a minimum of 100us.
 382          */
 383         gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
 384         HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST);
 385         count = 10000;
 386         do {
 387                 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
 388                 if (!(gctl & HDAC_GCTL_CRST))
 389                         break;
 390                 DELAY(10);
 391         } while (--count);
 392         if (gctl & HDAC_GCTL_CRST) {
 393                 device_printf(sc->dev, "Unable to put hdac in reset\n");
 394                 return (ENXIO);
 395         }
 396
 397         /* If wakeup is not requested - leave the controller in reset state. */
 398         if (!wakeup)
 399                 return (0);
 400
 401         DELAY(100);
 402         gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
 403         HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST);
 404         count = 10000;
 405         do {
 406                 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
 407                 if (gctl & HDAC_GCTL_CRST)
 408                         break;
 409                 DELAY(10);
 410         } while (--count);
 411         if (!(gctl & HDAC_GCTL_CRST)) {
 412                 device_printf(sc->dev, "Device stuck in reset\n");
 413                 return (ENXIO);
 414         }
 415
 416         /*
 417          * Wait for codecs to finish their own reset sequence. The delay here
 418          * should be of 250us but for some reasons, on it's not enough on my
 419          * computer. Let's use twice as much as necessary to make sure that
 420          * it's reset properly.
 421          */
 422         DELAY(1000);
 423
 424         return (0);
 425 }
 426
 427
 428 /****************************************************************************
 429  * int hdac_get_capabilities(struct hdac_softc *);
 430  *
 431  * Retreive the general capabilities of the hdac;
 432  *      Number of Input Streams
 433  *      Number of Output Streams
 434  *      Number of bidirectional Streams
 435  *      64bit ready
 436  *      CORB and RIRB sizes
 437  ****************************************************************************/
 438 static int
 439 hdac_get_capabilities(struct hdac_softc *sc)
 440 {
 441         uint16_t gcap;
 442         uint8_t corbsize, rirbsize;
 443
 444         gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP);
 445         sc->num_iss = HDAC_GCAP_ISS(gcap);
 446         sc->num_oss = HDAC_GCAP_OSS(gcap);
 447         sc->num_bss = HDAC_GCAP_BSS(gcap);
 448         sc->num_ss = sc->num_iss + sc->num_oss + sc->num_bss;
 449         sc->num_sdo = HDAC_GCAP_NSDO(gcap);
 450         sc->support_64bit = (gcap & HDAC_GCAP_64OK) != 0;
 451         if (sc->quirks_on & HDAC_QUIRK_64BIT)
 452                 sc->support_64bit = 1;
 453         else if (sc->quirks_off & HDAC_QUIRK_64BIT)
 454                 sc->support_64bit = 0;
 455
 456         corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE);
 457         if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) ==
 458             HDAC_CORBSIZE_CORBSZCAP_256)
 459                 sc->corb_size = 256;
 460         else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) ==
 461             HDAC_CORBSIZE_CORBSZCAP_16)
 462                 sc->corb_size = 16;
 463         else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) ==
 464             HDAC_CORBSIZE_CORBSZCAP_2)
 465                 sc->corb_size = 2;
 466         else {
 467                 device_printf(sc->dev, "%s: Invalid corb size (%x)\n",
 468                     __func__, corbsize);
 469                 return (ENXIO);
 470         }
 471
 472         rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE);
 473         if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) ==
 474             HDAC_RIRBSIZE_RIRBSZCAP_256)
 475                 sc->rirb_size = 256;
 476         else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) ==
 477             HDAC_RIRBSIZE_RIRBSZCAP_16)
 478                 sc->rirb_size = 16;
 479         else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) ==
 480             HDAC_RIRBSIZE_RIRBSZCAP_2)
 481                 sc->rirb_size = 2;
 482         else {
 483                 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n",
 484                     __func__, rirbsize);
 485                 return (ENXIO);
 486         }
 487
 488         HDA_BOOTVERBOSE(
 489                 device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, "
 490                     "NSDO %d%s, CORB %d, RIRB %d\n",
 491                     sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo,
 492                     sc->support_64bit ? ", 64bit" : "",
 493                     sc->corb_size, sc->rirb_size);
 494         );
 495
 496         return (0);
 497 }
 498
 499
 500 /****************************************************************************
 501  * void hdac_dma_cb
 502  *
 503  * This function is called by bus_dmamap_load when the mapping has been
 504  * established. We just record the physical address of the mapping into
 505  * the struct hdac_dma passed in.
 506  ****************************************************************************/
 507 static void
 508 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error)
 509 {
 510         struct hdac_dma *dma;
 511
 512         if (error == 0) {
 513                 dma = (struct hdac_dma *)callback_arg;
 514                 dma->dma_paddr = segs[0].ds_addr;
 515         }
 516 }
 517
 518
 519 /****************************************************************************
 520  * int hdac_dma_alloc
 521  *
 522  * This function allocate and setup a dma region (struct hdac_dma).
 523  * It must be freed by a corresponding hdac_dma_free.
 524  ****************************************************************************/
 525 static int
 526 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size)
 527 {
 528         bus_size_t roundsz;
 529         int result;
 530
 531         roundsz = roundup2(size, HDA_DMA_ALIGNMENT);
 532         bzero(dma, sizeof(*dma));
 533
 534         /*
 535          * Create a DMA tag
 536          */
 537         result = bus_dma_tag_create(
 538             bus_get_dma_tag(sc->dev),           /* parent */
 539             HDA_DMA_ALIGNMENT,                  /* alignment */
 540             0,                                  /* boundary */
 541             (sc->support_64bit) ? BUS_SPACE_MAXADDR :
 542                 BUS_SPACE_MAXADDR_32BIT,        /* lowaddr */
 543             BUS_SPACE_MAXADDR,                  /* highaddr */
 544             NULL,                               /* filtfunc */
 545             NULL,                               /* fistfuncarg */
 546             roundsz,                            /* maxsize */
 547             1,                                  /* nsegments */
 548             roundsz,                            /* maxsegsz */
 549             0,                                  /* flags */
 550             NULL,                               /* lockfunc */
 551             NULL,                               /* lockfuncarg */
 552             &dma->dma_tag);                     /* dmat */
 553         if (result != 0) {
 554                 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n",
 555                     __func__, result);
 556                 goto hdac_dma_alloc_fail;
 557         }
 558
 559         /*
 560          * Allocate DMA memory
 561          */
 562         result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr,
 563             BUS_DMA_NOWAIT | BUS_DMA_ZERO |
 564             ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0),
 565             &dma->dma_map);
 566         if (result != 0) {
 567                 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n",
 568                     __func__, result);
 569                 goto hdac_dma_alloc_fail;
 570         }
 571
 572         dma->dma_size = roundsz;
 573
 574         /*
 575          * Map the memory
 576          */
 577         result = bus_dmamap_load(dma->dma_tag, dma->dma_map,
 578             (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0);
 579         if (result != 0 || dma->dma_paddr == 0) {
 580                 if (result == 0)
 581                         result = ENOMEM;
 582                 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n",
 583                     __func__, result);
 584                 goto hdac_dma_alloc_fail;
 585         }
 586
 587         HDA_BOOTHVERBOSE(
 588                 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n",
 589                     __func__, (uintmax_t)size, (uintmax_t)roundsz);
 590         );
 591
 592         return (0);
 593
 594 hdac_dma_alloc_fail:
 595         hdac_dma_free(sc, dma);
 596
 597         return (result);
 598 }
 599
 600
 601 /****************************************************************************
 602  * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *)
 603  *
 604  * Free a struct dhac_dma that has been previously allocated via the
 605  * hdac_dma_alloc function.
 606  ****************************************************************************/
 607 static void
 608 hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma)
 609 {
 610         if (dma->dma_map != NULL) {
 611 #if 0
 612                 /* Flush caches */
 613                 bus_dmamap_sync(dma->dma_tag, dma->dma_map,
 614                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 615 #endif
 616                 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
 617         }
 618         if (dma->dma_vaddr != NULL) {
 619                 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
 620                 dma->dma_vaddr = NULL;
 621         }
 622         dma->dma_map = NULL;
 623         if (dma->dma_tag != NULL) {
 624                 bus_dma_tag_destroy(dma->dma_tag);
 625                 dma->dma_tag = NULL;
 626         }
 627         dma->dma_size = 0;
 628 }
 629
 630 /****************************************************************************
 631  * int hdac_mem_alloc(struct hdac_softc *)
 632  *
 633  * Allocate all the bus resources necessary to speak with the physical
 634  * controller.
 635  ****************************************************************************/
 636 static int
 637 hdac_mem_alloc(struct hdac_softc *sc)
 638 {
 639         struct hdac_mem *mem;
 640
 641         mem = &sc->mem;
 642         mem->mem_rid = PCIR_BAR(0);
 643         mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
 644             &mem->mem_rid, RF_ACTIVE);
 645         if (mem->mem_res == NULL) {
 646                 device_printf(sc->dev,
 647                     "%s: Unable to allocate memory resource\n", __func__);
 648                 return (ENOMEM);
 649         }
 650         mem->mem_tag = rman_get_bustag(mem->mem_res);
 651         mem->mem_handle = rman_get_bushandle(mem->mem_res);
 652
 653         return (0);
 654 }
 655
 656 /****************************************************************************
 657  * void hdac_mem_free(struct hdac_softc *)
 658  *
 659  * Free up resources previously allocated by hdac_mem_alloc.
 660  ****************************************************************************/
 661 static void
 662 hdac_mem_free(struct hdac_softc *sc)
 663 {
 664         struct hdac_mem *mem;
 665
 666         mem = &sc->mem;
 667         if (mem->mem_res != NULL)
 668                 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid,
 669                     mem->mem_res);
 670         mem->mem_res = NULL;
 671 }
 672
 673 /****************************************************************************
 674  * int hdac_irq_alloc(struct hdac_softc *)
 675  *
 676  * Allocate and setup the resources necessary for interrupt handling.
 677  ****************************************************************************/
 678 static int
 679 hdac_irq_alloc(struct hdac_softc *sc)
 680 {
 681         struct hdac_irq *irq;
 682         int result;
 683
 684         irq = &sc->irq;
 685         irq->irq_rid = 0x0;
 686
 687         if ((sc->quirks_off & HDAC_QUIRK_MSI) == 0 &&
 688             (result = pci_msi_count(sc->dev)) == 1 &&
 689             pci_alloc_msi(sc->dev, &result) == 0)
 690                 irq->irq_rid = 0x1;
 691
 692         irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
 693             &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE);
 694         if (irq->irq_res == NULL) {
 695                 device_printf(sc->dev, "%s: Unable to allocate irq\n",
 696                     __func__);
 697                 goto hdac_irq_alloc_fail;
 698         }
 699         result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV,
 700             NULL, hdac_intr_handler, sc, &irq->irq_handle);
 701         if (result != 0) {
 702                 device_printf(sc->dev,
 703                     "%s: Unable to setup interrupt handler (%x)\n",
 704                     __func__, result);
 705                 goto hdac_irq_alloc_fail;
 706         }
 707
 708         return (0);
 709
 710 hdac_irq_alloc_fail:
 711         hdac_irq_free(sc);
 712
 713         return (ENXIO);
 714 }
 715
 716 /****************************************************************************
 717  * void hdac_irq_free(struct hdac_softc *)
 718  *
 719  * Free up resources previously allocated by hdac_irq_alloc.
 720  ****************************************************************************/
 721 static void
 722 hdac_irq_free(struct hdac_softc *sc)
 723 {
 724         struct hdac_irq *irq;
 725
 726         irq = &sc->irq;
 727         if (irq->irq_res != NULL && irq->irq_handle != NULL)
 728                 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle);
 729         if (irq->irq_res != NULL)
 730                 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid,
 731                     irq->irq_res);
 732         if (irq->irq_rid == 0x1)
 733                 pci_release_msi(sc->dev);
 734         irq->irq_handle = NULL;
 735         irq->irq_res = NULL;
 736         irq->irq_rid = 0x0;
 737 }
 738
 739 /****************************************************************************
 740  * void hdac_corb_init(struct hdac_softc *)
 741  *
 742  * Initialize the corb registers for operations but do not start it up yet.
 743  * The CORB engine must not be running when this function is called.
 744  ****************************************************************************/
 745 static void
 746 hdac_corb_init(struct hdac_softc *sc)
 747 {
 748         uint8_t corbsize;
 749         uint64_t corbpaddr;
 750
 751         /* Setup the CORB size. */
 752         switch (sc->corb_size) {
 753         case 256:
 754                 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256);
 755                 break;
 756         case 16:
 757                 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16);
 758                 break;
 759         case 2:
 760                 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2);
 761                 break;
 762         default:
 763                 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size);
 764         }
 765         HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize);
 766
 767         /* Setup the CORB Address in the hdac */
 768         corbpaddr = (uint64_t)sc->corb_dma.dma_paddr;
 769         HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr);
 770         HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32));
 771
 772         /* Set the WP and RP */
 773         sc->corb_wp = 0;
 774         HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
 775         HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST);
 776         /*
 777          * The HDA specification indicates that the CORBRPRST bit will always
 778          * read as zero. Unfortunately, it seems that at least the 82801G
 779          * doesn't reset the bit to zero, which stalls the corb engine.
 780          * manually reset the bit to zero before continuing.
 781          */
 782         HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0);
 783
 784         /* Enable CORB error reporting */
 785 #if 0
 786         HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE);
 787 #endif
 788 }
 789
 790 /****************************************************************************
 791  * void hdac_rirb_init(struct hdac_softc *)
 792  *
 793  * Initialize the rirb registers for operations but do not start it up yet.
 794  * The RIRB engine must not be running when this function is called.
 795  ****************************************************************************/
 796 static void
 797 hdac_rirb_init(struct hdac_softc *sc)
 798 {
 799         uint8_t rirbsize;
 800         uint64_t rirbpaddr;
 801
 802         /* Setup the RIRB size. */
 803         switch (sc->rirb_size) {
 804         case 256:
 805                 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256);
 806                 break;
 807         case 16:
 808                 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16);
 809                 break;
 810         case 2:
 811                 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2);
 812                 break;
 813         default:
 814                 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size);
 815         }
 816         HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize);
 817
 818         /* Setup the RIRB Address in the hdac */
 819         rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr;
 820         HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr);
 821         HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32));
 822
 823         /* Setup the WP and RP */
 824         sc->rirb_rp = 0;
 825         HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST);
 826
 827         /* Setup the interrupt threshold */
 828         HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2);
 829
 830         /* Enable Overrun and response received reporting */
 831 #if 0
 832         HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL,
 833             HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL);
 834 #else
 835         HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL);
 836 #endif
 837
 838 #if 0
 839         /*
 840          * Make sure that the Host CPU cache doesn't contain any dirty
 841          * cache lines that falls in the rirb. If I understood correctly, it
 842          * should be sufficient to do this only once as the rirb is purely
 843          * read-only from now on.
 844          */
 845         bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
 846             BUS_DMASYNC_PREREAD);
 847 #endif
 848 }
 849
 850 /****************************************************************************
 851  * void hdac_corb_start(hdac_softc *)
 852  *
 853  * Startup the corb DMA engine
 854  ****************************************************************************/
 855 static void
 856 hdac_corb_start(struct hdac_softc *sc)
 857 {
 858         uint32_t corbctl;
 859
 860         corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL);
 861         corbctl |= HDAC_CORBCTL_CORBRUN;
 862         HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl);
 863 }
 864
 865 /****************************************************************************
 866  * void hdac_rirb_start(hdac_softc *)
 867  *
 868  * Startup the rirb DMA engine
 869  ****************************************************************************/
 870 static void
 871 hdac_rirb_start(struct hdac_softc *sc)
 872 {
 873         uint32_t rirbctl;
 874
 875         rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL);
 876         rirbctl |= HDAC_RIRBCTL_RIRBDMAEN;
 877         HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl);
 878 }
 879
 880 static int
 881 hdac_rirb_flush(struct hdac_softc *sc)
 882 {
 883         struct hdac_rirb *rirb_base, *rirb;
 884         nid_t cad;
 885         uint32_t resp;
 886         uint8_t rirbwp;
 887         int ret;
 888
 889         rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
 890         rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP);
 891 #if 0
 892         bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
 893             BUS_DMASYNC_POSTREAD);
 894 #endif
 895
 896         ret = 0;
 897         while (sc->rirb_rp != rirbwp) {
 898                 sc->rirb_rp++;
 899                 sc->rirb_rp %= sc->rirb_size;
 900                 rirb = &rirb_base[sc->rirb_rp];
 901                 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex);
 902                 resp = rirb->response;
 903                 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) {
 904                         sc->unsolq[sc->unsolq_wp++] = resp;
 905                         sc->unsolq_wp %= HDAC_UNSOLQ_MAX;
 906                         sc->unsolq[sc->unsolq_wp++] = cad;
 907                         sc->unsolq_wp %= HDAC_UNSOLQ_MAX;
 908                 } else if (sc->codecs[cad].pending <= 0) {
 909                         device_printf(sc->dev, "Unexpected unsolicited "
 910                             "response from address %d: %08x\n", cad, resp);
 911                 } else {
 912                         sc->codecs[cad].response = resp;
 913                         sc->codecs[cad].pending--;
 914                 }
 915                 ret++;
 916         }
 917         return (ret);
 918 }
 919
 920 static int
 921 hdac_unsolq_flush(struct hdac_softc *sc)
 922 {
 923         device_t child;
 924         nid_t cad;
 925         uint32_t resp;
 926         int ret = 0;
 927
 928         if (sc->unsolq_st == HDAC_UNSOLQ_READY) {
 929                 sc->unsolq_st = HDAC_UNSOLQ_BUSY;
 930                 while (sc->unsolq_rp != sc->unsolq_wp) {
 931                         resp = sc->unsolq[sc->unsolq_rp++];
 932                         sc->unsolq_rp %= HDAC_UNSOLQ_MAX;
 933                         cad = sc->unsolq[sc->unsolq_rp++];
 934                         sc->unsolq_rp %= HDAC_UNSOLQ_MAX;
 935                         if ((child = sc->codecs[cad].dev) != NULL)
 936                                 HDAC_UNSOL_INTR(child, resp);
 937                         ret++;
 938                 }
 939                 sc->unsolq_st = HDAC_UNSOLQ_READY;
 940         }
 941
 942         return (ret);
 943 }
 944
 945 /****************************************************************************
 946  * uint32_t hdac_command_sendone_internal
 947  *
 948  * Wrapper function that sends only one command to a given codec
 949  ****************************************************************************/
 950 static uint32_t
 951 hdac_send_command(struct hdac_softc *sc, nid_t cad, uint32_t verb)
 952 {
 953         int timeout;
 954         uint32_t *corb;
 955
 956         if (!hdac_lockowned(sc))
 957                 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n");
 958         verb &= ~HDA_CMD_CAD_MASK;
 959         verb |= ((uint32_t)cad) << HDA_CMD_CAD_SHIFT;
 960         sc->codecs[cad].response = HDA_INVALID;
 961
 962         sc->codecs[cad].pending++;
 963         sc->corb_wp++;
 964         sc->corb_wp %= sc->corb_size;
 965         corb = (uint32_t *)sc->corb_dma.dma_vaddr;
 966 #if 0
 967         bus_dmamap_sync(sc->corb_dma.dma_tag,
 968             sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE);
 969 #endif
 970         corb[sc->corb_wp] = verb;
 971 #if 0
 972         bus_dmamap_sync(sc->corb_dma.dma_tag,
 973             sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE);
 974 #endif
 975         HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
 976
 977         timeout = 10000;
 978         do {
 979                 if (hdac_rirb_flush(sc) == 0)
 980                         DELAY(10);
 981         } while (sc->codecs[cad].pending != 0 && --timeout);
 982
 983         if (sc->codecs[cad].pending != 0) {
 984                 device_printf(sc->dev, "Command timeout on address %d\n", cad);
 985                 sc->codecs[cad].pending = 0;
 986         }
 987
 988         if (sc->unsolq_rp != sc->unsolq_wp)
 989                 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task);
 990         return (sc->codecs[cad].response);
 991 }
 992
 993 /****************************************************************************
 994  * Device Methods
 995  ****************************************************************************/
 996
 997 /****************************************************************************
 998  * int hdac_probe(device_t)
 999  *
1000  * Probe for the presence of an hdac. If none is found, check for a generic
1001  * match using the subclass of the device.
1002  ****************************************************************************/
1003 static int
1004 hdac_probe(device_t dev)
1005 {
1006         int i, result;
1007         uint32_t model;
1008         uint16_t class, subclass;
1009         char desc[64];
1010
1011         model = (uint32_t)pci_get_device(dev) << 16;
1012         model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
1013         class = pci_get_class(dev);
1014         subclass = pci_get_subclass(dev);
1015
1016         bzero(desc, sizeof(desc));
1017         result = ENXIO;
1018         for (i = 0; i < HDAC_DEVICES_LEN; i++) {
1019                 if (hdac_devices[i].model == model) {
1020                         strlcpy(desc, hdac_devices[i].desc, sizeof(desc));
1021                         result = BUS_PROBE_DEFAULT;
1022                         break;
1023                 }
1024                 if (HDA_DEV_MATCH(hdac_devices[i].model, model) &&
1025                     class == PCIC_MULTIMEDIA &&
1026                     subclass == PCIS_MULTIMEDIA_HDA) {
1027                         snprintf(desc, sizeof(desc),
1028                             "%s (0x%04x)",
1029                             hdac_devices[i].desc, pci_get_device(dev));
1030                         result = BUS_PROBE_GENERIC;
1031                         break;
1032                 }
1033         }
1034         if (result == ENXIO && class == PCIC_MULTIMEDIA &&
1035             subclass == PCIS_MULTIMEDIA_HDA) {
1036                 snprintf(desc, sizeof(desc), "Generic (0x%08x)", model);
1037                 result = BUS_PROBE_GENERIC;
1038         }
1039         if (result != ENXIO) {
1040                 strlcat(desc, " HDA Controller", sizeof(desc));
1041                 device_set_desc_copy(dev, desc);
1042         }
1043
1044         return (result);
1045 }
1046
1047 static void
1048 hdac_unsolq_task(void *context, int pending)
1049 {
1050         struct hdac_softc *sc;
1051
1052         sc = (struct hdac_softc *)context;
1053
1054         hdac_lock(sc);
1055         hdac_unsolq_flush(sc);
1056         hdac_unlock(sc);
1057 }
1058
1059 /****************************************************************************
1060  * int hdac_attach(device_t)
1061  *
1062  * Attach the device into the kernel. Interrupts usually won't be enabled
1063  * when this function is called. Setup everything that doesn't require
1064  * interrupts and defer probing of codecs until interrupts are enabled.
1065  ****************************************************************************/
1066 static int
1067 hdac_attach(device_t dev)
1068 {
1069         struct hdac_softc *sc;
1070         int result;
1071         int i, devid = -1;
1072         uint32_t model;
1073         uint16_t class, subclass;
1074         uint16_t vendor;
1075         uint8_t v;
1076
1077         sc = device_get_softc(dev);
1078         HDA_BOOTVERBOSE(
1079                 device_printf(dev, "PCI card vendor: 0x%04x, device: 0x%04x\n",
1080                     pci_get_subvendor(dev), pci_get_subdevice(dev));
1081                 device_printf(dev, "HDA Driver Revision: %s\n",
1082                     HDA_DRV_TEST_REV);
1083         );
1084
1085         model = (uint32_t)pci_get_device(dev) << 16;
1086         model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
1087         class = pci_get_class(dev);
1088         subclass = pci_get_subclass(dev);
1089
1090         for (i = 0; i < HDAC_DEVICES_LEN; i++) {
1091                 if (hdac_devices[i].model == model) {
1092                         devid = i;
1093                         break;
1094                 }
1095                 if (HDA_DEV_MATCH(hdac_devices[i].model, model) &&
1096                     class == PCIC_MULTIMEDIA &&
1097                     subclass == PCIS_MULTIMEDIA_HDA) {
1098                         devid = i;
1099                         break;
1100                 }
1101         }
1102
1103         sc->lock = snd_mtxcreate(device_get_nameunit(dev), "HDA driver mutex");
1104         sc->dev = dev;
1105         TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc);
1106         callout_init(&sc->poll_callout, CALLOUT_MPSAFE);
1107         for (i = 0; i < HDAC_CODEC_MAX; i++)
1108                 sc->codecs[i].dev = NULL;
1109         if (devid >= 0) {
1110                 sc->quirks_on = hdac_devices[devid].quirks_on;
1111                 sc->quirks_off = hdac_devices[devid].quirks_off;
1112         } else {
1113                 sc->quirks_on = 0;
1114                 sc->quirks_off = 0;
1115         }
1116         if (resource_int_value(device_get_name(dev),
1117             device_get_unit(dev), "msi", &i) == 0) {
1118                 if (i == 0)
1119                         sc->quirks_off |= HDAC_QUIRK_MSI;
1120                 else {
1121                         sc->quirks_on |= HDAC_QUIRK_MSI;
1122                         sc->quirks_off |= ~HDAC_QUIRK_MSI;
1123                 }
1124         }
1125         hdac_config_fetch(sc, &sc->quirks_on, &sc->quirks_off);
1126         HDA_BOOTVERBOSE(
1127                 device_printf(sc->dev,
1128                     "Config options: on=0x%08x off=0x%08x\n",
1129                     sc->quirks_on, sc->quirks_off);
1130         );
1131         sc->poll_ival = hz;
1132         if (resource_int_value(device_get_name(dev),
1133             device_get_unit(dev), "polling", &i) == 0 && i != 0)
1134                 sc->polling = 1;
1135         else
1136                 sc->polling = 0;
1137
1138         pci_enable_busmaster(dev);
1139
1140         vendor = pci_get_vendor(dev);
1141         if (vendor == INTEL_VENDORID) {
1142                 /* TCSEL -> TC0 */
1143                 v = pci_read_config(dev, 0x44, 1);
1144                 pci_write_config(dev, 0x44, v & 0xf8, 1);
1145                 HDA_BOOTHVERBOSE(
1146                         device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v,
1147                             pci_read_config(dev, 0x44, 1));
1148                 );
1149         }
1150
1151 #if defined(__i386__) || defined(__amd64__)
1152         sc->flags |= HDAC_F_DMA_NOCACHE;
1153
1154         if (resource_int_value(device_get_name(dev),
1155             device_get_unit(dev), "snoop", &i) == 0 && i != 0) {
1156 #else
1157         sc->flags &= ~HDAC_F_DMA_NOCACHE;
1158 #endif
1159                 /*
1160                  * Try to enable PCIe snoop to avoid messing around with
1161                  * uncacheable DMA attribute. Since PCIe snoop register
1162                  * config is pretty much vendor specific, there are no
1163                  * general solutions on how to enable it, forcing us (even
1164                  * Microsoft) to enable uncacheable or write combined DMA
1165                  * by default.
1166                  *
1167                  * http://msdn2.microsoft.com/en-us/library/ms790324.aspx
1168                  */
1169                 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) {
1170                         if (hdac_pcie_snoop[i].vendor != vendor)
1171                                 continue;
1172                         sc->flags &= ~HDAC_F_DMA_NOCACHE;
1173                         if (hdac_pcie_snoop[i].reg == 0x00)
1174                                 break;
1175                         v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1);
1176                         if ((v & hdac_pcie_snoop[i].enable) ==
1177                             hdac_pcie_snoop[i].enable)
1178                                 break;
1179                         v &= hdac_pcie_snoop[i].mask;
1180                         v |= hdac_pcie_snoop[i].enable;
1181                         pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1);
1182                         v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1);
1183                         if ((v & hdac_pcie_snoop[i].enable) !=
1184                             hdac_pcie_snoop[i].enable) {
1185                                 HDA_BOOTVERBOSE(
1186                                         device_printf(dev,
1187                                             "WARNING: Failed to enable PCIe "
1188                                             "snoop!\n");
1189                                 );
1190 #if defined(__i386__) || defined(__amd64__)
1191                                 sc->flags |= HDAC_F_DMA_NOCACHE;
1192 #endif
1193                         }
1194                         break;
1195                 }
1196 #if defined(__i386__) || defined(__amd64__)
1197         }
1198 #endif
1199
1200         HDA_BOOTHVERBOSE(
1201                 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n",
1202                     (sc->flags & HDAC_F_DMA_NOCACHE) ?
1203                     "Uncacheable" : "PCIe snoop", vendor);
1204         );
1205
1206         /* Allocate resources */
1207         result = hdac_mem_alloc(sc);
1208         if (result != 0)
1209                 goto hdac_attach_fail;
1210         result = hdac_irq_alloc(sc);
1211         if (result != 0)
1212                 goto hdac_attach_fail;
1213
1214         /* Get Capabilities */
1215         result = hdac_get_capabilities(sc);
1216         if (result != 0)
1217                 goto hdac_attach_fail;
1218
1219         /* Allocate CORB, RIRB, POS and BDLs dma memory */
1220         result = hdac_dma_alloc(sc, &sc->corb_dma,
1221             sc->corb_size * sizeof(uint32_t));
1222         if (result != 0)
1223                 goto hdac_attach_fail;
1224         result = hdac_dma_alloc(sc, &sc->rirb_dma,
1225             sc->rirb_size * sizeof(struct hdac_rirb));
1226         if (result != 0)
1227                 goto hdac_attach_fail;
1228         sc->streams = malloc(sizeof(struct hdac_stream) * sc->num_ss,
1229             M_HDAC, M_ZERO | M_WAITOK);
1230         for (i = 0; i < sc->num_ss; i++) {
1231                 result = hdac_dma_alloc(sc, &sc->streams[i].bdl,
1232                     sizeof(struct hdac_bdle) * HDA_BDL_MAX);
1233                 if (result != 0)
1234                         goto hdac_attach_fail;
1235         }
1236         if (sc->quirks_on & HDAC_QUIRK_DMAPOS) {
1237                 if (hdac_dma_alloc(sc, &sc->pos_dma, (sc->num_ss) * 8) != 0) {
1238                         HDA_BOOTVERBOSE(
1239                                 device_printf(dev, "Failed to "
1240                                     "allocate DMA pos buffer "
1241                                     "(non-fatal)\n");
1242                         );
1243                 } else {
1244                         uint64_t addr = sc->pos_dma.dma_paddr;
1245
1246                         HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, addr >> 32);
1247                         HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE,
1248                             (addr & HDAC_DPLBASE_DPLBASE_MASK) |
1249                             HDAC_DPLBASE_DPLBASE_DMAPBE);
1250                 }
1251         }
1252
1253         result = bus_dma_tag_create(
1254             bus_get_dma_tag(sc->dev),           /* parent */
1255             HDA_DMA_ALIGNMENT,                  /* alignment */
1256             0,                                  /* boundary */
1257             (sc->support_64bit) ? BUS_SPACE_MAXADDR :
1258                 BUS_SPACE_MAXADDR_32BIT,        /* lowaddr */
1259             BUS_SPACE_MAXADDR,                  /* highaddr */
1260             NULL,                               /* filtfunc */
1261             NULL,                               /* fistfuncarg */
1262             HDA_BUFSZ_MAX,                      /* maxsize */
1263             1,                                  /* nsegments */
1264             HDA_BUFSZ_MAX,                      /* maxsegsz */
1265             0,                                  /* flags */
1266             NULL,                               /* lockfunc */
1267             NULL,                               /* lockfuncarg */
1268             &sc->chan_dmat);                    /* dmat */
1269         if (result != 0) {
1270                 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n",
1271                      __func__, result);
1272                 goto hdac_attach_fail;
1273         }
1274
1275         /* Quiesce everything */
1276         HDA_BOOTHVERBOSE(
1277                 device_printf(dev, "Reset controller...\n");
1278         );
1279         hdac_reset(sc, 1);
1280
1281         /* Initialize the CORB and RIRB */
1282         hdac_corb_init(sc);
1283         hdac_rirb_init(sc);
1284
1285         /* Defer remaining of initialization until interrupts are enabled */
1286         sc->intrhook.ich_func = hdac_attach2;
1287         sc->intrhook.ich_arg = (void *)sc;
1288         if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) {
1289                 sc->intrhook.ich_func = NULL;
1290                 hdac_attach2((void *)sc);
1291         }
1292
1293         return (0);
1294
1295 hdac_attach_fail:
1296         hdac_irq_free(sc);
1297         for (i = 0; i < sc->num_ss; i++)
1298                 hdac_dma_free(sc, &sc->streams[i].bdl);
1299         free(sc->streams, M_HDAC);
1300         hdac_dma_free(sc, &sc->rirb_dma);
1301         hdac_dma_free(sc, &sc->corb_dma);
1302         hdac_mem_free(sc);
1303         snd_mtxfree(sc->lock);
1304
1305         return (ENXIO);
1306 }
1307
1308 static int
1309 sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS)
1310 {
1311         struct hdac_softc *sc;
1312         device_t *devlist;
1313         device_t dev;
1314         int devcount, i, err, val;
1315
1316         dev = oidp->oid_arg1;
1317         sc = device_get_softc(dev);
1318         if (sc == NULL)
1319                 return (EINVAL);
1320         val = 0;
1321         err = sysctl_handle_int(oidp, &val, 0, req);
1322         if (err != 0 || req->newptr == NULL || val == 0)
1323                 return (err);
1324
1325         /* XXX: Temporary. For debugging. */
1326         if (val == 100) {
1327                 hdac_suspend(dev);
1328                 return (0);
1329         } else if (val == 101) {
1330                 hdac_resume(dev);
1331                 return (0);
1332         }
1333
1334         if ((err = device_get_children(dev, &devlist, &devcount)) != 0)
1335                 return (err);
1336         hdac_lock(sc);
1337         for (i = 0; i < devcount; i++)
1338                 HDAC_PINDUMP(devlist[i]);
1339         hdac_unlock(sc);
1340         free(devlist, M_TEMP);
1341         return (0);
1342 }
1343
1344 static int
1345 hdac_mdata_rate(uint16_t fmt)
1346 {
1347         static const int mbits[8] = { 8, 16, 32, 32, 32, 32, 32, 32 };
1348         int rate, bits;
1349
1350         if (fmt & (1 << 14))
1351                 rate = 44100;
1352         else
1353                 rate = 48000;
1354         rate *= ((fmt >> 11) & 0x07) + 1;
1355         rate /= ((fmt >> 8) & 0x07) + 1;
1356         bits = mbits[(fmt >> 4) & 0x03];
1357         bits *= (fmt & 0x0f) + 1;
1358         return (rate * bits);
1359 }
1360
1361 static int
1362 hdac_bdata_rate(uint16_t fmt, int output)
1363 {
1364         static const int bbits[8] = { 8, 16, 20, 24, 32, 32, 32, 32 };
1365         int rate, bits;
1366
1367         rate = 48000;
1368         rate *= ((fmt >> 11) & 0x07) + 1;
1369         bits = bbits[(fmt >> 4) & 0x03];
1370         bits *= (fmt & 0x0f) + 1;
1371         if (!output)
1372                 bits = ((bits + 7) & ~0x07) + 10;
1373         return (rate * bits);
1374 }
1375
1376 static void
1377 hdac_poll_reinit(struct hdac_softc *sc)
1378 {
1379         int i, pollticks, min = 1000000;
1380         struct hdac_stream *s;
1381
1382         if (sc->polling == 0)
1383                 return;
1384         if (sc->unsol_registered > 0)
1385                 min = hz / 2;
1386         for (i = 0; i < sc->num_ss; i++) {
1387                 s = &sc->streams[i];
1388                 if (s->running == 0)
1389                         continue;
1390                 pollticks = ((uint64_t)hz * s->blksz) /
1391                     (hdac_mdata_rate(s->format) / 8);
1392                 pollticks >>= 1;
1393                 if (pollticks > hz)
1394                         pollticks = hz;
1395                 if (pollticks < 1) {
1396                         HDA_BOOTVERBOSE(
1397                                 device_printf(sc->dev,
1398                                     "poll interval < 1 tick !\n");
1399                         );
1400                         pollticks = 1;
1401                 }
1402                 if (min > pollticks)
1403                         min = pollticks;
1404         }
1405         HDA_BOOTVERBOSE(
1406                 device_printf(sc->dev,
1407                     "poll interval %d -> %d ticks\n",
1408                     sc->poll_ival, min);
1409         );
1410         sc->poll_ival = min;
1411         if (min == 1000000)
1412                 callout_stop(&sc->poll_callout);
1413         else
1414                 callout_reset(&sc->poll_callout, 1, hdac_poll_callback, sc);
1415 }
1416
1417 static int
1418 sysctl_hdac_polling(SYSCTL_HANDLER_ARGS)
1419 {
1420         struct hdac_softc *sc;
1421         device_t dev;
1422         uint32_t ctl;
1423         int err, val;
1424
1425         dev = oidp->oid_arg1;
1426         sc = device_get_softc(dev);
1427         if (sc == NULL)
1428                 return (EINVAL);
1429         hdac_lock(sc);
1430         val = sc->polling;
1431         hdac_unlock(sc);
1432         err = sysctl_handle_int(oidp, &val, 0, req);
1433
1434         if (err != 0 || req->newptr == NULL)
1435                 return (err);
1436         if (val < 0 || val > 1)
1437                 return (EINVAL);
1438
1439         hdac_lock(sc);
1440         if (val != sc->polling) {
1441                 if (val == 0) {
1442                         callout_stop(&sc->poll_callout);
1443                         hdac_unlock(sc);
1444                         callout_drain(&sc->poll_callout);
1445                         hdac_lock(sc);
1446                         sc->polling = 0;
1447                         ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1448                         ctl |= HDAC_INTCTL_GIE;
1449                         HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1450                 } else {
1451                         ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1452                         ctl &= ~HDAC_INTCTL_GIE;
1453                         HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1454                         sc->polling = 1;
1455                         hdac_poll_reinit(sc);
1456                 }
1457         }
1458         hdac_unlock(sc);
1459
1460         return (err);
1461 }
1462
1463 static void
1464 hdac_attach2(void *arg)
1465 {
1466         struct hdac_softc *sc;
1467         device_t child;
1468         uint32_t vendorid, revisionid;
1469         int i;
1470         uint16_t statests;
1471
1472         sc = (struct hdac_softc *)arg;
1473
1474         hdac_lock(sc);
1475
1476         /* Remove ourselves from the config hooks */
1477         if (sc->intrhook.ich_func != NULL) {
1478                 config_intrhook_disestablish(&sc->intrhook);
1479                 sc->intrhook.ich_func = NULL;
1480         }
1481
1482         HDA_BOOTHVERBOSE(
1483                 device_printf(sc->dev, "Starting CORB Engine...\n");
1484         );
1485         hdac_corb_start(sc);
1486         HDA_BOOTHVERBOSE(
1487                 device_printf(sc->dev, "Starting RIRB Engine...\n");
1488         );
1489         hdac_rirb_start(sc);
1490         HDA_BOOTHVERBOSE(
1491                 device_printf(sc->dev,
1492                     "Enabling controller interrupt...\n");
1493         );
1494         HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) |
1495             HDAC_GCTL_UNSOL);
1496         if (sc->polling == 0) {
1497                 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL,
1498                     HDAC_INTCTL_CIE | HDAC_INTCTL_GIE);
1499         }
1500         DELAY(1000);
1501
1502         HDA_BOOTHVERBOSE(
1503                 device_printf(sc->dev, "Scanning HDA codecs ...\n");
1504         );
1505         statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS);
1506         hdac_unlock(sc);
1507         for (i = 0; i < HDAC_CODEC_MAX; i++) {
1508                 if (HDAC_STATESTS_SDIWAKE(statests, i)) {
1509                         HDA_BOOTHVERBOSE(
1510                                 device_printf(sc->dev,
1511                                     "Found CODEC at address %d\n", i);
1512                         );
1513                         hdac_lock(sc);
1514                         vendorid = hdac_send_command(sc, i,
1515                             HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_VENDOR_ID));
1516                         revisionid = hdac_send_command(sc, i,
1517                             HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_REVISION_ID));
1518                         hdac_unlock(sc);
1519                         if (vendorid == HDA_INVALID &&
1520                             revisionid == HDA_INVALID) {
1521                                 device_printf(sc->dev,
1522                                     "CODEC is not responding!\n");
1523                                 continue;
1524                         }
1525                         sc->codecs[i].vendor_id =
1526                             HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid);
1527                         sc->codecs[i].device_id =
1528                             HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid);
1529                         sc->codecs[i].revision_id =
1530                             HDA_PARAM_REVISION_ID_REVISION_ID(revisionid);
1531                         sc->codecs[i].stepping_id =
1532                             HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid);
1533                         child = device_add_child(sc->dev, "hdacc", -1);
1534                         if (child == NULL) {
1535                                 device_printf(sc->dev,
1536                                     "Failed to add CODEC device\n");
1537                                 continue;
1538                         }
1539                         device_set_ivars(child, (void *)(intptr_t)i);
1540                         sc->codecs[i].dev = child;
1541                 }
1542         }
1543         bus_generic_attach(sc->dev);
1544
1545         SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev),
1546             SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO,
1547             "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev),
1548             sysctl_hdac_pindump, "I", "Dump pin states/data");
1549         SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev),
1550             SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO,
1551             "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev),
1552             sysctl_hdac_polling, "I", "Enable polling mode");
1553 }
1554
1555 /****************************************************************************
1556  * int hdac_suspend(device_t)
1557  *
1558  * Suspend and power down HDA bus and codecs.
1559  ****************************************************************************/
1560 static int
1561 hdac_suspend(device_t dev)
1562 {
1563         struct hdac_softc *sc = device_get_softc(dev);
1564
1565         HDA_BOOTHVERBOSE(
1566                 device_printf(dev, "Suspend...\n");
1567         );
1568         bus_generic_suspend(dev);
1569
1570         hdac_lock(sc);
1571         HDA_BOOTHVERBOSE(
1572                 device_printf(dev, "Reset controller...\n");
1573         );
1574         callout_stop(&sc->poll_callout);
1575         hdac_reset(sc, 0);
1576         hdac_unlock(sc);
1577         callout_drain(&sc->poll_callout);
1578         taskqueue_drain(taskqueue_thread, &sc->unsolq_task);
1579         HDA_BOOTHVERBOSE(
1580                 device_printf(dev, "Suspend done\n");
1581         );
1582         return (0);
1583 }
1584
1585 /****************************************************************************
1586  * int hdac_resume(device_t)
1587  *
1588  * Powerup and restore HDA bus and codecs state.
1589  ****************************************************************************/
1590 static int
1591 hdac_resume(device_t dev)
1592 {
1593         struct hdac_softc *sc = device_get_softc(dev);
1594         int error;
1595
1596         HDA_BOOTHVERBOSE(
1597                 device_printf(dev, "Resume...\n");
1598         );
1599         hdac_lock(sc);
1600
1601         /* Quiesce everything */
1602         HDA_BOOTHVERBOSE(
1603                 device_printf(dev, "Reset controller...\n");
1604         );
1605         hdac_reset(sc, 1);
1606
1607         /* Initialize the CORB and RIRB */
1608         hdac_corb_init(sc);
1609         hdac_rirb_init(sc);
1610
1611         HDA_BOOTHVERBOSE(
1612                 device_printf(dev, "Starting CORB Engine...\n");
1613         );
1614         hdac_corb_start(sc);
1615         HDA_BOOTHVERBOSE(
1616                 device_printf(dev, "Starting RIRB Engine...\n");
1617         );
1618         hdac_rirb_start(sc);
1619         HDA_BOOTHVERBOSE(
1620                 device_printf(dev, "Enabling controller interrupt...\n");
1621         );
1622         HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) |
1623             HDAC_GCTL_UNSOL);
1624         HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, HDAC_INTCTL_CIE | HDAC_INTCTL_GIE);
1625         DELAY(1000);
1626         hdac_poll_reinit(sc);
1627         hdac_unlock(sc);
1628
1629         error = bus_generic_resume(dev);
1630         HDA_BOOTHVERBOSE(
1631                 device_printf(dev, "Resume done\n");
1632         );
1633         return (error);
1634 }
1635
1636 /****************************************************************************
1637  * int hdac_detach(device_t)
1638  *
1639  * Detach and free up resources utilized by the hdac device.
1640  ****************************************************************************/
1641 static int
1642 hdac_detach(device_t dev)
1643 {
1644         struct hdac_softc *sc = device_get_softc(dev);
1645         device_t *devlist;
1646         int cad, i, devcount, error;
1647
1648         if ((error = device_get_children(dev, &devlist, &devcount)) != 0)
1649                 return (error);
1650         for (i = 0; i < devcount; i++) {
1651                 cad = (intptr_t)device_get_ivars(devlist[i]);
1652                 if ((error = device_delete_child(dev, devlist[i])) != 0) {
1653                         free(devlist, M_TEMP);
1654                         return (error);
1655                 }
1656                 sc->codecs[cad].dev = NULL;
1657         }
1658         free(devlist, M_TEMP);
1659
1660         hdac_lock(sc);
1661         hdac_reset(sc, 0);
1662         hdac_unlock(sc);
1663         taskqueue_drain(taskqueue_thread, &sc->unsolq_task);
1664         hdac_irq_free(sc);
1665
1666         for (i = 0; i < sc->num_ss; i++)
1667                 hdac_dma_free(sc, &sc->streams[i].bdl);
1668         free(sc->streams, M_HDAC);
1669         hdac_dma_free(sc, &sc->pos_dma);
1670         hdac_dma_free(sc, &sc->rirb_dma);
1671         hdac_dma_free(sc, &sc->corb_dma);
1672         if (sc->chan_dmat != NULL) {
1673                 bus_dma_tag_destroy(sc->chan_dmat);
1674                 sc->chan_dmat = NULL;
1675         }
1676         hdac_mem_free(sc);
1677         snd_mtxfree(sc->lock);
1678         return (0);
1679 }
1680
1681 static bus_dma_tag_t
1682 hdac_get_dma_tag(device_t dev, device_t child)
1683 {
1684         struct hdac_softc *sc = device_get_softc(dev);
1685
1686         return (sc->chan_dmat);
1687 }
1688
1689 static int
1690 hdac_print_child(device_t dev, device_t child)
1691 {
1692         int retval;
1693
1694         retval = bus_print_child_header(dev, child);
1695         retval += printf(" at cad %d",
1696             (int)(intptr_t)device_get_ivars(child));
1697         retval += bus_print_child_footer(dev, child);
1698
1699         return (retval);
1700 }
1701
1702 static int
1703 hdac_child_location_str(device_t dev, device_t child, char *buf,
1704     size_t buflen)
1705 {
1706
1707         snprintf(buf, buflen, "cad=%d",
1708             (int)(intptr_t)device_get_ivars(child));
1709         return (0);
1710 }
1711
1712 static int
1713 hdac_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
1714     size_t buflen)
1715 {
1716         struct hdac_softc *sc = device_get_softc(dev);
1717         nid_t cad = (uintptr_t)device_get_ivars(child);
1718
1719         snprintf(buf, buflen, "vendor=0x%04x device=0x%04x revision=0x%02x "
1720             "stepping=0x%02x",
1721             sc->codecs[cad].vendor_id, sc->codecs[cad].device_id,
1722             sc->codecs[cad].revision_id, sc->codecs[cad].stepping_id);
1723         return (0);
1724 }
1725
1726 static int
1727 hdac_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1728 {
1729         struct hdac_softc *sc = device_get_softc(dev);
1730         nid_t cad = (uintptr_t)device_get_ivars(child);
1731
1732         switch (which) {
1733         case HDA_IVAR_CODEC_ID:
1734                 *result = cad;
1735                 break;
1736         case HDA_IVAR_VENDOR_ID:
1737                 *result = sc->codecs[cad].vendor_id;
1738                 break;
1739         case HDA_IVAR_DEVICE_ID:
1740                 *result = sc->codecs[cad].device_id;
1741                 break;
1742         case HDA_IVAR_REVISION_ID:
1743                 *result = sc->codecs[cad].revision_id;
1744                 break;
1745         case HDA_IVAR_STEPPING_ID:
1746                 *result = sc->codecs[cad].stepping_id;
1747                 break;
1748         case HDA_IVAR_SUBVENDOR_ID:
1749                 *result = pci_get_subvendor(dev);
1750                 break;
1751         case HDA_IVAR_SUBDEVICE_ID:
1752                 *result = pci_get_subdevice(dev);
1753                 break;
1754         case HDA_IVAR_DMA_NOCACHE:
1755                 *result = (sc->flags & HDAC_F_DMA_NOCACHE) != 0;
1756                 break;
1757         default:
1758                 return (ENOENT);
1759         }
1760         return (0);
1761 }
1762
1763 static struct mtx *
1764 hdac_get_mtx(device_t dev, device_t child)
1765 {
1766         struct hdac_softc *sc = device_get_softc(dev);
1767
1768         return (sc->lock);
1769 }
1770
1771 static uint32_t
1772 hdac_codec_command(device_t dev, device_t child, uint32_t verb)
1773 {
1774
1775         return (hdac_send_command(device_get_softc(dev),
1776             (intptr_t)device_get_ivars(child), verb));
1777 }
1778
1779 static int
1780 hdac_find_stream(struct hdac_softc *sc, int dir, int stream)
1781 {
1782         int i, ss;
1783
1784         ss = -1;
1785         /* Allocate ISS/BSS first. */
1786         if (dir == 0) {
1787                 for (i = 0; i < sc->num_iss; i++) {
1788                         if (sc->streams[i].stream == stream) {
1789                                 ss = i;
1790                                 break;
1791                         }
1792                 }
1793         } else {
1794                 for (i = 0; i < sc->num_oss; i++) {
1795                         if (sc->streams[i + sc->num_iss].stream == stream) {
1796                                 ss = i + sc->num_iss;
1797                                 break;
1798                         }
1799                 }
1800         }
1801         /* Fallback to BSS. */
1802         if (ss == -1) {
1803                 for (i = 0; i < sc->num_bss; i++) {
1804                         if (sc->streams[i + sc->num_iss + sc->num_oss].stream
1805                             == stream) {
1806                                 ss = i + sc->num_iss + sc->num_oss;
1807                                 break;
1808                         }
1809                 }
1810         }
1811         return (ss);
1812 }
1813
1814 static int
1815 hdac_stream_alloc(device_t dev, device_t child, int dir, int format, int stripe,
1816     uint32_t **dmapos)
1817 {
1818         struct hdac_softc *sc = device_get_softc(dev);
1819         nid_t cad = (uintptr_t)device_get_ivars(child);
1820         int stream, ss, bw, maxbw, prevbw;
1821
1822         /* Look for empty stream. */
1823         ss = hdac_find_stream(sc, dir, 0);
1824
1825         /* Return if found nothing. */
1826         if (ss < 0)
1827                 return (0);
1828
1829         /* Check bus bandwidth. */
1830         bw = hdac_bdata_rate(format, dir);
1831         if (dir == 1) {
1832                 bw *= 1 << (sc->num_sdo - stripe);
1833                 prevbw = sc->sdo_bw_used;
1834                 maxbw = 48000 * 960 * (1 << sc->num_sdo);
1835         } else {
1836                 prevbw = sc->codecs[cad].sdi_bw_used;
1837                 maxbw = 48000 * 464;
1838         }
1839         HDA_BOOTHVERBOSE(
1840                 device_printf(dev, "%dKbps of %dKbps bandwidth used%s\n",
1841                     (bw + prevbw) / 1000, maxbw / 1000,
1842                     bw + prevbw > maxbw ? " -- OVERFLOW!" : "");
1843         );
1844         if (bw + prevbw > maxbw)
1845                 return (0);
1846         if (dir == 1)
1847                 sc->sdo_bw_used += bw;
1848         else
1849                 sc->codecs[cad].sdi_bw_used += bw;
1850
1851         /* Allocate stream number */
1852         if (ss >= sc->num_iss + sc->num_oss)
1853                 stream = 15 - (ss - sc->num_iss + sc->num_oss);
1854         else if (ss >= sc->num_iss)
1855                 stream = ss - sc->num_iss + 1;
1856         else
1857                 stream = ss + 1;
1858
1859         sc->streams[ss].dev = child;
1860         sc->streams[ss].dir = dir;
1861         sc->streams[ss].stream = stream;
1862         sc->streams[ss].bw = bw;
1863         sc->streams[ss].format = format;
1864         sc->streams[ss].stripe = stripe;
1865         if (dmapos != NULL) {
1866                 if (sc->pos_dma.dma_vaddr != NULL)
1867                         *dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + ss * 8);
1868                 else
1869                         *dmapos = NULL;
1870         }
1871         return (stream);
1872 }
1873
1874 static void
1875 hdac_stream_free(device_t dev, device_t child, int dir, int stream)
1876 {
1877         struct hdac_softc *sc = device_get_softc(dev);
1878         nid_t cad = (uintptr_t)device_get_ivars(child);
1879         int ss;
1880
1881         ss = hdac_find_stream(sc, dir, stream);
1882         KASSERT(ss >= 0,
1883             ("Free for not allocated stream (%d/%d)\n", dir, stream));
1884         if (dir == 1)
1885                 sc->sdo_bw_used -= sc->streams[ss].bw;
1886         else
1887                 sc->codecs[cad].sdi_bw_used -= sc->streams[ss].bw;
1888         sc->streams[ss].stream = 0;
1889         sc->streams[ss].dev = NULL;
1890 }
1891
1892 static int
1893 hdac_stream_start(device_t dev, device_t child,
1894     int dir, int stream, bus_addr_t buf, int blksz, int blkcnt)
1895 {
1896         struct hdac_softc *sc = device_get_softc(dev);
1897         struct hdac_bdle *bdle;
1898         uint64_t addr;
1899         int i, ss, off;
1900         uint32_t ctl;
1901
1902         ss = hdac_find_stream(sc, dir, stream);
1903         KASSERT(ss >= 0,
1904             ("Start for not allocated stream (%d/%d)\n", dir, stream));
1905
1906         addr = (uint64_t)buf;
1907         bdle = (struct hdac_bdle *)sc->streams[ss].bdl.dma_vaddr;
1908         for (i = 0; i < blkcnt; i++, bdle++) {
1909                 bdle->addrl = (uint32_t)addr;
1910                 bdle->addrh = (uint32_t)(addr >> 32);
1911                 bdle->len = blksz;
1912                 bdle->ioc = 1;
1913                 addr += blksz;
1914         }
1915
1916         off = ss << 5;
1917         HDAC_WRITE_4(&sc->mem, off + HDAC_SDCBL, blksz * blkcnt);
1918         HDAC_WRITE_2(&sc->mem, off + HDAC_SDLVI, blkcnt - 1);
1919         addr = sc->streams[ss].bdl.dma_paddr;
1920         HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPL, (uint32_t)addr);
1921         HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPU, (uint32_t)(addr >> 32));
1922
1923         ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL2);
1924         if (dir)
1925                 ctl |= HDAC_SDCTL2_DIR;
1926         else
1927                 ctl &= ~HDAC_SDCTL2_DIR;
1928         ctl &= ~HDAC_SDCTL2_STRM_MASK;
1929         ctl |= stream << HDAC_SDCTL2_STRM_SHIFT;
1930         ctl &= ~HDAC_SDCTL2_STRIPE_MASK;
1931         ctl |= sc->streams[ss].stripe << HDAC_SDCTL2_STRIPE_SHIFT;
1932         HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL2, ctl);
1933
1934         HDAC_WRITE_2(&sc->mem, off + HDAC_SDFMT, sc->streams[ss].format);
1935
1936         ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1937         ctl |= 1 << ss;
1938         HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1939
1940         HDAC_WRITE_1(&sc->mem, off + HDAC_SDSTS,
1941             HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS);
1942         ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
1943         ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
1944             HDAC_SDCTL_RUN;
1945         HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
1946
1947         sc->streams[ss].blksz = blksz;
1948         sc->streams[ss].running = 1;
1949         hdac_poll_reinit(sc);
1950         return (0);
1951 }
1952
1953 static void
1954 hdac_stream_stop(device_t dev, device_t child, int dir, int stream)
1955 {
1956         struct hdac_softc *sc = device_get_softc(dev);
1957         int ss, off;
1958         uint32_t ctl;
1959
1960         ss = hdac_find_stream(sc, dir, stream);
1961         KASSERT(ss >= 0,
1962             ("Stop for not allocated stream (%d/%d)\n", dir, stream));
1963
1964         off = ss << 5;
1965         ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
1966         ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
1967             HDAC_SDCTL_RUN);
1968         HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
1969
1970         ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1971         ctl &= ~(1 << ss);
1972         HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1973
1974         sc->streams[ss].running = 0;
1975         hdac_poll_reinit(sc);
1976 }
1977
1978 static void
1979 hdac_stream_reset(device_t dev, device_t child, int dir, int stream)
1980 {
1981         struct hdac_softc *sc = device_get_softc(dev);
1982         int timeout = 1000;
1983         int to = timeout;
1984         int ss, off;
1985         uint32_t ctl;
1986
1987         ss = hdac_find_stream(sc, dir, stream);
1988         KASSERT(ss >= 0,
1989             ("Reset for not allocated stream (%d/%d)\n", dir, stream));
1990
1991         off = ss << 5;
1992         ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
1993         ctl |= HDAC_SDCTL_SRST;
1994         HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
1995         do {
1996                 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
1997                 if (ctl & HDAC_SDCTL_SRST)
1998                         break;
1999                 DELAY(10);
2000         } while (--to);
2001         if (!(ctl & HDAC_SDCTL_SRST))
2002                 device_printf(dev, "Reset setting timeout\n");
2003         ctl &= ~HDAC_SDCTL_SRST;
2004         HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
2005         to = timeout;
2006         do {
2007                 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
2008                 if (!(ctl & HDAC_SDCTL_SRST))
2009                         break;
2010                 DELAY(10);
2011         } while (--to);
2012         if (ctl & HDAC_SDCTL_SRST)
2013                 device_printf(dev, "Reset timeout!\n");
2014 }
2015
2016 static uint32_t
2017 hdac_stream_getptr(device_t dev, device_t child, int dir, int stream)
2018 {
2019         struct hdac_softc *sc = device_get_softc(dev);
2020         int ss, off;
2021
2022         ss = hdac_find_stream(sc, dir, stream);
2023         KASSERT(ss >= 0,
2024             ("Reset for not allocated stream (%d/%d)\n", dir, stream));
2025
2026         off = ss << 5;
2027         return (HDAC_READ_4(&sc->mem, off + HDAC_SDLPIB));
2028 }
2029
2030 static int
2031 hdac_unsol_alloc(device_t dev, device_t child, int tag)
2032 {
2033         struct hdac_softc *sc = device_get_softc(dev);
2034
2035         sc->unsol_registered++;
2036         hdac_poll_reinit(sc);
2037         return (tag);
2038 }
2039
2040 static void
2041 hdac_unsol_free(device_t dev, device_t child, int tag)
2042 {
2043         struct hdac_softc *sc = device_get_softc(dev);
2044
2045         sc->unsol_registered--;
2046         hdac_poll_reinit(sc);
2047 }
2048
2049 static device_method_t hdac_methods[] = {
2050         /* device interface */
2051         DEVMETHOD(device_probe,         hdac_probe),
2052         DEVMETHOD(device_attach,        hdac_attach),
2053         DEVMETHOD(device_detach,        hdac_detach),
2054         DEVMETHOD(device_suspend,       hdac_suspend),
2055         DEVMETHOD(device_resume,        hdac_resume),
2056         /* Bus interface */
2057         DEVMETHOD(bus_get_dma_tag,      hdac_get_dma_tag),
2058         DEVMETHOD(bus_print_child,      hdac_print_child),
2059         DEVMETHOD(bus_child_location_str, hdac_child_location_str),
2060         DEVMETHOD(bus_child_pnpinfo_str, hdac_child_pnpinfo_str_method),
2061         DEVMETHOD(bus_read_ivar,        hdac_read_ivar),
2062         DEVMETHOD(hdac_get_mtx,         hdac_get_mtx),
2063         DEVMETHOD(hdac_codec_command,   hdac_codec_command),
2064         DEVMETHOD(hdac_stream_alloc,    hdac_stream_alloc),
2065         DEVMETHOD(hdac_stream_free,     hdac_stream_free),
2066         DEVMETHOD(hdac_stream_start,    hdac_stream_start),
2067         DEVMETHOD(hdac_stream_stop,     hdac_stream_stop),
2068         DEVMETHOD(hdac_stream_reset,    hdac_stream_reset),
2069         DEVMETHOD(hdac_stream_getptr,   hdac_stream_getptr),
2070         DEVMETHOD(hdac_unsol_alloc,     hdac_unsol_alloc),
2071         DEVMETHOD(hdac_unsol_free,      hdac_unsol_free),
2072         { 0, 0 }
2073 };
2074
2075 static driver_t hdac_driver = {
2076         "hdac",
2077         hdac_methods,
2078         sizeof(struct hdac_softc),
2079 };
2080
2081 static devclass_t hdac_devclass;
2082
2083 DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0);