2 * Copyright (c) 2012 Semihalf.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/kernel.h>
34 #include <machine/bus.h>
36 #include <dev/uart/uart.h>
37 #include <dev/uart/uart_cpu.h>
38 #include <dev/uart/uart_bus.h>
43 /* PL011 UART registers and masks*/
44 #define UART_DR 0x00 /* Data register */
45 #define DR_FE (1 << 8) /* Framing error */
46 #define DR_PE (1 << 9) /* Parity error */
47 #define DR_BE (1 << 10) /* Break error */
48 #define DR_OE (1 << 11) /* Overrun error */
50 #define UART_FR 0x06 /* Flag register */
51 #define FR_RXFF (1 << 6) /* Receive FIFO/reg full */
52 #define FR_TXFE (1 << 7) /* Transmit FIFO/reg empty */
54 #define UART_IBRD 0x09 /* Integer baud rate register */
55 #define IBRD_BDIVINT 0xffff /* Significant part of int. divisor value */
57 #define UART_FBRD 0x0a /* Fractional baud rate register */
58 #define FBRD_BDIVFRAC 0x3f /* Significant part of frac. divisor value */
60 #define UART_LCR_H 0x0b /* Line control register */
61 #define LCR_H_WLEN8 (0x3 << 5)
62 #define LCR_H_WLEN7 (0x2 << 5)
63 #define LCR_H_WLEN6 (0x1 << 5)
64 #define LCR_H_FEN (1 << 4) /* FIFO mode enable */
65 #define LCR_H_STP2 (1 << 3) /* 2 stop frames at the end */
66 #define LCR_H_EPS (1 << 2) /* Even parity select */
67 #define LCR_H_PEN (1 << 1) /* Parity enable */
69 #define UART_CR 0x0c /* Control register */
70 #define CR_RXE (1 << 9) /* Receive enable */
71 #define CR_TXE (1 << 8) /* Transmit enable */
72 #define CR_UARTEN (1 << 0) /* UART enable */
74 #define UART_IMSC 0x0e /* Interrupt mask set/clear register */
75 #define IMSC_MASK_ALL 0x7ff /* Mask all interrupts */
77 #define UART_RIS 0x0f /* Raw interrupt status register */
78 #define UART_RXREADY (1 << 4) /* RX buffer full */
79 #define UART_TXEMPTY (1 << 5) /* TX buffer empty */
80 #define RIS_FE (1 << 7) /* Framing error interrupt status */
81 #define RIS_PE (1 << 8) /* Parity error interrupt status */
82 #define RIS_BE (1 << 9) /* Break error interrupt status */
83 #define RIS_OE (1 << 10) /* Overrun interrupt status */
85 #define UART_MIS 0x10 /* Masked interrupt status register */
86 #define UART_ICR 0x11 /* Interrupt clear register */
89 * FIXME: actual register size is SoC-dependent, we need to handle it
91 #define __uart_getreg(bas, reg) \
92 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg))
93 #define __uart_setreg(bas, reg, value) \
94 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value)
97 * Low-level UART interface.
99 static int uart_pl011_probe(struct uart_bas *bas);
100 static void uart_pl011_init(struct uart_bas *bas, int, int, int, int);
101 static void uart_pl011_term(struct uart_bas *bas);
102 static void uart_pl011_putc(struct uart_bas *bas, int);
103 static int uart_pl011_rxready(struct uart_bas *bas);
104 static int uart_pl011_getc(struct uart_bas *bas, struct mtx *);
106 static struct uart_ops uart_pl011_ops = {
107 .probe = uart_pl011_probe,
108 .init = uart_pl011_init,
109 .term = uart_pl011_term,
110 .putc = uart_pl011_putc,
111 .rxready = uart_pl011_rxready,
112 .getc = uart_pl011_getc,
116 uart_pl011_probe(struct uart_bas *bas)
123 uart_pl011_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
130 * Zero all settings to make sure
131 * UART is disabled and not configured
134 __uart_setreg(bas, UART_CR, ctrl);
136 /* As we know UART is disabled we may setup the line */
150 /* TODO: Calculate divisors */
151 baud = (0x1 << 16) | 0x28;
163 /* Configure the rest */
165 ctrl |= (CR_RXE | CR_TXE | CR_UARTEN);
167 __uart_setreg(bas, UART_IBRD, ((uint32_t)(baud >> 16)) & IBRD_BDIVINT);
168 __uart_setreg(bas, UART_FBRD, (uint32_t)(baud) & FBRD_BDIVFRAC);
170 /* Add config. to line before reenabling UART */
171 __uart_setreg(bas, UART_LCR_H, (__uart_getreg(bas, UART_LCR_H) &
174 __uart_setreg(bas, UART_CR, ctrl);
178 uart_pl011_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
181 /* Mask all interrupts */
182 __uart_setreg(bas, UART_IMSC, __uart_getreg(bas, UART_IMSC) &
185 uart_pl011_param(bas, baudrate, databits, stopbits, parity);
189 uart_pl011_term(struct uart_bas *bas)
194 uart_pl011_putc(struct uart_bas *bas, int c)
197 while (!(__uart_getreg(bas, UART_FR) & FR_TXFE))
199 __uart_setreg(bas, UART_DR, c & 0xff);
203 uart_pl011_rxready(struct uart_bas *bas)
206 return (__uart_getreg(bas, UART_FR) & FR_RXFF);
210 uart_pl011_getc(struct uart_bas *bas, struct mtx *hwmtx)
214 while (!uart_pl011_rxready(bas))
216 c = __uart_getreg(bas, UART_DR) & 0xff;
222 * High-level UART interface.
224 struct uart_pl011_softc {
225 struct uart_softc base;
234 static int uart_pl011_bus_attach(struct uart_softc *);
235 static int uart_pl011_bus_detach(struct uart_softc *);
236 static int uart_pl011_bus_flush(struct uart_softc *, int);
237 static int uart_pl011_bus_getsig(struct uart_softc *);
238 static int uart_pl011_bus_ioctl(struct uart_softc *, int, intptr_t);
239 static int uart_pl011_bus_ipend(struct uart_softc *);
240 static int uart_pl011_bus_param(struct uart_softc *, int, int, int, int);
241 static int uart_pl011_bus_probe(struct uart_softc *);
242 static int uart_pl011_bus_receive(struct uart_softc *);
243 static int uart_pl011_bus_setsig(struct uart_softc *, int);
244 static int uart_pl011_bus_transmit(struct uart_softc *);
246 static kobj_method_t uart_pl011_methods[] = {
247 KOBJMETHOD(uart_attach, uart_pl011_bus_attach),
248 KOBJMETHOD(uart_detach, uart_pl011_bus_detach),
249 KOBJMETHOD(uart_flush, uart_pl011_bus_flush),
250 KOBJMETHOD(uart_getsig, uart_pl011_bus_getsig),
251 KOBJMETHOD(uart_ioctl, uart_pl011_bus_ioctl),
252 KOBJMETHOD(uart_ipend, uart_pl011_bus_ipend),
253 KOBJMETHOD(uart_param, uart_pl011_bus_param),
254 KOBJMETHOD(uart_probe, uart_pl011_bus_probe),
255 KOBJMETHOD(uart_receive, uart_pl011_bus_receive),
256 KOBJMETHOD(uart_setsig, uart_pl011_bus_setsig),
257 KOBJMETHOD(uart_transmit, uart_pl011_bus_transmit),
261 struct uart_class uart_pl011_class = {
264 sizeof(struct uart_pl011_softc),
265 .uc_ops = &uart_pl011_ops,
271 uart_pl011_bus_attach(struct uart_softc *sc)
273 struct uart_bas *bas;
276 /* Enable RX & TX interrupts */
277 __uart_setreg(bas, UART_IMSC, (UART_RXREADY | UART_TXEMPTY));
278 /* Clear RX & TX interrupts */
279 __uart_setreg(bas, UART_ICR, IMSC_MASK_ALL);
285 uart_pl011_bus_detach(struct uart_softc *sc)
292 uart_pl011_bus_flush(struct uart_softc *sc, int what)
299 uart_pl011_bus_getsig(struct uart_softc *sc)
306 uart_pl011_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
308 struct uart_bas *bas;
313 uart_lock(sc->sc_hwmtx);
315 case UART_IOCTL_BREAK:
317 case UART_IOCTL_BAUD:
318 *(int*)data = 115200;
324 uart_unlock(sc->sc_hwmtx);
330 uart_pl011_bus_ipend(struct uart_softc *sc)
332 struct uart_bas *bas;
337 uart_lock(sc->sc_hwmtx);
338 ints = __uart_getreg(bas, UART_MIS);
341 if (ints & UART_RXREADY)
342 ipend |= SER_INT_RXREADY;
344 ipend |= SER_INT_BREAK;
346 ipend |= SER_INT_OVERRUN;
347 if (ints & UART_TXEMPTY) {
349 ipend |= SER_INT_TXIDLE;
351 __uart_setreg(bas, UART_IMSC, UART_RXREADY);
354 uart_unlock(sc->sc_hwmtx);
360 uart_pl011_bus_param(struct uart_softc *sc, int baudrate, int databits,
361 int stopbits, int parity)
364 uart_lock(sc->sc_hwmtx);
365 uart_pl011_param(&sc->sc_bas, baudrate, databits, stopbits, parity);
366 uart_unlock(sc->sc_hwmtx);
372 uart_pl011_bus_probe(struct uart_softc *sc)
375 device_set_desc(sc->sc_dev, "PrimeCell UART (PL011)");
384 uart_pl011_bus_receive(struct uart_softc *sc)
386 struct uart_bas *bas;
391 uart_lock(sc->sc_hwmtx);
393 ints = __uart_getreg(bas, UART_MIS);
394 while (ints & UART_RXREADY) {
395 if (uart_rx_full(sc)) {
396 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
399 xc = __uart_getreg(bas, UART_DR);
403 rx |= UART_STAT_FRAMERR;
405 rx |= UART_STAT_PARERR;
407 __uart_setreg(bas, UART_ICR, UART_RXREADY);
410 ints = __uart_getreg(bas, UART_MIS);
413 uart_unlock(sc->sc_hwmtx);
419 uart_pl011_bus_setsig(struct uart_softc *sc, int sig)
426 uart_pl011_bus_transmit(struct uart_softc *sc)
428 struct uart_bas *bas;
432 uart_lock(sc->sc_hwmtx);
434 for (i = 0; i < sc->sc_txdatasz; i++) {
435 __uart_setreg(bas, UART_DR, sc->sc_txbuf[i]);
439 __uart_setreg(bas, UART_IMSC, (UART_RXREADY | UART_TXEMPTY));
440 uart_unlock(sc->sc_hwmtx);