3 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * Thanks to Mentor Graphics for providing a reference driver for this USB chip
33 * This file contains the driver for the Mentor Graphics Inventra USB
34 * 2.0 High Speed Dual-Role controller.
36 * NOTE: The current implementation only supports Device Side Mode!
39 #ifdef USB_GLOBAL_INCLUDE_FILE
40 #include USB_GLOBAL_INCLUDE_FILE
42 #include <sys/stdint.h>
43 #include <sys/stddef.h>
44 #include <sys/param.h>
45 #include <sys/queue.h>
46 #include <sys/types.h>
47 #include <sys/systm.h>
48 #include <sys/kernel.h>
50 #include <sys/module.h>
52 #include <sys/mutex.h>
53 #include <sys/condvar.h>
54 #include <sys/sysctl.h>
56 #include <sys/unistd.h>
57 #include <sys/callout.h>
58 #include <sys/malloc.h>
61 #include <dev/usb/usb.h>
62 #include <dev/usb/usbdi.h>
64 #define USB_DEBUG_VAR musbotgdebug
66 #include <dev/usb/usb_core.h>
67 #include <dev/usb/usb_debug.h>
68 #include <dev/usb/usb_busdma.h>
69 #include <dev/usb/usb_process.h>
70 #include <dev/usb/usb_transfer.h>
71 #include <dev/usb/usb_device.h>
72 #include <dev/usb/usb_hub.h>
73 #include <dev/usb/usb_util.h>
75 #include <dev/usb/usb_controller.h>
76 #include <dev/usb/usb_bus.h>
77 #endif /* USB_GLOBAL_INCLUDE_FILE */
79 #include <dev/usb/controller/musb_otg.h>
81 #define MUSBOTG_INTR_ENDPT 1
83 #define MUSBOTG_BUS2SC(bus) \
84 ((struct musbotg_softc *)(((uint8_t *)(bus)) - \
85 USB_P2U(&(((struct musbotg_softc *)0)->sc_bus))))
87 #define MUSBOTG_PC2SC(pc) \
88 MUSBOTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus)
91 static int musbotgdebug = 0;
93 static SYSCTL_NODE(_hw_usb, OID_AUTO, musbotg, CTLFLAG_RW, 0, "USB musbotg");
94 SYSCTL_INT(_hw_usb_musbotg, OID_AUTO, debug, CTLFLAG_RW,
95 &musbotgdebug, 0, "Debug level");
102 struct usb_bus_methods musbotg_bus_methods;
103 struct usb_pipe_methods musbotg_device_bulk_methods;
104 struct usb_pipe_methods musbotg_device_ctrl_methods;
105 struct usb_pipe_methods musbotg_device_intr_methods;
106 struct usb_pipe_methods musbotg_device_isoc_methods;
108 /* Control transfers: Device mode */
109 static musbotg_cmd_t musbotg_dev_ctrl_setup_rx;
110 static musbotg_cmd_t musbotg_dev_ctrl_data_rx;
111 static musbotg_cmd_t musbotg_dev_ctrl_data_tx;
112 static musbotg_cmd_t musbotg_dev_ctrl_status;
114 /* Control transfers: Host mode */
115 static musbotg_cmd_t musbotg_host_ctrl_setup_tx;
116 static musbotg_cmd_t musbotg_host_ctrl_data_rx;
117 static musbotg_cmd_t musbotg_host_ctrl_data_tx;
118 static musbotg_cmd_t musbotg_host_ctrl_status_rx;
119 static musbotg_cmd_t musbotg_host_ctrl_status_tx;
121 /* Bulk, Interrupt, Isochronous: Device mode */
122 static musbotg_cmd_t musbotg_dev_data_rx;
123 static musbotg_cmd_t musbotg_dev_data_tx;
125 /* Bulk, Interrupt, Isochronous: Host mode */
126 static musbotg_cmd_t musbotg_host_data_rx;
127 static musbotg_cmd_t musbotg_host_data_tx;
129 static void musbotg_device_done(struct usb_xfer *, usb_error_t);
130 static void musbotg_do_poll(struct usb_bus *);
131 static void musbotg_standard_done(struct usb_xfer *);
132 static void musbotg_interrupt_poll(struct musbotg_softc *);
133 static void musbotg_root_intr(struct musbotg_softc *);
134 static int musbotg_channel_alloc(struct musbotg_softc *, struct musbotg_td *td);
135 static void musbotg_channel_free(struct musbotg_softc *, struct musbotg_td *td);
136 static void musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on);
139 * Here is a configuration that the chip supports.
141 static const struct usb_hw_ep_profile musbotg_ep_profile[1] = {
144 .max_in_frame_size = 64,/* fixed */
145 .max_out_frame_size = 64, /* fixed */
147 .support_control = 1,
152 musbotg_channel_alloc(struct musbotg_softc *sc, struct musbotg_td *td)
159 /* In device mode each EP got its own channel */
160 if (sc->sc_mode == MUSB2_DEVICE_MODE) {
161 musbotg_ep_int_set(sc, ep, 1);
166 * All control transactions go through EP0
169 if (sc->sc_channel_mask & (1 << 0))
171 sc->sc_channel_mask |= (1 << 0);
172 musbotg_ep_int_set(sc, ep, 1);
176 for (ch = 1; ch < MUSB2_EP_MAX; ch++) {
177 if (!(sc->sc_channel_mask & (1 << ch))) {
178 sc->sc_channel_mask |= (1 << ch);
179 musbotg_ep_int_set(sc, ch, 1);
184 DPRINTFN(-1, "No available channels. Mask: %04x\n", sc->sc_channel_mask);
190 musbotg_channel_free(struct musbotg_softc *sc, struct musbotg_td *td)
193 DPRINTFN(1, "ep_no=%d\n", td->channel);
195 if (sc->sc_mode == MUSB2_DEVICE_MODE)
200 if (td->channel == -1)
203 musbotg_ep_int_set(sc, td->channel, 0);
204 sc->sc_channel_mask &= ~(1 << td->channel);
210 musbotg_get_hw_ep_profile(struct usb_device *udev,
211 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
213 struct musbotg_softc *sc;
215 sc = MUSBOTG_BUS2SC(udev->bus);
218 /* control endpoint */
219 *ppf = musbotg_ep_profile;
220 } else if (ep_addr <= sc->sc_ep_max) {
221 /* other endpoints */
222 *ppf = sc->sc_hw_ep_profile + ep_addr;
229 musbotg_clocks_on(struct musbotg_softc *sc)
231 if (sc->sc_flags.clocks_off &&
232 sc->sc_flags.port_powered) {
236 if (sc->sc_clocks_on) {
237 (sc->sc_clocks_on) (sc->sc_clocks_arg);
239 sc->sc_flags.clocks_off = 0;
241 /* XXX enable Transceiver */
246 musbotg_clocks_off(struct musbotg_softc *sc)
248 if (!sc->sc_flags.clocks_off) {
252 /* XXX disable Transceiver */
254 if (sc->sc_clocks_off) {
255 (sc->sc_clocks_off) (sc->sc_clocks_arg);
257 sc->sc_flags.clocks_off = 1;
262 musbotg_pull_common(struct musbotg_softc *sc, uint8_t on)
266 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
268 temp |= MUSB2_MASK_SOFTC;
270 temp &= ~MUSB2_MASK_SOFTC;
272 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
276 musbotg_pull_up(struct musbotg_softc *sc)
278 /* pullup D+, if possible */
280 if (!sc->sc_flags.d_pulled_up &&
281 sc->sc_flags.port_powered) {
282 sc->sc_flags.d_pulled_up = 1;
283 musbotg_pull_common(sc, 1);
288 musbotg_pull_down(struct musbotg_softc *sc)
290 /* pulldown D+, if possible */
292 if (sc->sc_flags.d_pulled_up) {
293 sc->sc_flags.d_pulled_up = 0;
294 musbotg_pull_common(sc, 0);
299 musbotg_suspend_host(struct musbotg_softc *sc)
303 if (sc->sc_flags.status_suspend) {
307 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
308 temp |= MUSB2_MASK_SUSPMODE;
309 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
310 sc->sc_flags.status_suspend = 1;
314 musbotg_wakeup_host(struct musbotg_softc *sc)
318 if (!(sc->sc_flags.status_suspend)) {
322 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
323 temp &= ~MUSB2_MASK_SUSPMODE;
324 temp |= MUSB2_MASK_RESUME;
325 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
327 /* wait 20 milliseconds */
328 /* Wait for reset to complete. */
329 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
331 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
332 temp &= ~MUSB2_MASK_RESUME;
333 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
335 sc->sc_flags.status_suspend = 0;
339 musbotg_wakeup_peer(struct musbotg_softc *sc)
343 if (!(sc->sc_flags.status_suspend)) {
347 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
348 temp |= MUSB2_MASK_RESUME;
349 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
351 /* wait 8 milliseconds */
352 /* Wait for reset to complete. */
353 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
355 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
356 temp &= ~MUSB2_MASK_RESUME;
357 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
361 musbotg_set_address(struct musbotg_softc *sc, uint8_t addr)
363 DPRINTFN(4, "addr=%d\n", addr);
365 MUSB2_WRITE_1(sc, MUSB2_REG_FADDR, addr);
369 musbotg_dev_ctrl_setup_rx(struct musbotg_td *td)
371 struct musbotg_softc *sc;
372 struct usb_device_request req;
376 /* get pointer to softc */
377 sc = MUSBOTG_PC2SC(td->pc);
379 if (td->channel == -1)
380 td->channel = musbotg_channel_alloc(sc, td);
382 /* EP0 is busy, wait */
383 if (td->channel == -1)
386 DPRINTFN(1, "ep_no=%d\n", td->channel);
388 /* select endpoint 0 */
389 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
391 /* read out FIFO status */
392 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
394 DPRINTFN(4, "csr=0x%02x\n", csr);
397 * NOTE: If DATAEND is set we should not call the
398 * callback, hence the status stage is not complete.
400 if (csr & MUSB2_MASK_CSR0L_DATAEND) {
401 /* do not stall at this point */
403 /* wait for interrupt */
404 DPRINTFN(0, "CSR0 DATAEND\n");
408 if (csr & MUSB2_MASK_CSR0L_SENTSTALL) {
409 /* clear SENTSTALL */
410 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
411 /* get latest status */
412 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
413 /* update EP0 state */
416 if (csr & MUSB2_MASK_CSR0L_SETUPEND) {
418 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
419 MUSB2_MASK_CSR0L_SETUPEND_CLR);
420 /* get latest status */
421 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
422 /* update EP0 state */
425 if (sc->sc_ep0_busy) {
426 DPRINTFN(0, "EP0 BUSY\n");
429 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) {
432 /* clear did stall flag */
434 /* get the packet byte count */
435 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
437 /* verify data length */
438 if (count != td->remainder) {
439 DPRINTFN(0, "Invalid SETUP packet "
440 "length, %d bytes\n", count);
441 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
442 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
445 if (count != sizeof(req)) {
446 DPRINTFN(0, "Unsupported SETUP packet "
447 "length, %d bytes\n", count);
448 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
449 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
453 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
454 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req));
456 /* copy data into real buffer */
457 usbd_copy_in(td->pc, 0, &req, sizeof(req));
459 td->offset = sizeof(req);
462 /* set pending command */
463 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR;
465 /* we need set stall or dataend after this */
468 /* sneak peek the set address */
469 if ((req.bmRequestType == UT_WRITE_DEVICE) &&
470 (req.bRequest == UR_SET_ADDRESS)) {
471 sc->sc_dv_addr = req.wValue[0] & 0x7F;
473 sc->sc_dv_addr = 0xFF;
476 musbotg_channel_free(sc, td);
477 return (0); /* complete */
480 /* abort any ongoing transfer */
481 if (!td->did_stall) {
482 DPRINTFN(4, "stalling\n");
483 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
484 MUSB2_MASK_CSR0L_SENDSTALL);
487 return (1); /* not complete */
491 musbotg_host_ctrl_setup_tx(struct musbotg_td *td)
493 struct musbotg_softc *sc;
494 struct usb_device_request req;
497 /* get pointer to softc */
498 sc = MUSBOTG_PC2SC(td->pc);
500 if (td->channel == -1)
501 td->channel = musbotg_channel_alloc(sc, td);
503 /* EP0 is busy, wait */
504 if (td->channel == -1)
507 DPRINTFN(1, "ep_no=%d\n", td->channel);
509 /* select endpoint 0 */
510 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
512 /* read out FIFO status */
513 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
514 DPRINTFN(4, "csr=0x%02x\n", csr);
516 /* Not ready yet yet */
517 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
521 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
522 MUSB2_MASK_CSR0L_ERROR))
524 /* Clear status bit */
525 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
526 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
530 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
531 DPRINTFN(1, "NAK timeout\n");
533 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
534 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
535 csrh |= MUSB2_MASK_CSR0H_FFLUSH;
536 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
537 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
538 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
539 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
540 csrh |= MUSB2_MASK_CSR0H_FFLUSH;
541 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
542 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
546 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
547 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
553 musbotg_channel_free(sc, td);
557 /* Fifo is not empty and there is no NAK timeout */
558 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
561 /* check if we are complete */
562 if (td->remainder == 0) {
563 /* we are complete */
564 musbotg_channel_free(sc, td);
568 /* copy data into real buffer */
569 usbd_copy_out(td->pc, 0, &req, sizeof(req));
572 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
573 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req));
575 /* update offset and remainder */
576 td->offset += sizeof(req);
577 td->remainder -= sizeof(req);
580 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
581 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr);
582 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr);
583 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport);
584 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
587 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
588 MUSB2_MASK_CSR0L_TXPKTRDY |
589 MUSB2_MASK_CSR0L_SETUPPKT);
591 /* Just to be consistent, not used above */
592 td->transaction_started = 1;
594 return (1); /* in progress */
597 /* Control endpoint only data handling functions (RX/TX/SYNC) */
600 musbotg_dev_ctrl_data_rx(struct musbotg_td *td)
602 struct usb_page_search buf_res;
603 struct musbotg_softc *sc;
608 /* get pointer to softc */
609 sc = MUSBOTG_PC2SC(td->pc);
611 /* select endpoint 0 */
612 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
614 /* check if a command is pending */
615 if (sc->sc_ep0_cmd) {
616 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
619 /* read out FIFO status */
620 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
622 DPRINTFN(4, "csr=0x%02x\n", csr);
626 if (csr & (MUSB2_MASK_CSR0L_SETUPEND |
627 MUSB2_MASK_CSR0L_SENTSTALL)) {
628 if (td->remainder == 0) {
630 * We are actually complete and have
631 * received the next SETUP
633 DPRINTFN(4, "faking complete\n");
634 return (0); /* complete */
637 * USB Host Aborted the transfer.
640 return (0); /* complete */
642 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) {
643 return (1); /* not complete */
645 /* get the packet byte count */
646 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
648 /* verify the packet byte count */
649 if (count != td->max_frame_size) {
650 if (count < td->max_frame_size) {
651 /* we have a short packet */
655 /* invalid USB packet */
657 return (0); /* we are complete */
660 /* verify the packet byte count */
661 if (count > td->remainder) {
662 /* invalid USB packet */
664 return (0); /* we are complete */
669 usbd_get_page(td->pc, td->offset, &buf_res);
671 /* get correct length */
672 if (buf_res.length > count) {
673 buf_res.length = count;
675 /* check for unaligned memory address */
676 if (USB_P2U(buf_res.buffer) & 3) {
681 /* receive data 4 bytes at a time */
682 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
683 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf,
688 /* receive data 1 byte at a time */
689 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
691 (void *)(&sc->sc_bounce_buf[count / 4]), temp);
693 usbd_copy_in(td->pc, td->offset,
694 sc->sc_bounce_buf, count);
696 /* update offset and remainder */
698 td->remainder -= count;
701 /* check if we can optimise */
702 if (buf_res.length >= 4) {
704 /* receive data 4 bytes at a time */
705 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
706 MUSB2_REG_EPFIFO(0), buf_res.buffer,
709 temp = buf_res.length & ~3;
711 /* update counters */
714 td->remainder -= temp;
718 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
719 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length);
721 /* update counters */
722 count -= buf_res.length;
723 td->offset += buf_res.length;
724 td->remainder -= buf_res.length;
727 /* check if we are complete */
728 if ((td->remainder == 0) || got_short) {
730 /* we are complete */
731 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR;
734 /* else need to receive a zero length packet */
736 /* write command - need more data */
737 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
738 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
739 return (1); /* not complete */
743 musbotg_dev_ctrl_data_tx(struct musbotg_td *td)
745 struct usb_page_search buf_res;
746 struct musbotg_softc *sc;
750 /* get pointer to softc */
751 sc = MUSBOTG_PC2SC(td->pc);
753 /* select endpoint 0 */
754 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
756 /* check if a command is pending */
757 if (sc->sc_ep0_cmd) {
758 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
761 /* read out FIFO status */
762 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
764 DPRINTFN(4, "csr=0x%02x\n", csr);
766 if (csr & (MUSB2_MASK_CSR0L_SETUPEND |
767 MUSB2_MASK_CSR0L_SENTSTALL)) {
769 * The current transfer was aborted
773 return (0); /* complete */
775 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) {
776 return (1); /* not complete */
778 count = td->max_frame_size;
779 if (td->remainder < count) {
780 /* we have a short packet */
782 count = td->remainder;
787 usbd_get_page(td->pc, td->offset, &buf_res);
789 /* get correct length */
790 if (buf_res.length > count) {
791 buf_res.length = count;
793 /* check for unaligned memory address */
794 if (USB_P2U(buf_res.buffer) & 3) {
796 usbd_copy_out(td->pc, td->offset,
797 sc->sc_bounce_buf, count);
802 /* transmit data 4 bytes at a time */
803 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
804 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf,
809 /* receive data 1 byte at a time */
810 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
812 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
814 /* update offset and remainder */
816 td->remainder -= count;
819 /* check if we can optimise */
820 if (buf_res.length >= 4) {
822 /* transmit data 4 bytes at a time */
823 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
824 MUSB2_REG_EPFIFO(0), buf_res.buffer,
827 temp = buf_res.length & ~3;
829 /* update counters */
832 td->remainder -= temp;
836 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
837 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length);
839 /* update counters */
840 count -= buf_res.length;
841 td->offset += buf_res.length;
842 td->remainder -= buf_res.length;
845 /* check remainder */
846 if (td->remainder == 0) {
848 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_TXPKTRDY;
849 return (0); /* complete */
851 /* else we need to transmit a short packet */
854 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
855 MUSB2_MASK_CSR0L_TXPKTRDY);
857 return (1); /* not complete */
861 musbotg_host_ctrl_data_rx(struct musbotg_td *td)
863 struct usb_page_search buf_res;
864 struct musbotg_softc *sc;
869 /* get pointer to softc */
870 sc = MUSBOTG_PC2SC(td->pc);
872 if (td->channel == -1)
873 td->channel = musbotg_channel_alloc(sc, td);
875 /* EP0 is busy, wait */
876 if (td->channel == -1)
879 DPRINTFN(1, "ep_no=%d\n", td->channel);
881 /* select endpoint 0 */
882 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
884 /* read out FIFO status */
885 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
887 DPRINTFN(4, "csr=0x%02x\n", csr);
890 if (!td->transaction_started) {
891 td->transaction_started = 1;
893 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO);
895 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0),
897 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr);
898 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport);
899 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type);
901 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
902 MUSB2_MASK_CSR0L_REQPKT);
907 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
908 csr &= ~MUSB2_MASK_CSR0L_REQPKT;
909 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
911 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
912 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
918 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
919 MUSB2_MASK_CSR0L_ERROR))
921 /* Clear status bit */
922 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
923 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
928 musbotg_channel_free(sc, td);
929 return (0); /* we are complete */
932 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY))
933 return (1); /* not yet */
935 /* get the packet byte count */
936 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
938 /* verify the packet byte count */
939 if (count != td->max_frame_size) {
940 if (count < td->max_frame_size) {
941 /* we have a short packet */
945 /* invalid USB packet */
947 musbotg_channel_free(sc, td);
948 return (0); /* we are complete */
951 /* verify the packet byte count */
952 if (count > td->remainder) {
953 /* invalid USB packet */
955 musbotg_channel_free(sc, td);
956 return (0); /* we are complete */
961 usbd_get_page(td->pc, td->offset, &buf_res);
963 /* get correct length */
964 if (buf_res.length > count) {
965 buf_res.length = count;
967 /* check for unaligned memory address */
968 if (USB_P2U(buf_res.buffer) & 3) {
973 /* receive data 4 bytes at a time */
974 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
975 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf,
980 /* receive data 1 byte at a time */
981 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
983 (void *)(&sc->sc_bounce_buf[count / 4]), temp);
985 usbd_copy_in(td->pc, td->offset,
986 sc->sc_bounce_buf, count);
988 /* update offset and remainder */
990 td->remainder -= count;
993 /* check if we can optimise */
994 if (buf_res.length >= 4) {
996 /* receive data 4 bytes at a time */
997 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
998 MUSB2_REG_EPFIFO(0), buf_res.buffer,
1001 temp = buf_res.length & ~3;
1003 /* update counters */
1006 td->remainder -= temp;
1010 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1011 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length);
1013 /* update counters */
1014 count -= buf_res.length;
1015 td->offset += buf_res.length;
1016 td->remainder -= buf_res.length;
1019 csr &= ~MUSB2_MASK_CSR0L_RXPKTRDY;
1020 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1022 /* check if we are complete */
1023 if ((td->remainder == 0) || got_short) {
1024 if (td->short_pkt) {
1025 /* we are complete */
1027 musbotg_channel_free(sc, td);
1030 /* else need to receive a zero length packet */
1033 td->transaction_started = 1;
1034 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1035 MUSB2_MASK_CSR0L_REQPKT);
1037 return (1); /* not complete */
1041 musbotg_host_ctrl_data_tx(struct musbotg_td *td)
1043 struct usb_page_search buf_res;
1044 struct musbotg_softc *sc;
1048 /* get pointer to softc */
1049 sc = MUSBOTG_PC2SC(td->pc);
1051 if (td->channel == -1)
1052 td->channel = musbotg_channel_alloc(sc, td);
1055 if (td->channel == -1)
1058 DPRINTFN(1, "ep_no=%d\n", td->channel);
1060 /* select endpoint */
1061 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1063 /* read out FIFO status */
1064 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1065 DPRINTFN(4, "csr=0x%02x\n", csr);
1067 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
1068 MUSB2_MASK_CSR0L_ERROR)) {
1069 /* clear status bits */
1070 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1074 if (csr & MUSB2_MASK_CSR0L_NAKTIMO ) {
1076 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
1077 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
1078 csrh |= MUSB2_MASK_CSR0H_FFLUSH;
1079 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
1080 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1081 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
1082 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
1083 csrh |= MUSB2_MASK_CSR0H_FFLUSH;
1084 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
1085 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1089 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
1090 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1097 musbotg_channel_free(sc, td);
1098 return (0); /* complete */
1102 * Wait while FIFO is empty.
1103 * Do not flush it because it will cause transactions
1104 * with size more then packet size. It might upset
1107 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY)
1110 /* Packet still being processed */
1111 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
1114 if (td->transaction_started) {
1115 /* check remainder */
1116 if (td->remainder == 0) {
1117 if (td->short_pkt) {
1118 musbotg_channel_free(sc, td);
1119 return (0); /* complete */
1121 /* else we need to transmit a short packet */
1124 /* We're not complete - more transactions required */
1125 td->transaction_started = 0;
1128 /* check for short packet */
1129 count = td->max_frame_size;
1130 if (td->remainder < count) {
1131 /* we have a short packet */
1133 count = td->remainder;
1139 usbd_get_page(td->pc, td->offset, &buf_res);
1141 /* get correct length */
1142 if (buf_res.length > count) {
1143 buf_res.length = count;
1145 /* check for unaligned memory address */
1146 if (USB_P2U(buf_res.buffer) & 3) {
1148 usbd_copy_out(td->pc, td->offset,
1149 sc->sc_bounce_buf, count);
1154 /* transmit data 4 bytes at a time */
1155 bus_space_write_multi_4(sc->sc_io_tag,
1156 sc->sc_io_hdl, MUSB2_REG_EPFIFO(0),
1157 sc->sc_bounce_buf, temp / 4);
1161 /* receive data 1 byte at a time */
1162 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1163 MUSB2_REG_EPFIFO(0),
1164 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1166 /* update offset and remainder */
1167 td->offset += count;
1168 td->remainder -= count;
1171 /* check if we can optimise */
1172 if (buf_res.length >= 4) {
1174 /* transmit data 4 bytes at a time */
1175 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1176 MUSB2_REG_EPFIFO(0), buf_res.buffer,
1177 buf_res.length / 4);
1179 temp = buf_res.length & ~3;
1181 /* update counters */
1184 td->remainder -= temp;
1188 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1189 MUSB2_REG_EPFIFO(0), buf_res.buffer,
1192 /* update counters */
1193 count -= buf_res.length;
1194 td->offset += buf_res.length;
1195 td->remainder -= buf_res.length;
1198 /* Function address */
1199 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr);
1200 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr);
1201 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport);
1202 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
1204 /* TX NAK timeout */
1205 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
1208 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1209 MUSB2_MASK_CSR0L_TXPKTRDY);
1211 td->transaction_started = 1;
1213 return (1); /* not complete */
1217 musbotg_dev_ctrl_status(struct musbotg_td *td)
1219 struct musbotg_softc *sc;
1222 /* get pointer to softc */
1223 sc = MUSBOTG_PC2SC(td->pc);
1225 /* select endpoint 0 */
1226 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1228 if (sc->sc_ep0_busy) {
1229 sc->sc_ep0_busy = 0;
1230 sc->sc_ep0_cmd |= MUSB2_MASK_CSR0L_DATAEND;
1231 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
1234 /* read out FIFO status */
1235 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1237 DPRINTFN(4, "csr=0x%02x\n", csr);
1239 if (csr & MUSB2_MASK_CSR0L_DATAEND) {
1240 /* wait for interrupt */
1241 return (1); /* not complete */
1243 if (sc->sc_dv_addr != 0xFF) {
1244 /* write function address */
1245 musbotg_set_address(sc, sc->sc_dv_addr);
1248 musbotg_channel_free(sc, td);
1249 return (0); /* complete */
1253 musbotg_host_ctrl_status_rx(struct musbotg_td *td)
1255 struct musbotg_softc *sc;
1258 /* get pointer to softc */
1259 sc = MUSBOTG_PC2SC(td->pc);
1261 if (td->channel == -1)
1262 td->channel = musbotg_channel_alloc(sc, td);
1264 /* EP0 is busy, wait */
1265 if (td->channel == -1)
1268 DPRINTFN(1, "ep_no=%d\n", td->channel);
1270 /* select endpoint 0 */
1271 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1273 if (!td->transaction_started) {
1274 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0),
1277 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr);
1278 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport);
1279 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type);
1281 /* RX NAK timeout */
1282 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO);
1284 td->transaction_started = 1;
1287 csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH);
1288 csrh |= MUSB2_MASK_CSR0H_PING_DIS;
1289 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh);
1292 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1293 MUSB2_MASK_CSR0L_STATUSPKT |
1294 MUSB2_MASK_CSR0L_REQPKT);
1296 return (1); /* Just started */
1300 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1302 DPRINTFN(4, "IN STATUS csr=0x%02x\n", csr);
1304 if (csr & MUSB2_MASK_CSR0L_RXPKTRDY) {
1305 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1306 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
1307 musbotg_channel_free(sc, td);
1308 return (0); /* complete */
1311 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
1312 csr &= ~ (MUSB2_MASK_CSR0L_STATUSPKT |
1313 MUSB2_MASK_CSR0L_REQPKT);
1314 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1316 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
1317 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1322 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
1323 MUSB2_MASK_CSR0L_ERROR))
1325 /* Clear status bit */
1326 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1327 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
1332 musbotg_channel_free(sc, td);
1336 return (1); /* Not ready yet */
1340 musbotg_host_ctrl_status_tx(struct musbotg_td *td)
1342 struct musbotg_softc *sc;
1345 /* get pointer to softc */
1346 sc = MUSBOTG_PC2SC(td->pc);
1348 if (td->channel == -1)
1349 td->channel = musbotg_channel_alloc(sc, td);
1351 /* EP0 is busy, wait */
1352 if (td->channel == -1)
1355 DPRINTFN(1, "ep_no=%d/%d [%d@%d.%d/%02x]\n", td->channel, td->transaction_started,
1356 td->dev_addr,td->haddr,td->hport, td->transfer_type);
1358 /* select endpoint 0 */
1359 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1361 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1362 DPRINTFN(4, "csr=0x%02x\n", csr);
1365 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
1369 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
1370 MUSB2_MASK_CSR0L_ERROR))
1372 /* Clear status bit */
1373 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1374 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
1376 musbotg_channel_free(sc, td);
1377 return (0); /* complete */
1380 if (td->transaction_started) {
1381 musbotg_channel_free(sc, td);
1382 return (0); /* complete */
1385 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, MUSB2_MASK_CSR0H_PING_DIS);
1387 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr);
1388 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr);
1389 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport);
1390 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
1392 /* TX NAK timeout */
1393 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
1395 td->transaction_started = 1;
1398 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1399 MUSB2_MASK_CSR0L_STATUSPKT |
1400 MUSB2_MASK_CSR0L_TXPKTRDY);
1402 return (1); /* wait for interrupt */
1406 musbotg_dev_data_rx(struct musbotg_td *td)
1408 struct usb_page_search buf_res;
1409 struct musbotg_softc *sc;
1415 to = 8; /* don't loop forever! */
1418 /* get pointer to softc */
1419 sc = MUSBOTG_PC2SC(td->pc);
1421 if (td->channel == -1)
1422 td->channel = musbotg_channel_alloc(sc, td);
1424 /* EP0 is busy, wait */
1425 if (td->channel == -1)
1428 /* select endpoint */
1429 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1432 /* read out FIFO status */
1433 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
1435 DPRINTFN(4, "csr=0x%02x\n", csr);
1438 if (csr & MUSB2_MASK_CSRL_RXOVERRUN) {
1439 /* make sure we don't clear "RXPKTRDY" */
1440 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
1441 MUSB2_MASK_CSRL_RXPKTRDY);
1445 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY))
1446 return (1); /* not complete */
1448 /* get the packet byte count */
1449 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
1451 DPRINTFN(4, "count=0x%04x\n", count);
1454 * Check for short or invalid packet:
1456 if (count != td->max_frame_size) {
1457 if (count < td->max_frame_size) {
1458 /* we have a short packet */
1462 /* invalid USB packet */
1464 musbotg_channel_free(sc, td);
1465 return (0); /* we are complete */
1468 /* verify the packet byte count */
1469 if (count > td->remainder) {
1470 /* invalid USB packet */
1472 musbotg_channel_free(sc, td);
1473 return (0); /* we are complete */
1478 usbd_get_page(td->pc, td->offset, &buf_res);
1480 /* get correct length */
1481 if (buf_res.length > count) {
1482 buf_res.length = count;
1484 /* check for unaligned memory address */
1485 if (USB_P2U(buf_res.buffer) & 3) {
1490 /* receive data 4 bytes at a time */
1491 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1492 MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf,
1497 /* receive data 1 byte at a time */
1498 bus_space_read_multi_1(sc->sc_io_tag,
1499 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
1500 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1502 usbd_copy_in(td->pc, td->offset,
1503 sc->sc_bounce_buf, count);
1505 /* update offset and remainder */
1506 td->offset += count;
1507 td->remainder -= count;
1510 /* check if we can optimise */
1511 if (buf_res.length >= 4) {
1513 /* receive data 4 bytes at a time */
1514 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1515 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1516 buf_res.length / 4);
1518 temp = buf_res.length & ~3;
1520 /* update counters */
1523 td->remainder -= temp;
1527 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1528 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1531 /* update counters */
1532 count -= buf_res.length;
1533 td->offset += buf_res.length;
1534 td->remainder -= buf_res.length;
1537 /* clear status bits */
1538 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
1540 /* check if we are complete */
1541 if ((td->remainder == 0) || got_short) {
1542 if (td->short_pkt) {
1543 /* we are complete */
1544 musbotg_channel_free(sc, td);
1547 /* else need to receive a zero length packet */
1552 return (1); /* not complete */
1556 musbotg_dev_data_tx(struct musbotg_td *td)
1558 struct usb_page_search buf_res;
1559 struct musbotg_softc *sc;
1564 to = 8; /* don't loop forever! */
1566 /* get pointer to softc */
1567 sc = MUSBOTG_PC2SC(td->pc);
1569 if (td->channel == -1)
1570 td->channel = musbotg_channel_alloc(sc, td);
1572 /* EP0 is busy, wait */
1573 if (td->channel == -1)
1576 /* select endpoint */
1577 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1581 /* read out FIFO status */
1582 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1584 DPRINTFN(4, "csr=0x%02x\n", csr);
1586 if (csr & (MUSB2_MASK_CSRL_TXINCOMP |
1587 MUSB2_MASK_CSRL_TXUNDERRUN)) {
1588 /* clear status bits */
1589 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1591 if (csr & MUSB2_MASK_CSRL_TXPKTRDY) {
1592 return (1); /* not complete */
1594 /* check for short packet */
1595 count = td->max_frame_size;
1596 if (td->remainder < count) {
1597 /* we have a short packet */
1599 count = td->remainder;
1604 usbd_get_page(td->pc, td->offset, &buf_res);
1606 /* get correct length */
1607 if (buf_res.length > count) {
1608 buf_res.length = count;
1610 /* check for unaligned memory address */
1611 if (USB_P2U(buf_res.buffer) & 3) {
1613 usbd_copy_out(td->pc, td->offset,
1614 sc->sc_bounce_buf, count);
1619 /* transmit data 4 bytes at a time */
1620 bus_space_write_multi_4(sc->sc_io_tag,
1621 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
1622 sc->sc_bounce_buf, temp / 4);
1626 /* receive data 1 byte at a time */
1627 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1628 MUSB2_REG_EPFIFO(td->channel),
1629 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1631 /* update offset and remainder */
1632 td->offset += count;
1633 td->remainder -= count;
1636 /* check if we can optimise */
1637 if (buf_res.length >= 4) {
1639 /* transmit data 4 bytes at a time */
1640 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1641 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1642 buf_res.length / 4);
1644 temp = buf_res.length & ~3;
1646 /* update counters */
1649 td->remainder -= temp;
1653 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1654 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1657 /* update counters */
1658 count -= buf_res.length;
1659 td->offset += buf_res.length;
1660 td->remainder -= buf_res.length;
1663 /* Max packet size */
1664 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, td->reg_max_packet);
1667 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1668 MUSB2_MASK_CSRL_TXPKTRDY);
1670 /* check remainder */
1671 if (td->remainder == 0) {
1672 if (td->short_pkt) {
1673 musbotg_channel_free(sc, td);
1674 return (0); /* complete */
1676 /* else we need to transmit a short packet */
1681 return (1); /* not complete */
1685 musbotg_host_data_rx(struct musbotg_td *td)
1687 struct usb_page_search buf_res;
1688 struct musbotg_softc *sc;
1694 /* get pointer to softc */
1695 sc = MUSBOTG_PC2SC(td->pc);
1697 if (td->channel == -1)
1698 td->channel = musbotg_channel_alloc(sc, td);
1701 if (td->channel == -1)
1704 DPRINTFN(1, "ep_no=%d\n", td->channel);
1706 to = 8; /* don't loop forever! */
1709 /* select endpoint */
1710 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1713 /* read out FIFO status */
1714 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
1715 DPRINTFN(4, "csr=0x%02x\n", csr);
1717 if (!td->transaction_started) {
1718 /* Function address */
1719 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(td->channel),
1722 /* SPLIT transaction */
1723 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(td->channel),
1725 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(td->channel),
1728 /* RX NAK timeout */
1729 if (td->transfer_type & MUSB2_MASK_TI_PROTO_ISOC)
1730 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, 0);
1732 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO);
1734 /* Protocol, speed, device endpoint */
1735 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type);
1737 /* Max packet size */
1738 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, td->reg_max_packet);
1741 csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH);
1742 DPRINTFN(4, "csrh=0x%02x\n", csrh);
1744 csrh |= MUSB2_MASK_CSRH_RXDT_WREN;
1746 csrh |= MUSB2_MASK_CSRH_RXDT_VAL;
1748 csrh &= ~MUSB2_MASK_CSRH_RXDT_VAL;
1750 /* Set data toggle */
1751 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh);
1754 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
1755 MUSB2_MASK_CSRL_RXREQPKT);
1757 td->transaction_started = 1;
1761 /* clear NAK timeout */
1762 if (csr & MUSB2_MASK_CSRL_RXNAKTO) {
1763 DPRINTFN(4, "NAK Timeout\n");
1764 if (csr & MUSB2_MASK_CSRL_RXREQPKT) {
1765 csr &= ~MUSB2_MASK_CSRL_RXREQPKT;
1766 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr);
1768 csr &= ~MUSB2_MASK_CSRL_RXNAKTO;
1769 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr);
1775 if (csr & MUSB2_MASK_CSRL_RXERROR) {
1776 DPRINTFN(4, "RXERROR\n");
1780 if (csr & MUSB2_MASK_CSRL_RXSTALL) {
1781 DPRINTFN(4, "RXSTALL\n");
1786 musbotg_channel_free(sc, td);
1787 return (0); /* we are complete */
1790 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) {
1791 /* No data available yet */
1796 /* get the packet byte count */
1797 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
1798 DPRINTFN(4, "count=0x%04x\n", count);
1801 * Check for short or invalid packet:
1803 if (count != td->max_frame_size) {
1804 if (count < td->max_frame_size) {
1805 /* we have a short packet */
1809 /* invalid USB packet */
1811 musbotg_channel_free(sc, td);
1812 return (0); /* we are complete */
1816 /* verify the packet byte count */
1817 if (count > td->remainder) {
1818 /* invalid USB packet */
1820 musbotg_channel_free(sc, td);
1821 return (0); /* we are complete */
1827 usbd_get_page(td->pc, td->offset, &buf_res);
1829 /* get correct length */
1830 if (buf_res.length > count) {
1831 buf_res.length = count;
1833 /* check for unaligned memory address */
1834 if (USB_P2U(buf_res.buffer) & 3) {
1839 /* receive data 4 bytes at a time */
1840 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1841 MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf,
1846 /* receive data 1 byte at a time */
1847 bus_space_read_multi_1(sc->sc_io_tag,
1848 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
1849 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1851 usbd_copy_in(td->pc, td->offset,
1852 sc->sc_bounce_buf, count);
1854 /* update offset and remainder */
1855 td->offset += count;
1856 td->remainder -= count;
1859 /* check if we can optimise */
1860 if (buf_res.length >= 4) {
1862 /* receive data 4 bytes at a time */
1863 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1864 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1865 buf_res.length / 4);
1867 temp = buf_res.length & ~3;
1869 /* update counters */
1872 td->remainder -= temp;
1876 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1877 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1880 /* update counters */
1881 count -= buf_res.length;
1882 td->offset += buf_res.length;
1883 td->remainder -= buf_res.length;
1886 /* clear status bits */
1887 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
1889 /* check if we are complete */
1890 if ((td->remainder == 0) || got_short) {
1891 if (td->short_pkt) {
1892 /* we are complete */
1893 musbotg_channel_free(sc, td);
1896 /* else need to receive a zero length packet */
1899 /* Reset transaction state and restart */
1900 td->transaction_started = 0;
1905 return (1); /* not complete */
1909 musbotg_host_data_tx(struct musbotg_td *td)
1911 struct usb_page_search buf_res;
1912 struct musbotg_softc *sc;
1916 /* get pointer to softc */
1917 sc = MUSBOTG_PC2SC(td->pc);
1919 if (td->channel == -1)
1920 td->channel = musbotg_channel_alloc(sc, td);
1923 if (td->channel == -1)
1926 DPRINTFN(1, "ep_no=%d\n", td->channel);
1928 /* select endpoint */
1929 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1931 /* read out FIFO status */
1932 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1933 DPRINTFN(4, "csr=0x%02x\n", csr);
1935 if (csr & (MUSB2_MASK_CSRL_TXSTALLED |
1936 MUSB2_MASK_CSRL_TXERROR)) {
1937 /* clear status bits */
1938 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1940 musbotg_channel_free(sc, td);
1941 return (0); /* complete */
1944 if (csr & MUSB2_MASK_CSRL_TXNAKTO) {
1946 * Flush TX FIFO before clearing NAK TO
1948 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
1949 csr |= MUSB2_MASK_CSRL_TXFFLUSH;
1950 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1951 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1952 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
1953 csr |= MUSB2_MASK_CSRL_TXFFLUSH;
1954 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1955 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1959 csr &= ~MUSB2_MASK_CSRL_TXNAKTO;
1960 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1963 musbotg_channel_free(sc, td);
1964 return (0); /* complete */
1968 * Wait while FIFO is empty.
1969 * Do not flush it because it will cause transactions
1970 * with size more then packet size. It might upset
1973 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY)
1976 /* Packet still being processed */
1977 if (csr & MUSB2_MASK_CSRL_TXPKTRDY)
1980 if (td->transaction_started) {
1981 /* check remainder */
1982 if (td->remainder == 0) {
1983 if (td->short_pkt) {
1984 musbotg_channel_free(sc, td);
1985 return (0); /* complete */
1987 /* else we need to transmit a short packet */
1990 /* We're not complete - more transactions required */
1991 td->transaction_started = 0;
1994 /* check for short packet */
1995 count = td->max_frame_size;
1996 if (td->remainder < count) {
1997 /* we have a short packet */
1999 count = td->remainder;
2005 usbd_get_page(td->pc, td->offset, &buf_res);
2007 /* get correct length */
2008 if (buf_res.length > count) {
2009 buf_res.length = count;
2011 /* check for unaligned memory address */
2012 if (USB_P2U(buf_res.buffer) & 3) {
2014 usbd_copy_out(td->pc, td->offset,
2015 sc->sc_bounce_buf, count);
2020 /* transmit data 4 bytes at a time */
2021 bus_space_write_multi_4(sc->sc_io_tag,
2022 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
2023 sc->sc_bounce_buf, temp / 4);
2027 /* receive data 1 byte at a time */
2028 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
2029 MUSB2_REG_EPFIFO(td->channel),
2030 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
2032 /* update offset and remainder */
2033 td->offset += count;
2034 td->remainder -= count;
2037 /* check if we can optimise */
2038 if (buf_res.length >= 4) {
2040 /* transmit data 4 bytes at a time */
2041 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
2042 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
2043 buf_res.length / 4);
2045 temp = buf_res.length & ~3;
2047 /* update counters */
2050 td->remainder -= temp;
2054 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
2055 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
2058 /* update counters */
2059 count -= buf_res.length;
2060 td->offset += buf_res.length;
2061 td->remainder -= buf_res.length;
2064 /* Function address */
2065 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(td->channel),
2068 /* SPLIT transaction */
2069 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(td->channel),
2071 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(td->channel),
2074 /* TX NAK timeout */
2075 if (td->transfer_type & MUSB2_MASK_TI_PROTO_ISOC)
2076 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, 0);
2078 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
2080 /* Protocol, speed, device endpoint */
2081 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
2083 /* Max packet size */
2084 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, td->reg_max_packet);
2086 if (!td->transaction_started) {
2087 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
2088 DPRINTFN(4, "csrh=0x%02x\n", csrh);
2090 csrh |= MUSB2_MASK_CSRH_TXDT_WREN;
2092 csrh |= MUSB2_MASK_CSRH_TXDT_VAL;
2094 csrh &= ~MUSB2_MASK_CSRH_TXDT_VAL;
2096 /* Set data toggle */
2097 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
2101 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2102 MUSB2_MASK_CSRL_TXPKTRDY);
2104 /* Update Data Toggle */
2106 td->transaction_started = 1;
2108 return (1); /* not complete */
2112 musbotg_xfer_do_fifo(struct usb_xfer *xfer)
2114 struct musbotg_softc *sc;
2115 struct musbotg_td *td;
2118 sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
2120 td = xfer->td_transfer_cache;
2123 if ((td->func) (td)) {
2124 /* operation in progress */
2128 if (((void *)td) == xfer->td_transfer_last) {
2133 } else if (td->remainder > 0) {
2135 * We had a short transfer. If there is no alternate
2136 * next, stop processing !
2138 if (!td->alt_next) {
2143 * Fetch the next transfer descriptor and transfer
2144 * some flags to the next transfer descriptor
2147 xfer->td_transfer_cache = td;
2150 return (1); /* not complete */
2152 /* compute all actual lengths */
2153 musbotg_standard_done(xfer);
2155 return (0); /* complete */
2159 musbotg_interrupt_poll(struct musbotg_softc *sc)
2161 struct usb_xfer *xfer;
2164 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
2165 if (!musbotg_xfer_do_fifo(xfer)) {
2166 /* queue has been modified */
2173 musbotg_vbus_interrupt(struct musbotg_softc *sc, uint8_t is_on)
2175 DPRINTFN(4, "vbus = %u\n", is_on);
2177 USB_BUS_LOCK(&sc->sc_bus);
2179 if (!sc->sc_flags.status_vbus) {
2180 sc->sc_flags.status_vbus = 1;
2182 /* complete root HUB interrupt endpoint */
2183 musbotg_root_intr(sc);
2186 if (sc->sc_flags.status_vbus) {
2187 sc->sc_flags.status_vbus = 0;
2188 sc->sc_flags.status_bus_reset = 0;
2189 sc->sc_flags.status_suspend = 0;
2190 sc->sc_flags.change_suspend = 0;
2191 sc->sc_flags.change_connect = 1;
2193 /* complete root HUB interrupt endpoint */
2194 musbotg_root_intr(sc);
2198 USB_BUS_UNLOCK(&sc->sc_bus);
2202 musbotg_connect_interrupt(struct musbotg_softc *sc)
2204 USB_BUS_LOCK(&sc->sc_bus);
2205 sc->sc_flags.change_connect = 1;
2207 /* complete root HUB interrupt endpoint */
2208 musbotg_root_intr(sc);
2209 USB_BUS_UNLOCK(&sc->sc_bus);
2213 musbotg_interrupt(struct musbotg_softc *sc,
2214 uint16_t rxstat, uint16_t txstat, uint8_t stat)
2222 USB_BUS_LOCK(&sc->sc_bus);
2226 /* read all interrupt registers */
2227 usb_status = MUSB2_READ_1(sc, MUSB2_REG_INTUSB);
2229 /* read all FIFO interrupts */
2230 rx_status = MUSB2_READ_2(sc, MUSB2_REG_INTRX);
2231 tx_status = MUSB2_READ_2(sc, MUSB2_REG_INTTX);
2232 rx_status |= rxstat;
2233 tx_status |= txstat;
2236 /* Clear platform flags after first time */
2241 /* check for any bus state change interrupts */
2243 if (usb_status & (MUSB2_MASK_IRESET |
2244 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP |
2245 MUSB2_MASK_ICONN | MUSB2_MASK_IDISC)) {
2247 DPRINTFN(4, "real bus interrupt 0x%08x\n", usb_status);
2249 if (usb_status & MUSB2_MASK_IRESET) {
2251 /* set correct state */
2252 sc->sc_flags.status_bus_reset = 1;
2253 sc->sc_flags.status_suspend = 0;
2254 sc->sc_flags.change_suspend = 0;
2255 sc->sc_flags.change_connect = 1;
2257 /* determine line speed */
2258 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
2259 if (temp & MUSB2_MASK_HSMODE)
2260 sc->sc_flags.status_high_speed = 1;
2262 sc->sc_flags.status_high_speed = 0;
2265 * After reset all interrupts are on and we need to
2268 temp = MUSB2_MASK_IRESET;
2269 /* disable resume interrupt */
2270 temp &= ~MUSB2_MASK_IRESUME;
2271 /* enable suspend interrupt */
2272 temp |= MUSB2_MASK_ISUSP;
2273 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp);
2274 /* disable TX and RX interrupts */
2275 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0);
2276 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0);
2279 * If RXRSM and RXSUSP is set at the same time we interpret
2280 * that like RESUME. Resume is set when there is at least 3
2281 * milliseconds of inactivity on the USB BUS.
2283 if (usb_status & MUSB2_MASK_IRESUME) {
2284 if (sc->sc_flags.status_suspend) {
2285 sc->sc_flags.status_suspend = 0;
2286 sc->sc_flags.change_suspend = 1;
2288 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE);
2289 /* disable resume interrupt */
2290 temp &= ~MUSB2_MASK_IRESUME;
2291 /* enable suspend interrupt */
2292 temp |= MUSB2_MASK_ISUSP;
2293 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp);
2295 } else if (usb_status & MUSB2_MASK_ISUSP) {
2296 if (!sc->sc_flags.status_suspend) {
2297 sc->sc_flags.status_suspend = 1;
2298 sc->sc_flags.change_suspend = 1;
2300 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE);
2301 /* disable suspend interrupt */
2302 temp &= ~MUSB2_MASK_ISUSP;
2303 /* enable resume interrupt */
2304 temp |= MUSB2_MASK_IRESUME;
2305 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp);
2309 (MUSB2_MASK_ICONN | MUSB2_MASK_IDISC))
2310 sc->sc_flags.change_connect = 1;
2313 * Host Mode: There is no IRESET so assume bus is
2314 * always in reset state once device is connected.
2316 if (sc->sc_mode == MUSB2_HOST_MODE) {
2317 if (usb_status & MUSB2_MASK_ICONN)
2318 sc->sc_flags.status_bus_reset = 1;
2319 if (usb_status & MUSB2_MASK_IDISC)
2320 sc->sc_flags.status_bus_reset = 0;
2323 /* complete root HUB interrupt endpoint */
2324 musbotg_root_intr(sc);
2326 /* check for any endpoint interrupts */
2328 if (rx_status || tx_status) {
2329 DPRINTFN(4, "real endpoint interrupt "
2330 "rx=0x%04x, tx=0x%04x\n", rx_status, tx_status);
2332 /* poll one time regardless of FIFO status */
2334 musbotg_interrupt_poll(sc);
2339 USB_BUS_UNLOCK(&sc->sc_bus);
2343 musbotg_setup_standard_chain_sub(struct musbotg_std_temp *temp)
2345 struct musbotg_td *td;
2347 /* get current Transfer Descriptor */
2351 /* prepare for next TD */
2352 temp->td_next = td->obj_next;
2354 /* fill out the Transfer Descriptor */
2355 td->func = temp->func;
2357 td->offset = temp->offset;
2358 td->remainder = temp->len;
2360 td->transaction_started = 0;
2361 td->did_stall = temp->did_stall;
2362 td->short_pkt = temp->short_pkt;
2363 td->alt_next = temp->setup_alt_next;
2364 td->channel = temp->channel;
2365 td->dev_addr = temp->dev_addr;
2366 td->haddr = temp->haddr;
2367 td->hport = temp->hport;
2368 td->transfer_type = temp->transfer_type;
2372 musbotg_setup_standard_chain(struct usb_xfer *xfer)
2374 struct musbotg_std_temp temp;
2375 struct musbotg_softc *sc;
2376 struct musbotg_td *td;
2380 enum usb_dev_speed speed;
2384 DPRINTFN(8, "addr=%d endpt=%d sumlen=%d speed=%d\n",
2385 xfer->address, UE_GET_ADDR(xfer->endpointno),
2386 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
2388 sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
2389 ep_no = (xfer->endpointno & UE_ADDR);
2391 temp.max_frame_size = xfer->max_frame_size;
2393 td = xfer->td_start[0];
2394 xfer->td_transfer_first = td;
2395 xfer->td_transfer_cache = td;
2398 dev_addr = xfer->address;
2400 xfer_type = xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE;
2404 temp.td_next = xfer->td_start[0];
2406 temp.setup_alt_next = xfer->flags_int.short_frames_ok;
2407 temp.did_stall = !xfer->flags_int.control_stall;
2409 temp.dev_addr = dev_addr;
2410 temp.haddr = xfer->xroot->udev->hs_hub_addr;
2411 temp.hport = xfer->xroot->udev->hs_port_no;
2413 if (xfer->flags_int.usb_mode == USB_MODE_HOST) {
2414 speed = usbd_get_speed(xfer->xroot->udev);
2418 temp.transfer_type = MUSB2_MASK_TI_SPEED_LO;
2420 case USB_SPEED_FULL:
2421 temp.transfer_type = MUSB2_MASK_TI_SPEED_FS;
2423 case USB_SPEED_HIGH:
2424 temp.transfer_type = MUSB2_MASK_TI_SPEED_HS;
2427 temp.transfer_type = 0;
2428 DPRINTFN(-1, "Invalid USB speed: %d\n", speed);
2432 switch (xfer_type) {
2434 temp.transfer_type |= MUSB2_MASK_TI_PROTO_CTRL;
2436 case UE_ISOCHRONOUS:
2437 temp.transfer_type |= MUSB2_MASK_TI_PROTO_ISOC;
2440 temp.transfer_type |= MUSB2_MASK_TI_PROTO_BULK;
2443 temp.transfer_type |= MUSB2_MASK_TI_PROTO_INTR;
2446 DPRINTFN(-1, "Invalid USB transfer type: %d\n",
2451 temp.transfer_type |= ep_no;
2452 td->toggle = xfer->endpoint->toggle_next;
2455 /* check if we should prepend a setup message */
2457 if (xfer->flags_int.control_xfr) {
2458 if (xfer->flags_int.control_hdr) {
2460 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE)
2461 temp.func = &musbotg_dev_ctrl_setup_rx;
2463 temp.func = &musbotg_host_ctrl_setup_tx;
2465 temp.len = xfer->frlengths[0];
2466 temp.pc = xfer->frbuffers + 0;
2467 temp.short_pkt = temp.len ? 1 : 0;
2469 musbotg_setup_standard_chain_sub(&temp);
2478 if (x != xfer->nframes) {
2479 if (xfer->endpointno & UE_DIR_IN)
2482 if (xfer->flags_int.usb_mode == USB_MODE_HOST) {
2486 if (xfer->flags_int.control_xfr)
2487 temp.func = &musbotg_host_ctrl_data_tx;
2489 temp.func = &musbotg_host_data_tx;
2491 if (xfer->flags_int.control_xfr)
2492 temp.func = &musbotg_host_ctrl_data_rx;
2494 temp.func = &musbotg_host_data_rx;
2499 if (xfer->flags_int.control_xfr)
2500 temp.func = &musbotg_dev_ctrl_data_tx;
2502 temp.func = &musbotg_dev_data_tx;
2504 if (xfer->flags_int.control_xfr)
2505 temp.func = &musbotg_dev_ctrl_data_rx;
2507 temp.func = &musbotg_dev_data_rx;
2511 /* setup "pc" pointer */
2512 temp.pc = xfer->frbuffers + x;
2514 while (x != xfer->nframes) {
2516 /* DATA0 / DATA1 message */
2518 temp.len = xfer->frlengths[x];
2522 if (x == xfer->nframes) {
2523 if (xfer->flags_int.control_xfr) {
2524 if (xfer->flags_int.control_act) {
2525 temp.setup_alt_next = 0;
2528 temp.setup_alt_next = 0;
2531 if (temp.len == 0) {
2533 /* make sure that we send an USB packet */
2539 if (xfer->flags_int.isochronous_xfr) {
2540 /* isochronous data transfer */
2541 /* don't force short */
2544 /* regular data transfer */
2545 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1);
2549 musbotg_setup_standard_chain_sub(&temp);
2551 if (xfer->flags_int.isochronous_xfr) {
2552 temp.offset += temp.len;
2554 /* get next Page Cache pointer */
2555 temp.pc = xfer->frbuffers + x;
2559 /* check for control transfer */
2560 if (xfer->flags_int.control_xfr) {
2562 /* always setup a valid "pc" pointer for status and sync */
2563 temp.pc = xfer->frbuffers + 0;
2566 temp.setup_alt_next = 0;
2568 /* check if we should append a status stage */
2569 if (!xfer->flags_int.control_act) {
2571 * Send a DATA1 message and invert the current
2572 * endpoint direction.
2574 if (sc->sc_mode == MUSB2_DEVICE_MODE)
2575 temp.func = &musbotg_dev_ctrl_status;
2577 if (xfer->endpointno & UE_DIR_IN)
2578 temp.func = musbotg_host_ctrl_status_tx;
2580 temp.func = musbotg_host_ctrl_status_rx;
2582 musbotg_setup_standard_chain_sub(&temp);
2585 /* must have at least one frame! */
2587 xfer->td_transfer_last = td;
2591 musbotg_timeout(void *arg)
2593 struct usb_xfer *xfer = arg;
2595 DPRINTFN(1, "xfer=%p\n", xfer);
2597 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
2599 /* transfer is transferred */
2600 musbotg_device_done(xfer, USB_ERR_TIMEOUT);
2604 musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on)
2609 * Only enable the endpoint interrupt when we are
2610 * actually waiting for data, hence we are dealing
2611 * with level triggered interrupts !
2613 DPRINTFN(1, "ep_no=%d, on=%d\n", channel, on);
2619 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE);
2621 temp |= MUSB2_MASK_EPINT(0);
2623 temp &= ~MUSB2_MASK_EPINT(0);
2625 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp);
2627 temp = MUSB2_READ_2(sc, MUSB2_REG_INTRXE);
2629 temp |= MUSB2_MASK_EPINT(channel);
2631 temp &= ~MUSB2_MASK_EPINT(channel);
2632 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, temp);
2634 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE);
2636 temp |= MUSB2_MASK_EPINT(channel);
2638 temp &= ~MUSB2_MASK_EPINT(channel);
2639 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp);
2642 if (sc->sc_ep_int_set)
2643 sc->sc_ep_int_set(sc, channel, on);
2647 musbotg_start_standard_chain(struct usb_xfer *xfer)
2652 if (musbotg_xfer_do_fifo(xfer)) {
2654 DPRINTFN(14, "enabled interrupts on endpoint\n");
2656 /* put transfer on interrupt queue */
2657 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
2659 /* start timeout, if any */
2660 if (xfer->timeout != 0) {
2661 usbd_transfer_timeout_ms(xfer,
2662 &musbotg_timeout, xfer->timeout);
2668 musbotg_root_intr(struct musbotg_softc *sc)
2672 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2675 sc->sc_hub_idata[0] = 0x02; /* we only have one port */
2677 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2678 sizeof(sc->sc_hub_idata));
2682 musbotg_standard_done_sub(struct usb_xfer *xfer)
2684 struct musbotg_td *td;
2690 td = xfer->td_transfer_cache;
2693 len = td->remainder;
2695 xfer->endpoint->toggle_next = td->toggle;
2697 if (xfer->aframes != xfer->nframes) {
2699 * Verify the length and subtract
2700 * the remainder from "frlengths[]":
2702 if (len > xfer->frlengths[xfer->aframes]) {
2705 xfer->frlengths[xfer->aframes] -= len;
2708 /* Check for transfer error */
2710 /* the transfer is finished */
2715 /* Check for short transfer */
2717 if (xfer->flags_int.short_frames_ok) {
2718 /* follow alt next */
2725 /* the transfer is finished */
2733 /* this USB frame is complete */
2739 /* update transfer cache */
2741 xfer->td_transfer_cache = td;
2744 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
2748 musbotg_standard_done(struct usb_xfer *xfer)
2750 usb_error_t err = 0;
2752 DPRINTFN(12, "xfer=%p endpoint=%p transfer done\n",
2753 xfer, xfer->endpoint);
2757 xfer->td_transfer_cache = xfer->td_transfer_first;
2759 if (xfer->flags_int.control_xfr) {
2761 if (xfer->flags_int.control_hdr) {
2763 err = musbotg_standard_done_sub(xfer);
2767 if (xfer->td_transfer_cache == NULL) {
2771 while (xfer->aframes != xfer->nframes) {
2773 err = musbotg_standard_done_sub(xfer);
2776 if (xfer->td_transfer_cache == NULL) {
2781 if (xfer->flags_int.control_xfr &&
2782 !xfer->flags_int.control_act) {
2784 err = musbotg_standard_done_sub(xfer);
2787 musbotg_device_done(xfer, err);
2790 /*------------------------------------------------------------------------*
2791 * musbotg_device_done
2793 * NOTE: this function can be called more than one time on the
2794 * same USB transfer!
2795 *------------------------------------------------------------------------*/
2797 musbotg_device_done(struct usb_xfer *xfer, usb_error_t error)
2799 struct musbotg_td *td;
2800 struct musbotg_softc *sc;
2802 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
2804 DPRINTFN(1, "xfer=%p, endpoint=%p, error=%d\n",
2805 xfer, xfer->endpoint, error);
2807 DPRINTFN(14, "disabled interrupts on endpoint\n");
2809 sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
2810 td = xfer->td_transfer_cache;
2812 if (td && (td->channel != -1))
2813 musbotg_channel_free(sc, td);
2815 /* dequeue transfer and start next transfer */
2816 usbd_transfer_done(xfer, error);
2820 musbotg_xfer_stall(struct usb_xfer *xfer)
2822 musbotg_device_done(xfer, USB_ERR_STALLED);
2826 musbotg_set_stall(struct usb_device *udev,
2827 struct usb_endpoint *ep, uint8_t *did_stall)
2829 struct musbotg_softc *sc;
2832 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
2834 DPRINTFN(4, "endpoint=%p\n", ep);
2836 /* set FORCESTALL */
2837 sc = MUSBOTG_BUS2SC(udev->bus);
2839 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR);
2841 /* select endpoint */
2842 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no);
2844 if (ep->edesc->bEndpointAddress & UE_DIR_IN) {
2845 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2846 MUSB2_MASK_CSRL_TXSENDSTALL);
2848 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
2849 MUSB2_MASK_CSRL_RXSENDSTALL);
2854 musbotg_clear_stall_sub(struct musbotg_softc *sc, uint16_t wMaxPacket,
2855 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir)
2861 if (ep_type == UE_CONTROL) {
2862 /* clearing stall is not needed */
2865 /* select endpoint */
2866 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no);
2868 /* compute max frame size */
2869 mps = wMaxPacket & 0x7FF;
2870 switch ((wMaxPacket >> 11) & 3) {
2881 if (ep_dir == UE_DIR_IN) {
2885 /* Configure endpoint */
2888 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket);
2889 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH,
2890 MUSB2_MASK_CSRH_TXMODE | temp);
2892 case UE_ISOCHRONOUS:
2893 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket);
2894 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH,
2895 MUSB2_MASK_CSRH_TXMODE |
2896 MUSB2_MASK_CSRH_TXISO | temp);
2899 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket);
2900 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH,
2901 MUSB2_MASK_CSRH_TXMODE | temp);
2907 /* Need to flush twice in case of double bufring */
2908 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2909 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
2910 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2911 MUSB2_MASK_CSRL_TXFFLUSH);
2912 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2913 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
2914 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2915 MUSB2_MASK_CSRL_TXFFLUSH);
2916 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2919 /* reset data toggle */
2920 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2921 MUSB2_MASK_CSRL_TXDT_CLR);
2922 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
2923 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2925 /* set double/single buffering */
2926 temp = MUSB2_READ_2(sc, MUSB2_REG_TXDBDIS);
2927 if (mps <= (sc->sc_hw_ep_profile[ep_no].
2928 max_in_frame_size / 2)) {
2930 temp &= ~(1 << ep_no);
2933 temp |= (1 << ep_no);
2935 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, temp);
2937 /* clear sent stall */
2938 if (csr & MUSB2_MASK_CSRL_TXSENTSTALL) {
2939 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
2940 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2946 /* Configure endpoint */
2949 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket);
2950 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH,
2951 MUSB2_MASK_CSRH_RXNYET | temp);
2953 case UE_ISOCHRONOUS:
2954 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket);
2955 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH,
2956 MUSB2_MASK_CSRH_RXNYET |
2957 MUSB2_MASK_CSRH_RXISO | temp);
2960 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket);
2961 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, temp);
2967 /* Need to flush twice in case of double bufring */
2968 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
2969 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) {
2970 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
2971 MUSB2_MASK_CSRL_RXFFLUSH);
2972 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
2973 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) {
2974 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
2975 MUSB2_MASK_CSRL_RXFFLUSH);
2976 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
2979 /* reset data toggle */
2980 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
2981 MUSB2_MASK_CSRL_RXDT_CLR);
2982 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
2983 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
2985 /* set double/single buffering */
2986 temp = MUSB2_READ_2(sc, MUSB2_REG_RXDBDIS);
2987 if (mps <= (sc->sc_hw_ep_profile[ep_no].
2988 max_out_frame_size / 2)) {
2990 temp &= ~(1 << ep_no);
2993 temp |= (1 << ep_no);
2995 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, temp);
2997 /* clear sent stall */
2998 if (csr & MUSB2_MASK_CSRL_RXSENTSTALL) {
2999 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
3005 musbotg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
3007 struct musbotg_softc *sc;
3008 struct usb_endpoint_descriptor *ed;
3010 DPRINTFN(4, "endpoint=%p\n", ep);
3012 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
3015 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
3020 sc = MUSBOTG_BUS2SC(udev->bus);
3022 /* get endpoint descriptor */
3025 /* reset endpoint */
3026 musbotg_clear_stall_sub(sc,
3027 UGETW(ed->wMaxPacketSize),
3028 (ed->bEndpointAddress & UE_ADDR),
3029 (ed->bmAttributes & UE_XFERTYPE),
3030 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
3034 musbotg_init(struct musbotg_softc *sc)
3036 struct usb_hw_ep_profile *pf;
3046 DPRINTFN(1, "start\n");
3048 /* set up the bus structure */
3049 sc->sc_bus.usbrev = USB_REV_2_0;
3050 sc->sc_bus.methods = &musbotg_bus_methods;
3052 USB_BUS_LOCK(&sc->sc_bus);
3054 /* turn on clocks */
3056 if (sc->sc_clocks_on) {
3057 (sc->sc_clocks_on) (sc->sc_clocks_arg);
3060 /* wait a little for things to stabilise */
3061 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
3063 /* disable all interrupts */
3065 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
3066 DPRINTF("pre-DEVCTL=0x%02x\n", temp);
3068 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0);
3069 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0);
3070 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0);
3072 /* disable pullup */
3074 musbotg_pull_common(sc, 0);
3076 /* wait a little bit (10ms) */
3077 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
3080 /* disable double packet buffering */
3081 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, 0xFFFF);
3082 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, 0xFFFF);
3084 /* enable HighSpeed and ISO Update flags */
3086 MUSB2_WRITE_1(sc, MUSB2_REG_POWER,
3087 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD);
3089 if (sc->sc_mode == MUSB2_DEVICE_MODE) {
3090 /* clear Session bit, if set */
3091 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
3092 temp &= ~MUSB2_MASK_SESS;
3093 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp);
3095 /* Enter session for Host mode */
3096 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
3097 temp |= MUSB2_MASK_SESS;
3098 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp);
3101 /* wait a little for things to stabilise */
3102 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10);
3104 DPRINTF("DEVCTL=0x%02x\n", temp);
3106 /* disable testmode */
3108 MUSB2_WRITE_1(sc, MUSB2_REG_TESTMODE, 0);
3110 /* set default value */
3112 MUSB2_WRITE_1(sc, MUSB2_REG_MISC, 0);
3114 /* select endpoint index 0 */
3116 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
3118 /* read out number of endpoints */
3121 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) / 16);
3124 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) % 16);
3126 /* these numbers exclude the control endpoint */
3128 DPRINTFN(2, "RX/TX endpoints: %u/%u\n", nrx, ntx);
3130 sc->sc_ep_max = (nrx > ntx) ? nrx : ntx;
3131 if (sc->sc_ep_max == 0) {
3132 DPRINTFN(2, "ERROR: Looks like the clocks are off!\n");
3134 /* read out configuration data */
3136 sc->sc_conf_data = MUSB2_READ_1(sc, MUSB2_REG_CONFDATA);
3138 DPRINTFN(2, "Config Data: 0x%02x\n",
3141 dynfifo = (sc->sc_conf_data & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0;
3144 device_printf(sc->sc_bus.bdev, "Dynamic FIFO sizing detected, "
3145 "assuming 16Kbytes of FIFO RAM\n");
3148 DPRINTFN(2, "HW version: 0x%04x\n",
3149 MUSB2_READ_1(sc, MUSB2_REG_HWVERS));
3151 /* initialise endpoint profiles */
3155 for (temp = 1; temp <= sc->sc_ep_max; temp++) {
3156 pf = sc->sc_hw_ep_profile + temp;
3158 /* select endpoint */
3159 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, temp);
3161 fsize = MUSB2_READ_1(sc, MUSB2_REG_FSIZE);
3162 frx = (fsize & MUSB2_MASK_RX_FSIZE) / 16;
3163 ftx = (fsize & MUSB2_MASK_TX_FSIZE);
3165 DPRINTF("Endpoint %u FIFO size: IN=%u, OUT=%u, DYN=%d\n",
3166 temp, ftx, frx, dynfifo);
3169 if (frx && (temp <= nrx)) {
3172 MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ,
3173 MUSB2_VAL_FIFOSZ_4096 |
3175 } else if (temp < 8) {
3177 MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ,
3178 MUSB2_VAL_FIFOSZ_512 |
3181 frx = 7; /* 128 bytes */
3182 MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ,
3183 MUSB2_VAL_FIFOSZ_128);
3186 MUSB2_WRITE_2(sc, MUSB2_REG_RXFIFOADD,
3189 offset += (1 << frx);
3191 if (ftx && (temp <= ntx)) {
3194 MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ,
3195 MUSB2_VAL_FIFOSZ_4096 |
3197 } else if (temp < 8) {
3199 MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ,
3200 MUSB2_VAL_FIFOSZ_512 |
3203 ftx = 7; /* 128 bytes */
3204 MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ,
3205 MUSB2_VAL_FIFOSZ_128);
3208 MUSB2_WRITE_2(sc, MUSB2_REG_TXFIFOADD,
3211 offset += (1 << ftx);
3215 if (frx && ftx && (temp <= nrx) && (temp <= ntx)) {
3216 pf->max_in_frame_size = 1 << ftx;
3217 pf->max_out_frame_size = 1 << frx;
3218 pf->is_simplex = 0; /* duplex */
3219 pf->support_multi_buffer = 1;
3220 pf->support_bulk = 1;
3221 pf->support_interrupt = 1;
3222 pf->support_isochronous = 1;
3224 pf->support_out = 1;
3225 } else if (frx && (temp <= nrx)) {
3226 pf->max_out_frame_size = 1 << frx;
3227 pf->is_simplex = 1; /* simplex */
3228 pf->support_multi_buffer = 1;
3229 pf->support_bulk = 1;
3230 pf->support_interrupt = 1;
3231 pf->support_isochronous = 1;
3232 pf->support_out = 1;
3233 } else if (ftx && (temp <= ntx)) {
3234 pf->max_in_frame_size = 1 << ftx;
3235 pf->is_simplex = 1; /* simplex */
3236 pf->support_multi_buffer = 1;
3237 pf->support_bulk = 1;
3238 pf->support_interrupt = 1;
3239 pf->support_isochronous = 1;
3244 DPRINTFN(2, "Dynamic FIFO size = %d bytes\n", offset);
3246 /* turn on default interrupts */
3248 if (sc->sc_mode == MUSB2_HOST_MODE)
3249 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0xff);
3251 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE,
3254 musbotg_clocks_off(sc);
3256 USB_BUS_UNLOCK(&sc->sc_bus);
3258 /* catch any lost interrupts */
3260 musbotg_do_poll(&sc->sc_bus);
3262 return (0); /* success */
3266 musbotg_uninit(struct musbotg_softc *sc)
3268 USB_BUS_LOCK(&sc->sc_bus);
3270 /* disable all interrupts */
3271 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0);
3272 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0);
3273 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0);
3275 sc->sc_flags.port_powered = 0;
3276 sc->sc_flags.status_vbus = 0;
3277 sc->sc_flags.status_bus_reset = 0;
3278 sc->sc_flags.status_suspend = 0;
3279 sc->sc_flags.change_suspend = 0;
3280 sc->sc_flags.change_connect = 1;
3282 musbotg_pull_down(sc);
3283 musbotg_clocks_off(sc);
3284 USB_BUS_UNLOCK(&sc->sc_bus);
3288 musbotg_suspend(struct musbotg_softc *sc)
3294 musbotg_resume(struct musbotg_softc *sc)
3300 musbotg_do_poll(struct usb_bus *bus)
3302 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus);
3304 USB_BUS_LOCK(&sc->sc_bus);
3305 musbotg_interrupt_poll(sc);
3306 USB_BUS_UNLOCK(&sc->sc_bus);
3309 /*------------------------------------------------------------------------*
3310 * musbotg bulk support
3311 *------------------------------------------------------------------------*/
3313 musbotg_device_bulk_open(struct usb_xfer *xfer)
3319 musbotg_device_bulk_close(struct usb_xfer *xfer)
3321 musbotg_device_done(xfer, USB_ERR_CANCELLED);
3325 musbotg_device_bulk_enter(struct usb_xfer *xfer)
3331 musbotg_device_bulk_start(struct usb_xfer *xfer)
3334 musbotg_setup_standard_chain(xfer);
3335 musbotg_start_standard_chain(xfer);
3338 struct usb_pipe_methods musbotg_device_bulk_methods =
3340 .open = musbotg_device_bulk_open,
3341 .close = musbotg_device_bulk_close,
3342 .enter = musbotg_device_bulk_enter,
3343 .start = musbotg_device_bulk_start,
3346 /*------------------------------------------------------------------------*
3347 * musbotg control support
3348 *------------------------------------------------------------------------*/
3350 musbotg_device_ctrl_open(struct usb_xfer *xfer)
3356 musbotg_device_ctrl_close(struct usb_xfer *xfer)
3358 musbotg_device_done(xfer, USB_ERR_CANCELLED);
3362 musbotg_device_ctrl_enter(struct usb_xfer *xfer)
3368 musbotg_device_ctrl_start(struct usb_xfer *xfer)
3371 musbotg_setup_standard_chain(xfer);
3372 musbotg_start_standard_chain(xfer);
3375 struct usb_pipe_methods musbotg_device_ctrl_methods =
3377 .open = musbotg_device_ctrl_open,
3378 .close = musbotg_device_ctrl_close,
3379 .enter = musbotg_device_ctrl_enter,
3380 .start = musbotg_device_ctrl_start,
3383 /*------------------------------------------------------------------------*
3384 * musbotg interrupt support
3385 *------------------------------------------------------------------------*/
3387 musbotg_device_intr_open(struct usb_xfer *xfer)
3393 musbotg_device_intr_close(struct usb_xfer *xfer)
3395 musbotg_device_done(xfer, USB_ERR_CANCELLED);
3399 musbotg_device_intr_enter(struct usb_xfer *xfer)
3405 musbotg_device_intr_start(struct usb_xfer *xfer)
3408 musbotg_setup_standard_chain(xfer);
3409 musbotg_start_standard_chain(xfer);
3412 struct usb_pipe_methods musbotg_device_intr_methods =
3414 .open = musbotg_device_intr_open,
3415 .close = musbotg_device_intr_close,
3416 .enter = musbotg_device_intr_enter,
3417 .start = musbotg_device_intr_start,
3420 /*------------------------------------------------------------------------*
3421 * musbotg full speed isochronous support
3422 *------------------------------------------------------------------------*/
3424 musbotg_device_isoc_open(struct usb_xfer *xfer)
3430 musbotg_device_isoc_close(struct usb_xfer *xfer)
3432 musbotg_device_done(xfer, USB_ERR_CANCELLED);
3436 musbotg_device_isoc_enter(struct usb_xfer *xfer)
3438 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
3443 DPRINTFN(5, "xfer=%p next=%d nframes=%d\n",
3444 xfer, xfer->endpoint->isoc_next, xfer->nframes);
3446 /* get the current frame index */
3448 nframes = MUSB2_READ_2(sc, MUSB2_REG_FRAME);
3451 * check if the frame index is within the window where the frames
3454 temp = (nframes - xfer->endpoint->isoc_next) & MUSB2_MASK_FRAME;
3456 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) {
3457 fs_frames = (xfer->nframes + 7) / 8;
3459 fs_frames = xfer->nframes;
3462 if ((xfer->endpoint->is_synced == 0) ||
3463 (temp < fs_frames)) {
3465 * If there is data underflow or the pipe queue is
3466 * empty we schedule the transfer a few frames ahead
3467 * of the current frame position. Else two isochronous
3468 * transfers might overlap.
3470 xfer->endpoint->isoc_next = (nframes + 3) & MUSB2_MASK_FRAME;
3471 xfer->endpoint->is_synced = 1;
3472 DPRINTFN(2, "start next=%d\n", xfer->endpoint->isoc_next);
3475 * compute how many milliseconds the insertion is ahead of the
3476 * current frame position:
3478 temp = (xfer->endpoint->isoc_next - nframes) & MUSB2_MASK_FRAME;
3481 * pre-compute when the isochronous transfer will be finished:
3483 xfer->isoc_time_complete =
3484 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
3487 /* compute frame number for next insertion */
3488 xfer->endpoint->isoc_next += fs_frames;
3491 musbotg_setup_standard_chain(xfer);
3495 musbotg_device_isoc_start(struct usb_xfer *xfer)
3497 /* start TD chain */
3498 musbotg_start_standard_chain(xfer);
3501 struct usb_pipe_methods musbotg_device_isoc_methods =
3503 .open = musbotg_device_isoc_open,
3504 .close = musbotg_device_isoc_close,
3505 .enter = musbotg_device_isoc_enter,
3506 .start = musbotg_device_isoc_start,
3509 /*------------------------------------------------------------------------*
3510 * musbotg root control support
3511 *------------------------------------------------------------------------*
3512 * Simulate a hardware HUB by handling all the necessary requests.
3513 *------------------------------------------------------------------------*/
3515 static const struct usb_device_descriptor musbotg_devd = {
3516 .bLength = sizeof(struct usb_device_descriptor),
3517 .bDescriptorType = UDESC_DEVICE,
3518 .bcdUSB = {0x00, 0x02},
3519 .bDeviceClass = UDCLASS_HUB,
3520 .bDeviceSubClass = UDSUBCLASS_HUB,
3521 .bDeviceProtocol = UDPROTO_HSHUBSTT,
3522 .bMaxPacketSize = 64,
3523 .bcdDevice = {0x00, 0x01},
3526 .bNumConfigurations = 1,
3529 static const struct usb_device_qualifier musbotg_odevd = {
3530 .bLength = sizeof(struct usb_device_qualifier),
3531 .bDescriptorType = UDESC_DEVICE_QUALIFIER,
3532 .bcdUSB = {0x00, 0x02},
3533 .bDeviceClass = UDCLASS_HUB,
3534 .bDeviceSubClass = UDSUBCLASS_HUB,
3535 .bDeviceProtocol = UDPROTO_FSHUB,
3536 .bMaxPacketSize0 = 0,
3537 .bNumConfigurations = 0,
3540 static const struct musbotg_config_desc musbotg_confd = {
3542 .bLength = sizeof(struct usb_config_descriptor),
3543 .bDescriptorType = UDESC_CONFIG,
3544 .wTotalLength[0] = sizeof(musbotg_confd),
3546 .bConfigurationValue = 1,
3547 .iConfiguration = 0,
3548 .bmAttributes = UC_SELF_POWERED,
3552 .bLength = sizeof(struct usb_interface_descriptor),
3553 .bDescriptorType = UDESC_INTERFACE,
3555 .bInterfaceClass = UICLASS_HUB,
3556 .bInterfaceSubClass = UISUBCLASS_HUB,
3557 .bInterfaceProtocol = 0,
3560 .bLength = sizeof(struct usb_endpoint_descriptor),
3561 .bDescriptorType = UDESC_ENDPOINT,
3562 .bEndpointAddress = (UE_DIR_IN | MUSBOTG_INTR_ENDPT),
3563 .bmAttributes = UE_INTERRUPT,
3564 .wMaxPacketSize[0] = 8,
3569 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3571 static const struct usb_hub_descriptor_min musbotg_hubd = {
3572 .bDescLength = sizeof(musbotg_hubd),
3573 .bDescriptorType = UDESC_HUB,
3575 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)),
3576 .bPwrOn2PwrGood = 50,
3577 .bHubContrCurrent = 0,
3578 .DeviceRemovable = {0}, /* port is removable */
3581 #define STRING_VENDOR \
3582 "M\0e\0n\0t\0o\0r\0 \0G\0r\0a\0p\0h\0i\0c\0s"
3584 #define STRING_PRODUCT \
3585 "O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B"
3587 USB_MAKE_STRING_DESC(STRING_VENDOR, musbotg_vendor);
3588 USB_MAKE_STRING_DESC(STRING_PRODUCT, musbotg_product);
3591 musbotg_roothub_exec(struct usb_device *udev,
3592 struct usb_device_request *req, const void **pptr, uint16_t *plength)
3594 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus);
3602 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3605 ptr = (const void *)&sc->sc_hub_temp;
3609 value = UGETW(req->wValue);
3610 index = UGETW(req->wIndex);
3612 /* demultiplex the control request */
3614 switch (req->bmRequestType) {
3615 case UT_READ_DEVICE:
3616 switch (req->bRequest) {
3617 case UR_GET_DESCRIPTOR:
3618 goto tr_handle_get_descriptor;
3620 goto tr_handle_get_config;
3622 goto tr_handle_get_status;
3628 case UT_WRITE_DEVICE:
3629 switch (req->bRequest) {
3630 case UR_SET_ADDRESS:
3631 goto tr_handle_set_address;
3633 goto tr_handle_set_config;
3634 case UR_CLEAR_FEATURE:
3635 goto tr_valid; /* nop */
3636 case UR_SET_DESCRIPTOR:
3637 goto tr_valid; /* nop */
3638 case UR_SET_FEATURE:
3644 case UT_WRITE_ENDPOINT:
3645 switch (req->bRequest) {
3646 case UR_CLEAR_FEATURE:
3647 switch (UGETW(req->wValue)) {
3648 case UF_ENDPOINT_HALT:
3649 goto tr_handle_clear_halt;
3650 case UF_DEVICE_REMOTE_WAKEUP:
3651 goto tr_handle_clear_wakeup;
3656 case UR_SET_FEATURE:
3657 switch (UGETW(req->wValue)) {
3658 case UF_ENDPOINT_HALT:
3659 goto tr_handle_set_halt;
3660 case UF_DEVICE_REMOTE_WAKEUP:
3661 goto tr_handle_set_wakeup;
3666 case UR_SYNCH_FRAME:
3667 goto tr_valid; /* nop */
3673 case UT_READ_ENDPOINT:
3674 switch (req->bRequest) {
3676 goto tr_handle_get_ep_status;
3682 case UT_WRITE_INTERFACE:
3683 switch (req->bRequest) {
3684 case UR_SET_INTERFACE:
3685 goto tr_handle_set_interface;
3686 case UR_CLEAR_FEATURE:
3687 goto tr_valid; /* nop */
3688 case UR_SET_FEATURE:
3694 case UT_READ_INTERFACE:
3695 switch (req->bRequest) {
3696 case UR_GET_INTERFACE:
3697 goto tr_handle_get_interface;
3699 goto tr_handle_get_iface_status;
3705 case UT_WRITE_CLASS_INTERFACE:
3706 case UT_WRITE_VENDOR_INTERFACE:
3710 case UT_READ_CLASS_INTERFACE:
3711 case UT_READ_VENDOR_INTERFACE:
3715 case UT_WRITE_CLASS_DEVICE:
3716 switch (req->bRequest) {
3717 case UR_CLEAR_FEATURE:
3719 case UR_SET_DESCRIPTOR:
3720 case UR_SET_FEATURE:
3727 case UT_WRITE_CLASS_OTHER:
3728 switch (req->bRequest) {
3729 case UR_CLEAR_FEATURE:
3730 goto tr_handle_clear_port_feature;
3731 case UR_SET_FEATURE:
3732 goto tr_handle_set_port_feature;
3733 case UR_CLEAR_TT_BUFFER:
3743 case UT_READ_CLASS_OTHER:
3744 switch (req->bRequest) {
3745 case UR_GET_TT_STATE:
3746 goto tr_handle_get_tt_state;
3748 goto tr_handle_get_port_status;
3754 case UT_READ_CLASS_DEVICE:
3755 switch (req->bRequest) {
3756 case UR_GET_DESCRIPTOR:
3757 goto tr_handle_get_class_descriptor;
3759 goto tr_handle_get_class_status;
3770 tr_handle_get_descriptor:
3771 switch (value >> 8) {
3776 len = sizeof(musbotg_devd);
3777 ptr = (const void *)&musbotg_devd;
3783 len = sizeof(musbotg_confd);
3784 ptr = (const void *)&musbotg_confd;
3787 switch (value & 0xff) {
3788 case 0: /* Language table */
3789 len = sizeof(usb_string_lang_en);
3790 ptr = (const void *)&usb_string_lang_en;
3793 case 1: /* Vendor */
3794 len = sizeof(musbotg_vendor);
3795 ptr = (const void *)&musbotg_vendor;
3798 case 2: /* Product */
3799 len = sizeof(musbotg_product);
3800 ptr = (const void *)&musbotg_product;
3811 tr_handle_get_config:
3813 sc->sc_hub_temp.wValue[0] = sc->sc_conf;
3816 tr_handle_get_status:
3818 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
3821 tr_handle_set_address:
3822 if (value & 0xFF00) {
3825 sc->sc_rt_addr = value;
3828 tr_handle_set_config:
3832 sc->sc_conf = value;
3835 tr_handle_get_interface:
3837 sc->sc_hub_temp.wValue[0] = 0;
3840 tr_handle_get_tt_state:
3841 tr_handle_get_class_status:
3842 tr_handle_get_iface_status:
3843 tr_handle_get_ep_status:
3845 USETW(sc->sc_hub_temp.wValue, 0);
3849 tr_handle_set_interface:
3850 tr_handle_set_wakeup:
3851 tr_handle_clear_wakeup:
3852 tr_handle_clear_halt:
3855 tr_handle_clear_port_feature:
3859 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE on port %d\n", index);
3862 case UHF_PORT_SUSPEND:
3863 if (sc->sc_mode == MUSB2_HOST_MODE)
3864 musbotg_wakeup_host(sc);
3866 musbotg_wakeup_peer(sc);
3869 case UHF_PORT_ENABLE:
3870 sc->sc_flags.port_enabled = 0;
3873 case UHF_C_PORT_ENABLE:
3874 sc->sc_flags.change_enabled = 0;
3877 case UHF_C_PORT_OVER_CURRENT:
3878 sc->sc_flags.change_over_current = 0;
3881 case UHF_C_PORT_RESET:
3882 sc->sc_flags.change_reset = 0;
3886 case UHF_PORT_INDICATOR:
3890 case UHF_PORT_POWER:
3891 sc->sc_flags.port_powered = 0;
3892 musbotg_pull_down(sc);
3893 musbotg_clocks_off(sc);
3895 case UHF_C_PORT_CONNECTION:
3896 sc->sc_flags.change_connect = 0;
3898 case UHF_C_PORT_SUSPEND:
3899 sc->sc_flags.change_suspend = 0;
3902 err = USB_ERR_IOERROR;
3907 tr_handle_set_port_feature:
3911 DPRINTFN(8, "UR_SET_PORT_FEATURE\n");
3914 case UHF_PORT_ENABLE:
3915 sc->sc_flags.port_enabled = 1;
3917 case UHF_PORT_SUSPEND:
3918 if (sc->sc_mode == MUSB2_HOST_MODE)
3919 musbotg_suspend_host(sc);
3922 case UHF_PORT_RESET:
3923 if (sc->sc_mode == MUSB2_HOST_MODE) {
3924 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER);
3925 reg |= MUSB2_MASK_RESET;
3926 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg);
3928 /* Wait for 20 msec */
3929 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 5);
3931 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER);
3932 reg &= ~MUSB2_MASK_RESET;
3933 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg);
3935 /* determine line speed */
3936 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER);
3937 if (reg & MUSB2_MASK_HSMODE)
3938 sc->sc_flags.status_high_speed = 1;
3940 sc->sc_flags.status_high_speed = 0;
3942 sc->sc_flags.change_reset = 1;
3944 err = USB_ERR_IOERROR;
3948 case UHF_PORT_INDICATOR:
3951 case UHF_PORT_POWER:
3952 sc->sc_flags.port_powered = 1;
3955 err = USB_ERR_IOERROR;
3960 tr_handle_get_port_status:
3962 DPRINTFN(8, "UR_GET_PORT_STATUS\n");
3967 if (sc->sc_flags.status_vbus) {
3968 musbotg_clocks_on(sc);
3969 musbotg_pull_up(sc);
3971 musbotg_pull_down(sc);
3972 musbotg_clocks_off(sc);
3975 /* Select Device Side Mode */
3976 if (sc->sc_mode == MUSB2_DEVICE_MODE)
3977 value = UPS_PORT_MODE_DEVICE;
3981 if (sc->sc_flags.status_high_speed) {
3982 value |= UPS_HIGH_SPEED;
3984 if (sc->sc_flags.port_powered) {
3985 value |= UPS_PORT_POWER;
3987 if (sc->sc_flags.port_enabled) {
3988 value |= UPS_PORT_ENABLED;
3991 if (sc->sc_flags.port_over_current)
3992 value |= UPS_OVERCURRENT_INDICATOR;
3994 if (sc->sc_flags.status_vbus &&
3995 sc->sc_flags.status_bus_reset) {
3996 value |= UPS_CURRENT_CONNECT_STATUS;
3998 if (sc->sc_flags.status_suspend) {
3999 value |= UPS_SUSPEND;
4001 USETW(sc->sc_hub_temp.ps.wPortStatus, value);
4005 if (sc->sc_flags.change_connect) {
4006 value |= UPS_C_CONNECT_STATUS;
4008 if (sc->sc_mode == MUSB2_DEVICE_MODE) {
4009 if (sc->sc_flags.status_vbus &&
4010 sc->sc_flags.status_bus_reset) {
4011 /* reset EP0 state */
4012 sc->sc_ep0_busy = 0;
4017 if (sc->sc_flags.change_suspend)
4018 value |= UPS_C_SUSPEND;
4019 if (sc->sc_flags.change_reset)
4020 value |= UPS_C_PORT_RESET;
4021 if (sc->sc_flags.change_over_current)
4022 value |= UPS_C_OVERCURRENT_INDICATOR;
4024 USETW(sc->sc_hub_temp.ps.wPortChange, value);
4025 len = sizeof(sc->sc_hub_temp.ps);
4028 tr_handle_get_class_descriptor:
4032 ptr = (const void *)&musbotg_hubd;
4033 len = sizeof(musbotg_hubd);
4037 err = USB_ERR_STALLED;
4046 musbotg_xfer_setup(struct usb_setup_params *parm)
4048 struct musbotg_softc *sc;
4049 struct usb_xfer *xfer;
4055 sc = MUSBOTG_BUS2SC(parm->udev->bus);
4056 xfer = parm->curr_xfer;
4059 * NOTE: This driver does not use any of the parameters that
4060 * are computed from the following values. Just set some
4061 * reasonable dummies:
4063 parm->hc_max_packet_size = 0x400;
4064 parm->hc_max_frame_size = 0xc00;
4066 if ((parm->methods == &musbotg_device_isoc_methods) ||
4067 (parm->methods == &musbotg_device_intr_methods))
4068 parm->hc_max_packet_count = 3;
4070 parm->hc_max_packet_count = 1;
4072 usbd_transfer_setup_sub(parm);
4075 * compute maximum number of TDs
4077 if (parm->methods == &musbotg_device_ctrl_methods) {
4079 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ;
4081 } else if (parm->methods == &musbotg_device_bulk_methods) {
4083 ntd = xfer->nframes + 1 /* SYNC */ ;
4085 } else if (parm->methods == &musbotg_device_intr_methods) {
4087 ntd = xfer->nframes + 1 /* SYNC */ ;
4089 } else if (parm->methods == &musbotg_device_isoc_methods) {
4091 ntd = xfer->nframes + 1 /* SYNC */ ;
4099 * check if "usbd_transfer_setup_sub" set an error
4105 * allocate transfer descriptors
4109 ep_no = xfer->endpointno & UE_ADDR;
4112 * Check for a valid endpoint profile in USB device mode:
4114 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
4115 const struct usb_hw_ep_profile *pf;
4117 musbotg_get_hw_ep_profile(parm->udev, &pf, ep_no);
4120 /* should not happen */
4121 parm->err = USB_ERR_INVAL;
4127 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
4129 for (n = 0; n != ntd; n++) {
4131 struct musbotg_td *td;
4135 td = USB_ADD_BYTES(parm->buf, parm->size[0]);
4138 td->max_frame_size = xfer->max_frame_size;
4139 td->reg_max_packet = xfer->max_packet_size |
4140 ((xfer->max_packet_count - 1) << 11);
4142 td->obj_next = last_obj;
4146 parm->size[0] += sizeof(*td);
4149 xfer->td_start[0] = last_obj;
4153 musbotg_xfer_unsetup(struct usb_xfer *xfer)
4159 musbotg_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4161 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus);
4163 if (sc->sc_mode == MUSB2_HOST_MODE)
4164 *pus = 2000; /* microseconds */
4170 musbotg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
4171 struct usb_endpoint *ep)
4173 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus);
4175 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
4177 edesc->bEndpointAddress, udev->flags.usb_mode,
4180 if (udev->device_index != sc->sc_rt_addr) {
4181 switch (edesc->bmAttributes & UE_XFERTYPE) {
4183 ep->methods = &musbotg_device_ctrl_methods;
4186 ep->methods = &musbotg_device_intr_methods;
4188 case UE_ISOCHRONOUS:
4189 ep->methods = &musbotg_device_isoc_methods;
4192 ep->methods = &musbotg_device_bulk_methods;
4202 musbotg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
4204 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus);
4207 case USB_HW_POWER_SUSPEND:
4208 musbotg_suspend(sc);
4210 case USB_HW_POWER_SHUTDOWN:
4213 case USB_HW_POWER_RESUME:
4221 struct usb_bus_methods musbotg_bus_methods =
4223 .endpoint_init = &musbotg_ep_init,
4224 .get_dma_delay = &musbotg_get_dma_delay,
4225 .xfer_setup = &musbotg_xfer_setup,
4226 .xfer_unsetup = &musbotg_xfer_unsetup,
4227 .get_hw_ep_profile = &musbotg_get_hw_ep_profile,
4228 .xfer_stall = &musbotg_xfer_stall,
4229 .set_stall = &musbotg_set_stall,
4230 .clear_stall = &musbotg_clear_stall,
4231 .roothub_exec = &musbotg_roothub_exec,
4232 .xfer_poll = &musbotg_do_poll,
4233 .set_hw_power_sleep = &musbotg_set_hw_power_sleep,